drivers/dma/dmatest.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * DMA Engine test module
   4  *
   5  * Copyright (C) 2007 Atmel Corporation
   6  * Copyright (C) 2013 Intel Corporation
   7  */
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/freezer.h>
  14 #include <linux/init.h>
  15 #include <linux/kthread.h>
  16 #include <linux/sched/task.h>
  17 #include <linux/module.h>
  18 #include <linux/moduleparam.h>
  19 #include <linux/random.h>
  20 #include <linux/slab.h>
  21 #include <linux/wait.h>
  22
  23 static unsigned int test_buf_size = 16384;
  24 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
  25 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
  26
  27 static char test_device[32];
  28 module_param_string(device, test_device, sizeof(test_device),
  29                 S_IRUGO | S_IWUSR);
  30 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
  31
  32 static unsigned int threads_per_chan = 1;
  33 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
  34 MODULE_PARM_DESC(threads_per_chan,
  35                 "Number of threads to start per channel (default: 1)");
  36
  37 static unsigned int max_channels;
  38 module_param(max_channels, uint, S_IRUGO | S_IWUSR);
  39 MODULE_PARM_DESC(max_channels,
  40                 "Maximum number of channels to use (default: all)");
  41
  42 static unsigned int iterations;
  43 module_param(iterations, uint, S_IRUGO | S_IWUSR);
  44 MODULE_PARM_DESC(iterations,
  45                 "Iterations before stopping test (default: infinite)");
  46
  47 static unsigned int dmatest;
  48 module_param(dmatest, uint, S_IRUGO | S_IWUSR);
  49 MODULE_PARM_DESC(dmatest,
  50                 "dmatest 0-memcpy 1-memset (default: 0)");
  51
  52 static unsigned int xor_sources = 3;
  53 module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
  54 MODULE_PARM_DESC(xor_sources,
  55                 "Number of xor source buffers (default: 3)");
  56
  57 static unsigned int pq_sources = 3;
  58 module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
  59 MODULE_PARM_DESC(pq_sources,
  60                 "Number of p+q source buffers (default: 3)");
  61
  62 static int timeout = 3000;
  63 module_param(timeout, int, S_IRUGO | S_IWUSR);
  64 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
  65                  "Pass -1 for infinite timeout");
  66
  67 static bool noverify;
  68 module_param(noverify, bool, S_IRUGO | S_IWUSR);
  69 MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
  70
  71 static bool norandom;
  72 module_param(norandom, bool, 0644);
  73 MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
  74
  75 static bool verbose;
  76 module_param(verbose, bool, S_IRUGO | S_IWUSR);
  77 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
  78
  79 static int alignment = -1;
  80 module_param(alignment, int, 0644);
  81 MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
  82
  83 static unsigned int transfer_size;
  84 module_param(transfer_size, uint, 0644);
  85 MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
  86
  87 static bool polled;
  88 module_param(polled, bool, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
  90
  91 /**
  92  * struct dmatest_params - test parameters.
  93  * @buf_size:           size of the memcpy test buffer
  94  * @channel:            bus ID of the channel to test
  95  * @device:             bus ID of the DMA Engine to test
  96  * @threads_per_chan:   number of threads to start per channel
  97  * @max_channels:       maximum number of channels to use
  98  * @iterations:         iterations before stopping test
  99  * @xor_sources:        number of xor source buffers
 100  * @pq_sources:         number of p+q source buffers
 101  * @timeout:            transfer timeout in msec, -1 for infinite timeout
 102  * @noverify:           disable data verification
 103  * @norandom:           disable random offset setup
 104  * @alignment:          custom data address alignment taken as 2^alignment
 105  * @transfer_size:      custom transfer size in bytes
 106  * @polled:             use polling for completion instead of interrupts
 107  */
 108 struct dmatest_params {
 109         unsigned int    buf_size;
 110         char            channel[20];
 111         char            device[32];
 112         unsigned int    threads_per_chan;
 113         unsigned int    max_channels;
 114         unsigned int    iterations;
 115         unsigned int    xor_sources;
 116         unsigned int    pq_sources;
 117         int             timeout;
 118         bool            noverify;
 119         bool            norandom;
 120         int             alignment;
 121         unsigned int    transfer_size;
 122         bool            polled;
 123 };
 124
 125 /**
 126  * struct dmatest_info - test information.
 127  * @params:             test parameters
 128  * @channels:           channels under test
 129  * @nr_channels:        number of channels under test
 130  * @lock:               access protection to the fields of this structure
 131  * @did_init:           module has been initialized completely
 132  * @last_error:         test has faced configuration issues
 133  */
 134 static struct dmatest_info {
 135         /* Test parameters */
 136         struct dmatest_params   params;
 137
 138         /* Internal state */
 139         struct list_head        channels;
 140         unsigned int            nr_channels;
 141         int                     last_error;
 142         struct mutex            lock;
 143         bool                    did_init;
 144 } test_info = {
 145         .channels = LIST_HEAD_INIT(test_info.channels),
 146         .lock = __MUTEX_INITIALIZER(test_info.lock),
 147 };
 148
 149 static int dmatest_run_set(const char *val, const struct kernel_param *kp);
 150 static int dmatest_run_get(char *val, const struct kernel_param *kp);
 151 static const struct kernel_param_ops run_ops = {
 152         .set = dmatest_run_set,
 153         .get = dmatest_run_get,
 154 };
 155 static bool dmatest_run;
 156 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
 157 MODULE_PARM_DESC(run, "Run the test (default: false)");
 158
 159 static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
 160 static int dmatest_chan_get(char *val, const struct kernel_param *kp);
 161 static const struct kernel_param_ops multi_chan_ops = {
 162         .set = dmatest_chan_set,
 163         .get = dmatest_chan_get,
 164 };
 165
 166 static char test_channel[20];
 167 static struct kparam_string newchan_kps = {
 168         .string = test_channel,
 169         .maxlen = 20,
 170 };
 171 module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644);
 172 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
 173
 174 static int dmatest_test_list_get(char *val, const struct kernel_param *kp);
 175 static const struct kernel_param_ops test_list_ops = {
 176         .get = dmatest_test_list_get,
 177 };
 178 module_param_cb(test_list, &test_list_ops, NULL, 0444);
 179 MODULE_PARM_DESC(test_list, "Print current test list");
 180
 181 /* Maximum amount of mismatched bytes in buffer to print */
 182 #define MAX_ERROR_COUNT         32
 183
 184 /*
 185  * Initialization patterns. All bytes in the source buffer has bit 7
 186  * set, all bytes in the destination buffer has bit 7 cleared.
 187  *
 188  * Bit 6 is set for all bytes which are to be copied by the DMA
 189  * engine. Bit 5 is set for all bytes which are to be overwritten by
 190  * the DMA engine.
 191  *
 192  * The remaining bits are the inverse of a counter which increments by
 193  * one for each byte address.
 194  */
 195 #define PATTERN_SRC             0x80
 196 #define PATTERN_DST             0x00
 197 #define PATTERN_COPY            0x40
 198 #define PATTERN_OVERWRITE       0x20
 199 #define PATTERN_COUNT_MASK      0x1f
 200 #define PATTERN_MEMSET_IDX      0x01
 201
 202 /* Fixed point arithmetic ops */
 203 #define FIXPT_SHIFT             8
 204 #define FIXPNT_MASK             0xFF
 205 #define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT)
 206 #define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT)
 207 #define FIXPT_GET_FRAC(a)       ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT)
 208
 209 /* poor man's completion - we want to use wait_event_freezable() on it */
 210 struct dmatest_done {
 211         bool                    done;
 212         wait_queue_head_t       *wait;
 213 };
 214
 215 struct dmatest_data {
 216         u8              **raw;
 217         u8              **aligned;
 218         unsigned int    cnt;
 219         unsigned int    off;
 220 };
 221
 222 struct dmatest_thread {
 223         struct list_head        node;
 224         struct dmatest_info     *info;
 225         struct task_struct      *task;
 226         struct dma_chan         *chan;
 227         struct dmatest_data     src;
 228         struct dmatest_data     dst;
 229         enum dma_transaction_type type;
 230         wait_queue_head_t done_wait;
 231         struct dmatest_done test_done;
 232         bool                    done;
 233         bool                    pending;
 234 };
 235
 236 struct dmatest_chan {
 237         struct list_head        node;
 238         struct dma_chan         *chan;
 239         struct list_head        threads;
 240 };
 241
 242 static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
 243 static bool wait;
 244
 245 static bool is_threaded_test_run(struct dmatest_info *info)
 246 {
 247         struct dmatest_chan *dtc;
 248
 249         list_for_each_entry(dtc, &info->channels, node) {
 250                 struct dmatest_thread *thread;
 251
 252                 list_for_each_entry(thread, &dtc->threads, node) {
 253                         if (!thread->done && !thread->pending)
 254                                 return true;
 255                 }
 256         }
 257
 258         return false;
 259 }
 260
 261 static bool is_threaded_test_pending(struct dmatest_info *info)
 262 {
 263         struct dmatest_chan *dtc;
 264
 265         list_for_each_entry(dtc, &info->channels, node) {
 266                 struct dmatest_thread *thread;
 267
 268                 list_for_each_entry(thread, &dtc->threads, node) {
 269                         if (thread->pending)
 270                                 return true;
 271                 }
 272         }
 273
 274         return false;
 275 }
 276
 277 static int dmatest_wait_get(char *val, const struct kernel_param *kp)
 278 {
 279         struct dmatest_info *info = &test_info;
 280         struct dmatest_params *params = &info->params;
 281
 282         if (params->iterations)
 283                 wait_event(thread_wait, !is_threaded_test_run(info));
 284         wait = true;
 285         return param_get_bool(val, kp);
 286 }
 287
 288 static const struct kernel_param_ops wait_ops = {
 289         .get = dmatest_wait_get,
 290         .set = param_set_bool,
 291 };
 292 module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
 293 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
 294
 295 static bool dmatest_match_channel(struct dmatest_params *params,
 296                 struct dma_chan *chan)
 297 {
 298         if (params->channel[0] == '\0')
 299                 return true;
 300         return strcmp(dma_chan_name(chan), params->channel) == 0;
 301 }
 302
 303 static bool dmatest_match_device(struct dmatest_params *params,
 304                 struct dma_device *device)
 305 {
 306         if (params->device[0] == '\0')
 307                 return true;
 308         return strcmp(dev_name(device->dev), params->device) == 0;
 309 }
 310
 311 static unsigned long dmatest_random(void)
 312 {
 313         unsigned long buf;
 314
 315         prandom_bytes(&buf, sizeof(buf));
 316         return buf;
 317 }
 318
 319 static inline u8 gen_inv_idx(u8 index, bool is_memset)
 320 {
 321         u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
 322
 323         return ~val & PATTERN_COUNT_MASK;
 324 }
 325
 326 static inline u8 gen_src_value(u8 index, bool is_memset)
 327 {
 328         return PATTERN_SRC | gen_inv_idx(index, is_memset);
 329 }
 330
 331 static inline u8 gen_dst_value(u8 index, bool is_memset)
 332 {
 333         return PATTERN_DST | gen_inv_idx(index, is_memset);
 334 }
 335
 336 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
 337                 unsigned int buf_size, bool is_memset)
 338 {
 339         unsigned int i;
 340         u8 *buf;
 341
 342         for (; (buf = *bufs); bufs++) {
 343                 for (i = 0; i < start; i++)
 344                         buf[i] = gen_src_value(i, is_memset);
 345                 for ( ; i < start + len; i++)
 346                         buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
 347                 for ( ; i < buf_size; i++)
 348                         buf[i] = gen_src_value(i, is_memset);
 349                 buf++;
 350         }
 351 }
 352
 353 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
 354                 unsigned int buf_size, bool is_memset)
 355 {
 356         unsigned int i;
 357         u8 *buf;
 358
 359         for (; (buf = *bufs); bufs++) {
 360                 for (i = 0; i < start; i++)
 361                         buf[i] = gen_dst_value(i, is_memset);
 362                 for ( ; i < start + len; i++)
 363                         buf[i] = gen_dst_value(i, is_memset) |
 364                                                 PATTERN_OVERWRITE;
 365                 for ( ; i < buf_size; i++)
 366                         buf[i] = gen_dst_value(i, is_memset);
 367         }
 368 }
 369
 370 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
 371                 unsigned int counter, bool is_srcbuf, bool is_memset)
 372 {
 373         u8              diff = actual ^ pattern;
 374         u8              expected = pattern | gen_inv_idx(counter, is_memset);
 375         const char      *thread_name = current->comm;
 376
 377         if (is_srcbuf)
 378                 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
 379                         thread_name, index, expected, actual);
 380         else if ((pattern & PATTERN_COPY)
 381                         && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
 382                 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
 383                         thread_name, index, expected, actual);
 384         else if (diff & PATTERN_SRC)
 385                 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
 386                         thread_name, index, expected, actual);
 387         else
 388                 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
 389                         thread_name, index, expected, actual);
 390 }
 391
 392 static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
 393                 unsigned int end, unsigned int counter, u8 pattern,
 394                 bool is_srcbuf, bool is_memset)
 395 {
 396         unsigned int i;
 397         unsigned int error_count = 0;
 398         u8 actual;
 399         u8 expected;
 400         u8 *buf;
 401         unsigned int counter_orig = counter;
 402
 403         for (; (buf = *bufs); bufs++) {
 404                 counter = counter_orig;
 405                 for (i = start; i < end; i++) {
 406                         actual = buf[i];
 407                         expected = pattern | gen_inv_idx(counter, is_memset);
 408                         if (actual != expected) {
 409                                 if (error_count < MAX_ERROR_COUNT)
 410                                         dmatest_mismatch(actual, pattern, i,
 411                                                          counter, is_srcbuf,
 412                                                          is_memset);
 413                                 error_count++;
 414                         }
 415                         counter++;
 416                 }
 417         }
 418
 419         if (error_count > MAX_ERROR_COUNT)
 420                 pr_warn("%s: %u errors suppressed\n",
 421                         current->comm, error_count - MAX_ERROR_COUNT);
 422
 423         return error_count;
 424 }
 425
 426
 427 static void dmatest_callback(void *arg)
 428 {
 429         struct dmatest_done *done = arg;
 430         struct dmatest_thread *thread =
 431                 container_of(done, struct dmatest_thread, test_done);
 432         if (!thread->done) {
 433                 done->done = true;
 434                 wake_up_all(done->wait);
 435         } else {
 436                 /*
 437                  * If thread->done, it means that this callback occurred
 438                  * after the parent thread has cleaned up. This can
 439                  * happen in the case that driver doesn't implement
 440                  * the terminate_all() functionality and a dma operation
 441                  * did not occur within the timeout period
 442                  */
 443                 WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
 444         }
 445 }
 446
 447 static unsigned int min_odd(unsigned int x, unsigned int y)
 448 {
 449         unsigned int val = min(x, y);
 450
 451         return val % 2 ? val : val - 1;
 452 }
 453
 454 static void result(const char *err, unsigned int n, unsigned int src_off,
 455                    unsigned int dst_off, unsigned int len, unsigned long data)
 456 {
 457         pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
 458                 current->comm, n, err, src_off, dst_off, len, data);
 459 }
 460
 461 static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
 462                        unsigned int dst_off, unsigned int len,
 463                        unsigned long data)
 464 {
 465         pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
 466                  current->comm, n, err, src_off, dst_off, len, data);
 467 }
 468
 469 #define verbose_result(err, n, src_off, dst_off, len, data) ({  \
 470         if (verbose)                                            \
 471                 result(err, n, src_off, dst_off, len, data);    \
 472         else                                                    \
 473                 dbg_result(err, n, src_off, dst_off, len, data);\
 474 })
 475
 476 static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
 477 {
 478         unsigned long long per_sec = 1000000;
 479
 480         if (runtime <= 0)
 481                 return 0;
 482
 483         /* drop precision until runtime is 32-bits */
 484         while (runtime > UINT_MAX) {
 485                 runtime >>= 1;
 486                 per_sec <<= 1;
 487         }
 488
 489         per_sec *= val;
 490         per_sec = INT_TO_FIXPT(per_sec);
 491         do_div(per_sec, runtime);
 492
 493         return per_sec;
 494 }
 495
 496 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
 497 {
 498         return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10));
 499 }
 500
 501 static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt)
 502 {
 503         unsigned int i;
 504
 505         for (i = 0; i < cnt; i++)
 506                 kfree(d->raw[i]);
 507
 508         kfree(d->aligned);
 509         kfree(d->raw);
 510 }
 511
 512 static void dmatest_free_test_data(struct dmatest_data *d)
 513 {
 514         __dmatest_free_test_data(d, d->cnt);
 515 }
 516
 517 static int dmatest_alloc_test_data(struct dmatest_data *d,
 518                 unsigned int buf_size, u8 align)
 519 {
 520         unsigned int i = 0;
 521
 522         d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
 523         if (!d->raw)
 524                 return -ENOMEM;
 525
 526         d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
 527         if (!d->aligned)
 528                 goto err;
 529
 530         for (i = 0; i < d->cnt; i++) {
 531                 d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL);
 532                 if (!d->raw[i])
 533                         goto err;
 534
 535                 /* align to alignment restriction */
 536                 if (align)
 537                         d->aligned[i] = PTR_ALIGN(d->raw[i], align);
 538                 else
 539                         d->aligned[i] = d->raw[i];
 540         }
 541
 542         return 0;
 543 err:
 544         __dmatest_free_test_data(d, i);
 545         return -ENOMEM;
 546 }
 547
 548 /*
 549  * This function repeatedly tests DMA transfers of various lengths and
 550  * offsets for a given operation type until it is told to exit by
 551  * kthread_stop(). There may be multiple threads running this function
 552  * in parallel for a single channel, and there may be multiple channels
 553  * being tested in parallel.
 554  *
 555  * Before each test, the source and destination buffer is initialized
 556  * with a known pattern. This pattern is different depending on
 557  * whether it's in an area which is supposed to be copied or
 558  * overwritten, and different in the source and destination buffers.
 559  * So if the DMA engine doesn't copy exactly what we tell it to copy,
 560  * we'll notice.
 561  */
 562 static int dmatest_func(void *data)
 563 {
 564         struct dmatest_thread   *thread = data;
 565         struct dmatest_done     *done = &thread->test_done;
 566         struct dmatest_info     *info;
 567         struct dmatest_params   *params;
 568         struct dma_chan         *chan;
 569         struct dma_device       *dev;
 570         unsigned int            error_count;
 571         unsigned int            failed_tests = 0;
 572         unsigned int            total_tests = 0;
 573         dma_cookie_t            cookie;
 574         enum dma_status         status;
 575         enum dma_ctrl_flags     flags;
 576         u8                      *pq_coefs = NULL;
 577         int                     ret;
 578         unsigned int            buf_size;
 579         struct dmatest_data     *src;
 580         struct dmatest_data     *dst;
 581         int                     i;
 582         ktime_t                 ktime, start, diff;
 583         ktime_t                 filltime = 0;
 584         ktime_t                 comparetime = 0;
 585         s64                     runtime = 0;
 586         unsigned long long      total_len = 0;
 587         unsigned long long      iops = 0;
 588         u8                      align = 0;
 589         bool                    is_memset = false;
 590         dma_addr_t              *srcs;
 591         dma_addr_t              *dma_pq;
 592
 593         set_freezable();
 594
 595         ret = -ENOMEM;
 596
 597         smp_rmb();
 598         thread->pending = false;
 599         info = thread->info;
 600         params = &info->params;
 601         chan = thread->chan;
 602         dev = chan->device;
 603         src = &thread->src;
 604         dst = &thread->dst;
 605         if (thread->type == DMA_MEMCPY) {
 606                 align = params->alignment < 0 ? dev->copy_align :
 607                                                 params->alignment;
 608                 src->cnt = dst->cnt = 1;
 609         } else if (thread->type == DMA_MEMSET) {
 610                 align = params->alignment < 0 ? dev->fill_align :
 611                                                 params->alignment;
 612                 src->cnt = dst->cnt = 1;
 613                 is_memset = true;
 614         } else if (thread->type == DMA_XOR) {
 615                 /* force odd to ensure dst = src */
 616                 src->cnt = min_odd(params->xor_sources | 1, dev->max_xor);
 617                 dst->cnt = 1;
 618                 align = params->alignment < 0 ? dev->xor_align :
 619                                                 params->alignment;
 620         } else if (thread->type == DMA_PQ) {
 621                 /* force odd to ensure dst = src */
 622                 src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
 623                 dst->cnt = 2;
 624                 align = params->alignment < 0 ? dev->pq_align :
 625                                                 params->alignment;
 626
 627                 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
 628                 if (!pq_coefs)
 629                         goto err_thread_type;
 630
 631                 for (i = 0; i < src->cnt; i++)
 632                         pq_coefs[i] = 1;
 633         } else
 634                 goto err_thread_type;
 635
 636         /* Check if buffer count fits into map count variable (u8) */
 637         if ((src->cnt + dst->cnt) >= 255) {
 638                 pr_err("too many buffers (%d of 255 supported)\n",
 639                        src->cnt + dst->cnt);
 640                 goto err_free_coefs;
 641         }
 642
 643         buf_size = params->buf_size;
 644         if (1 << align > buf_size) {
 645                 pr_err("%u-byte buffer too small for %d-byte alignment\n",
 646                        buf_size, 1 << align);
 647                 goto err_free_coefs;
 648         }
 649
 650         if (dmatest_alloc_test_data(src, buf_size, align) < 0)
 651                 goto err_free_coefs;
 652
 653         if (dmatest_alloc_test_data(dst, buf_size, align) < 0)
 654                 goto err_src;
 655
 656         set_user_nice(current, 10);
 657
 658         srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL);
 659         if (!srcs)
 660                 goto err_dst;
 661
 662         dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL);
 663         if (!dma_pq)
 664                 goto err_srcs_array;
 665
 666         /*
 667          * src and dst buffers are freed by ourselves below
 668          */
 669         if (params->polled)
 670                 flags = DMA_CTRL_ACK;
 671         else
 672                 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 673
 674         ktime = ktime_get();
 675         while (!(kthread_should_stop() ||
 676                (params->iterations && total_tests >= params->iterations))) {
 677                 struct dma_async_tx_descriptor *tx = NULL;
 678                 struct dmaengine_unmap_data *um;
 679                 dma_addr_t *dsts;
 680                 unsigned int len;
 681
 682                 total_tests++;
 683
 684                 if (params->transfer_size) {
 685                         if (params->transfer_size >= buf_size) {
 686                                 pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
 687                                        params->transfer_size, buf_size);
 688                                 break;
 689                         }
 690                         len = params->transfer_size;
 691                 } else if (params->norandom) {
 692                         len = buf_size;
 693                 } else {
 694                         len = dmatest_random() % buf_size + 1;
 695                 }
 696
 697                 /* Do not alter transfer size explicitly defined by user */
 698                 if (!params->transfer_size) {
 699                         len = (len >> align) << align;
 700                         if (!len)
 701                                 len = 1 << align;
 702                 }
 703                 total_len += len;
 704
 705                 if (params->norandom) {
 706                         src->off = 0;
 707                         dst->off = 0;
 708                 } else {
 709                         src->off = dmatest_random() % (buf_size - len + 1);
 710                         dst->off = dmatest_random() % (buf_size - len + 1);
 711
 712                         src->off = (src->off >> align) << align;
 713                         dst->off = (dst->off >> align) << align;
 714                 }
 715
 716                 if (!params->noverify) {
 717                         start = ktime_get();
 718                         dmatest_init_srcs(src->aligned, src->off, len,
 719                                           buf_size, is_memset);
 720                         dmatest_init_dsts(dst->aligned, dst->off, len,
 721                                           buf_size, is_memset);
 722
 723                         diff = ktime_sub(ktime_get(), start);
 724                         filltime = ktime_add(filltime, diff);
 725                 }
 726
 727                 um = dmaengine_get_unmap_data(dev->dev, src->cnt + dst->cnt,
 728                                               GFP_KERNEL);
 729                 if (!um) {
 730                         failed_tests++;
 731                         result("unmap data NULL", total_tests,
 732                                src->off, dst->off, len, ret);
 733                         continue;
 734                 }
 735
 736                 um->len = buf_size;
 737                 for (i = 0; i < src->cnt; i++) {
 738                         void *buf = src->aligned[i];
 739                         struct page *pg = virt_to_page(buf);
 740                         unsigned long pg_off = offset_in_page(buf);
 741
 742                         um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
 743                                                    um->len, DMA_TO_DEVICE);
 744                         srcs[i] = um->addr[i] + src->off;
 745                         ret = dma_mapping_error(dev->dev, um->addr[i]);
 746                         if (ret) {
 747                                 result("src mapping error", total_tests,
 748                                        src->off, dst->off, len, ret);
 749                                 goto error_unmap_continue;
 750                         }
 751                         um->to_cnt++;
 752                 }
 753                 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
 754                 dsts = &um->addr[src->cnt];
 755                 for (i = 0; i < dst->cnt; i++) {
 756                         void *buf = dst->aligned[i];
 757                         struct page *pg = virt_to_page(buf);
 758                         unsigned long pg_off = offset_in_page(buf);
 759
 760                         dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
 761                                                DMA_BIDIRECTIONAL);
 762                         ret = dma_mapping_error(dev->dev, dsts[i]);
 763                         if (ret) {
 764                                 result("dst mapping error", total_tests,
 765                                        src->off, dst->off, len, ret);
 766                                 goto error_unmap_continue;
 767                         }
 768                         um->bidi_cnt++;
 769                 }
 770
 771                 if (thread->type == DMA_MEMCPY)
 772                         tx = dev->device_prep_dma_memcpy(chan,
 773                                                          dsts[0] + dst->off,
 774                                                          srcs[0], len, flags);
 775                 else if (thread->type == DMA_MEMSET)
 776                         tx = dev->device_prep_dma_memset(chan,
 777                                                 dsts[0] + dst->off,
 778                                                 *(src->aligned[0] + src->off),
 779                                                 len, flags);
 780                 else if (thread->type == DMA_XOR)
 781                         tx = dev->device_prep_dma_xor(chan,
 782                                                       dsts[0] + dst->off,
 783                                                       srcs, src->cnt,
 784                                                       len, flags);
 785                 else if (thread->type == DMA_PQ) {
 786                         for (i = 0; i < dst->cnt; i++)
 787                                 dma_pq[i] = dsts[i] + dst->off;
 788                         tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
 789                                                      src->cnt, pq_coefs,
 790                                                      len, flags);
 791                 }
 792
 793                 if (!tx) {
 794                         result("prep error", total_tests, src->off,
 795                                dst->off, len, ret);
 796                         msleep(100);
 797                         goto error_unmap_continue;
 798                 }
 799
 800                 done->done = false;
 801                 if (!params->polled) {
 802                         tx->callback = dmatest_callback;
 803                         tx->callback_param = done;
 804                 }
 805                 cookie = tx->tx_submit(tx);
 806
 807                 if (dma_submit_error(cookie)) {
 808                         result("submit error", total_tests, src->off,
 809                                dst->off, len, ret);
 810                         msleep(100);
 811                         goto error_unmap_continue;
 812                 }
 813
 814                 if (params->polled) {
 815                         status = dma_sync_wait(chan, cookie);
 816                         dmaengine_terminate_sync(chan);
 817                         if (status == DMA_COMPLETE)
 818                                 done->done = true;
 819                 } else {
 820                         dma_async_issue_pending(chan);
 821
 822                         wait_event_freezable_timeout(thread->done_wait,
 823                                         done->done,
 824                                         msecs_to_jiffies(params->timeout));
 825
 826                         status = dma_async_is_tx_complete(chan, cookie, NULL,
 827                                                           NULL);
 828                 }
 829
 830                 if (!done->done) {
 831                         result("test timed out", total_tests, src->off, dst->off,
 832                                len, 0);
 833                         goto error_unmap_continue;
 834                 } else if (status != DMA_COMPLETE &&
 835                            !(dma_has_cap(DMA_COMPLETION_NO_ORDER,
 836                                          dev->cap_mask) &&
 837                              status == DMA_OUT_OF_ORDER)) {
 838                         result(status == DMA_ERROR ?
 839                                "completion error status" :
 840                                "completion busy status", total_tests, src->off,
 841                                dst->off, len, ret);
 842                         goto error_unmap_continue;
 843                 }
 844
 845                 dmaengine_unmap_put(um);
 846
 847                 if (params->noverify) {
 848                         verbose_result("test passed", total_tests, src->off,
 849                                        dst->off, len, 0);
 850                         continue;
 851                 }
 852
 853                 start = ktime_get();
 854                 pr_debug("%s: verifying source buffer...\n", current->comm);
 855                 error_count = dmatest_verify(src->aligned, 0, src->off,
 856                                 0, PATTERN_SRC, true, is_memset);
 857                 error_count += dmatest_verify(src->aligned, src->off,
 858                                 src->off + len, src->off,
 859                                 PATTERN_SRC | PATTERN_COPY, true, is_memset);
 860                 error_count += dmatest_verify(src->aligned, src->off + len,
 861                                 buf_size, src->off + len,
 862                                 PATTERN_SRC, true, is_memset);
 863
 864                 pr_debug("%s: verifying dest buffer...\n", current->comm);
 865                 error_count += dmatest_verify(dst->aligned, 0, dst->off,
 866                                 0, PATTERN_DST, false, is_memset);
 867
 868                 error_count += dmatest_verify(dst->aligned, dst->off,
 869                                 dst->off + len, src->off,
 870                                 PATTERN_SRC | PATTERN_COPY, false, is_memset);
 871
 872                 error_count += dmatest_verify(dst->aligned, dst->off + len,
 873                                 buf_size, dst->off + len,
 874                                 PATTERN_DST, false, is_memset);
 875
 876                 diff = ktime_sub(ktime_get(), start);
 877                 comparetime = ktime_add(comparetime, diff);
 878
 879                 if (error_count) {
 880                         result("data error", total_tests, src->off, dst->off,
 881                                len, error_count);
 882                         failed_tests++;
 883                 } else {
 884                         verbose_result("test passed", total_tests, src->off,
 885                                        dst->off, len, 0);
 886                 }
 887
 888                 continue;
 889
 890 error_unmap_continue:
 891                 dmaengine_unmap_put(um);
 892                 failed_tests++;
 893         }
 894         ktime = ktime_sub(ktime_get(), ktime);
 895         ktime = ktime_sub(ktime, comparetime);
 896         ktime = ktime_sub(ktime, filltime);
 897         runtime = ktime_to_us(ktime);
 898
 899         ret = 0;
 900         kfree(dma_pq);
 901 err_srcs_array:
 902         kfree(srcs);
 903 err_dst:
 904         dmatest_free_test_data(dst);
 905 err_src:
 906         dmatest_free_test_data(src);
 907 err_free_coefs:
 908         kfree(pq_coefs);
 909 err_thread_type:
 910         iops = dmatest_persec(runtime, total_tests);
 911         pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n",
 912                 current->comm, total_tests, failed_tests,
 913                 FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops),
 914                 dmatest_KBs(runtime, total_len), ret);
 915
 916         /* terminate all transfers on specified channels */
 917         if (ret || failed_tests)
 918                 dmaengine_terminate_sync(chan);
 919
 920         thread->done = true;
 921         wake_up(&thread_wait);
 922
 923         return ret;
 924 }
 925
 926 static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
 927 {
 928         struct dmatest_thread   *thread;
 929         struct dmatest_thread   *_thread;
 930         int                     ret;
 931
 932         list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
 933                 ret = kthread_stop(thread->task);
 934                 pr_debug("thread %s exited with status %d\n",
 935                          thread->task->comm, ret);
 936                 list_del(&thread->node);
 937                 put_task_struct(thread->task);
 938                 kfree(thread);
 939         }
 940
 941         /* terminate all transfers on specified channels */
 942         dmaengine_terminate_sync(dtc->chan);
 943
 944         kfree(dtc);
 945 }
 946
 947 static int dmatest_add_threads(struct dmatest_info *info,
 948                 struct dmatest_chan *dtc, enum dma_transaction_type type)
 949 {
 950         struct dmatest_params *params = &info->params;
 951         struct dmatest_thread *thread;
 952         struct dma_chan *chan = dtc->chan;
 953         char *op;
 954         unsigned int i;
 955
 956         if (type == DMA_MEMCPY)
 957                 op = "copy";
 958         else if (type == DMA_MEMSET)
 959                 op = "set";
 960         else if (type == DMA_XOR)
 961                 op = "xor";
 962         else if (type == DMA_PQ)
 963                 op = "pq";
 964         else
 965                 return -EINVAL;
 966
 967         for (i = 0; i < params->threads_per_chan; i++) {
 968                 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
 969                 if (!thread) {
 970                         pr_warn("No memory for %s-%s%u\n",
 971                                 dma_chan_name(chan), op, i);
 972                         break;
 973                 }
 974                 thread->info = info;
 975                 thread->chan = dtc->chan;
 976                 thread->type = type;
 977                 thread->test_done.wait = &thread->done_wait;
 978                 init_waitqueue_head(&thread->done_wait);
 979                 smp_wmb();
 980                 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
 981                                 dma_chan_name(chan), op, i);
 982                 if (IS_ERR(thread->task)) {
 983                         pr_warn("Failed to create thread %s-%s%u\n",
 984                                 dma_chan_name(chan), op, i);
 985                         kfree(thread);
 986                         break;
 987                 }
 988
 989                 /* srcbuf and dstbuf are allocated by the thread itself */
 990                 get_task_struct(thread->task);
 991                 list_add_tail(&thread->node, &dtc->threads);
 992                 thread->pending = true;
 993         }
 994
 995         return i;
 996 }
 997
 998 static int dmatest_add_channel(struct dmatest_info *info,
 999                 struct dma_chan *chan)
1000 {
1001         struct dmatest_chan     *dtc;
1002         struct dma_device       *dma_dev = chan->device;
1003         unsigned int            thread_count = 0;
1004         int cnt;
1005
1006         dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
1007         if (!dtc) {
1008                 pr_warn("No memory for %s\n", dma_chan_name(chan));
1009                 return -ENOMEM;
1010         }
1011
1012         dtc->chan = chan;
1013         INIT_LIST_HEAD(&dtc->threads);
1014
1015         if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) &&
1016             info->params.polled) {
1017                 info->params.polled = false;
1018                 pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n");
1019         }
1020
1021         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1022                 if (dmatest == 0) {
1023                         cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
1024                         thread_count += cnt > 0 ? cnt : 0;
1025                 }
1026         }
1027
1028         if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1029                 if (dmatest == 1) {
1030                         cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
1031                         thread_count += cnt > 0 ? cnt : 0;
1032                 }
1033         }
1034
1035         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1036                 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
1037                 thread_count += cnt > 0 ? cnt : 0;
1038         }
1039         if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1040                 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
1041                 thread_count += cnt > 0 ? cnt : 0;
1042         }
1043
1044         pr_info("Added %u threads using %s\n",
1045                 thread_count, dma_chan_name(chan));
1046
1047         list_add_tail(&dtc->node, &info->channels);
1048         info->nr_channels++;
1049
1050         return 0;
1051 }
1052
1053 static bool filter(struct dma_chan *chan, void *param)
1054 {
1055         struct dmatest_params *params = param;
1056
1057         if (!dmatest_match_channel(params, chan) ||
1058             !dmatest_match_device(params, chan->device))
1059                 return false;
1060         else
1061                 return true;
1062 }
1063
1064 static void request_channels(struct dmatest_info *info,
1065                              enum dma_transaction_type type)
1066 {
1067         dma_cap_mask_t mask;
1068
1069         dma_cap_zero(mask);
1070         dma_cap_set(type, mask);
1071         for (;;) {
1072                 struct dmatest_params *params = &info->params;
1073                 struct dma_chan *chan;
1074
1075                 chan = dma_request_channel(mask, filter, params);
1076                 if (chan) {
1077                         if (dmatest_add_channel(info, chan)) {
1078                                 dma_release_channel(chan);
1079                                 break; /* add_channel failed, punt */
1080                         }
1081                 } else
1082                         break; /* no more channels available */
1083                 if (params->max_channels &&
1084                     info->nr_channels >= params->max_channels)
1085                         break; /* we have all we need */
1086         }
1087 }
1088
1089 static void add_threaded_test(struct dmatest_info *info)
1090 {
1091         struct dmatest_params *params = &info->params;
1092
1093         /* Copy test parameters */
1094         params->buf_size = test_buf_size;
1095         strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
1096         strlcpy(params->device, strim(test_device), sizeof(params->device));
1097         params->threads_per_chan = threads_per_chan;
1098         params->max_channels = max_channels;
1099         params->iterations = iterations;
1100         params->xor_sources = xor_sources;
1101         params->pq_sources = pq_sources;
1102         params->timeout = timeout;
1103         params->noverify = noverify;
1104         params->norandom = norandom;
1105         params->alignment = alignment;
1106         params->transfer_size = transfer_size;
1107         params->polled = polled;
1108
1109         request_channels(info, DMA_MEMCPY);
1110         request_channels(info, DMA_MEMSET);
1111         request_channels(info, DMA_XOR);
1112         request_channels(info, DMA_PQ);
1113 }
1114
1115 static void run_pending_tests(struct dmatest_info *info)
1116 {
1117         struct dmatest_chan *dtc;
1118         unsigned int thread_count = 0;
1119
1120         list_for_each_entry(dtc, &info->channels, node) {
1121                 struct dmatest_thread *thread;
1122
1123                 thread_count = 0;
1124                 list_for_each_entry(thread, &dtc->threads, node) {
1125                         wake_up_process(thread->task);
1126                         thread_count++;
1127                 }
1128                 pr_info("Started %u threads using %s\n",
1129                         thread_count, dma_chan_name(dtc->chan));
1130         }
1131 }
1132
1133 static void stop_threaded_test(struct dmatest_info *info)
1134 {
1135         struct dmatest_chan *dtc, *_dtc;
1136         struct dma_chan *chan;
1137
1138         list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
1139                 list_del(&dtc->node);
1140                 chan = dtc->chan;
1141                 dmatest_cleanup_channel(dtc);
1142                 pr_debug("dropped channel %s\n", dma_chan_name(chan));
1143                 dma_release_channel(chan);
1144         }
1145
1146         info->nr_channels = 0;
1147 }
1148
1149 static void start_threaded_tests(struct dmatest_info *info)
1150 {
1151         /* we might be called early to set run=, defer running until all
1152          * parameters have been evaluated
1153          */
1154         if (!info->did_init)
1155                 return;
1156
1157         run_pending_tests(info);
1158 }
1159
1160 static int dmatest_run_get(char *val, const struct kernel_param *kp)
1161 {
1162         struct dmatest_info *info = &test_info;
1163
1164         mutex_lock(&info->lock);
1165         if (is_threaded_test_run(info)) {
1166                 dmatest_run = true;
1167         } else {
1168                 if (!is_threaded_test_pending(info))
1169                         stop_threaded_test(info);
1170                 dmatest_run = false;
1171         }
1172         mutex_unlock(&info->lock);
1173
1174         return param_get_bool(val, kp);
1175 }
1176
1177 static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1178 {
1179         struct dmatest_info *info = &test_info;
1180         int ret;
1181
1182         mutex_lock(&info->lock);
1183         ret = param_set_bool(val, kp);
1184         if (ret) {
1185                 mutex_unlock(&info->lock);
1186                 return ret;
1187         } else if (dmatest_run) {
1188                 if (!is_threaded_test_pending(info)) {
1189                         /*
1190                          * We have nothing to run. This can be due to:
1191                          */
1192                         ret = info->last_error;
1193                         if (ret) {
1194                                 /* 1) Misconfiguration */
1195                                 pr_err("Channel misconfigured, can't continue\n");
1196                                 mutex_unlock(&info->lock);
1197                                 return ret;
1198                         } else {
1199                                 /* 2) We rely on defaults */
1200                                 pr_info("No channels configured, continue with any\n");
1201                                 if (!is_threaded_test_run(info))
1202                                         stop_threaded_test(info);
1203                                 add_threaded_test(info);
1204                         }
1205                 }
1206                 start_threaded_tests(info);
1207         } else {
1208                 stop_threaded_test(info);
1209         }
1210
1211         mutex_unlock(&info->lock);
1212
1213         return ret;
1214 }
1215
1216 static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
1217 {
1218         struct dmatest_info *info = &test_info;
1219         struct dmatest_chan *dtc;
1220         char chan_reset_val[20];
1221         int ret;
1222
1223         mutex_lock(&info->lock);
1224         ret = param_set_copystring(val, kp);
1225         if (ret) {
1226                 mutex_unlock(&info->lock);
1227                 return ret;
1228         }
1229         /*Clear any previously run threads */
1230         if (!is_threaded_test_run(info) && !is_threaded_test_pending(info))
1231                 stop_threaded_test(info);
1232         /* Reject channels that are already registered */
1233         if (is_threaded_test_pending(info)) {
1234                 list_for_each_entry(dtc, &info->channels, node) {
1235                         if (strcmp(dma_chan_name(dtc->chan),
1236                                    strim(test_channel)) == 0) {
1237                                 dtc = list_last_entry(&info->channels,
1238                                                       struct dmatest_chan,
1239                                                       node);
1240                                 strlcpy(chan_reset_val,
1241                                         dma_chan_name(dtc->chan),
1242                                         sizeof(chan_reset_val));
1243                                 ret = -EBUSY;
1244                                 goto add_chan_err;
1245                         }
1246                 }
1247         }
1248
1249         add_threaded_test(info);
1250
1251         /* Check if channel was added successfully */
1252         dtc = list_last_entry(&info->channels, struct dmatest_chan, node);
1253
1254         if (dtc->chan) {
1255                 /*
1256                  * if new channel was not successfully added, revert the
1257                  * "test_channel" string to the name of the last successfully
1258                  * added channel. exception for when users issues empty string
1259                  * to channel parameter.
1260                  */
1261                 if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0)
1262                     && (strcmp("", strim(test_channel)) != 0)) {
1263                         ret = -EINVAL;
1264                         strlcpy(chan_reset_val, dma_chan_name(dtc->chan),
1265                                 sizeof(chan_reset_val));
1266                         goto add_chan_err;
1267                 }
1268
1269         } else {
1270                 /* Clear test_channel if no channels were added successfully */
1271                 strlcpy(chan_reset_val, "", sizeof(chan_reset_val));
1272                 ret = -EBUSY;
1273                 goto add_chan_err;
1274         }
1275
1276         info->last_error = ret;
1277         mutex_unlock(&info->lock);
1278
1279         return ret;
1280
1281 add_chan_err:
1282         param_set_copystring(chan_reset_val, kp);
1283         info->last_error = ret;
1284         mutex_unlock(&info->lock);
1285
1286         return ret;
1287 }
1288
1289 static int dmatest_chan_get(char *val, const struct kernel_param *kp)
1290 {
1291         struct dmatest_info *info = &test_info;
1292
1293         mutex_lock(&info->lock);
1294         if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) {
1295                 stop_threaded_test(info);
1296                 strlcpy(test_channel, "", sizeof(test_channel));
1297         }
1298         mutex_unlock(&info->lock);
1299
1300         return param_get_string(val, kp);
1301 }
1302
1303 static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
1304 {
1305         struct dmatest_info *info = &test_info;
1306         struct dmatest_chan *dtc;
1307         unsigned int thread_count = 0;
1308
1309         list_for_each_entry(dtc, &info->channels, node) {
1310                 struct dmatest_thread *thread;
1311
1312                 thread_count = 0;
1313                 list_for_each_entry(thread, &dtc->threads, node) {
1314                         thread_count++;
1315                 }
1316                 pr_info("%u threads using %s\n",
1317                         thread_count, dma_chan_name(dtc->chan));
1318         }
1319
1320         return 0;
1321 }
1322
1323 static int __init dmatest_init(void)
1324 {
1325         struct dmatest_info *info = &test_info;
1326         struct dmatest_params *params = &info->params;
1327
1328         if (dmatest_run) {
1329                 mutex_lock(&info->lock);
1330                 add_threaded_test(info);
1331                 run_pending_tests(info);
1332                 mutex_unlock(&info->lock);
1333         }
1334
1335         if (params->iterations && wait)
1336                 wait_event(thread_wait, !is_threaded_test_run(info));
1337
1338         /* module parameters are stable, inittime tests are started,
1339          * let userspace take over 'run' control
1340          */
1341         info->did_init = true;
1342
1343         return 0;
1344 }
1345 /* when compiled-in wait for drivers to load first */
1346 late_initcall(dmatest_init);
1347
1348 static void __exit dmatest_exit(void)
1349 {
1350         struct dmatest_info *info = &test_info;
1351
1352         mutex_lock(&info->lock);
1353         stop_threaded_test(info);
1354         mutex_unlock(&info->lock);
1355 }
1356 module_exit(dmatest_exit);
1357
1358 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1359 MODULE_LICENSE("GPL v2");