drivers/crypto/picoxcell_crypto_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (c) 2010 Picochip Ltd., Jamie Iles
   4  */
   5 #ifndef __PICOXCELL_CRYPTO_REGS_H__
   6 #define __PICOXCELL_CRYPTO_REGS_H__
   7
   8 #define SPA_STATUS_OK                   0
   9 #define SPA_STATUS_ICV_FAIL             1
  10 #define SPA_STATUS_MEMORY_ERROR         2
  11 #define SPA_STATUS_BLOCK_ERROR          3
  12
  13 #define SPA_IRQ_CTRL_STAT_CNT_OFFSET    16
  14 #define SPA_IRQ_STAT_STAT_MASK          (1 << 4)
  15 #define SPA_FIFO_STAT_STAT_OFFSET       16
  16 #define SPA_FIFO_STAT_STAT_CNT_MASK     (0x3F << SPA_FIFO_STAT_STAT_OFFSET)
  17 #define SPA_STATUS_RES_CODE_OFFSET      24
  18 #define SPA_STATUS_RES_CODE_MASK        (0x3 << SPA_STATUS_RES_CODE_OFFSET)
  19 #define SPA_KEY_SZ_CTX_INDEX_OFFSET     8
  20 #define SPA_KEY_SZ_CIPHER_OFFSET        31
  21
  22 #define SPA_IRQ_EN_REG_OFFSET           0x00000000
  23 #define SPA_IRQ_STAT_REG_OFFSET         0x00000004
  24 #define SPA_IRQ_CTRL_REG_OFFSET         0x00000008
  25 #define SPA_FIFO_STAT_REG_OFFSET        0x0000000C
  26 #define SPA_SDMA_BRST_SZ_REG_OFFSET     0x00000010
  27 #define SPA_SRC_PTR_REG_OFFSET          0x00000020
  28 #define SPA_DST_PTR_REG_OFFSET          0x00000024
  29 #define SPA_OFFSET_REG_OFFSET           0x00000028
  30 #define SPA_AAD_LEN_REG_OFFSET          0x0000002C
  31 #define SPA_PROC_LEN_REG_OFFSET         0x00000030
  32 #define SPA_ICV_LEN_REG_OFFSET          0x00000034
  33 #define SPA_ICV_OFFSET_REG_OFFSET       0x00000038
  34 #define SPA_SW_CTRL_REG_OFFSET          0x0000003C
  35 #define SPA_CTRL_REG_OFFSET             0x00000040
  36 #define SPA_AUX_INFO_REG_OFFSET         0x0000004C
  37 #define SPA_STAT_POP_REG_OFFSET         0x00000050
  38 #define SPA_STATUS_REG_OFFSET           0x00000054
  39 #define SPA_KEY_SZ_REG_OFFSET           0x00000100
  40 #define SPA_CIPH_KEY_BASE_REG_OFFSET    0x00004000
  41 #define SPA_HASH_KEY_BASE_REG_OFFSET    0x00008000
  42 #define SPA_RC4_CTX_BASE_REG_OFFSET     0x00020000
  43
  44 #define SPA_IRQ_EN_REG_RESET            0x00000000
  45 #define SPA_IRQ_CTRL_REG_RESET          0x00000000
  46 #define SPA_FIFO_STAT_REG_RESET         0x00000000
  47 #define SPA_SDMA_BRST_SZ_REG_RESET      0x00000000
  48 #define SPA_SRC_PTR_REG_RESET           0x00000000
  49 #define SPA_DST_PTR_REG_RESET           0x00000000
  50 #define SPA_OFFSET_REG_RESET            0x00000000
  51 #define SPA_AAD_LEN_REG_RESET           0x00000000
  52 #define SPA_PROC_LEN_REG_RESET          0x00000000
  53 #define SPA_ICV_LEN_REG_RESET           0x00000000
  54 #define SPA_ICV_OFFSET_REG_RESET        0x00000000
  55 #define SPA_SW_CTRL_REG_RESET           0x00000000
  56 #define SPA_CTRL_REG_RESET              0x00000000
  57 #define SPA_AUX_INFO_REG_RESET          0x00000000
  58 #define SPA_STAT_POP_REG_RESET          0x00000000
  59 #define SPA_STATUS_REG_RESET            0x00000000
  60 #define SPA_KEY_SZ_REG_RESET            0x00000000
  61
  62 #define SPA_CTRL_HASH_ALG_IDX           4
  63 #define SPA_CTRL_CIPH_MODE_IDX          8
  64 #define SPA_CTRL_HASH_MODE_IDX          12
  65 #define SPA_CTRL_CTX_IDX                16
  66 #define SPA_CTRL_ENCRYPT_IDX            24
  67 #define SPA_CTRL_AAD_COPY               25
  68 #define SPA_CTRL_ICV_PT                 26
  69 #define SPA_CTRL_ICV_ENC                27
  70 #define SPA_CTRL_ICV_APPEND             28
  71 #define SPA_CTRL_KEY_EXP                29
  72
  73 #define SPA_KEY_SZ_CXT_IDX              8
  74 #define SPA_KEY_SZ_CIPHER_IDX           31
  75
  76 #define SPA_IRQ_EN_CMD0_EN              (1 << 0)
  77 #define SPA_IRQ_EN_STAT_EN              (1 << 4)
  78 #define SPA_IRQ_EN_GLBL_EN              (1 << 31)
  79
  80 #define SPA_CTRL_CIPH_ALG_NULL          0x00
  81 #define SPA_CTRL_CIPH_ALG_DES           0x01
  82 #define SPA_CTRL_CIPH_ALG_AES           0x02
  83 #define SPA_CTRL_CIPH_ALG_RC4           0x03
  84 #define SPA_CTRL_CIPH_ALG_MULTI2        0x04
  85 #define SPA_CTRL_CIPH_ALG_KASUMI        0x05
  86
  87 #define SPA_CTRL_HASH_ALG_NULL          (0x00 << SPA_CTRL_HASH_ALG_IDX)
  88 #define SPA_CTRL_HASH_ALG_MD5           (0x01 << SPA_CTRL_HASH_ALG_IDX)
  89 #define SPA_CTRL_HASH_ALG_SHA           (0x02 << SPA_CTRL_HASH_ALG_IDX)
  90 #define SPA_CTRL_HASH_ALG_SHA224        (0x03 << SPA_CTRL_HASH_ALG_IDX)
  91 #define SPA_CTRL_HASH_ALG_SHA256        (0x04 << SPA_CTRL_HASH_ALG_IDX)
  92 #define SPA_CTRL_HASH_ALG_SHA384        (0x05 << SPA_CTRL_HASH_ALG_IDX)
  93 #define SPA_CTRL_HASH_ALG_SHA512        (0x06 << SPA_CTRL_HASH_ALG_IDX)
  94 #define SPA_CTRL_HASH_ALG_AESMAC        (0x07 << SPA_CTRL_HASH_ALG_IDX)
  95 #define SPA_CTRL_HASH_ALG_AESCMAC       (0x08 << SPA_CTRL_HASH_ALG_IDX)
  96 #define SPA_CTRL_HASH_ALG_KASF9         (0x09 << SPA_CTRL_HASH_ALG_IDX)
  97
  98 #define SPA_CTRL_CIPH_MODE_NULL         (0x00 << SPA_CTRL_CIPH_MODE_IDX)
  99 #define SPA_CTRL_CIPH_MODE_ECB          (0x00 << SPA_CTRL_CIPH_MODE_IDX)
 100 #define SPA_CTRL_CIPH_MODE_CBC          (0x01 << SPA_CTRL_CIPH_MODE_IDX)
 101 #define SPA_CTRL_CIPH_MODE_CTR          (0x02 << SPA_CTRL_CIPH_MODE_IDX)
 102 #define SPA_CTRL_CIPH_MODE_CCM          (0x03 << SPA_CTRL_CIPH_MODE_IDX)
 103 #define SPA_CTRL_CIPH_MODE_GCM          (0x05 << SPA_CTRL_CIPH_MODE_IDX)
 104 #define SPA_CTRL_CIPH_MODE_OFB          (0x07 << SPA_CTRL_CIPH_MODE_IDX)
 105 #define SPA_CTRL_CIPH_MODE_CFB          (0x08 << SPA_CTRL_CIPH_MODE_IDX)
 106 #define SPA_CTRL_CIPH_MODE_F8           (0x09 << SPA_CTRL_CIPH_MODE_IDX)
 107
 108 #define SPA_CTRL_HASH_MODE_RAW          (0x00 << SPA_CTRL_HASH_MODE_IDX)
 109 #define SPA_CTRL_HASH_MODE_SSLMAC       (0x01 << SPA_CTRL_HASH_MODE_IDX)
 110 #define SPA_CTRL_HASH_MODE_HMAC         (0x02 << SPA_CTRL_HASH_MODE_IDX)
 111
 112 #define SPA_FIFO_STAT_EMPTY             (1 << 31)
 113 #define SPA_FIFO_CMD_FULL               (1 << 7)
 114
 115 #endif /* __PICOXCELL_CRYPTO_REGS_H__ */