drivers/counter/stm32-timer-cnt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * STM32 Timer Encoder and Counter driver
   4  *
   5  * Copyright (C) STMicroelectronics 2018
   6  *
   7  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
   8  *
   9  */
  10 #include <linux/counter.h>
  11 #include <linux/mfd/stm32-timers.h>
  12 #include <linux/mod_devicetable.h>
  13 #include <linux/module.h>
  14 #include <linux/pinctrl/consumer.h>
  15 #include <linux/platform_device.h>
  16
  17 #define TIM_CCMR_CCXS   (BIT(8) | BIT(0))
  18 #define TIM_CCMR_MASK   (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
  19                          TIM_CCMR_IC1F | TIM_CCMR_IC2F)
  20 #define TIM_CCER_MASK   (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
  21                          TIM_CCER_CC2P | TIM_CCER_CC2NP)
  22
  23 struct stm32_timer_regs {
  24         u32 cr1;
  25         u32 cnt;
  26         u32 smcr;
  27         u32 arr;
  28 };
  29
  30 struct stm32_timer_cnt {
  31         struct counter_device counter;
  32         struct regmap *regmap;
  33         struct clk *clk;
  34         u32 ceiling;
  35         bool enabled;
  36         struct stm32_timer_regs bak;
  37 };
  38
  39 /**
  40  * enum stm32_count_function - enumerates stm32 timer counter encoder modes
  41  * @STM32_COUNT_SLAVE_MODE_DISABLED: counts on internal clock when CEN=1
  42  * @STM32_COUNT_ENCODER_MODE_1: counts TI1FP1 edges, depending on TI2FP2 level
  43  * @STM32_COUNT_ENCODER_MODE_2: counts TI2FP2 edges, depending on TI1FP1 level
  44  * @STM32_COUNT_ENCODER_MODE_3: counts on both TI1FP1 and TI2FP2 edges
  45  */
  46 enum stm32_count_function {
  47         STM32_COUNT_SLAVE_MODE_DISABLED = -1,
  48         STM32_COUNT_ENCODER_MODE_1,
  49         STM32_COUNT_ENCODER_MODE_2,
  50         STM32_COUNT_ENCODER_MODE_3,
  51 };
  52
  53 static enum counter_count_function stm32_count_functions[] = {
  54         [STM32_COUNT_ENCODER_MODE_1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A,
  55         [STM32_COUNT_ENCODER_MODE_2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B,
  56         [STM32_COUNT_ENCODER_MODE_3] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
  57 };
  58
  59 static int stm32_count_read(struct counter_device *counter,
  60                             struct counter_count *count, unsigned long *val)
  61 {
  62         struct stm32_timer_cnt *const priv = counter->priv;
  63         u32 cnt;
  64
  65         regmap_read(priv->regmap, TIM_CNT, &cnt);
  66         *val = cnt;
  67
  68         return 0;
  69 }
  70
  71 static int stm32_count_write(struct counter_device *counter,
  72                              struct counter_count *count,
  73                              const unsigned long val)
  74 {
  75         struct stm32_timer_cnt *const priv = counter->priv;
  76
  77         if (val > priv->ceiling)
  78                 return -EINVAL;
  79
  80         return regmap_write(priv->regmap, TIM_CNT, val);
  81 }
  82
  83 static int stm32_count_function_get(struct counter_device *counter,
  84                                     struct counter_count *count,
  85                                     size_t *function)
  86 {
  87         struct stm32_timer_cnt *const priv = counter->priv;
  88         u32 smcr;
  89
  90         regmap_read(priv->regmap, TIM_SMCR, &smcr);
  91
  92         switch (smcr & TIM_SMCR_SMS) {
  93         case 1:
  94                 *function = STM32_COUNT_ENCODER_MODE_1;
  95                 return 0;
  96         case 2:
  97                 *function = STM32_COUNT_ENCODER_MODE_2;
  98                 return 0;
  99         case 3:
 100                 *function = STM32_COUNT_ENCODER_MODE_3;
 101                 return 0;
 102         }
 103
 104         return -EINVAL;
 105 }
 106
 107 static int stm32_count_function_set(struct counter_device *counter,
 108                                     struct counter_count *count,
 109                                     size_t function)
 110 {
 111         struct stm32_timer_cnt *const priv = counter->priv;
 112         u32 cr1, sms;
 113
 114         switch (function) {
 115         case STM32_COUNT_ENCODER_MODE_1:
 116                 sms = 1;
 117                 break;
 118         case STM32_COUNT_ENCODER_MODE_2:
 119                 sms = 2;
 120                 break;
 121         case STM32_COUNT_ENCODER_MODE_3:
 122                 sms = 3;
 123                 break;
 124         default:
 125                 sms = 0;
 126                 break;
 127         }
 128
 129         /* Store enable status */
 130         regmap_read(priv->regmap, TIM_CR1, &cr1);
 131
 132         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 133
 134         /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
 135         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 136         regmap_write(priv->regmap, TIM_ARR, priv->ceiling);
 137
 138         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
 139
 140         /* Make sure that registers are updated */
 141         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 142
 143         /* Restore the enable status */
 144         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
 145
 146         return 0;
 147 }
 148
 149 static ssize_t stm32_count_direction_read(struct counter_device *counter,
 150                                       struct counter_count *count,
 151                                       void *private, char *buf)
 152 {
 153         struct stm32_timer_cnt *const priv = counter->priv;
 154         const char *direction;
 155         u32 cr1;
 156
 157         regmap_read(priv->regmap, TIM_CR1, &cr1);
 158         direction = (cr1 & TIM_CR1_DIR) ? "backward" : "forward";
 159
 160         return scnprintf(buf, PAGE_SIZE, "%s\n", direction);
 161 }
 162
 163 static ssize_t stm32_count_ceiling_read(struct counter_device *counter,
 164                                         struct counter_count *count,
 165                                         void *private, char *buf)
 166 {
 167         struct stm32_timer_cnt *const priv = counter->priv;
 168         u32 arr;
 169
 170         regmap_read(priv->regmap, TIM_ARR, &arr);
 171
 172         return snprintf(buf, PAGE_SIZE, "%u\n", arr);
 173 }
 174
 175 static ssize_t stm32_count_ceiling_write(struct counter_device *counter,
 176                                          struct counter_count *count,
 177                                          void *private,
 178                                          const char *buf, size_t len)
 179 {
 180         struct stm32_timer_cnt *const priv = counter->priv;
 181         unsigned int ceiling;
 182         int ret;
 183
 184         ret = kstrtouint(buf, 0, &ceiling);
 185         if (ret)
 186                 return ret;
 187
 188         /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
 189         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 190         regmap_write(priv->regmap, TIM_ARR, ceiling);
 191
 192         priv->ceiling = ceiling;
 193         return len;
 194 }
 195
 196 static ssize_t stm32_count_enable_read(struct counter_device *counter,
 197                                        struct counter_count *count,
 198                                        void *private, char *buf)
 199 {
 200         struct stm32_timer_cnt *const priv = counter->priv;
 201         u32 cr1;
 202
 203         regmap_read(priv->regmap, TIM_CR1, &cr1);
 204
 205         return scnprintf(buf, PAGE_SIZE, "%d\n", (bool)(cr1 & TIM_CR1_CEN));
 206 }
 207
 208 static ssize_t stm32_count_enable_write(struct counter_device *counter,
 209                                         struct counter_count *count,
 210                                         void *private,
 211                                         const char *buf, size_t len)
 212 {
 213         struct stm32_timer_cnt *const priv = counter->priv;
 214         int err;
 215         u32 cr1;
 216         bool enable;
 217
 218         err = kstrtobool(buf, &enable);
 219         if (err)
 220                 return err;
 221
 222         if (enable) {
 223                 regmap_read(priv->regmap, TIM_CR1, &cr1);
 224                 if (!(cr1 & TIM_CR1_CEN))
 225                         clk_enable(priv->clk);
 226
 227                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 228                                    TIM_CR1_CEN);
 229         } else {
 230                 regmap_read(priv->regmap, TIM_CR1, &cr1);
 231                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 232                 if (cr1 & TIM_CR1_CEN)
 233                         clk_disable(priv->clk);
 234         }
 235
 236         /* Keep enabled state to properly handle low power states */
 237         priv->enabled = enable;
 238
 239         return len;
 240 }
 241
 242 static const struct counter_count_ext stm32_count_ext[] = {
 243         {
 244                 .name = "direction",
 245                 .read = stm32_count_direction_read,
 246         },
 247         {
 248                 .name = "enable",
 249                 .read = stm32_count_enable_read,
 250                 .write = stm32_count_enable_write
 251         },
 252         {
 253                 .name = "ceiling",
 254                 .read = stm32_count_ceiling_read,
 255                 .write = stm32_count_ceiling_write
 256         },
 257 };
 258
 259 enum stm32_synapse_action {
 260         STM32_SYNAPSE_ACTION_NONE,
 261         STM32_SYNAPSE_ACTION_BOTH_EDGES
 262 };
 263
 264 static enum counter_synapse_action stm32_synapse_actions[] = {
 265         [STM32_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
 266         [STM32_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES
 267 };
 268
 269 static int stm32_action_get(struct counter_device *counter,
 270                             struct counter_count *count,
 271                             struct counter_synapse *synapse,
 272                             size_t *action)
 273 {
 274         size_t function;
 275         int err;
 276
 277         /* Default action mode (e.g. STM32_COUNT_SLAVE_MODE_DISABLED) */
 278         *action = STM32_SYNAPSE_ACTION_NONE;
 279
 280         err = stm32_count_function_get(counter, count, &function);
 281         if (err)
 282                 return 0;
 283
 284         switch (function) {
 285         case STM32_COUNT_ENCODER_MODE_1:
 286                 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */
 287                 if (synapse->signal->id == count->synapses[0].signal->id)
 288                         *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
 289                 break;
 290         case STM32_COUNT_ENCODER_MODE_2:
 291                 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */
 292                 if (synapse->signal->id == count->synapses[1].signal->id)
 293                         *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
 294                 break;
 295         case STM32_COUNT_ENCODER_MODE_3:
 296                 /* counts up/down on both TI1FP1 and TI2FP2 edges */
 297                 *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
 298                 break;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static const struct counter_ops stm32_timer_cnt_ops = {
 305         .count_read = stm32_count_read,
 306         .count_write = stm32_count_write,
 307         .function_get = stm32_count_function_get,
 308         .function_set = stm32_count_function_set,
 309         .action_get = stm32_action_get,
 310 };
 311
 312 static struct counter_signal stm32_signals[] = {
 313         {
 314                 .id = 0,
 315                 .name = "Channel 1 Quadrature A"
 316         },
 317         {
 318                 .id = 1,
 319                 .name = "Channel 1 Quadrature B"
 320         }
 321 };
 322
 323 static struct counter_synapse stm32_count_synapses[] = {
 324         {
 325                 .actions_list = stm32_synapse_actions,
 326                 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
 327                 .signal = &stm32_signals[0]
 328         },
 329         {
 330                 .actions_list = stm32_synapse_actions,
 331                 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
 332                 .signal = &stm32_signals[1]
 333         }
 334 };
 335
 336 static struct counter_count stm32_counts = {
 337         .id = 0,
 338         .name = "Channel 1 Count",
 339         .functions_list = stm32_count_functions,
 340         .num_functions = ARRAY_SIZE(stm32_count_functions),
 341         .synapses = stm32_count_synapses,
 342         .num_synapses = ARRAY_SIZE(stm32_count_synapses),
 343         .ext = stm32_count_ext,
 344         .num_ext = ARRAY_SIZE(stm32_count_ext)
 345 };
 346
 347 static int stm32_timer_cnt_probe(struct platform_device *pdev)
 348 {
 349         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 350         struct device *dev = &pdev->dev;
 351         struct stm32_timer_cnt *priv;
 352
 353         if (IS_ERR_OR_NULL(ddata))
 354                 return -EINVAL;
 355
 356         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 357         if (!priv)
 358                 return -ENOMEM;
 359
 360         priv->regmap = ddata->regmap;
 361         priv->clk = ddata->clk;
 362         priv->ceiling = ddata->max_arr;
 363
 364         priv->counter.name = dev_name(dev);
 365         priv->counter.parent = dev;
 366         priv->counter.ops = &stm32_timer_cnt_ops;
 367         priv->counter.counts = &stm32_counts;
 368         priv->counter.num_counts = 1;
 369         priv->counter.signals = stm32_signals;
 370         priv->counter.num_signals = ARRAY_SIZE(stm32_signals);
 371         priv->counter.priv = priv;
 372
 373         platform_set_drvdata(pdev, priv);
 374
 375         /* Register Counter device */
 376         return devm_counter_register(dev, &priv->counter);
 377 }
 378
 379 static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev)
 380 {
 381         struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
 382
 383         /* Only take care of enabled counter: don't disturb other MFD child */
 384         if (priv->enabled) {
 385                 /* Backup registers that may get lost in low power mode */
 386                 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
 387                 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
 388                 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
 389                 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
 390
 391                 /* Disable the counter */
 392                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 393                 clk_disable(priv->clk);
 394         }
 395
 396         return pinctrl_pm_select_sleep_state(dev);
 397 }
 398
 399 static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)
 400 {
 401         struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
 402         int ret;
 403
 404         ret = pinctrl_pm_select_default_state(dev);
 405         if (ret)
 406                 return ret;
 407
 408         if (priv->enabled) {
 409                 clk_enable(priv->clk);
 410
 411                 /* Restore registers that may have been lost */
 412                 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
 413                 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
 414                 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
 415
 416                 /* Also re-enables the counter */
 417                 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
 418         }
 419
 420         return 0;
 421 }
 422
 423 static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend,
 424                          stm32_timer_cnt_resume);
 425
 426 static const struct of_device_id stm32_timer_cnt_of_match[] = {
 427         { .compatible = "st,stm32-timer-counter", },
 428         {},
 429 };
 430 MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
 431
 432 static struct platform_driver stm32_timer_cnt_driver = {
 433         .probe = stm32_timer_cnt_probe,
 434         .driver = {
 435                 .name = "stm32-timer-counter",
 436                 .of_match_table = stm32_timer_cnt_of_match,
 437                 .pm = &stm32_timer_cnt_pm_ops,
 438         },
 439 };
 440 module_platform_driver(stm32_timer_cnt_driver);
 441
 442 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
 443 MODULE_ALIAS("platform:stm32-timer-counter");
 444 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
 445 MODULE_LICENSE("GPL v2");