drivers/clocksource/timer-tegra20.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * Author:
   5  *      Colin Cross <ccross@google.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/clockchips.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/delay.h>
  23 #include <linux/err.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/percpu.h>
  28 #include <linux/sched_clock.h>
  29 #include <linux/time.h>
  30
  31 #include "timer-of.h"
  32
  33 #ifdef CONFIG_ARM
  34 #include <asm/mach/time.h>
  35 #endif
  36
  37 #define RTC_SECONDS            0x08
  38 #define RTC_SHADOW_SECONDS     0x0c
  39 #define RTC_MILLISECONDS       0x10
  40
  41 #define TIMERUS_CNTR_1US 0x10
  42 #define TIMERUS_USEC_CFG 0x14
  43 #define TIMERUS_CNTR_FREEZE 0x4c
  44
  45 #define TIMER_PTV               0x0
  46 #define TIMER_PTV_EN            BIT(31)
  47 #define TIMER_PTV_PER           BIT(30)
  48 #define TIMER_PCR               0x4
  49 #define TIMER_PCR_INTR_CLR      BIT(30)
  50
  51 #ifdef CONFIG_ARM
  52 #define TIMER_CPU0              0x50 /* TIMER3 */
  53 #else
  54 #define TIMER_CPU0              0x90 /* TIMER10 */
  55 #define TIMER10_IRQ_IDX         10
  56 #define IRQ_IDX_FOR_CPU(cpu)    (TIMER10_IRQ_IDX + cpu)
  57 #endif
  58 #define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8)
  59
  60 static u32 usec_config;
  61 static void __iomem *timer_reg_base;
  62 #ifdef CONFIG_ARM
  63 static struct delay_timer tegra_delay_timer;
  64 #endif
  65
  66 static int tegra_timer_set_next_event(unsigned long cycles,
  67                                          struct clock_event_device *evt)
  68 {
  69         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  70
  71         writel(TIMER_PTV_EN |
  72                ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
  73                reg_base + TIMER_PTV);
  74
  75         return 0;
  76 }
  77
  78 static int tegra_timer_shutdown(struct clock_event_device *evt)
  79 {
  80         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  81
  82         writel(0, reg_base + TIMER_PTV);
  83
  84         return 0;
  85 }
  86
  87 static int tegra_timer_set_periodic(struct clock_event_device *evt)
  88 {
  89         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  90
  91         writel(TIMER_PTV_EN | TIMER_PTV_PER |
  92                ((timer_of_rate(to_timer_of(evt)) / HZ) - 1),
  93                reg_base + TIMER_PTV);
  94
  95         return 0;
  96 }
  97
  98 static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
  99 {
 100         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 101         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
 102
 103         writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
 104         evt->event_handler(evt);
 105
 106         return IRQ_HANDLED;
 107 }
 108
 109 static void tegra_timer_suspend(struct clock_event_device *evt)
 110 {
 111         void __iomem *reg_base = timer_of_base(to_timer_of(evt));
 112
 113         writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
 114 }
 115
 116 static void tegra_timer_resume(struct clock_event_device *evt)
 117 {
 118         writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
 119 }
 120
 121 #ifdef CONFIG_ARM64
 122 static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
 123         .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
 124
 125         .clkevt = {
 126                 .name = "tegra_timer",
 127                 .rating = 460,
 128                 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 129                 .set_next_event = tegra_timer_set_next_event,
 130                 .set_state_shutdown = tegra_timer_shutdown,
 131                 .set_state_periodic = tegra_timer_set_periodic,
 132                 .set_state_oneshot = tegra_timer_shutdown,
 133                 .tick_resume = tegra_timer_shutdown,
 134                 .suspend = tegra_timer_suspend,
 135                 .resume = tegra_timer_resume,
 136         },
 137 };
 138
 139 static int tegra_timer_setup(unsigned int cpu)
 140 {
 141         struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
 142
 143         irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
 144         enable_irq(to->clkevt.irq);
 145
 146         clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
 147                                         1, /* min */
 148                                         0x1fffffff); /* 29 bits */
 149
 150         return 0;
 151 }
 152
 153 static int tegra_timer_stop(unsigned int cpu)
 154 {
 155         struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
 156
 157         to->clkevt.set_state_shutdown(&to->clkevt);
 158         disable_irq_nosync(to->clkevt.irq);
 159
 160         return 0;
 161 }
 162 #else /* CONFIG_ARM */
 163 static struct timer_of tegra_to = {
 164         .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ,
 165
 166         .clkevt = {
 167                 .name = "tegra_timer",
 168                 .rating = 300,
 169                 .features = CLOCK_EVT_FEAT_ONESHOT |
 170                             CLOCK_EVT_FEAT_PERIODIC |
 171                             CLOCK_EVT_FEAT_DYNIRQ,
 172                 .set_next_event = tegra_timer_set_next_event,
 173                 .set_state_shutdown = tegra_timer_shutdown,
 174                 .set_state_periodic = tegra_timer_set_periodic,
 175                 .set_state_oneshot = tegra_timer_shutdown,
 176                 .tick_resume = tegra_timer_shutdown,
 177                 .suspend = tegra_timer_suspend,
 178                 .resume = tegra_timer_resume,
 179                 .cpumask = cpu_possible_mask,
 180         },
 181
 182         .of_irq = {
 183                 .index = 2,
 184                 .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH,
 185                 .handler = tegra_timer_isr,
 186         },
 187 };
 188
 189 static u64 notrace tegra_read_sched_clock(void)
 190 {
 191         return readl(timer_reg_base + TIMERUS_CNTR_1US);
 192 }
 193
 194 static unsigned long tegra_delay_timer_read_counter_long(void)
 195 {
 196         return readl(timer_reg_base + TIMERUS_CNTR_1US);
 197 }
 198
 199 static struct timer_of suspend_rtc_to = {
 200         .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
 201 };
 202
 203 /*
 204  * tegra_rtc_read - Reads the Tegra RTC registers
 205  * Care must be taken that this funciton is not called while the
 206  * tegra_rtc driver could be executing to avoid race conditions
 207  * on the RTC shadow register
 208  */
 209 static u64 tegra_rtc_read_ms(struct clocksource *cs)
 210 {
 211         u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS);
 212         u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS);
 213         return (u64)s * MSEC_PER_SEC + ms;
 214 }
 215
 216 static struct clocksource suspend_rtc_clocksource = {
 217         .name   = "tegra_suspend_timer",
 218         .rating = 200,
 219         .read   = tegra_rtc_read_ms,
 220         .mask   = CLOCKSOURCE_MASK(32),
 221         .flags  = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
 222 };
 223 #endif
 224
 225 static int tegra_timer_common_init(struct device_node *np, struct timer_of *to)
 226 {
 227         int ret = 0;
 228
 229         ret = timer_of_init(np, to);
 230         if (ret < 0)
 231                 goto out;
 232
 233         timer_reg_base = timer_of_base(to);
 234
 235         /*
 236          * Configure microsecond timers to have 1MHz clock
 237          * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
 238          * Uses n+1 scheme
 239          */
 240         switch (timer_of_rate(to)) {
 241         case 12000000:
 242                 usec_config = 0x000b; /* (11+1)/(0+1) */
 243                 break;
 244         case 12800000:
 245                 usec_config = 0x043f; /* (63+1)/(4+1) */
 246                 break;
 247         case 13000000:
 248                 usec_config = 0x000c; /* (12+1)/(0+1) */
 249                 break;
 250         case 16800000:
 251                 usec_config = 0x0453; /* (83+1)/(4+1) */
 252                 break;
 253         case 19200000:
 254                 usec_config = 0x045f; /* (95+1)/(4+1) */
 255                 break;
 256         case 26000000:
 257                 usec_config = 0x0019; /* (25+1)/(0+1) */
 258                 break;
 259         case 38400000:
 260                 usec_config = 0x04bf; /* (191+1)/(4+1) */
 261                 break;
 262         case 48000000:
 263                 usec_config = 0x002f; /* (47+1)/(0+1) */
 264                 break;
 265         default:
 266                 ret = -EINVAL;
 267                 goto out;
 268         }
 269
 270         writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG);
 271
 272 out:
 273         return ret;
 274 }
 275
 276 #ifdef CONFIG_ARM64
 277 static int __init tegra_init_timer(struct device_node *np)
 278 {
 279         int cpu, ret = 0;
 280         struct timer_of *to;
 281
 282         to = this_cpu_ptr(&tegra_to);
 283         ret = tegra_timer_common_init(np, to);
 284         if (ret < 0)
 285                 goto out;
 286
 287         for_each_possible_cpu(cpu) {
 288                 struct timer_of *cpu_to;
 289
 290                 cpu_to = per_cpu_ptr(&tegra_to, cpu);
 291                 cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu);
 292                 cpu_to->of_clk.rate = timer_of_rate(to);
 293                 cpu_to->clkevt.cpumask = cpumask_of(cpu);
 294                 cpu_to->clkevt.irq =
 295                         irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu));
 296                 if (!cpu_to->clkevt.irq) {
 297                         pr_err("%s: can't map IRQ for CPU%d\n",
 298                                __func__, cpu);
 299                         ret = -EINVAL;
 300                         goto out;
 301                 }
 302
 303                 irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
 304                 ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
 305                                   IRQF_TIMER | IRQF_NOBALANCING,
 306                                   cpu_to->clkevt.name, &cpu_to->clkevt);
 307                 if (ret) {
 308                         pr_err("%s: cannot setup irq %d for CPU%d\n",
 309                                 __func__, cpu_to->clkevt.irq, cpu);
 310                         ret = -EINVAL;
 311                         goto out_irq;
 312                 }
 313         }
 314
 315         cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
 316                           "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
 317                           tegra_timer_stop);
 318
 319         return ret;
 320 out_irq:
 321         for_each_possible_cpu(cpu) {
 322                 struct timer_of *cpu_to;
 323
 324                 cpu_to = per_cpu_ptr(&tegra_to, cpu);
 325                 if (cpu_to->clkevt.irq) {
 326                         free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
 327                         irq_dispose_mapping(cpu_to->clkevt.irq);
 328                 }
 329         }
 330 out:
 331         timer_of_cleanup(to);
 332         return ret;
 333 }
 334 #else /* CONFIG_ARM */
 335 static int __init tegra_init_timer(struct device_node *np)
 336 {
 337         int ret = 0;
 338
 339         ret = tegra_timer_common_init(np, &tegra_to);
 340         if (ret < 0)
 341                 goto out;
 342
 343         tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0);
 344         tegra_to.of_clk.rate = 1000000; /* microsecond timer */
 345
 346         sched_clock_register(tegra_read_sched_clock, 32,
 347                              timer_of_rate(&tegra_to));
 348         ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
 349                                     "timer_us", timer_of_rate(&tegra_to),
 350                                     300, 32, clocksource_mmio_readl_up);
 351         if (ret) {
 352                 pr_err("Failed to register clocksource\n");
 353                 goto out;
 354         }
 355
 356         tegra_delay_timer.read_current_timer =
 357                         tegra_delay_timer_read_counter_long;
 358         tegra_delay_timer.freq = timer_of_rate(&tegra_to);
 359         register_current_timer_delay(&tegra_delay_timer);
 360
 361         clockevents_config_and_register(&tegra_to.clkevt,
 362                                         timer_of_rate(&tegra_to),
 363                                         0x1,
 364                                         0x1fffffff);
 365
 366         return ret;
 367 out:
 368         timer_of_cleanup(&tegra_to);
 369
 370         return ret;
 371 }
 372
 373 static int __init tegra20_init_rtc(struct device_node *np)
 374 {
 375         int ret;
 376
 377         ret = timer_of_init(np, &suspend_rtc_to);
 378         if (ret)
 379                 return ret;
 380
 381         clocksource_register_hz(&suspend_rtc_clocksource, 1000);
 382
 383         return 0;
 384 }
 385 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
 386 #endif
 387 TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer);
 388 TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer);