drivers/clocksource/timer-sp804.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  linux/drivers/clocksource/timer-sp.c
   4  *
   5  *  Copyright (C) 1999 - 2003 ARM Limited
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/clocksource.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_clk.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/sched_clock.h>
  20
  21 #include "timer-sp.h"
  22
  23 /* Hisilicon 64-bit timer(a variant of ARM SP804) */
  24 #define HISI_TIMER_1_BASE       0x00
  25 #define HISI_TIMER_2_BASE       0x40
  26 #define HISI_TIMER_LOAD         0x00
  27 #define HISI_TIMER_LOAD_H       0x04
  28 #define HISI_TIMER_VALUE        0x08
  29 #define HISI_TIMER_VALUE_H      0x0c
  30 #define HISI_TIMER_CTRL         0x10
  31 #define HISI_TIMER_INTCLR       0x14
  32 #define HISI_TIMER_RIS          0x18
  33 #define HISI_TIMER_MIS          0x1c
  34 #define HISI_TIMER_BGLOAD       0x20
  35 #define HISI_TIMER_BGLOAD_H     0x24
  36
  37
  38 struct sp804_timer __initdata arm_sp804_timer = {
  39         .load           = TIMER_LOAD,
  40         .value          = TIMER_VALUE,
  41         .ctrl           = TIMER_CTRL,
  42         .intclr         = TIMER_INTCLR,
  43         .timer_base     = {TIMER_1_BASE, TIMER_2_BASE},
  44         .width          = 32,
  45 };
  46
  47 struct sp804_timer __initdata hisi_sp804_timer = {
  48         .load           = HISI_TIMER_LOAD,
  49         .load_h         = HISI_TIMER_LOAD_H,
  50         .value          = HISI_TIMER_VALUE,
  51         .value_h        = HISI_TIMER_VALUE_H,
  52         .ctrl           = HISI_TIMER_CTRL,
  53         .intclr         = HISI_TIMER_INTCLR,
  54         .timer_base     = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE},
  55         .width          = 64,
  56 };
  57
  58 static struct sp804_clkevt sp804_clkevt[NR_TIMERS];
  59
  60 static long __init sp804_get_clock_rate(struct clk *clk, const char *name)
  61 {
  62         long rate;
  63         int err;
  64
  65         if (!clk)
  66                 clk = clk_get_sys("sp804", name);
  67         if (IS_ERR(clk)) {
  68                 pr_err("sp804: %s clock not found: %ld\n", name, PTR_ERR(clk));
  69                 return PTR_ERR(clk);
  70         }
  71
  72         err = clk_prepare(clk);
  73         if (err) {
  74                 pr_err("sp804: clock failed to prepare: %d\n", err);
  75                 clk_put(clk);
  76                 return err;
  77         }
  78
  79         err = clk_enable(clk);
  80         if (err) {
  81                 pr_err("sp804: clock failed to enable: %d\n", err);
  82                 clk_unprepare(clk);
  83                 clk_put(clk);
  84                 return err;
  85         }
  86
  87         rate = clk_get_rate(clk);
  88         if (rate < 0) {
  89                 pr_err("sp804: clock failed to get rate: %ld\n", rate);
  90                 clk_disable(clk);
  91                 clk_unprepare(clk);
  92                 clk_put(clk);
  93         }
  94
  95         return rate;
  96 }
  97
  98 static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base)
  99 {
 100         int i;
 101
 102         for (i = 0; i < NR_TIMERS; i++) {
 103                 if (sp804_clkevt[i].base == base)
 104                         return &sp804_clkevt[i];
 105         }
 106
 107         /* It's impossible to reach here */
 108         WARN_ON(1);
 109
 110         return NULL;
 111 }
 112
 113 static struct sp804_clkevt *sched_clkevt;
 114
 115 static u64 notrace sp804_read(void)
 116 {
 117         return ~readl_relaxed(sched_clkevt->value);
 118 }
 119
 120 int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
 121                                                   const char *name,
 122                                                   struct clk *clk,
 123                                                   int use_sched_clock)
 124 {
 125         long rate;
 126         struct sp804_clkevt *clkevt;
 127
 128         rate = sp804_get_clock_rate(clk, name);
 129         if (rate < 0)
 130                 return -EINVAL;
 131
 132         clkevt = sp804_clkevt_get(base);
 133
 134         writel(0, clkevt->ctrl);
 135         writel(0xffffffff, clkevt->load);
 136         writel(0xffffffff, clkevt->value);
 137         if (clkevt->width == 64) {
 138                 writel(0xffffffff, clkevt->load_h);
 139                 writel(0xffffffff, clkevt->value_h);
 140         }
 141         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 142                 clkevt->ctrl);
 143
 144         clocksource_mmio_init(clkevt->value, name,
 145                 rate, 200, 32, clocksource_mmio_readl_down);
 146
 147         if (use_sched_clock) {
 148                 sched_clkevt = clkevt;
 149                 sched_clock_register(sp804_read, 32, rate);
 150         }
 151
 152         return 0;
 153 }
 154
 155
 156 static struct sp804_clkevt *common_clkevt;
 157
 158 /*
 159  * IRQ handler for the timer
 160  */
 161 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
 162 {
 163         struct clock_event_device *evt = dev_id;
 164
 165         /* clear the interrupt */
 166         writel(1, common_clkevt->intclr);
 167
 168         evt->event_handler(evt);
 169
 170         return IRQ_HANDLED;
 171 }
 172
 173 static inline void timer_shutdown(struct clock_event_device *evt)
 174 {
 175         writel(0, common_clkevt->ctrl);
 176 }
 177
 178 static int sp804_shutdown(struct clock_event_device *evt)
 179 {
 180         timer_shutdown(evt);
 181         return 0;
 182 }
 183
 184 static int sp804_set_periodic(struct clock_event_device *evt)
 185 {
 186         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 187                              TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 188
 189         timer_shutdown(evt);
 190         writel(common_clkevt->reload, common_clkevt->load);
 191         writel(ctrl, common_clkevt->ctrl);
 192         return 0;
 193 }
 194
 195 static int sp804_set_next_event(unsigned long next,
 196         struct clock_event_device *evt)
 197 {
 198         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 199                              TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;
 200
 201         writel(next, common_clkevt->load);
 202         writel(ctrl, common_clkevt->ctrl);
 203
 204         return 0;
 205 }
 206
 207 static struct clock_event_device sp804_clockevent = {
 208         .features               = CLOCK_EVT_FEAT_PERIODIC |
 209                                   CLOCK_EVT_FEAT_ONESHOT |
 210                                   CLOCK_EVT_FEAT_DYNIRQ,
 211         .set_state_shutdown     = sp804_shutdown,
 212         .set_state_periodic     = sp804_set_periodic,
 213         .set_state_oneshot      = sp804_shutdown,
 214         .tick_resume            = sp804_shutdown,
 215         .set_next_event         = sp804_set_next_event,
 216         .rating                 = 300,
 217 };
 218
 219 int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
 220                                   struct clk *clk, const char *name)
 221 {
 222         struct clock_event_device *evt = &sp804_clockevent;
 223         long rate;
 224
 225         rate = sp804_get_clock_rate(clk, name);
 226         if (rate < 0)
 227                 return -EINVAL;
 228
 229         common_clkevt = sp804_clkevt_get(base);
 230         common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ);
 231         evt->name = name;
 232         evt->irq = irq;
 233         evt->cpumask = cpu_possible_mask;
 234
 235         writel(0, common_clkevt->ctrl);
 236
 237         if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
 238                         "timer", &sp804_clockevent))
 239                 pr_err("%s: request_irq() failed\n", "timer");
 240         clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
 241
 242         return 0;
 243 }
 244
 245 static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base)
 246 {
 247         int i;
 248
 249         for (i = 0; i < NR_TIMERS; i++) {
 250                 void __iomem *timer_base;
 251                 struct sp804_clkevt *clkevt;
 252
 253                 timer_base = base + timer->timer_base[i];
 254                 clkevt = &sp804_clkevt[i];
 255                 clkevt->base    = timer_base;
 256                 clkevt->load    = timer_base + timer->load;
 257                 clkevt->load_h  = timer_base + timer->load_h;
 258                 clkevt->value   = timer_base + timer->value;
 259                 clkevt->value_h = timer_base + timer->value_h;
 260                 clkevt->ctrl    = timer_base + timer->ctrl;
 261                 clkevt->intclr  = timer_base + timer->intclr;
 262                 clkevt->width   = timer->width;
 263         }
 264 }
 265
 266 static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer)
 267 {
 268         static bool initialized = false;
 269         void __iomem *base;
 270         void __iomem *timer1_base;
 271         void __iomem *timer2_base;
 272         int irq, ret = -EINVAL;
 273         u32 irq_num = 0;
 274         struct clk *clk1, *clk2;
 275         const char *name = of_get_property(np, "compatible", NULL);
 276
 277         base = of_iomap(np, 0);
 278         if (!base)
 279                 return -ENXIO;
 280
 281         timer1_base = base + timer->timer_base[0];
 282         timer2_base = base + timer->timer_base[1];
 283
 284         /* Ensure timers are disabled */
 285         writel(0, timer1_base + timer->ctrl);
 286         writel(0, timer2_base + timer->ctrl);
 287
 288         if (initialized || !of_device_is_available(np)) {
 289                 ret = -EINVAL;
 290                 goto err;
 291         }
 292
 293         clk1 = of_clk_get(np, 0);
 294         if (IS_ERR(clk1))
 295                 clk1 = NULL;
 296
 297         /* Get the 2nd clock if the timer has 3 timer clocks */
 298         if (of_clk_get_parent_count(np) == 3) {
 299                 clk2 = of_clk_get(np, 1);
 300                 if (IS_ERR(clk2)) {
 301                         pr_err("sp804: %pOFn clock not found: %d\n", np,
 302                                 (int)PTR_ERR(clk2));
 303                         clk2 = NULL;
 304                 }
 305         } else
 306                 clk2 = clk1;
 307
 308         irq = irq_of_parse_and_map(np, 0);
 309         if (irq <= 0)
 310                 goto err;
 311
 312         sp804_clkevt_init(timer, base);
 313
 314         of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
 315         if (irq_num == 2) {
 316
 317                 ret = sp804_clockevents_init(timer2_base, irq, clk2, name);
 318                 if (ret)
 319                         goto err;
 320
 321                 ret = sp804_clocksource_and_sched_clock_init(timer1_base,
 322                                                              name, clk1, 1);
 323                 if (ret)
 324                         goto err;
 325         } else {
 326
 327                 ret = sp804_clockevents_init(timer1_base, irq, clk1, name);
 328                 if (ret)
 329                         goto err;
 330
 331                 ret = sp804_clocksource_and_sched_clock_init(timer2_base,
 332                                                              name, clk2, 1);
 333                 if (ret)
 334                         goto err;
 335         }
 336         initialized = true;
 337
 338         return 0;
 339 err:
 340         iounmap(base);
 341         return ret;
 342 }
 343
 344 static int __init arm_sp804_of_init(struct device_node *np)
 345 {
 346         return sp804_of_init(np, &arm_sp804_timer);
 347 }
 348 TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init);
 349
 350 static int __init hisi_sp804_of_init(struct device_node *np)
 351 {
 352         return sp804_of_init(np, &hisi_sp804_timer);
 353 }
 354 TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init);
 355
 356 static int __init integrator_cp_of_init(struct device_node *np)
 357 {
 358         static int init_count = 0;
 359         void __iomem *base;
 360         int irq, ret = -EINVAL;
 361         const char *name = of_get_property(np, "compatible", NULL);
 362         struct clk *clk;
 363
 364         base = of_iomap(np, 0);
 365         if (!base) {
 366                 pr_err("Failed to iomap\n");
 367                 return -ENXIO;
 368         }
 369
 370         clk = of_clk_get(np, 0);
 371         if (IS_ERR(clk)) {
 372                 pr_err("Failed to get clock\n");
 373                 return PTR_ERR(clk);
 374         }
 375
 376         /* Ensure timer is disabled */
 377         writel(0, base + arm_sp804_timer.ctrl);
 378
 379         if (init_count == 2 || !of_device_is_available(np))
 380                 goto err;
 381
 382         sp804_clkevt_init(&arm_sp804_timer, base);
 383
 384         if (!init_count) {
 385                 ret = sp804_clocksource_and_sched_clock_init(base,
 386                                                              name, clk, 0);
 387                 if (ret)
 388                         goto err;
 389         } else {
 390                 irq = irq_of_parse_and_map(np, 0);
 391                 if (irq <= 0)
 392                         goto err;
 393
 394                 ret = sp804_clockevents_init(base, irq, clk, name);
 395                 if (ret)
 396                         goto err;
 397         }
 398
 399         init_count++;
 400         return 0;
 401 err:
 402         iounmap(base);
 403         return ret;
 404 }
 405 TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);