drivers/clocksource/sh_cmt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SuperH Timer Support - CMT
   4  *
   5  *  Copyright (C) 2008 Magnus Damm
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clockchips.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <linux/irq.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/sh_timer.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27
  28 #ifdef CONFIG_SUPERH
  29 #include <asm/platform_early.h>
  30 #endif
  31
  32 struct sh_cmt_device;
  33
  34 /*
  35  * The CMT comes in 5 different identified flavours, depending not only on the
  36  * SoC but also on the particular instance. The following table lists the main
  37  * characteristics of those flavours.
  38  *
  39  *                      16B     32B     32B-F   48B     R-Car Gen2
  40  * -----------------------------------------------------------------------------
  41  * Channels             2       1/4     1       6       2/8
  42  * Control Width        16      16      16      16      32
  43  * Counter Width        16      32      32      32/48   32/48
  44  * Shared Start/Stop    Y       Y       Y       Y       N
  45  *
  46  * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
  47  * located in the channel registers block. All other versions have a shared
  48  * start/stop register located in the global space.
  49  *
  50  * Channels are indexed from 0 to N-1 in the documentation. The channel index
  51  * infers the start/stop bit position in the control register and the channel
  52  * registers block address. Some CMT instances have a subset of channels
  53  * available, in which case the index in the documentation doesn't match the
  54  * "real" index as implemented in hardware. This is for instance the case with
  55  * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
  56  * in the documentation but using start/stop bit 5 and having its registers
  57  * block at 0x60.
  58  *
  59  * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
  60  * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
  61  */
  62
  63 enum sh_cmt_model {
  64         SH_CMT_16BIT,
  65         SH_CMT_32BIT,
  66         SH_CMT_48BIT,
  67         SH_CMT0_RCAR_GEN2,
  68         SH_CMT1_RCAR_GEN2,
  69 };
  70
  71 struct sh_cmt_info {
  72         enum sh_cmt_model model;
  73
  74         unsigned int channels_mask;
  75
  76         unsigned long width; /* 16 or 32 bit version of hardware block */
  77         u32 overflow_bit;
  78         u32 clear_bits;
  79
  80         /* callbacks for CMSTR and CMCSR access */
  81         u32 (*read_control)(void __iomem *base, unsigned long offs);
  82         void (*write_control)(void __iomem *base, unsigned long offs,
  83                               u32 value);
  84
  85         /* callbacks for CMCNT and CMCOR access */
  86         u32 (*read_count)(void __iomem *base, unsigned long offs);
  87         void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
  88 };
  89
  90 struct sh_cmt_channel {
  91         struct sh_cmt_device *cmt;
  92
  93         unsigned int index;     /* Index in the documentation */
  94         unsigned int hwidx;     /* Real hardware index */
  95
  96         void __iomem *iostart;
  97         void __iomem *ioctrl;
  98
  99         unsigned int timer_bit;
 100         unsigned long flags;
 101         u32 match_value;
 102         u32 next_match_value;
 103         u32 max_match_value;
 104         raw_spinlock_t lock;
 105         struct clock_event_device ced;
 106         struct clocksource cs;
 107         u64 total_cycles;
 108         bool cs_enabled;
 109 };
 110
 111 struct sh_cmt_device {
 112         struct platform_device *pdev;
 113
 114         const struct sh_cmt_info *info;
 115
 116         void __iomem *mapbase;
 117         struct clk *clk;
 118         unsigned long rate;
 119
 120         raw_spinlock_t lock; /* Protect the shared start/stop register */
 121
 122         struct sh_cmt_channel *channels;
 123         unsigned int num_channels;
 124         unsigned int hw_channels;
 125
 126         bool has_clockevent;
 127         bool has_clocksource;
 128 };
 129
 130 #define SH_CMT16_CMCSR_CMF              (1 << 7)
 131 #define SH_CMT16_CMCSR_CMIE             (1 << 6)
 132 #define SH_CMT16_CMCSR_CKS8             (0 << 0)
 133 #define SH_CMT16_CMCSR_CKS32            (1 << 0)
 134 #define SH_CMT16_CMCSR_CKS128           (2 << 0)
 135 #define SH_CMT16_CMCSR_CKS512           (3 << 0)
 136 #define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
 137
 138 #define SH_CMT32_CMCSR_CMF              (1 << 15)
 139 #define SH_CMT32_CMCSR_OVF              (1 << 14)
 140 #define SH_CMT32_CMCSR_WRFLG            (1 << 13)
 141 #define SH_CMT32_CMCSR_STTF             (1 << 12)
 142 #define SH_CMT32_CMCSR_STPF             (1 << 11)
 143 #define SH_CMT32_CMCSR_SSIE             (1 << 10)
 144 #define SH_CMT32_CMCSR_CMS              (1 << 9)
 145 #define SH_CMT32_CMCSR_CMM              (1 << 8)
 146 #define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
 147 #define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
 148 #define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
 149 #define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)
 150 #define SH_CMT32_CMCSR_CMR_MASK         (3 << 4)
 151 #define SH_CMT32_CMCSR_DBGIVD           (1 << 3)
 152 #define SH_CMT32_CMCSR_CKS_RCLK8        (4 << 0)
 153 #define SH_CMT32_CMCSR_CKS_RCLK32       (5 << 0)
 154 #define SH_CMT32_CMCSR_CKS_RCLK128      (6 << 0)
 155 #define SH_CMT32_CMCSR_CKS_RCLK1        (7 << 0)
 156 #define SH_CMT32_CMCSR_CKS_MASK         (7 << 0)
 157
 158 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
 159 {
 160         return ioread16(base + (offs << 1));
 161 }
 162
 163 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
 164 {
 165         return ioread32(base + (offs << 2));
 166 }
 167
 168 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
 169 {
 170         iowrite16(value, base + (offs << 1));
 171 }
 172
 173 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
 174 {
 175         iowrite32(value, base + (offs << 2));
 176 }
 177
 178 static const struct sh_cmt_info sh_cmt_info[] = {
 179         [SH_CMT_16BIT] = {
 180                 .model = SH_CMT_16BIT,
 181                 .width = 16,
 182                 .overflow_bit = SH_CMT16_CMCSR_CMF,
 183                 .clear_bits = ~SH_CMT16_CMCSR_CMF,
 184                 .read_control = sh_cmt_read16,
 185                 .write_control = sh_cmt_write16,
 186                 .read_count = sh_cmt_read16,
 187                 .write_count = sh_cmt_write16,
 188         },
 189         [SH_CMT_32BIT] = {
 190                 .model = SH_CMT_32BIT,
 191                 .width = 32,
 192                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 193                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 194                 .read_control = sh_cmt_read16,
 195                 .write_control = sh_cmt_write16,
 196                 .read_count = sh_cmt_read32,
 197                 .write_count = sh_cmt_write32,
 198         },
 199         [SH_CMT_48BIT] = {
 200                 .model = SH_CMT_48BIT,
 201                 .channels_mask = 0x3f,
 202                 .width = 32,
 203                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 204                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 205                 .read_control = sh_cmt_read32,
 206                 .write_control = sh_cmt_write32,
 207                 .read_count = sh_cmt_read32,
 208                 .write_count = sh_cmt_write32,
 209         },
 210         [SH_CMT0_RCAR_GEN2] = {
 211                 .model = SH_CMT0_RCAR_GEN2,
 212                 .channels_mask = 0x60,
 213                 .width = 32,
 214                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 215                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 216                 .read_control = sh_cmt_read32,
 217                 .write_control = sh_cmt_write32,
 218                 .read_count = sh_cmt_read32,
 219                 .write_count = sh_cmt_write32,
 220         },
 221         [SH_CMT1_RCAR_GEN2] = {
 222                 .model = SH_CMT1_RCAR_GEN2,
 223                 .channels_mask = 0xff,
 224                 .width = 32,
 225                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 226                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 227                 .read_control = sh_cmt_read32,
 228                 .write_control = sh_cmt_write32,
 229                 .read_count = sh_cmt_read32,
 230                 .write_count = sh_cmt_write32,
 231         },
 232 };
 233
 234 #define CMCSR 0 /* channel register */
 235 #define CMCNT 1 /* channel register */
 236 #define CMCOR 2 /* channel register */
 237
 238 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 239 {
 240         if (ch->iostart)
 241                 return ch->cmt->info->read_control(ch->iostart, 0);
 242         else
 243                 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
 244 }
 245
 246 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
 247 {
 248         if (ch->iostart)
 249                 ch->cmt->info->write_control(ch->iostart, 0, value);
 250         else
 251                 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
 252 }
 253
 254 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 255 {
 256         return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
 257 }
 258
 259 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
 260 {
 261         ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
 262 }
 263
 264 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 265 {
 266         return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
 267 }
 268
 269 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
 270 {
 271         ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
 272 }
 273
 274 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
 275 {
 276         ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
 277 }
 278
 279 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
 280 {
 281         u32 v1, v2, v3;
 282         u32 o1, o2;
 283
 284         o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 285
 286         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 287         do {
 288                 o2 = o1;
 289                 v1 = sh_cmt_read_cmcnt(ch);
 290                 v2 = sh_cmt_read_cmcnt(ch);
 291                 v3 = sh_cmt_read_cmcnt(ch);
 292                 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 293         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 294                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 295
 296         *has_wrapped = o1;
 297         return v2;
 298 }
 299
 300 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 301 {
 302         unsigned long flags;
 303         u32 value;
 304
 305         /* start stop register shared by multiple timer channels */
 306         raw_spin_lock_irqsave(&ch->cmt->lock, flags);
 307         value = sh_cmt_read_cmstr(ch);
 308
 309         if (start)
 310                 value |= 1 << ch->timer_bit;
 311         else
 312                 value &= ~(1 << ch->timer_bit);
 313
 314         sh_cmt_write_cmstr(ch, value);
 315         raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
 316 }
 317
 318 static int sh_cmt_enable(struct sh_cmt_channel *ch)
 319 {
 320         int k, ret;
 321
 322         dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 323
 324         /* enable clock */
 325         ret = clk_enable(ch->cmt->clk);
 326         if (ret) {
 327                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
 328                         ch->index);
 329                 goto err0;
 330         }
 331
 332         /* make sure channel is disabled */
 333         sh_cmt_start_stop_ch(ch, 0);
 334
 335         /* configure channel, periodic mode and maximum timeout */
 336         if (ch->cmt->info->width == 16) {
 337                 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
 338                                    SH_CMT16_CMCSR_CKS512);
 339         } else {
 340                 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
 341                                    SH_CMT32_CMCSR_CMTOUT_IE |
 342                                    SH_CMT32_CMCSR_CMR_IRQ |
 343                                    SH_CMT32_CMCSR_CKS_RCLK8);
 344         }
 345
 346         sh_cmt_write_cmcor(ch, 0xffffffff);
 347         sh_cmt_write_cmcnt(ch, 0);
 348
 349         /*
 350          * According to the sh73a0 user's manual, as CMCNT can be operated
 351          * only by the RCLK (Pseudo 32 kHz), there's one restriction on
 352          * modifying CMCNT register; two RCLK cycles are necessary before
 353          * this register is either read or any modification of the value
 354          * it holds is reflected in the LSI's actual operation.
 355          *
 356          * While at it, we're supposed to clear out the CMCNT as of this
 357          * moment, so make sure it's processed properly here.  This will
 358          * take RCLKx2 at maximum.
 359          */
 360         for (k = 0; k < 100; k++) {
 361                 if (!sh_cmt_read_cmcnt(ch))
 362                         break;
 363                 udelay(1);
 364         }
 365
 366         if (sh_cmt_read_cmcnt(ch)) {
 367                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
 368                         ch->index);
 369                 ret = -ETIMEDOUT;
 370                 goto err1;
 371         }
 372
 373         /* enable channel */
 374         sh_cmt_start_stop_ch(ch, 1);
 375         return 0;
 376  err1:
 377         /* stop clock */
 378         clk_disable(ch->cmt->clk);
 379
 380  err0:
 381         return ret;
 382 }
 383
 384 static void sh_cmt_disable(struct sh_cmt_channel *ch)
 385 {
 386         /* disable channel */
 387         sh_cmt_start_stop_ch(ch, 0);
 388
 389         /* disable interrupts in CMT block */
 390         sh_cmt_write_cmcsr(ch, 0);
 391
 392         /* stop clock */
 393         clk_disable(ch->cmt->clk);
 394
 395         dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 396 }
 397
 398 /* private flags */
 399 #define FLAG_CLOCKEVENT (1 << 0)
 400 #define FLAG_CLOCKSOURCE (1 << 1)
 401 #define FLAG_REPROGRAM (1 << 2)
 402 #define FLAG_SKIPEVENT (1 << 3)
 403 #define FLAG_IRQCONTEXT (1 << 4)
 404
 405 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 406                                               int absolute)
 407 {
 408         u32 value = ch->next_match_value;
 409         u32 new_match;
 410         u32 delay = 0;
 411         u32 now = 0;
 412         u32 has_wrapped;
 413
 414         now = sh_cmt_get_counter(ch, &has_wrapped);
 415         ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 416
 417         if (has_wrapped) {
 418                 /* we're competing with the interrupt handler.
 419                  *  -> let the interrupt handler reprogram the timer.
 420                  *  -> interrupt number two handles the event.
 421                  */
 422                 ch->flags |= FLAG_SKIPEVENT;
 423                 return;
 424         }
 425
 426         if (absolute)
 427                 now = 0;
 428
 429         do {
 430                 /* reprogram the timer hardware,
 431                  * but don't save the new match value yet.
 432                  */
 433                 new_match = now + value + delay;
 434                 if (new_match > ch->max_match_value)
 435                         new_match = ch->max_match_value;
 436
 437                 sh_cmt_write_cmcor(ch, new_match);
 438
 439                 now = sh_cmt_get_counter(ch, &has_wrapped);
 440                 if (has_wrapped && (new_match > ch->match_value)) {
 441                         /* we are changing to a greater match value,
 442                          * so this wrap must be caused by the counter
 443                          * matching the old value.
 444                          * -> first interrupt reprograms the timer.
 445                          * -> interrupt number two handles the event.
 446                          */
 447                         ch->flags |= FLAG_SKIPEVENT;
 448                         break;
 449                 }
 450
 451                 if (has_wrapped) {
 452                         /* we are changing to a smaller match value,
 453                          * so the wrap must be caused by the counter
 454                          * matching the new value.
 455                          * -> save programmed match value.
 456                          * -> let isr handle the event.
 457                          */
 458                         ch->match_value = new_match;
 459                         break;
 460                 }
 461
 462                 /* be safe: verify hardware settings */
 463                 if (now < new_match) {
 464                         /* timer value is below match value, all good.
 465                          * this makes sure we won't miss any match events.
 466                          * -> save programmed match value.
 467                          * -> let isr handle the event.
 468                          */
 469                         ch->match_value = new_match;
 470                         break;
 471                 }
 472
 473                 /* the counter has reached a value greater
 474                  * than our new match value. and since the
 475                  * has_wrapped flag isn't set we must have
 476                  * programmed a too close event.
 477                  * -> increase delay and retry.
 478                  */
 479                 if (delay)
 480                         delay <<= 1;
 481                 else
 482                         delay = 1;
 483
 484                 if (!delay)
 485                         dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
 486                                  ch->index);
 487
 488         } while (delay);
 489 }
 490
 491 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 492 {
 493         if (delta > ch->max_match_value)
 494                 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
 495                          ch->index);
 496
 497         ch->next_match_value = delta;
 498         sh_cmt_clock_event_program_verify(ch, 0);
 499 }
 500
 501 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 502 {
 503         unsigned long flags;
 504
 505         raw_spin_lock_irqsave(&ch->lock, flags);
 506         __sh_cmt_set_next(ch, delta);
 507         raw_spin_unlock_irqrestore(&ch->lock, flags);
 508 }
 509
 510 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 511 {
 512         struct sh_cmt_channel *ch = dev_id;
 513
 514         /* clear flags */
 515         sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
 516                            ch->cmt->info->clear_bits);
 517
 518         /* update clock source counter to begin with if enabled
 519          * the wrap flag should be cleared by the timer specific
 520          * isr before we end up here.
 521          */
 522         if (ch->flags & FLAG_CLOCKSOURCE)
 523                 ch->total_cycles += ch->match_value + 1;
 524
 525         if (!(ch->flags & FLAG_REPROGRAM))
 526                 ch->next_match_value = ch->max_match_value;
 527
 528         ch->flags |= FLAG_IRQCONTEXT;
 529
 530         if (ch->flags & FLAG_CLOCKEVENT) {
 531                 if (!(ch->flags & FLAG_SKIPEVENT)) {
 532                         if (clockevent_state_oneshot(&ch->ced)) {
 533                                 ch->next_match_value = ch->max_match_value;
 534                                 ch->flags |= FLAG_REPROGRAM;
 535                         }
 536
 537                         ch->ced.event_handler(&ch->ced);
 538                 }
 539         }
 540
 541         ch->flags &= ~FLAG_SKIPEVENT;
 542
 543         if (ch->flags & FLAG_REPROGRAM) {
 544                 ch->flags &= ~FLAG_REPROGRAM;
 545                 sh_cmt_clock_event_program_verify(ch, 1);
 546
 547                 if (ch->flags & FLAG_CLOCKEVENT)
 548                         if ((clockevent_state_shutdown(&ch->ced))
 549                             || (ch->match_value == ch->next_match_value))
 550                                 ch->flags &= ~FLAG_REPROGRAM;
 551         }
 552
 553         ch->flags &= ~FLAG_IRQCONTEXT;
 554
 555         return IRQ_HANDLED;
 556 }
 557
 558 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 559 {
 560         int ret = 0;
 561         unsigned long flags;
 562
 563         if (flag & FLAG_CLOCKSOURCE)
 564                 pm_runtime_get_sync(&ch->cmt->pdev->dev);
 565
 566         raw_spin_lock_irqsave(&ch->lock, flags);
 567
 568         if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
 569                 if (flag & FLAG_CLOCKEVENT)
 570                         pm_runtime_get_sync(&ch->cmt->pdev->dev);
 571                 ret = sh_cmt_enable(ch);
 572         }
 573
 574         if (ret)
 575                 goto out;
 576         ch->flags |= flag;
 577
 578         /* setup timeout if no clockevent */
 579         if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
 580                 __sh_cmt_set_next(ch, ch->max_match_value);
 581  out:
 582         raw_spin_unlock_irqrestore(&ch->lock, flags);
 583
 584         return ret;
 585 }
 586
 587 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 588 {
 589         unsigned long flags;
 590         unsigned long f;
 591
 592         raw_spin_lock_irqsave(&ch->lock, flags);
 593
 594         f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 595         ch->flags &= ~flag;
 596
 597         if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
 598                 sh_cmt_disable(ch);
 599                 if (flag & FLAG_CLOCKEVENT)
 600                         pm_runtime_put(&ch->cmt->pdev->dev);
 601         }
 602
 603         /* adjust the timeout to maximum if only clocksource left */
 604         if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 605                 __sh_cmt_set_next(ch, ch->max_match_value);
 606
 607         raw_spin_unlock_irqrestore(&ch->lock, flags);
 608
 609         if (flag & FLAG_CLOCKSOURCE)
 610                 pm_runtime_put(&ch->cmt->pdev->dev);
 611 }
 612
 613 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 614 {
 615         return container_of(cs, struct sh_cmt_channel, cs);
 616 }
 617
 618 static u64 sh_cmt_clocksource_read(struct clocksource *cs)
 619 {
 620         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 621         unsigned long flags;
 622         u32 has_wrapped;
 623         u64 value;
 624         u32 raw;
 625
 626         raw_spin_lock_irqsave(&ch->lock, flags);
 627         value = ch->total_cycles;
 628         raw = sh_cmt_get_counter(ch, &has_wrapped);
 629
 630         if (unlikely(has_wrapped))
 631                 raw += ch->match_value + 1;
 632         raw_spin_unlock_irqrestore(&ch->lock, flags);
 633
 634         return value + raw;
 635 }
 636
 637 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 638 {
 639         int ret;
 640         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 641
 642         WARN_ON(ch->cs_enabled);
 643
 644         ch->total_cycles = 0;
 645
 646         ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 647         if (!ret)
 648                 ch->cs_enabled = true;
 649
 650         return ret;
 651 }
 652
 653 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 654 {
 655         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 656
 657         WARN_ON(!ch->cs_enabled);
 658
 659         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 660         ch->cs_enabled = false;
 661 }
 662
 663 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 664 {
 665         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 666
 667         if (!ch->cs_enabled)
 668                 return;
 669
 670         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 671         dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
 672 }
 673
 674 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 675 {
 676         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 677
 678         if (!ch->cs_enabled)
 679                 return;
 680
 681         dev_pm_genpd_resume(&ch->cmt->pdev->dev);
 682         sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 683 }
 684
 685 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 686                                        const char *name)
 687 {
 688         struct clocksource *cs = &ch->cs;
 689
 690         cs->name = name;
 691         cs->rating = 125;
 692         cs->read = sh_cmt_clocksource_read;
 693         cs->enable = sh_cmt_clocksource_enable;
 694         cs->disable = sh_cmt_clocksource_disable;
 695         cs->suspend = sh_cmt_clocksource_suspend;
 696         cs->resume = sh_cmt_clocksource_resume;
 697         cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8);
 698         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 699
 700         dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
 701                  ch->index);
 702
 703         clocksource_register_hz(cs, ch->cmt->rate);
 704         return 0;
 705 }
 706
 707 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 708 {
 709         return container_of(ced, struct sh_cmt_channel, ced);
 710 }
 711
 712 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 713 {
 714         sh_cmt_start(ch, FLAG_CLOCKEVENT);
 715
 716         if (periodic)
 717                 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
 718         else
 719                 sh_cmt_set_next(ch, ch->max_match_value);
 720 }
 721
 722 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
 723 {
 724         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 725
 726         sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 727         return 0;
 728 }
 729
 730 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
 731                                         int periodic)
 732 {
 733         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 734
 735         /* deal with old setting first */
 736         if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
 737                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 738
 739         dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
 740                  ch->index, periodic ? "periodic" : "oneshot");
 741         sh_cmt_clock_event_start(ch, periodic);
 742         return 0;
 743 }
 744
 745 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
 746 {
 747         return sh_cmt_clock_event_set_state(ced, 0);
 748 }
 749
 750 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
 751 {
 752         return sh_cmt_clock_event_set_state(ced, 1);
 753 }
 754
 755 static int sh_cmt_clock_event_next(unsigned long delta,
 756                                    struct clock_event_device *ced)
 757 {
 758         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 759
 760         BUG_ON(!clockevent_state_oneshot(ced));
 761         if (likely(ch->flags & FLAG_IRQCONTEXT))
 762                 ch->next_match_value = delta - 1;
 763         else
 764                 sh_cmt_set_next(ch, delta - 1);
 765
 766         return 0;
 767 }
 768
 769 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 770 {
 771         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 772
 773         dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
 774         clk_unprepare(ch->cmt->clk);
 775 }
 776
 777 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 778 {
 779         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 780
 781         clk_prepare(ch->cmt->clk);
 782         dev_pm_genpd_resume(&ch->cmt->pdev->dev);
 783 }
 784
 785 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 786                                       const char *name)
 787 {
 788         struct clock_event_device *ced = &ch->ced;
 789         int irq;
 790         int ret;
 791
 792         irq = platform_get_irq(ch->cmt->pdev, ch->index);
 793         if (irq < 0)
 794                 return irq;
 795
 796         ret = request_irq(irq, sh_cmt_interrupt,
 797                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 798                           dev_name(&ch->cmt->pdev->dev), ch);
 799         if (ret) {
 800                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
 801                         ch->index, irq);
 802                 return ret;
 803         }
 804
 805         ced->name = name;
 806         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 807         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 808         ced->rating = 125;
 809         ced->cpumask = cpu_possible_mask;
 810         ced->set_next_event = sh_cmt_clock_event_next;
 811         ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
 812         ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
 813         ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
 814         ced->suspend = sh_cmt_clock_event_suspend;
 815         ced->resume = sh_cmt_clock_event_resume;
 816
 817         /* TODO: calculate good shift from rate and counter bit width */
 818         ced->shift = 32;
 819         ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
 820         ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 821         ced->max_delta_ticks = ch->max_match_value;
 822         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 823         ced->min_delta_ticks = 0x1f;
 824
 825         dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
 826                  ch->index);
 827         clockevents_register_device(ced);
 828
 829         return 0;
 830 }
 831
 832 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
 833                            bool clockevent, bool clocksource)
 834 {
 835         int ret;
 836
 837         if (clockevent) {
 838                 ch->cmt->has_clockevent = true;
 839                 ret = sh_cmt_register_clockevent(ch, name);
 840                 if (ret < 0)
 841                         return ret;
 842         }
 843
 844         if (clocksource) {
 845                 ch->cmt->has_clocksource = true;
 846                 sh_cmt_register_clocksource(ch, name);
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
 853                                 unsigned int hwidx, bool clockevent,
 854                                 bool clocksource, struct sh_cmt_device *cmt)
 855 {
 856         int ret;
 857
 858         /* Skip unused channels. */
 859         if (!clockevent && !clocksource)
 860                 return 0;
 861
 862         ch->cmt = cmt;
 863         ch->index = index;
 864         ch->hwidx = hwidx;
 865         ch->timer_bit = hwidx;
 866
 867         /*
 868          * Compute the address of the channel control register block. For the
 869          * timers with a per-channel start/stop register, compute its address
 870          * as well.
 871          */
 872         switch (cmt->info->model) {
 873         case SH_CMT_16BIT:
 874                 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
 875                 break;
 876         case SH_CMT_32BIT:
 877         case SH_CMT_48BIT:
 878                 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
 879                 break;
 880         case SH_CMT0_RCAR_GEN2:
 881         case SH_CMT1_RCAR_GEN2:
 882                 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
 883                 ch->ioctrl = ch->iostart + 0x10;
 884                 ch->timer_bit = 0;
 885                 break;
 886         }
 887
 888         if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
 889                 ch->max_match_value = ~0;
 890         else
 891                 ch->max_match_value = (1 << cmt->info->width) - 1;
 892
 893         ch->match_value = ch->max_match_value;
 894         raw_spin_lock_init(&ch->lock);
 895
 896         ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
 897                               clockevent, clocksource);
 898         if (ret) {
 899                 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
 900                         ch->index);
 901                 return ret;
 902         }
 903         ch->cs_enabled = false;
 904
 905         return 0;
 906 }
 907
 908 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
 909 {
 910         struct resource *mem;
 911
 912         mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 913         if (!mem) {
 914                 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 915                 return -ENXIO;
 916         }
 917
 918         cmt->mapbase = ioremap(mem->start, resource_size(mem));
 919         if (cmt->mapbase == NULL) {
 920                 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 921                 return -ENXIO;
 922         }
 923
 924         return 0;
 925 }
 926
 927 static const struct platform_device_id sh_cmt_id_table[] = {
 928         { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
 929         { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
 930         { }
 931 };
 932 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
 933
 934 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
 935         {
 936                 /* deprecated, preserved for backward compatibility */
 937                 .compatible = "renesas,cmt-48",
 938                 .data = &sh_cmt_info[SH_CMT_48BIT]
 939         },
 940         {
 941                 /* deprecated, preserved for backward compatibility */
 942                 .compatible = "renesas,cmt-48-gen2",
 943                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 944         },
 945         {
 946                 .compatible = "renesas,r8a7740-cmt1",
 947                 .data = &sh_cmt_info[SH_CMT_48BIT]
 948         },
 949         {
 950                 .compatible = "renesas,sh73a0-cmt1",
 951                 .data = &sh_cmt_info[SH_CMT_48BIT]
 952         },
 953         {
 954                 .compatible = "renesas,rcar-gen2-cmt0",
 955                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 956         },
 957         {
 958                 .compatible = "renesas,rcar-gen2-cmt1",
 959                 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 960         },
 961         {
 962                 .compatible = "renesas,rcar-gen3-cmt0",
 963                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 964         },
 965         {
 966                 .compatible = "renesas,rcar-gen3-cmt1",
 967                 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 968         },
 969         { }
 970 };
 971 MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
 972
 973 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 974 {
 975         unsigned int mask;
 976         unsigned int i;
 977         int ret;
 978
 979         cmt->pdev = pdev;
 980         raw_spin_lock_init(&cmt->lock);
 981
 982         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
 983                 cmt->info = of_device_get_match_data(&pdev->dev);
 984                 cmt->hw_channels = cmt->info->channels_mask;
 985         } else if (pdev->dev.platform_data) {
 986                 struct sh_timer_config *cfg = pdev->dev.platform_data;
 987                 const struct platform_device_id *id = pdev->id_entry;
 988
 989                 cmt->info = (const struct sh_cmt_info *)id->driver_data;
 990                 cmt->hw_channels = cfg->channels_mask;
 991         } else {
 992                 dev_err(&cmt->pdev->dev, "missing platform data\n");
 993                 return -ENXIO;
 994         }
 995
 996         /* Get hold of clock. */
 997         cmt->clk = clk_get(&cmt->pdev->dev, "fck");
 998         if (IS_ERR(cmt->clk)) {
 999                 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1000                 return PTR_ERR(cmt->clk);
1001         }
1002
1003         ret = clk_prepare(cmt->clk);
1004         if (ret < 0)
1005                 goto err_clk_put;
1006
1007         /* Determine clock rate. */
1008         ret = clk_enable(cmt->clk);
1009         if (ret < 0)
1010                 goto err_clk_unprepare;
1011
1012         if (cmt->info->width == 16)
1013                 cmt->rate = clk_get_rate(cmt->clk) / 512;
1014         else
1015                 cmt->rate = clk_get_rate(cmt->clk) / 8;
1016
1017         clk_disable(cmt->clk);
1018
1019         /* Map the memory resource(s). */
1020         ret = sh_cmt_map_memory(cmt);
1021         if (ret < 0)
1022                 goto err_clk_unprepare;
1023
1024         /* Allocate and setup the channels. */
1025         cmt->num_channels = hweight8(cmt->hw_channels);
1026         cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1027                                 GFP_KERNEL);
1028         if (cmt->channels == NULL) {
1029                 ret = -ENOMEM;
1030                 goto err_unmap;
1031         }
1032
1033         /*
1034          * Use the first channel as a clock event device and the second channel
1035          * as a clock source. If only one channel is available use it for both.
1036          */
1037         for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1038                 unsigned int hwidx = ffs(mask) - 1;
1039                 bool clocksource = i == 1 || cmt->num_channels == 1;
1040                 bool clockevent = i == 0;
1041
1042                 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1043                                            clockevent, clocksource, cmt);
1044                 if (ret < 0)
1045                         goto err_unmap;
1046
1047                 mask &= ~(1 << hwidx);
1048         }
1049
1050         platform_set_drvdata(pdev, cmt);
1051
1052         return 0;
1053
1054 err_unmap:
1055         kfree(cmt->channels);
1056         iounmap(cmt->mapbase);
1057 err_clk_unprepare:
1058         clk_unprepare(cmt->clk);
1059 err_clk_put:
1060         clk_put(cmt->clk);
1061         return ret;
1062 }
1063
1064 static int sh_cmt_probe(struct platform_device *pdev)
1065 {
1066         struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1067         int ret;
1068
1069         if (!is_sh_early_platform_device(pdev)) {
1070                 pm_runtime_set_active(&pdev->dev);
1071                 pm_runtime_enable(&pdev->dev);
1072         }
1073
1074         if (cmt) {
1075                 dev_info(&pdev->dev, "kept as earlytimer\n");
1076                 goto out;
1077         }
1078
1079         cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1080         if (cmt == NULL)
1081                 return -ENOMEM;
1082
1083         ret = sh_cmt_setup(cmt, pdev);
1084         if (ret) {
1085                 kfree(cmt);
1086                 pm_runtime_idle(&pdev->dev);
1087                 return ret;
1088         }
1089         if (is_sh_early_platform_device(pdev))
1090                 return 0;
1091
1092  out:
1093         if (cmt->has_clockevent || cmt->has_clocksource)
1094                 pm_runtime_irq_safe(&pdev->dev);
1095         else
1096                 pm_runtime_idle(&pdev->dev);
1097
1098         return 0;
1099 }
1100
1101 static int sh_cmt_remove(struct platform_device *pdev)
1102 {
1103         return -EBUSY; /* cannot unregister clockevent and clocksource */
1104 }
1105
1106 static struct platform_driver sh_cmt_device_driver = {
1107         .probe          = sh_cmt_probe,
1108         .remove         = sh_cmt_remove,
1109         .driver         = {
1110                 .name   = "sh_cmt",
1111                 .of_match_table = of_match_ptr(sh_cmt_of_table),
1112         },
1113         .id_table       = sh_cmt_id_table,
1114 };
1115
1116 static int __init sh_cmt_init(void)
1117 {
1118         return platform_driver_register(&sh_cmt_device_driver);
1119 }
1120
1121 static void __exit sh_cmt_exit(void)
1122 {
1123         platform_driver_unregister(&sh_cmt_device_driver);
1124 }
1125
1126 #ifdef CONFIG_SUPERH
1127 sh_early_platform_init("earlytimer", &sh_cmt_device_driver);
1128 #endif
1129
1130 subsys_initcall(sh_cmt_init);
1131 module_exit(sh_cmt_exit);
1132
1133 MODULE_AUTHOR("Magnus Damm");
1134 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1135 MODULE_LICENSE("GPL v2");