1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/clocksource/arm_arch_timer.c
5 * Copyright (C) 2011 ARM Ltd.
9 #define pr_fmt(fmt) "arch_timer: " fmt
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/device.h>
14 #include <linux/smp.h>
15 #include <linux/cpu.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/clockchips.h>
18 #include <linux/clocksource.h>
19 #include <linux/clocksource_ids.h>
20 #include <linux/interrupt.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_address.h>
24 #include <linux/slab.h>
25 #include <linux/sched/clock.h>
26 #include <linux/sched_clock.h>
27 #include <linux/acpi.h>
28 #include <linux/arm-smccc.h>
29 #include <linux/ptp_kvm.h>
31 #include <asm/arch_timer.h>
34 #include <clocksource/arm_arch_timer.h>
37 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
39 #define CNTACR(n) (0x40 + ((n) * 4))
40 #define CNTACR_RPCT BIT(0)
41 #define CNTACR_RVCT BIT(1)
42 #define CNTACR_RFRQ BIT(2)
43 #define CNTACR_RVOFF BIT(3)
44 #define CNTACR_RWVT BIT(4)
45 #define CNTACR_RWPT BIT(5)
47 #define CNTVCT_LO 0x08
48 #define CNTVCT_HI 0x0c
50 #define CNTP_TVAL 0x28
52 #define CNTV_TVAL 0x38
55 static unsigned arch_timers_present __initdata;
57 static void __iomem *arch_counter_base __ro_after_init;
61 struct clock_event_device evt;
64 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
66 static u32 arch_timer_rate __ro_after_init;
67 u32 arch_timer_rate1 __ro_after_init;
68 static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init;
70 static const char *arch_timer_ppi_names[ARCH_TIMER_MAX_TIMER_PPI] = {
71 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
72 [ARCH_TIMER_PHYS_NONSECURE_PPI] = "phys",
73 [ARCH_TIMER_VIRT_PPI] = "virt",
74 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
75 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
78 static struct clock_event_device __percpu *arch_timer_evt;
80 static enum arch_timer_ppi_nr arch_timer_uses_ppi __ro_after_init = ARCH_TIMER_VIRT_PPI;
81 static bool arch_timer_c3stop __ro_after_init;
82 static bool arch_timer_mem_use_virtual __ro_after_init;
83 static bool arch_counter_suspend_stop __ro_after_init;
84 #ifdef CONFIG_GENERIC_GETTIMEOFDAY
85 static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
87 static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE;
88 #endif /* CONFIG_GENERIC_GETTIMEOFDAY */
90 static cpumask_t evtstrm_available = CPU_MASK_NONE;
91 static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
93 static int __init early_evtstrm_cfg(char *buf)
95 return strtobool(buf, &evtstrm_enable);
97 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
100 * Architected system timer support.
103 static __always_inline
104 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
105 struct clock_event_device *clk)
107 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
108 struct arch_timer *timer = to_arch_timer(clk);
110 case ARCH_TIMER_REG_CTRL:
111 writel_relaxed(val, timer->base + CNTP_CTL);
113 case ARCH_TIMER_REG_TVAL:
114 writel_relaxed(val, timer->base + CNTP_TVAL);
117 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
118 struct arch_timer *timer = to_arch_timer(clk);
120 case ARCH_TIMER_REG_CTRL:
121 writel_relaxed(val, timer->base + CNTV_CTL);
123 case ARCH_TIMER_REG_TVAL:
124 writel_relaxed(val, timer->base + CNTV_TVAL);
128 arch_timer_reg_write_cp15(access, reg, val);
132 static __always_inline
133 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
134 struct clock_event_device *clk)
138 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
139 struct arch_timer *timer = to_arch_timer(clk);
141 case ARCH_TIMER_REG_CTRL:
142 val = readl_relaxed(timer->base + CNTP_CTL);
144 case ARCH_TIMER_REG_TVAL:
145 val = readl_relaxed(timer->base + CNTP_TVAL);
148 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
149 struct arch_timer *timer = to_arch_timer(clk);
151 case ARCH_TIMER_REG_CTRL:
152 val = readl_relaxed(timer->base + CNTV_CTL);
154 case ARCH_TIMER_REG_TVAL:
155 val = readl_relaxed(timer->base + CNTV_TVAL);
159 val = arch_timer_reg_read_cp15(access, reg);
165 static notrace u64 arch_counter_get_cntpct_stable(void)
167 return __arch_counter_get_cntpct_stable();
170 static notrace u64 arch_counter_get_cntpct(void)
172 return __arch_counter_get_cntpct();
175 static notrace u64 arch_counter_get_cntvct_stable(void)
177 return __arch_counter_get_cntvct_stable();
180 static notrace u64 arch_counter_get_cntvct(void)
182 return __arch_counter_get_cntvct();
186 * Default to cp15 based access because arm64 uses this function for
187 * sched_clock() before DT is probed and the cp15 method is guaranteed
188 * to exist on arm64. arm doesn't use this before DT is probed so even
189 * if we don't have the cp15 accessors we won't have a problem.
191 u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct;
192 EXPORT_SYMBOL_GPL(arch_timer_read_counter);
194 static u64 arch_counter_read(struct clocksource *cs)
196 return arch_timer_read_counter();
199 static u64 arch_counter_read_cc(const struct cyclecounter *cc)
201 return arch_timer_read_counter();
204 static struct clocksource clocksource_counter = {
205 .name = "arch_sys_counter",
206 .id = CSID_ARM_ARCH_COUNTER,
208 .read = arch_counter_read,
209 .mask = CLOCKSOURCE_MASK(56),
210 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
213 static struct cyclecounter cyclecounter __ro_after_init = {
214 .read = arch_counter_read_cc,
215 .mask = CLOCKSOURCE_MASK(56),
218 struct ate_acpi_oem_info {
219 char oem_id[ACPI_OEM_ID_SIZE + 1];
220 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
224 #ifdef CONFIG_FSL_ERRATUM_A008585
226 * The number of retries is an arbitrary value well beyond the highest number
227 * of iterations the loop has been observed to take.
229 #define __fsl_a008585_read_reg(reg) ({ \
231 int _retries = 200; \
234 _old = read_sysreg(reg); \
235 _new = read_sysreg(reg); \
237 } while (unlikely(_old != _new) && _retries); \
239 WARN_ON_ONCE(!_retries); \
243 static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
245 return __fsl_a008585_read_reg(cntp_tval_el0);
248 static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
250 return __fsl_a008585_read_reg(cntv_tval_el0);
253 static u64 notrace fsl_a008585_read_cntpct_el0(void)
255 return __fsl_a008585_read_reg(cntpct_el0);
258 static u64 notrace fsl_a008585_read_cntvct_el0(void)
260 return __fsl_a008585_read_reg(cntvct_el0);
264 #ifdef CONFIG_HISILICON_ERRATUM_161010101
266 * Verify whether the value of the second read is larger than the first by
267 * less than 32 is the only way to confirm the value is correct, so clear the
268 * lower 5 bits to check whether the difference is greater than 32 or not.
269 * Theoretically the erratum should not occur more than twice in succession
270 * when reading the system counter, but it is possible that some interrupts
271 * may lead to more than twice read errors, triggering the warning, so setting
272 * the number of retries far beyond the number of iterations the loop has been
275 #define __hisi_161010101_read_reg(reg) ({ \
280 _old = read_sysreg(reg); \
281 _new = read_sysreg(reg); \
283 } while (unlikely((_new - _old) >> 5) && _retries); \
285 WARN_ON_ONCE(!_retries); \
289 static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
291 return __hisi_161010101_read_reg(cntp_tval_el0);
294 static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
296 return __hisi_161010101_read_reg(cntv_tval_el0);
299 static u64 notrace hisi_161010101_read_cntpct_el0(void)
301 return __hisi_161010101_read_reg(cntpct_el0);
304 static u64 notrace hisi_161010101_read_cntvct_el0(void)
306 return __hisi_161010101_read_reg(cntvct_el0);
309 static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
311 * Note that trailing spaces are required to properly match
312 * the OEM table information.
316 .oem_table_id = "HIP05 ",
321 .oem_table_id = "HIP06 ",
326 .oem_table_id = "HIP07 ",
329 { /* Sentinel indicating the end of the OEM array */ },
333 #ifdef CONFIG_ARM64_ERRATUM_858921
334 static u64 notrace arm64_858921_read_cntpct_el0(void)
338 old = read_sysreg(cntpct_el0);
339 new = read_sysreg(cntpct_el0);
340 return (((old ^ new) >> 32) & 1) ? old : new;
343 static u64 notrace arm64_858921_read_cntvct_el0(void)
347 old = read_sysreg(cntvct_el0);
348 new = read_sysreg(cntvct_el0);
349 return (((old ^ new) >> 32) & 1) ? old : new;
353 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
355 * The low bits of the counter registers are indeterminate while bit 10 or
356 * greater is rolling over. Since the counter value can jump both backward
357 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
358 * with all ones or all zeros in the low bits. Bound the loop by the maximum
359 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
361 #define __sun50i_a64_read_reg(reg) ({ \
363 int _retries = 150; \
366 _val = read_sysreg(reg); \
368 } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
370 WARN_ON_ONCE(!_retries); \
374 static u64 notrace sun50i_a64_read_cntpct_el0(void)
376 return __sun50i_a64_read_reg(cntpct_el0);
379 static u64 notrace sun50i_a64_read_cntvct_el0(void)
381 return __sun50i_a64_read_reg(cntvct_el0);
384 static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
386 return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
389 static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
391 return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
395 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
396 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
397 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
399 static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
401 static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
402 struct clock_event_device *clk)
407 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
408 ctrl |= ARCH_TIMER_CTRL_ENABLE;
409 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
411 if (access == ARCH_TIMER_PHYS_ACCESS) {
412 cval = evt + arch_counter_get_cntpct_stable();
413 write_sysreg(cval, cntp_cval_el0);
415 cval = evt + arch_counter_get_cntvct_stable();
416 write_sysreg(cval, cntv_cval_el0);
419 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
422 static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
423 struct clock_event_device *clk)
425 erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
429 static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
430 struct clock_event_device *clk)
432 erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
436 static const struct arch_timer_erratum_workaround ool_workarounds[] = {
437 #ifdef CONFIG_FSL_ERRATUM_A008585
439 .match_type = ate_match_dt,
440 .id = "fsl,erratum-a008585",
441 .desc = "Freescale erratum a005858",
442 .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
443 .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
444 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
445 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
446 .set_next_event_phys = erratum_set_next_event_tval_phys,
447 .set_next_event_virt = erratum_set_next_event_tval_virt,
450 #ifdef CONFIG_HISILICON_ERRATUM_161010101
452 .match_type = ate_match_dt,
453 .id = "hisilicon,erratum-161010101",
454 .desc = "HiSilicon erratum 161010101",
455 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
456 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
457 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
458 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
459 .set_next_event_phys = erratum_set_next_event_tval_phys,
460 .set_next_event_virt = erratum_set_next_event_tval_virt,
463 .match_type = ate_match_acpi_oem_info,
464 .id = hisi_161010101_oem_info,
465 .desc = "HiSilicon erratum 161010101",
466 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
467 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
468 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
469 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
470 .set_next_event_phys = erratum_set_next_event_tval_phys,
471 .set_next_event_virt = erratum_set_next_event_tval_virt,
474 #ifdef CONFIG_ARM64_ERRATUM_858921
476 .match_type = ate_match_local_cap_id,
477 .id = (void *)ARM64_WORKAROUND_858921,
478 .desc = "ARM erratum 858921",
479 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
480 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
483 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
485 .match_type = ate_match_dt,
486 .id = "allwinner,erratum-unknown1",
487 .desc = "Allwinner erratum UNKNOWN1",
488 .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
489 .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
490 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
491 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
492 .set_next_event_phys = erratum_set_next_event_tval_phys,
493 .set_next_event_virt = erratum_set_next_event_tval_virt,
496 #ifdef CONFIG_ARM64_ERRATUM_1418040
498 .match_type = ate_match_local_cap_id,
499 .id = (void *)ARM64_WORKAROUND_1418040,
500 .desc = "ARM erratum 1418040",
501 .disable_compat_vdso = true,
506 typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
510 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
513 const struct device_node *np = arg;
515 return of_property_read_bool(np, wa->id);
519 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
522 return this_cpu_has_cap((uintptr_t)wa->id);
527 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
530 static const struct ate_acpi_oem_info empty_oem_info = {};
531 const struct ate_acpi_oem_info *info = wa->id;
532 const struct acpi_table_header *table = arg;
534 /* Iterate over the ACPI OEM info array, looking for a match */
535 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
536 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
537 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
538 info->oem_revision == table->oem_revision)
547 static const struct arch_timer_erratum_workaround *
548 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
549 ate_match_fn_t match_fn,
554 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
555 if (ool_workarounds[i].match_type != type)
558 if (match_fn(&ool_workarounds[i], arg))
559 return &ool_workarounds[i];
566 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
572 __this_cpu_write(timer_unstable_counter_workaround, wa);
574 for_each_possible_cpu(i)
575 per_cpu(timer_unstable_counter_workaround, i) = wa;
578 if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
579 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
582 * Don't use the vdso fastpath if errata require using the
583 * out-of-line counter accessor. We may change our mind pretty
584 * late in the game (with a per-CPU erratum, for example), so
585 * change both the default value and the vdso itself.
587 if (wa->read_cntvct_el0) {
588 clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
589 vdso_default = VDSO_CLOCKMODE_NONE;
590 } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
591 vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
592 clocksource_counter.vdso_clock_mode = vdso_default;
596 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
599 const struct arch_timer_erratum_workaround *wa, *__wa;
600 ate_match_fn_t match_fn = NULL;
605 match_fn = arch_timer_check_dt_erratum;
607 case ate_match_local_cap_id:
608 match_fn = arch_timer_check_local_cap_erratum;
611 case ate_match_acpi_oem_info:
612 match_fn = arch_timer_check_acpi_oem_erratum;
619 wa = arch_timer_iterate_errata(type, match_fn, arg);
623 __wa = __this_cpu_read(timer_unstable_counter_workaround);
624 if (__wa && wa != __wa)
625 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
626 wa->desc, __wa->desc);
631 arch_timer_enable_workaround(wa, local);
632 pr_info("Enabling %s workaround for %s\n",
633 local ? "local" : "global", wa->desc);
636 static bool arch_timer_this_cpu_has_cntvct_wa(void)
638 return has_erratum_handler(read_cntvct_el0);
641 static bool arch_timer_counter_has_wa(void)
643 return atomic_read(&timer_unstable_counter_workaround_in_use);
646 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
647 #define arch_timer_this_cpu_has_cntvct_wa() ({false;})
648 #define arch_timer_counter_has_wa() ({false;})
649 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
651 static __always_inline irqreturn_t timer_handler(const int access,
652 struct clock_event_device *evt)
656 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
657 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
658 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
659 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
660 evt->event_handler(evt);
667 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
669 struct clock_event_device *evt = dev_id;
671 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
674 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
676 struct clock_event_device *evt = dev_id;
678 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
681 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
683 struct clock_event_device *evt = dev_id;
685 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
688 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
690 struct clock_event_device *evt = dev_id;
692 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
695 static __always_inline int timer_shutdown(const int access,
696 struct clock_event_device *clk)
700 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
701 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
702 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
707 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
709 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
712 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
714 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
717 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
719 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
722 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
724 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
727 static __always_inline void set_next_event(const int access, unsigned long evt,
728 struct clock_event_device *clk)
731 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
732 ctrl |= ARCH_TIMER_CTRL_ENABLE;
733 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
734 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
735 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
738 static int arch_timer_set_next_event_virt(unsigned long evt,
739 struct clock_event_device *clk)
741 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
745 static int arch_timer_set_next_event_phys(unsigned long evt,
746 struct clock_event_device *clk)
748 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
752 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
753 struct clock_event_device *clk)
755 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
759 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
760 struct clock_event_device *clk)
762 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
766 static void __arch_timer_setup(unsigned type,
767 struct clock_event_device *clk)
769 clk->features = CLOCK_EVT_FEAT_ONESHOT;
771 if (type == ARCH_TIMER_TYPE_CP15) {
772 typeof(clk->set_next_event) sne;
774 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
776 if (arch_timer_c3stop)
777 clk->features |= CLOCK_EVT_FEAT_C3STOP;
778 clk->name = "arch_sys_timer";
780 clk->cpumask = cpumask_of(smp_processor_id());
781 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
782 switch (arch_timer_uses_ppi) {
783 case ARCH_TIMER_VIRT_PPI:
784 clk->set_state_shutdown = arch_timer_shutdown_virt;
785 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
786 sne = erratum_handler(set_next_event_virt);
788 case ARCH_TIMER_PHYS_SECURE_PPI:
789 case ARCH_TIMER_PHYS_NONSECURE_PPI:
790 case ARCH_TIMER_HYP_PPI:
791 clk->set_state_shutdown = arch_timer_shutdown_phys;
792 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
793 sne = erratum_handler(set_next_event_phys);
799 clk->set_next_event = sne;
801 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
802 clk->name = "arch_mem_timer";
804 clk->cpumask = cpu_possible_mask;
805 if (arch_timer_mem_use_virtual) {
806 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
807 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
808 clk->set_next_event =
809 arch_timer_set_next_event_virt_mem;
811 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
812 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
813 clk->set_next_event =
814 arch_timer_set_next_event_phys_mem;
818 clk->set_state_shutdown(clk);
820 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
823 static void arch_timer_evtstrm_enable(int divider)
825 u32 cntkctl = arch_timer_get_cntkctl();
827 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
828 /* Set the divider and enable virtual event stream */
829 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
830 | ARCH_TIMER_VIRT_EVT_EN;
831 arch_timer_set_cntkctl(cntkctl);
832 arch_timer_set_evtstrm_feature();
833 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
836 static void arch_timer_configure_evtstream(void)
838 int evt_stream_div, lsb;
841 * As the event stream can at most be generated at half the frequency
842 * of the counter, use half the frequency when computing the divider.
844 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
847 * Find the closest power of two to the divisor. If the adjacent bit
848 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
850 lsb = fls(evt_stream_div) - 1;
851 if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
854 /* enable event stream */
855 arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
858 static void arch_counter_set_user_access(void)
860 u32 cntkctl = arch_timer_get_cntkctl();
862 /* Disable user access to the timers and both counters */
863 /* Also disable virtual event stream */
864 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
865 | ARCH_TIMER_USR_VT_ACCESS_EN
866 | ARCH_TIMER_USR_VCT_ACCESS_EN
867 | ARCH_TIMER_VIRT_EVT_EN
868 | ARCH_TIMER_USR_PCT_ACCESS_EN);
871 * Enable user access to the virtual counter if it doesn't
872 * need to be workaround. The vdso may have been already
875 if (arch_timer_this_cpu_has_cntvct_wa())
876 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
878 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
880 arch_timer_set_cntkctl(cntkctl);
883 static bool arch_timer_has_nonsecure_ppi(void)
885 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
886 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
889 static u32 check_ppi_trigger(int irq)
891 u32 flags = irq_get_trigger_type(irq);
893 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
894 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
895 pr_warn("WARNING: Please fix your firmware\n");
896 flags = IRQF_TRIGGER_LOW;
902 static int arch_timer_starting_cpu(unsigned int cpu)
904 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
907 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
909 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
910 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
912 if (arch_timer_has_nonsecure_ppi()) {
913 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
914 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
918 arch_counter_set_user_access();
920 arch_timer_configure_evtstream();
925 static int validate_timer_rate(void)
927 if (!arch_timer_rate)
930 /* Arch timer frequency < 1MHz can cause trouble */
931 WARN_ON(arch_timer_rate < 1000000);
937 * For historical reasons, when probing with DT we use whichever (non-zero)
938 * rate was probed first, and don't verify that others match. If the first node
939 * probed has a clock-frequency property, this overrides the HW register.
941 static void __init arch_timer_of_configure_rate(u32 rate, struct device_node *np)
943 /* Who has more than one independent system counter? */
947 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
948 arch_timer_rate = rate;
950 /* Check the timer frequency. */
951 if (validate_timer_rate())
952 pr_warn("frequency not available\n");
955 static void __init arch_timer_banner(unsigned type)
957 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
958 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
959 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
961 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
962 (unsigned long)arch_timer_rate / 1000000,
963 (unsigned long)(arch_timer_rate / 10000) % 100,
964 type & ARCH_TIMER_TYPE_CP15 ?
965 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
967 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
968 type & ARCH_TIMER_TYPE_MEM ?
969 arch_timer_mem_use_virtual ? "virt" : "phys" :
973 u32 arch_timer_get_rate(void)
975 return arch_timer_rate;
978 bool arch_timer_evtstrm_available(void)
981 * We might get called from a preemptible context. This is fine
982 * because availability of the event stream should be always the same
983 * for a preemptible context and context where we might resume a task.
985 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
988 static u64 arch_counter_get_cntvct_mem(void)
990 u32 vct_lo, vct_hi, tmp_hi;
993 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
994 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
995 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
996 } while (vct_hi != tmp_hi);
998 return ((u64) vct_hi << 32) | vct_lo;
1001 static struct arch_timer_kvm_info arch_timer_kvm_info;
1003 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
1005 return &arch_timer_kvm_info;
1008 static void __init arch_counter_register(unsigned type)
1012 /* Register the CP15 based counter if we have one */
1013 if (type & ARCH_TIMER_TYPE_CP15) {
1016 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
1017 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
1018 if (arch_timer_counter_has_wa())
1019 rd = arch_counter_get_cntvct_stable;
1021 rd = arch_counter_get_cntvct;
1023 if (arch_timer_counter_has_wa())
1024 rd = arch_counter_get_cntpct_stable;
1026 rd = arch_counter_get_cntpct;
1029 arch_timer_read_counter = rd;
1030 clocksource_counter.vdso_clock_mode = vdso_default;
1032 arch_timer_read_counter = arch_counter_get_cntvct_mem;
1035 if (!arch_counter_suspend_stop)
1036 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1037 start_count = arch_timer_read_counter();
1038 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1039 cyclecounter.mult = clocksource_counter.mult;
1040 cyclecounter.shift = clocksource_counter.shift;
1041 timecounter_init(&arch_timer_kvm_info.timecounter,
1042 &cyclecounter, start_count);
1044 /* 56 bits minimum, so we assume worst case rollover */
1045 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
1048 static void arch_timer_stop(struct clock_event_device *clk)
1050 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1052 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1053 if (arch_timer_has_nonsecure_ppi())
1054 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1056 clk->set_state_shutdown(clk);
1059 static int arch_timer_dying_cpu(unsigned int cpu)
1061 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1063 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1065 arch_timer_stop(clk);
1069 #ifdef CONFIG_CPU_PM
1070 static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1071 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1072 unsigned long action, void *hcpu)
1074 if (action == CPU_PM_ENTER) {
1075 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1077 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1078 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1079 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1081 if (arch_timer_have_evtstrm_feature())
1082 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1087 static struct notifier_block arch_timer_cpu_pm_notifier = {
1088 .notifier_call = arch_timer_cpu_pm_notify,
1091 static int __init arch_timer_cpu_pm_init(void)
1093 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1096 static void __init arch_timer_cpu_pm_deinit(void)
1098 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1102 static int __init arch_timer_cpu_pm_init(void)
1107 static void __init arch_timer_cpu_pm_deinit(void)
1112 static int __init arch_timer_register(void)
1117 arch_timer_evt = alloc_percpu(struct clock_event_device);
1118 if (!arch_timer_evt) {
1123 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1124 switch (arch_timer_uses_ppi) {
1125 case ARCH_TIMER_VIRT_PPI:
1126 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1127 "arch_timer", arch_timer_evt);
1129 case ARCH_TIMER_PHYS_SECURE_PPI:
1130 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1131 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1132 "arch_timer", arch_timer_evt);
1133 if (!err && arch_timer_has_nonsecure_ppi()) {
1134 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1135 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1136 "arch_timer", arch_timer_evt);
1138 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1142 case ARCH_TIMER_HYP_PPI:
1143 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1144 "arch_timer", arch_timer_evt);
1151 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1155 err = arch_timer_cpu_pm_init();
1157 goto out_unreg_notify;
1159 /* Register and immediately configure the timer on the boot CPU */
1160 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1161 "clockevents/arm/arch_timer:starting",
1162 arch_timer_starting_cpu, arch_timer_dying_cpu);
1164 goto out_unreg_cpupm;
1168 arch_timer_cpu_pm_deinit();
1171 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1172 if (arch_timer_has_nonsecure_ppi())
1173 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1177 free_percpu(arch_timer_evt);
1182 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1186 struct arch_timer *t;
1188 t = kzalloc(sizeof(*t), GFP_KERNEL);
1194 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
1196 if (arch_timer_mem_use_virtual)
1197 func = arch_timer_handler_virt_mem;
1199 func = arch_timer_handler_phys_mem;
1201 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
1203 pr_err("Failed to request mem timer irq\n");
1210 static const struct of_device_id arch_timer_of_match[] __initconst = {
1211 { .compatible = "arm,armv7-timer", },
1212 { .compatible = "arm,armv8-timer", },
1216 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1217 { .compatible = "arm,armv7-timer-mem", },
1221 static bool __init arch_timer_needs_of_probing(void)
1223 struct device_node *dn;
1224 bool needs_probing = false;
1225 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1227 /* We have two timers, and both device-tree nodes are probed. */
1228 if ((arch_timers_present & mask) == mask)
1232 * Only one type of timer is probed,
1233 * check if we have another type of timer node in device-tree.
1235 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1236 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1238 dn = of_find_matching_node(NULL, arch_timer_of_match);
1240 if (dn && of_device_is_available(dn))
1241 needs_probing = true;
1245 return needs_probing;
1248 static int __init arch_timer_common_init(void)
1250 arch_timer_banner(arch_timers_present);
1251 arch_counter_register(arch_timers_present);
1252 return arch_timer_arch_init();
1256 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1258 * If HYP mode is available, we know that the physical timer
1259 * has been configured to be accessible from PL1. Use it, so
1260 * that a guest can use the virtual timer instead.
1262 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1263 * accesses to CNTP_*_EL1 registers are silently redirected to
1264 * their CNTHP_*_EL2 counterparts, and use a different PPI
1267 * If no interrupt provided for virtual timer, we'll have to
1268 * stick to the physical timer. It'd better be accessible...
1269 * For arm64 we never use the secure interrupt.
1271 * Return: a suitable PPI type for the current system.
1273 static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1275 if (is_kernel_in_hyp_mode())
1276 return ARCH_TIMER_HYP_PPI;
1278 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1279 return ARCH_TIMER_VIRT_PPI;
1281 if (IS_ENABLED(CONFIG_ARM64))
1282 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1284 return ARCH_TIMER_PHYS_SECURE_PPI;
1287 static void __init arch_timer_populate_kvm_info(void)
1289 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1290 if (is_kernel_in_hyp_mode())
1291 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1294 static int __init arch_timer_of_init(struct device_node *np)
1300 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1301 pr_warn("multiple nodes in dt, skipping\n");
1305 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1307 has_names = of_property_read_bool(np, "interrupt-names");
1309 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) {
1311 irq = of_irq_get_byname(np, arch_timer_ppi_names[i]);
1313 irq = of_irq_get(np, i);
1315 arch_timer_ppi[i] = irq;
1318 arch_timer_populate_kvm_info();
1320 rate = arch_timer_get_cntfrq();
1321 arch_timer_of_configure_rate(rate, np);
1323 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1325 /* Check for globally applicable workarounds */
1326 arch_timer_check_ool_workaround(ate_match_dt, np);
1329 * If we cannot rely on firmware initializing the timer registers then
1330 * we should use the physical timers instead.
1332 if (IS_ENABLED(CONFIG_ARM) &&
1333 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1334 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1336 arch_timer_uses_ppi = arch_timer_select_ppi();
1338 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1339 pr_err("No interrupt available, giving up\n");
1343 /* On some systems, the counter stops ticking when in suspend. */
1344 arch_counter_suspend_stop = of_property_read_bool(np,
1345 "arm,no-tick-in-suspend");
1347 ret = arch_timer_register();
1351 if (arch_timer_needs_of_probing())
1354 return arch_timer_common_init();
1356 TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1357 TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1360 arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1365 base = ioremap(frame->cntbase, frame->size);
1367 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1371 rate = readl_relaxed(base + CNTFRQ);
1378 static struct arch_timer_mem_frame * __init
1379 arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1381 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1382 void __iomem *cntctlbase;
1386 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1388 pr_err("Can't map CNTCTLBase @ %pa\n",
1389 &timer_mem->cntctlbase);
1393 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1396 * Try to find a virtual capable frame. Otherwise fall back to a
1397 * physical capable frame.
1399 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1400 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1401 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1403 frame = &timer_mem->frame[i];
1407 /* Try enabling everything, and see what sticks */
1408 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1409 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1411 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1412 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1414 arch_timer_mem_use_virtual = true;
1418 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1424 iounmap(cntctlbase);
1430 arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1435 if (arch_timer_mem_use_virtual)
1436 irq = frame->virt_irq;
1438 irq = frame->phys_irq;
1441 pr_err("Frame missing %s irq.\n",
1442 arch_timer_mem_use_virtual ? "virt" : "phys");
1446 if (!request_mem_region(frame->cntbase, frame->size,
1450 base = ioremap(frame->cntbase, frame->size);
1452 pr_err("Can't map frame's registers\n");
1456 ret = arch_timer_mem_register(base, irq);
1462 arch_counter_base = base;
1463 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1468 static int __init arch_timer_mem_of_init(struct device_node *np)
1470 struct arch_timer_mem *timer_mem;
1471 struct arch_timer_mem_frame *frame;
1472 struct device_node *frame_node;
1473 struct resource res;
1477 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1481 if (of_address_to_resource(np, 0, &res))
1483 timer_mem->cntctlbase = res.start;
1484 timer_mem->size = resource_size(&res);
1486 for_each_available_child_of_node(np, frame_node) {
1488 struct arch_timer_mem_frame *frame;
1490 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1491 pr_err(FW_BUG "Missing frame-number.\n");
1492 of_node_put(frame_node);
1495 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1496 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1497 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1498 of_node_put(frame_node);
1501 frame = &timer_mem->frame[n];
1504 pr_err(FW_BUG "Duplicated frame-number.\n");
1505 of_node_put(frame_node);
1509 if (of_address_to_resource(frame_node, 0, &res)) {
1510 of_node_put(frame_node);
1513 frame->cntbase = res.start;
1514 frame->size = resource_size(&res);
1516 frame->virt_irq = irq_of_parse_and_map(frame_node,
1517 ARCH_TIMER_VIRT_SPI);
1518 frame->phys_irq = irq_of_parse_and_map(frame_node,
1519 ARCH_TIMER_PHYS_SPI);
1521 frame->valid = true;
1524 frame = arch_timer_mem_find_best_frame(timer_mem);
1526 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1527 &timer_mem->cntctlbase);
1532 rate = arch_timer_mem_frame_get_cntfrq(frame);
1533 arch_timer_of_configure_rate(rate, np);
1535 ret = arch_timer_mem_frame_register(frame);
1536 if (!ret && !arch_timer_needs_of_probing())
1537 ret = arch_timer_common_init();
1542 TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1543 arch_timer_mem_of_init);
1545 #ifdef CONFIG_ACPI_GTDT
1547 arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1549 struct arch_timer_mem_frame *frame;
1553 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1554 frame = &timer_mem->frame[i];
1559 rate = arch_timer_mem_frame_get_cntfrq(frame);
1560 if (rate == arch_timer_rate)
1563 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1565 (unsigned long)rate, (unsigned long)arch_timer_rate);
1573 static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1575 struct arch_timer_mem *timers, *timer;
1576 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1577 int timer_count, i, ret = 0;
1579 timers = kcalloc(platform_timer_count, sizeof(*timers),
1584 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1585 if (ret || !timer_count)
1589 * While unlikely, it's theoretically possible that none of the frames
1590 * in a timer expose the combination of feature we want.
1592 for (i = 0; i < timer_count; i++) {
1595 frame = arch_timer_mem_find_best_frame(timer);
1599 ret = arch_timer_mem_verify_cntfrq(timer);
1601 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1605 if (!best_frame) /* implies !frame */
1607 * Only complain about missing suitable frames if we
1608 * haven't already found one in a previous iteration.
1610 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1611 &timer->cntctlbase);
1615 ret = arch_timer_mem_frame_register(best_frame);
1621 /* Initialize per-processor generic timer and memory-mapped timer(if present) */
1622 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1624 int ret, platform_timer_count;
1626 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1627 pr_warn("already initialized, skipping\n");
1631 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1633 ret = acpi_gtdt_init(table, &platform_timer_count);
1637 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1638 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1640 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1641 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1643 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1644 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1646 arch_timer_populate_kvm_info();
1649 * When probing via ACPI, we have no mechanism to override the sysreg
1650 * CNTFRQ value. This *must* be correct.
1652 arch_timer_rate = arch_timer_get_cntfrq();
1653 ret = validate_timer_rate();
1655 pr_err(FW_BUG "frequency not available.\n");
1659 arch_timer_uses_ppi = arch_timer_select_ppi();
1660 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1661 pr_err("No interrupt available, giving up\n");
1665 /* Always-on capability */
1666 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1668 /* Check for globally applicable workarounds */
1669 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1671 ret = arch_timer_register();
1675 if (platform_timer_count &&
1676 arch_timer_mem_acpi_init(platform_timer_count))
1677 pr_err("Failed to initialize memory-mapped timer.\n");
1679 return arch_timer_common_init();
1681 TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1684 int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts,
1685 struct clocksource **cs)
1687 struct arm_smccc_res hvc_res;
1691 if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY))
1694 if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
1695 ptp_counter = KVM_PTP_VIRT_COUNTER;
1697 ptp_counter = KVM_PTP_PHYS_COUNTER;
1699 arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
1700 ptp_counter, &hvc_res);
1702 if ((int)(hvc_res.a0) < 0)
1705 ktime = (u64)hvc_res.a0 << 32 | hvc_res.a1;
1706 *ts = ktime_to_timespec64(ktime);
1708 *cycle = (u64)hvc_res.a2 << 32 | hvc_res.a3;
1710 *cs = &clocksource_counter;
1714 EXPORT_SYMBOL_GPL(kvm_arch_ptp_get_crosststamp);