1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2019 Xilinx
7 * Based on drivers/clk/zynq/clkc.c
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
18 #include "clk-zynqmp.h"
20 #define MAX_PARENT 100
22 #define MAX_NAME_LEN 50
24 /* Flags for parents */
25 #define PARENT_CLK_SELF 0
26 #define PARENT_CLK_NODE1 1
27 #define PARENT_CLK_NODE2 2
28 #define PARENT_CLK_NODE3 3
29 #define PARENT_CLK_NODE4 4
30 #define PARENT_CLK_EXTERNAL 5
32 #define END_OF_CLK_NAME "END_OF_CLK"
33 #define END_OF_TOPOLOGY_NODE 1
34 #define END_OF_PARENTS 1
35 #define RESERVED_CLK_NAME ""
37 #define CLK_GET_NAME_RESP_LEN 16
38 #define CLK_GET_TOPOLOGY_RESP_WORDS 3
39 #define CLK_GET_PARENTS_RESP_WORDS 3
40 #define CLK_GET_ATTR_RESP_WORDS 1
48 * struct clock_parent - Clock parent
50 * @id: Parent clock ID
54 char name[MAX_NAME_LEN];
60 * struct zynqmp_clock - Clock
61 * @clk_name: Clock name
62 * @valid: Validity flag of clock
63 * @type: Clock type (Output/External)
64 * @node: Clock topology nodes
65 * @num_nodes: Number of nodes present in topology
66 * @parent: Parent of clock
67 * @num_parents: Number of parents of clock
71 char clk_name[MAX_NAME_LEN];
74 struct clock_topology node[MAX_NODES];
76 struct clock_parent parent[MAX_PARENT];
82 char name[CLK_GET_NAME_RESP_LEN];
85 struct topology_resp {
86 #define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
87 #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
88 #define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
89 u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
93 #define NA_PARENT 0xFFFFFFFF
94 #define DUMMY_PARENT 0xFFFFFFFE
95 #define CLK_PARENTS_ID GENMASK(15, 0)
96 #define CLK_PARENTS_FLAGS GENMASK(31, 16)
97 u32 parents[CLK_GET_PARENTS_RESP_WORDS];
101 #define CLK_ATTR_VALID BIT(0)
102 #define CLK_ATTR_TYPE BIT(2)
103 #define CLK_ATTR_NODE_INDEX GENMASK(13, 0)
104 #define CLK_ATTR_NODE_TYPE GENMASK(19, 14)
105 #define CLK_ATTR_NODE_SUBCLASS GENMASK(25, 20)
106 #define CLK_ATTR_NODE_CLASS GENMASK(31, 26)
107 u32 attr[CLK_GET_ATTR_RESP_WORDS];
110 static const char clk_type_postfix[][10] = {
114 [TYPE_DIV1] = "_div1",
115 [TYPE_DIV2] = "_div2",
116 [TYPE_FIXEDFACTOR] = "_ff",
120 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
121 const char * const *parents,
123 const struct clock_topology *nodes)
125 [TYPE_INVALID] = NULL,
126 [TYPE_MUX] = zynqmp_clk_register_mux,
127 [TYPE_PLL] = zynqmp_clk_register_pll,
128 [TYPE_FIXEDFACTOR] = zynqmp_clk_register_fixed_factor,
129 [TYPE_DIV1] = zynqmp_clk_register_divider,
130 [TYPE_DIV2] = zynqmp_clk_register_divider,
131 [TYPE_GATE] = zynqmp_clk_register_gate
134 static struct zynqmp_clock *clock;
135 static struct clk_hw_onecell_data *zynqmp_data;
136 static unsigned int clock_max_idx;
139 * zynqmp_is_valid_clock() - Check whether clock is valid or not
140 * @clk_id: Clock index
142 * Return: 1 if clock is valid, 0 if clock is invalid else error code
144 static inline int zynqmp_is_valid_clock(u32 clk_id)
146 if (clk_id >= clock_max_idx)
149 return clock[clk_id].valid;
153 * zynqmp_get_clock_name() - Get name of clock from Clock index
154 * @clk_id: Clock index
155 * @clk_name: Name of clock
157 * Return: 0 on success else error code
159 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name)
163 ret = zynqmp_is_valid_clock(clk_id);
165 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
169 return ret == 0 ? -EINVAL : ret;
173 * zynqmp_get_clock_type() - Get type of clock
174 * @clk_id: Clock index
175 * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
177 * Return: 0 on success else error code
179 static int zynqmp_get_clock_type(u32 clk_id, u32 *type)
183 ret = zynqmp_is_valid_clock(clk_id);
185 *type = clock[clk_id].type;
189 return ret == 0 ? -EINVAL : ret;
193 * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
194 * @nclocks: Number of clocks in system/board.
196 * Call firmware API to get number of clocks.
198 * Return: 0 on success else error code.
200 static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
202 struct zynqmp_pm_query_data qdata = {0};
203 u32 ret_payload[PAYLOAD_ARG_CNT];
206 qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
208 ret = zynqmp_pm_query_data(qdata, ret_payload);
209 *nclocks = ret_payload[1];
215 * zynqmp_pm_clock_get_name() - Get the name of clock for given id
216 * @clock_id: ID of the clock to be queried
217 * @response: Name of the clock with the given id
219 * This function is used to get name of clock specified by given
224 static int zynqmp_pm_clock_get_name(u32 clock_id,
225 struct name_resp *response)
227 struct zynqmp_pm_query_data qdata = {0};
228 u32 ret_payload[PAYLOAD_ARG_CNT];
230 qdata.qid = PM_QID_CLOCK_GET_NAME;
231 qdata.arg1 = clock_id;
233 zynqmp_pm_query_data(qdata, ret_payload);
234 memcpy(response, ret_payload, sizeof(*response));
240 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
241 * @clock_id: ID of the clock to be queried
242 * @index: Node index of clock topology
243 * @response: Buffer used for the topology response
245 * This function is used to get topology information for the clock
246 * specified by given clock ID.
248 * This API will return 3 node of topology with a single response. To get
249 * other nodes, master should call same API in loop with new
250 * index till error is returned. E.g First call should have
251 * index 0 which will return nodes 0,1 and 2. Next call, index
252 * should be 3 which will return nodes 3,4 and 5 and so on.
254 * Return: 0 on success else error+reason
256 static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
257 struct topology_resp *response)
259 struct zynqmp_pm_query_data qdata = {0};
260 u32 ret_payload[PAYLOAD_ARG_CNT];
263 qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
264 qdata.arg1 = clock_id;
267 ret = zynqmp_pm_query_data(qdata, ret_payload);
268 memcpy(response, &ret_payload[1], sizeof(*response));
274 * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
276 * @name: Name of this clock
278 * @parents: Name of this clock's parents
279 * @num_parents: Number of parents
280 * @nodes: Clock topology node
282 * Return: clock hardware to the registered clock
284 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
285 const char * const *parents,
287 const struct clock_topology *nodes)
291 struct zynqmp_pm_query_data qdata = {0};
292 u32 ret_payload[PAYLOAD_ARG_CNT];
295 qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
298 ret = zynqmp_pm_query_data(qdata, ret_payload);
302 mult = ret_payload[1];
303 div = ret_payload[2];
305 hw = clk_hw_register_fixed_factor(NULL, name,
314 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
315 * @clock_id: Clock ID
316 * @index: Parent index
317 * @response: Parents of the given clock
319 * This function is used to get 3 parents for the clock specified by
322 * This API will return 3 parents with a single response. To get
323 * other parents, master should call same API in loop with new
324 * parent index till error is returned. E.g First call should have
325 * index 0 which will return parents 0,1 and 2. Next call, index
326 * should be 3 which will return parent 3,4 and 5 and so on.
328 * Return: 0 on success else error+reason
330 static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index,
331 struct parents_resp *response)
333 struct zynqmp_pm_query_data qdata = {0};
334 u32 ret_payload[PAYLOAD_ARG_CNT];
337 qdata.qid = PM_QID_CLOCK_GET_PARENTS;
338 qdata.arg1 = clock_id;
341 ret = zynqmp_pm_query_data(qdata, ret_payload);
342 memcpy(response, &ret_payload[1], sizeof(*response));
348 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
349 * @clock_id: Clock ID
350 * @response: Clock attributes response
352 * This function is used to get clock's attributes(e.g. valid, clock type, etc).
354 * Return: 0 on success else error+reason
356 static int zynqmp_pm_clock_get_attributes(u32 clock_id,
357 struct attr_resp *response)
359 struct zynqmp_pm_query_data qdata = {0};
360 u32 ret_payload[PAYLOAD_ARG_CNT];
363 qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
364 qdata.arg1 = clock_id;
366 ret = zynqmp_pm_query_data(qdata, ret_payload);
367 memcpy(response, &ret_payload[1], sizeof(*response));
373 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
375 * @topology: Clock topology
376 * @response: Clock topology data received from firmware
377 * @nnodes: Number of nodes
379 * Return: 0 on success else error+reason
381 static int __zynqmp_clock_get_topology(struct clock_topology *topology,
382 struct topology_resp *response,
388 for (i = 0; i < ARRAY_SIZE(response->topology); i++) {
389 type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);
390 if (type == TYPE_INVALID)
391 return END_OF_TOPOLOGY_NODE;
392 topology[*nnodes].type = type;
393 topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
394 response->topology[i]);
395 topology[*nnodes].type_flag =
396 FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
397 response->topology[i]);
405 * zynqmp_clock_get_topology() - Get topology of clock from firmware using
407 * @clk_id: Clock index
408 * @topology: Clock topology
409 * @num_nodes: Number of nodes
411 * Return: 0 on success else error+reason
413 static int zynqmp_clock_get_topology(u32 clk_id,
414 struct clock_topology *topology,
418 struct topology_resp response = { };
421 for (j = 0; j <= MAX_NODES; j += ARRAY_SIZE(response.topology)) {
422 ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j,
426 ret = __zynqmp_clock_get_topology(topology, &response,
428 if (ret == END_OF_TOPOLOGY_NODE)
436 * __zynqmp_clock_get_parents() - Get parents info of clock from firmware
438 * @parents: Clock parents
439 * @response: Clock parents data received from firmware
440 * @nparent: Number of parent
442 * Return: 0 on success else error+reason
444 static int __zynqmp_clock_get_parents(struct clock_parent *parents,
445 struct parents_resp *response,
449 struct clock_parent *parent;
451 for (i = 0; i < ARRAY_SIZE(response->parents); i++) {
452 if (response->parents[i] == NA_PARENT)
453 return END_OF_PARENTS;
455 parent = &parents[i];
456 parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]);
457 if (response->parents[i] == DUMMY_PARENT) {
458 strcpy(parent->name, "dummy_name");
461 parent->flag = FIELD_GET(CLK_PARENTS_FLAGS,
462 response->parents[i]);
463 if (zynqmp_get_clock_name(parent->id, parent->name))
473 * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
474 * @clk_id: Clock index
475 * @parents: Clock parents
476 * @num_parents: Total number of parents
478 * Return: 0 on success else error+reason
480 static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents,
484 struct parents_resp response = { };
488 /* Get parents from firmware */
489 ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j,
494 ret = __zynqmp_clock_get_parents(&parents[j], &response,
496 if (ret == END_OF_PARENTS)
498 j += ARRAY_SIZE(response.parents);
499 } while (*num_parents <= MAX_PARENT);
505 * zynqmp_get_parent_list() - Create list of parents name
507 * @clk_id: Clock index
508 * @parent_list: List of parent's name
509 * @num_parents: Total number of parents
511 * Return: 0 on success else error+reason
513 static int zynqmp_get_parent_list(struct device_node *np, u32 clk_id,
514 const char **parent_list, u32 *num_parents)
517 u32 total_parents = clock[clk_id].num_parents;
518 struct clock_topology *clk_nodes;
519 struct clock_parent *parents;
521 clk_nodes = clock[clk_id].node;
522 parents = clock[clk_id].parent;
524 for (i = 0; i < total_parents; i++) {
525 if (!parents[i].flag) {
526 parent_list[i] = parents[i].name;
527 } else if (parents[i].flag == PARENT_CLK_EXTERNAL) {
528 ret = of_property_match_string(np, "clock-names",
531 strcpy(parents[i].name, "dummy_name");
532 parent_list[i] = parents[i].name;
534 strcat(parents[i].name,
535 clk_type_postfix[clk_nodes[parents[i].flag - 1].
537 parent_list[i] = parents[i].name;
541 *num_parents = total_parents;
546 * zynqmp_register_clk_topology() - Register clock topology
547 * @clk_id: Clock index
548 * @clk_name: Clock Name
549 * @num_parents: Total number of parents
550 * @parent_names: List of parents name
552 * Return: Returns either clock hardware or error+reason
554 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
556 const char **parent_names)
559 u32 num_nodes, clk_dev_id;
560 char *clk_out = NULL;
561 struct clock_topology *nodes;
562 struct clk_hw *hw = NULL;
564 nodes = clock[clk_id].node;
565 num_nodes = clock[clk_id].num_nodes;
566 clk_dev_id = clock[clk_id].clk_id;
568 for (j = 0; j < num_nodes; j++) {
570 * Clock name received from firmware is output clock name.
571 * Intermediate clock names are postfixed with type of clock.
573 if (j != (num_nodes - 1)) {
574 clk_out = kasprintf(GFP_KERNEL, "%s%s", clk_name,
575 clk_type_postfix[nodes[j].type]);
577 clk_out = kasprintf(GFP_KERNEL, "%s", clk_name);
580 if (!clk_topology[nodes[j].type])
583 hw = (*clk_topology[nodes[j].type])(clk_out, clk_dev_id,
588 pr_warn_once("%s() 0x%x: %s register fail with %ld\n",
589 __func__, clk_dev_id, clk_name,
592 parent_names[0] = clk_out;
599 * zynqmp_register_clocks() - Register clocks
602 * Return: 0 on success else error code
604 static int zynqmp_register_clocks(struct device_node *np)
607 u32 i, total_parents = 0, type = 0;
608 const char *parent_names[MAX_PARENT];
610 for (i = 0; i < clock_max_idx; i++) {
611 char clk_name[MAX_NAME_LEN];
613 /* get clock name, continue to next clock if name not found */
614 if (zynqmp_get_clock_name(i, clk_name))
617 /* Check if clock is valid and output clock.
618 * Do not register invalid or external clock.
620 ret = zynqmp_get_clock_type(i, &type);
621 if (ret || type != CLK_TYPE_OUTPUT)
624 /* Get parents of clock*/
625 if (zynqmp_get_parent_list(np, i, parent_names,
627 WARN_ONCE(1, "No parents found for %s\n",
632 zynqmp_data->hws[i] =
633 zynqmp_register_clk_topology(i, clk_name,
638 for (i = 0; i < clock_max_idx; i++) {
639 if (IS_ERR(zynqmp_data->hws[i])) {
640 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n",
641 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
649 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
651 static void zynqmp_get_clock_info(void)
655 u32 nodetype, subclass, class;
656 struct attr_resp attr;
657 struct name_resp name;
659 for (i = 0; i < clock_max_idx; i++) {
660 ret = zynqmp_pm_clock_get_attributes(i, &attr);
664 clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]);
665 clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ?
666 CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
668 nodetype = FIELD_GET(CLK_ATTR_NODE_TYPE, attr.attr[0]);
669 subclass = FIELD_GET(CLK_ATTR_NODE_SUBCLASS, attr.attr[0]);
670 class = FIELD_GET(CLK_ATTR_NODE_CLASS, attr.attr[0]);
672 clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) |
673 FIELD_PREP(CLK_ATTR_NODE_SUBCLASS, subclass) |
674 FIELD_PREP(CLK_ATTR_NODE_TYPE, nodetype) |
675 FIELD_PREP(CLK_ATTR_NODE_INDEX, i);
677 zynqmp_pm_clock_get_name(clock[i].clk_id, &name);
678 if (!strcmp(name.name, RESERVED_CLK_NAME))
680 strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
683 /* Get topology of all clock */
684 for (i = 0; i < clock_max_idx; i++) {
685 ret = zynqmp_get_clock_type(i, &type);
686 if (ret || type != CLK_TYPE_OUTPUT)
689 ret = zynqmp_clock_get_topology(i, clock[i].node,
690 &clock[i].num_nodes);
694 ret = zynqmp_clock_get_parents(i, clock[i].parent,
695 &clock[i].num_parents);
702 * zynqmp_clk_setup() - Setup the clock framework and register clocks
705 * Return: 0 on success else error code
707 static int zynqmp_clk_setup(struct device_node *np)
711 ret = zynqmp_pm_clock_get_num_clocks(&clock_max_idx);
715 zynqmp_data = kzalloc(struct_size(zynqmp_data, hws, clock_max_idx),
720 clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
726 zynqmp_get_clock_info();
727 zynqmp_register_clocks(np);
729 zynqmp_data->num = clock_max_idx;
730 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, zynqmp_data);
735 static int zynqmp_clock_probe(struct platform_device *pdev)
738 struct device *dev = &pdev->dev;
740 ret = zynqmp_clk_setup(dev->of_node);
745 static const struct of_device_id zynqmp_clock_of_match[] = {
746 {.compatible = "xlnx,zynqmp-clk"},
747 {.compatible = "xlnx,versal-clk"},
750 MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);
752 static struct platform_driver zynqmp_clock_driver = {
754 .name = "zynqmp_clock",
755 .of_match_table = zynqmp_clock_of_match,
757 .probe = zynqmp_clock_probe,
759 module_platform_driver(zynqmp_clock_driver);