1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC mux
5 * Copyright (C) 2016-2018 Xilinx
8 #include <linux/clk-provider.h>
9 #include <linux/slab.h>
10 #include "clk-zynqmp.h"
13 * DOC: basic adjustable multiplexer clock that cannot gate
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is only affected by parent switching. No clk_set_rate support
19 * parent - parent is adjustable through clk_set_parent
23 * struct zynqmp_clk_mux - multiplexer clock
25 * @hw: handle between common and hardware-specific interfaces
26 * @flags: hardware-specific flags
27 * @clk_id: Id of clock
29 struct zynqmp_clk_mux {
35 #define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw)
38 * zynqmp_clk_mux_get_parent() - Get parent of clock
39 * @hw: handle between common and hardware-specific interfaces
41 * Return: Parent index on success or number of parents in case of error
43 static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw)
45 struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
46 const char *clk_name = clk_hw_get_name(hw);
47 u32 clk_id = mux->clk_id;
51 ret = zynqmp_pm_clock_getparent(clk_id, &val);
54 pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n",
55 __func__, clk_name, ret);
57 * clk_core_get_parent_by_index() takes num_parents as incorrect
58 * index which is exactly what I want to return here
60 return clk_hw_get_num_parents(hw);
67 * zynqmp_clk_mux_set_parent() - Set parent of clock
68 * @hw: handle between common and hardware-specific interfaces
69 * @index: Parent index
71 * Return: 0 on success else error+reason
73 static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index)
75 struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);
76 const char *clk_name = clk_hw_get_name(hw);
77 u32 clk_id = mux->clk_id;
80 ret = zynqmp_pm_clock_setparent(clk_id, index);
83 pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n",
84 __func__, clk_name, ret);
89 static const struct clk_ops zynqmp_clk_mux_ops = {
90 .get_parent = zynqmp_clk_mux_get_parent,
91 .set_parent = zynqmp_clk_mux_set_parent,
92 .determine_rate = __clk_mux_determine_rate,
95 static const struct clk_ops zynqmp_clk_mux_ro_ops = {
96 .get_parent = zynqmp_clk_mux_get_parent,
100 * zynqmp_clk_register_mux() - Register a mux table with the clock
102 * @name: Name of this clock
103 * @clk_id: Id of this clock
104 * @parents: Name of this clock's parents
105 * @num_parents: Number of parents
106 * @nodes: Clock topology node
108 * Return: clock hardware of the registered clock mux
110 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
111 const char * const *parents,
113 const struct clock_topology *nodes)
115 struct zynqmp_clk_mux *mux;
117 struct clk_init_data init;
120 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
122 return ERR_PTR(-ENOMEM);
125 if (nodes->type_flag & CLK_MUX_READ_ONLY)
126 init.ops = &zynqmp_clk_mux_ro_ops;
128 init.ops = &zynqmp_clk_mux_ops;
129 init.flags = nodes->flag;
130 init.parent_names = parents;
131 init.num_parents = num_parents;
132 mux->flags = nodes->type_flag;
133 mux->hw.init = &init;
134 mux->clk_id = clk_id;
137 ret = clk_hw_register(NULL, hw);