1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017, Intel Corporation
5 #include <linux/slab.h>
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
12 /* Clock Manager offsets */
13 #define CLK_MGR_PLL_CLK_SRC_SHIFT 16
14 #define CLK_MGR_PLL_CLK_SRC_MASK 0x3
16 /* PLL Clock enable bits */
17 #define SOCFPGA_PLL_POWER 0
18 #define SOCFPGA_PLL_RESET_MASK 0x2
19 #define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
20 #define SOCFPGA_PLL_REFDIV_SHIFT 8
21 #define SOCFPGA_PLL_MDIV_MASK 0xFF000000
22 #define SOCFPGA_PLL_MDIV_SHIFT 24
23 #define SWCTRLBTCLKSEL_MASK 0x200
24 #define SWCTRLBTCLKSEL_SHIFT 9
26 #define SOCFPGA_BOOT_CLK "boot_clk"
28 #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
30 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
31 unsigned long parent_rate)
33 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
37 unsigned long long vco_freq;
39 /* read VCO1 reg for numerator and denominator */
40 reg = readl(socfpgaclk->hw.reg);
41 refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
43 vco_freq = parent_rate;
44 do_div(vco_freq, refdiv);
46 /* Read mdiv and fdiv from the fdbck register */
47 reg = readl(socfpgaclk->hw.reg + 0x4);
48 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
49 vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
51 return (unsigned long)vco_freq;
54 static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
55 unsigned long parent_rate)
57 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
60 div = ((readl(socfpgaclk->hw.reg) &
61 SWCTRLBTCLKSEL_MASK) >>
62 SWCTRLBTCLKSEL_SHIFT);
64 return parent_rate /= div;
68 static u8 clk_pll_get_parent(struct clk_hw *hwclk)
70 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
73 pll_src = readl(socfpgaclk->hw.reg);
74 return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
75 CLK_MGR_PLL_CLK_SRC_MASK;
78 static u8 clk_boot_get_parent(struct clk_hw *hwclk)
80 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
83 pll_src = readl(socfpgaclk->hw.reg);
84 return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
88 static int clk_pll_prepare(struct clk_hw *hwclk)
90 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
93 /* Bring PLL out of reset */
94 reg = readl(socfpgaclk->hw.reg);
95 reg |= SOCFPGA_PLL_RESET_MASK;
96 writel(reg, socfpgaclk->hw.reg);
101 static struct clk_ops clk_pll_ops = {
102 .recalc_rate = clk_pll_recalc_rate,
103 .get_parent = clk_pll_get_parent,
104 .prepare = clk_pll_prepare,
107 static struct clk_ops clk_boot_ops = {
108 .recalc_rate = clk_boot_clk_recalc_rate,
109 .get_parent = clk_boot_get_parent,
110 .prepare = clk_pll_prepare,
113 struct clk *s10_register_pll(const char *name, const char * const *parent_names,
114 u8 num_parents, unsigned long flags,
115 void __iomem *reg, unsigned long offset)
118 struct socfpga_pll *pll_clk;
119 struct clk_init_data init;
121 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
122 if (WARN_ON(!pll_clk))
125 pll_clk->hw.reg = reg + offset;
127 if (streq(name, SOCFPGA_BOOT_CLK))
128 init.ops = &clk_boot_ops;
130 init.ops = &clk_pll_ops;
135 init.num_parents = num_parents;
136 init.parent_names = parent_names;
137 pll_clk->hw.hw.init = &init;
139 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
140 clk_pll_ops.enable = clk_gate_ops.enable;
141 clk_pll_ops.disable = clk_gate_ops.disable;
143 clk = clk_register(NULL, &pll_clk->hw.hw);
144 if (WARN_ON(IS_ERR(clk))) {