drivers/clk/qcom/mmcc-msm8994.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/clk.h>
  17
  18 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-regmap-divider.h"
  23 #include "clk-alpha-pll.h"
  24 #include "clk-rcg.h"
  25 #include "clk-branch.h"
  26 #include "reset.h"
  27 #include "gdsc.h"
  28
  29
  30 enum {
  31         P_XO,
  32         P_GPLL0,
  33         P_MMPLL0,
  34         P_MMPLL1,
  35         P_MMPLL3,
  36         P_MMPLL4,
  37         P_MMPLL5, /* Is this one even used by anything? Downstream doesn't tell. */
  38         P_DSI0PLL,
  39         P_DSI1PLL,
  40         P_DSI0PLL_BYTE,
  41         P_DSI1PLL_BYTE,
  42         P_HDMIPLL,
  43 };
  44 static const struct parent_map mmcc_xo_gpll0_map[] = {
  45         { P_XO, 0 },
  46         { P_GPLL0, 5 }
  47 };
  48
  49 static const struct clk_parent_data mmcc_xo_gpll0[] = {
  50         { .fw_name = "xo" },
  51         { .fw_name = "gpll0" },
  52 };
  53
  54 static const struct parent_map mmss_xo_hdmi_map[] = {
  55         { P_XO, 0 },
  56         { P_HDMIPLL, 3 }
  57 };
  58
  59 static const struct clk_parent_data mmss_xo_hdmi[] = {
  60         { .fw_name = "xo" },
  61         { .fw_name = "hdmipll" },
  62 };
  63
  64 static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
  65         { P_XO, 0 },
  66         { P_DSI0PLL, 1 },
  67         { P_DSI1PLL, 2 }
  68 };
  69
  70 static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
  71         { .fw_name = "xo" },
  72         { .fw_name = "dsi0pll" },
  73         { .fw_name = "dsi1pll" },
  74 };
  75
  76 static const struct parent_map mmcc_xo_dsibyte_map[] = {
  77         { P_XO, 0 },
  78         { P_DSI0PLL_BYTE, 1 },
  79         { P_DSI1PLL_BYTE, 2 }
  80 };
  81
  82 static const struct clk_parent_data mmcc_xo_dsibyte[] = {
  83         { .fw_name = "xo" },
  84         { .fw_name = "dsi0pllbyte" },
  85         { .fw_name = "dsi1pllbyte" },
  86 };
  87
  88 static struct pll_vco mmpll_p_vco[] = {
  89         { 250000000, 500000000, 3 },
  90         { 500000000, 1000000000, 2 },
  91         { 1000000000, 1500000000, 1 },
  92         { 1500000000, 2000000000, 0 },
  93 };
  94
  95 static struct pll_vco mmpll_t_vco[] = {
  96         { 500000000, 1500000000, 0 },
  97 };
  98
  99 static const struct alpha_pll_config mmpll_p_config = {
 100         .post_div_mask = 0xf00,
 101 };
 102
 103 static struct clk_alpha_pll mmpll0_early = {
 104         .offset = 0x0,
 105         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 106         .vco_table = mmpll_p_vco,
 107         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 108         .clkr = {
 109                 .enable_reg = 0x100,
 110                 .enable_mask = BIT(0),
 111                 .hw.init = &(struct clk_init_data){
 112                         .name = "mmpll0_early",
 113                         .parent_data = &(const struct clk_parent_data){
 114                                 .fw_name = "xo",
 115                         },
 116                         .num_parents = 1,
 117                         .ops = &clk_alpha_pll_ops,
 118                 },
 119         },
 120 };
 121
 122 static struct clk_alpha_pll_postdiv mmpll0 = {
 123         .offset = 0x0,
 124         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 125         .width = 4,
 126         .clkr.hw.init = &(struct clk_init_data){
 127                 .name = "mmpll0",
 128                 .parent_hws = (const struct clk_hw *[]){ &mmpll0_early.clkr.hw },
 129                 .num_parents = 1,
 130                 .ops = &clk_alpha_pll_postdiv_ops,
 131                 .flags = CLK_SET_RATE_PARENT,
 132         },
 133 };
 134
 135 static struct clk_alpha_pll mmpll1_early = {
 136         .offset = 0x30,
 137         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 138         .vco_table = mmpll_p_vco,
 139         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 140         .clkr = {
 141                 .enable_reg = 0x100,
 142                 .enable_mask = BIT(1),
 143                 .hw.init = &(struct clk_init_data){
 144                         .name = "mmpll1_early",
 145                         .parent_data = &(const struct clk_parent_data){
 146                                 .fw_name = "xo",
 147                         },
 148                         .num_parents = 1,
 149                         .ops = &clk_alpha_pll_ops,
 150                 }
 151         },
 152 };
 153
 154 static struct clk_alpha_pll_postdiv mmpll1 = {
 155         .offset = 0x30,
 156         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 157         .width = 4,
 158         .clkr.hw.init = &(struct clk_init_data){
 159                 .name = "mmpll1",
 160                 .parent_hws = (const struct clk_hw *[]){ &mmpll1_early.clkr.hw },
 161                 .num_parents = 1,
 162                 .ops = &clk_alpha_pll_postdiv_ops,
 163                 .flags = CLK_SET_RATE_PARENT,
 164         },
 165 };
 166
 167 static struct clk_alpha_pll mmpll3_early = {
 168         .offset = 0x60,
 169         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 170         .vco_table = mmpll_p_vco,
 171         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 172         .clkr.hw.init = &(struct clk_init_data){
 173                 .name = "mmpll3_early",
 174                 .parent_data = &(const struct clk_parent_data){
 175                                 .fw_name = "xo",
 176                 },
 177                 .num_parents = 1,
 178                 .ops = &clk_alpha_pll_ops,
 179         },
 180 };
 181
 182 static struct clk_alpha_pll_postdiv mmpll3 = {
 183         .offset = 0x60,
 184         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 185         .width = 4,
 186         .clkr.hw.init = &(struct clk_init_data){
 187                 .name = "mmpll3",
 188                 .parent_hws = (const struct clk_hw *[]){ &mmpll3_early.clkr.hw },
 189                 .num_parents = 1,
 190                 .ops = &clk_alpha_pll_postdiv_ops,
 191                 .flags = CLK_SET_RATE_PARENT,
 192         },
 193 };
 194
 195 static struct clk_alpha_pll mmpll4_early = {
 196         .offset = 0x90,
 197         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 198         .vco_table = mmpll_t_vco,
 199         .num_vco = ARRAY_SIZE(mmpll_t_vco),
 200         .clkr.hw.init = &(struct clk_init_data){
 201                 .name = "mmpll4_early",
 202                 .parent_data = &(const struct clk_parent_data){
 203                                 .fw_name = "xo",
 204                 },
 205                 .num_parents = 1,
 206                 .ops = &clk_alpha_pll_ops,
 207         },
 208 };
 209
 210 static struct clk_alpha_pll_postdiv mmpll4 = {
 211         .offset = 0x90,
 212         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 213         .width = 2,
 214         .clkr.hw.init = &(struct clk_init_data){
 215                 .name = "mmpll4",
 216                 .parent_hws = (const struct clk_hw *[]){ &mmpll4_early.clkr.hw },
 217                 .num_parents = 1,
 218                 .ops = &clk_alpha_pll_postdiv_ops,
 219                 .flags = CLK_SET_RATE_PARENT,
 220         },
 221 };
 222
 223 static const struct parent_map mmcc_xo_gpll0_mmpll1_map[] = {
 224         { P_XO, 0 },
 225         { P_GPLL0, 5 },
 226         { P_MMPLL1, 2 }
 227 };
 228
 229 static const struct clk_parent_data mmcc_xo_gpll0_mmpll1[] = {
 230         { .fw_name = "xo" },
 231         { .fw_name = "gpll0" },
 232         { .hw = &mmpll1.clkr.hw },
 233 };
 234
 235 static const struct parent_map mmcc_xo_gpll0_mmpll0_map[] = {
 236         { P_XO, 0 },
 237         { P_GPLL0, 5 },
 238         { P_MMPLL0, 1 }
 239 };
 240
 241 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0[] = {
 242         { .fw_name = "xo" },
 243         { .fw_name = "gpll0" },
 244         { .hw = &mmpll0.clkr.hw },
 245 };
 246
 247 static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll3_map[] = {
 248         { P_XO, 0 },
 249         { P_GPLL0, 5 },
 250         { P_MMPLL0, 1 },
 251         { P_MMPLL3, 3 }
 252 };
 253
 254 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll3[] = {
 255         { .fw_name = "xo" },
 256         { .fw_name = "gpll0" },
 257         { .hw = &mmpll0.clkr.hw },
 258         { .hw = &mmpll3.clkr.hw },
 259 };
 260
 261 static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll4_map[] = {
 262         { P_XO, 0 },
 263         { P_GPLL0, 5 },
 264         { P_MMPLL0, 1 },
 265         { P_MMPLL4, 3 }
 266 };
 267
 268 static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll4[] = {
 269         { .fw_name = "xo" },
 270         { .fw_name = "gpll0" },
 271         { .hw = &mmpll0.clkr.hw },
 272         { .hw = &mmpll4.clkr.hw },
 273 };
 274
 275 static struct clk_alpha_pll mmpll5_early = {
 276         .offset = 0xc0,
 277         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 278         .vco_table = mmpll_p_vco,
 279         .num_vco = ARRAY_SIZE(mmpll_p_vco),
 280         .clkr.hw.init = &(struct clk_init_data){
 281                 .name = "mmpll5_early",
 282                 .parent_data = &(const struct clk_parent_data){
 283                                 .fw_name = "xo",
 284                 },
 285                 .num_parents = 1,
 286                 .ops = &clk_alpha_pll_ops,
 287         },
 288 };
 289
 290 static struct clk_alpha_pll_postdiv mmpll5 = {
 291         .offset = 0xc0,
 292         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 293         .width = 4,
 294         .clkr.hw.init = &(struct clk_init_data){
 295                 .name = "mmpll5",
 296                 .parent_hws = (const struct clk_hw *[]){ &mmpll5_early.clkr.hw },
 297                 .num_parents = 1,
 298                 .ops = &clk_alpha_pll_postdiv_ops,
 299                 .flags = CLK_SET_RATE_PARENT,
 300         },
 301 };
 302
 303 static const struct freq_tbl ftbl_ahb_clk_src[] = {
 304         /* Note: There might be more frequencies desired here. */
 305         F(19200000, P_XO, 1, 0, 0),
 306         F(40000000, P_GPLL0, 15, 0, 0),
 307         F(80000000, P_MMPLL0, 10, 0, 0),
 308         { }
 309 };
 310
 311 static struct clk_rcg2 ahb_clk_src = {
 312         .cmd_rcgr = 0x5000,
 313         .hid_width = 5,
 314         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 315         .freq_tbl = ftbl_ahb_clk_src,
 316         .clkr.hw.init = &(struct clk_init_data){
 317                 .name = "ahb_clk_src",
 318                 .parent_data = mmcc_xo_gpll0_mmpll0,
 319                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 320                 .ops = &clk_rcg2_ops,
 321         },
 322 };
 323
 324 static const struct freq_tbl ftbl_axi_clk_src[] = {
 325         F(75000000, P_GPLL0, 8, 0, 0),
 326         F(150000000, P_GPLL0, 4, 0, 0),
 327         F(333430000, P_MMPLL1, 3.5, 0, 0),
 328         F(466800000, P_MMPLL1, 2.5, 0, 0),
 329         { }
 330 };
 331
 332 static const struct freq_tbl ftbl_axi_clk_src_8992[] = {
 333         F(75000000, P_GPLL0, 8, 0, 0),
 334         F(150000000, P_GPLL0, 4, 0, 0),
 335         F(300000000, P_GPLL0, 2, 0, 0),
 336         F(404000000, P_MMPLL1, 2, 0, 0),
 337         { }
 338 };
 339
 340 static struct clk_rcg2 axi_clk_src = {
 341         .cmd_rcgr = 0x5040,
 342         .hid_width = 5,
 343         .parent_map = mmcc_xo_gpll0_mmpll1_map,
 344         .freq_tbl = ftbl_axi_clk_src,
 345         .clkr.hw.init = &(struct clk_init_data){
 346                 .name = "axi_clk_src",
 347                 .parent_data = mmcc_xo_gpll0_mmpll1,
 348                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll1),
 349                 .ops = &clk_rcg2_ops,
 350         },
 351 };
 352
 353 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src[] = {
 354         F(100000000, P_GPLL0, 6, 0, 0),
 355         F(240000000, P_GPLL0, 2.5, 0, 0),
 356         F(266670000, P_MMPLL0, 3, 0, 0),
 357         { }
 358 };
 359
 360 static const struct freq_tbl ftbl_csi0_1_2_3_clk_src_8992[] = {
 361         F(100000000, P_GPLL0, 6, 0, 0),
 362         F(266670000, P_MMPLL0, 3, 0, 0),
 363         { }
 364 };
 365
 366 static struct clk_rcg2 csi0_clk_src = {
 367         .cmd_rcgr = 0x3090,
 368         .hid_width = 5,
 369         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 370         .freq_tbl = ftbl_csi0_1_2_3_clk_src,
 371         .clkr.hw.init = &(struct clk_init_data){
 372                 .name = "csi0_clk_src",
 373                 .parent_data = mmcc_xo_gpll0_mmpll0,
 374                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 375                 .ops = &clk_rcg2_ops,
 376         },
 377 };
 378
 379 static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
 380         F(66670000, P_GPLL0, 9, 0, 0),
 381         F(100000000, P_GPLL0, 6, 0, 0),
 382         F(133330000, P_GPLL0, 4.5, 0, 0),
 383         F(150000000, P_GPLL0, 4, 0, 0),
 384         F(200000000, P_MMPLL0, 4, 0, 0),
 385         F(240000000, P_GPLL0, 2.5, 0, 0),
 386         F(266670000, P_MMPLL0, 3, 0, 0),
 387         F(320000000, P_MMPLL0, 2.5, 0, 0),
 388         F(510000000, P_MMPLL3, 2, 0, 0),
 389         { }
 390 };
 391
 392 static const struct freq_tbl ftbl_vcodec0_clk_src_8992[] = {
 393         F(66670000, P_GPLL0, 9, 0, 0),
 394         F(100000000, P_GPLL0, 6, 0, 0),
 395         F(133330000, P_GPLL0, 4.5, 0, 0),
 396         F(200000000, P_MMPLL0, 4, 0, 0),
 397         F(320000000, P_MMPLL0, 2.5, 0, 0),
 398         F(510000000, P_MMPLL3, 2, 0, 0),
 399         { }
 400 };
 401
 402 static struct clk_rcg2 vcodec0_clk_src = {
 403         .cmd_rcgr = 0x1000,
 404         .mnd_width = 8,
 405         .hid_width = 5,
 406         .parent_map = mmcc_xo_gpll0_mmpll0_mmpll3_map,
 407         .freq_tbl = ftbl_vcodec0_clk_src,
 408         .clkr.hw.init = &(struct clk_init_data){
 409                 .name = "vcodec0_clk_src",
 410                 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll3,
 411                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll3),
 412                 .ops = &clk_rcg2_ops,
 413         },
 414 };
 415
 416 static struct clk_rcg2 csi1_clk_src = {
 417         .cmd_rcgr = 0x3100,
 418         .hid_width = 5,
 419         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 420         .freq_tbl = ftbl_csi0_1_2_3_clk_src,
 421         .clkr.hw.init = &(struct clk_init_data){
 422                 .name = "csi1_clk_src",
 423                 .parent_data = mmcc_xo_gpll0_mmpll0,
 424                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 425                 .ops = &clk_rcg2_ops,
 426         },
 427 };
 428
 429 static struct clk_rcg2 csi2_clk_src = {
 430         .cmd_rcgr = 0x3160,
 431         .hid_width = 5,
 432         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 433         .freq_tbl = ftbl_csi0_1_2_3_clk_src,
 434         .clkr.hw.init = &(struct clk_init_data){
 435                 .name = "csi2_clk_src",
 436                 .parent_data = mmcc_xo_gpll0_mmpll0,
 437                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 438                 .ops = &clk_rcg2_ops,
 439         },
 440 };
 441
 442 static struct clk_rcg2 csi3_clk_src = {
 443         .cmd_rcgr = 0x31c0,
 444         .hid_width = 5,
 445         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 446         .freq_tbl = ftbl_csi0_1_2_3_clk_src,
 447         .clkr.hw.init = &(struct clk_init_data){
 448                 .name = "csi3_clk_src",
 449                 .parent_data = mmcc_xo_gpll0_mmpll0,
 450                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 451                 .ops = &clk_rcg2_ops,
 452         },
 453 };
 454
 455 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
 456         F(80000000, P_GPLL0, 7.5, 0, 0),
 457         F(100000000, P_GPLL0, 6, 0, 0),
 458         F(200000000, P_GPLL0, 3, 0, 0),
 459         F(320000000, P_MMPLL0, 2.5, 0, 0),
 460         F(400000000, P_MMPLL0, 2, 0, 0),
 461         F(480000000, P_MMPLL4, 2, 0, 0),
 462         F(533330000, P_MMPLL0, 1.5, 0, 0),
 463         F(600000000, P_GPLL0, 1, 0, 0),
 464         { }
 465 };
 466
 467 static const struct freq_tbl ftbl_vfe0_1_clk_src_8992[] = {
 468         F(80000000, P_GPLL0, 7.5, 0, 0),
 469         F(100000000, P_GPLL0, 6, 0, 0),
 470         F(200000000, P_GPLL0, 3, 0, 0),
 471         F(320000000, P_MMPLL0, 2.5, 0, 0),
 472         F(480000000, P_MMPLL4, 2, 0, 0),
 473         F(600000000, P_GPLL0, 1, 0, 0),
 474         { }
 475 };
 476
 477 static struct clk_rcg2 vfe0_clk_src = {
 478         .cmd_rcgr = 0x3600,
 479         .hid_width = 5,
 480         .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 481         .freq_tbl = ftbl_vfe0_clk_src,
 482         .clkr.hw.init = &(struct clk_init_data){
 483                 .name = "vfe0_clk_src",
 484                 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 485                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 486                 .ops = &clk_rcg2_ops,
 487         },
 488 };
 489
 490 static const struct freq_tbl ftbl_vfe1_clk_src[] = {
 491         F(80000000, P_GPLL0, 7.5, 0, 0),
 492         F(100000000, P_GPLL0, 6, 0, 0),
 493         F(200000000, P_GPLL0, 3, 0, 0),
 494         F(320000000, P_MMPLL0, 2.5, 0, 0),
 495         F(400000000, P_MMPLL0, 2, 0, 0),
 496         F(533330000, P_MMPLL0, 1.5, 0, 0),
 497         { }
 498 };
 499
 500 static struct clk_rcg2 vfe1_clk_src = {
 501         .cmd_rcgr = 0x3620,
 502         .hid_width = 5,
 503         .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 504         .freq_tbl = ftbl_vfe1_clk_src,
 505         .clkr.hw.init = &(struct clk_init_data){
 506                 .name = "vfe1_clk_src",
 507                 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 508                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 509                 .ops = &clk_rcg2_ops,
 510         },
 511 };
 512
 513 static const struct freq_tbl ftbl_cpp_clk_src[] = {
 514         F(100000000, P_GPLL0, 6, 0, 0),
 515         F(200000000, P_GPLL0, 3, 0, 0),
 516         F(320000000, P_MMPLL0, 2.5, 0, 0),
 517         F(480000000, P_MMPLL4, 2, 0, 0),
 518         F(600000000, P_GPLL0, 1, 0, 0),
 519         F(640000000, P_MMPLL4, 1.5, 0, 0),
 520         { }
 521 };
 522
 523 static const struct freq_tbl ftbl_cpp_clk_src_8992[] = {
 524         F(100000000, P_GPLL0, 6, 0, 0),
 525         F(200000000, P_GPLL0, 3, 0, 0),
 526         F(320000000, P_MMPLL0, 2.5, 0, 0),
 527         F(480000000, P_MMPLL4, 2, 0, 0),
 528         F(640000000, P_MMPLL4, 1.5, 0, 0),
 529         { }
 530 };
 531
 532 static struct clk_rcg2 cpp_clk_src = {
 533         .cmd_rcgr = 0x3640,
 534         .hid_width = 5,
 535         .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 536         .freq_tbl = ftbl_cpp_clk_src,
 537         .clkr.hw.init = &(struct clk_init_data){
 538                 .name = "cpp_clk_src",
 539                 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 540                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 541                 .ops = &clk_rcg2_ops,
 542         },
 543 };
 544
 545 static const struct freq_tbl ftbl_jpeg0_1_clk_src[] = {
 546         F(75000000, P_GPLL0, 8, 0, 0),
 547         F(150000000, P_GPLL0, 4, 0, 0),
 548         F(228570000, P_MMPLL0, 3.5, 0, 0),
 549         F(266670000, P_MMPLL0, 3, 0, 0),
 550         F(320000000, P_MMPLL0, 2.5, 0, 0),
 551         F(480000000, P_MMPLL4, 2, 0, 0),
 552         { }
 553 };
 554
 555 static struct clk_rcg2 jpeg1_clk_src = {
 556         .cmd_rcgr = 0x3520,
 557         .hid_width = 5,
 558         .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 559         .freq_tbl = ftbl_jpeg0_1_clk_src,
 560         .clkr.hw.init = &(struct clk_init_data){
 561                 .name = "jpeg1_clk_src",
 562                 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 563                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 564                 .ops = &clk_rcg2_ops,
 565         },
 566 };
 567
 568 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
 569         F(75000000, P_GPLL0, 8, 0, 0),
 570         F(133330000, P_GPLL0, 4.5, 0, 0),
 571         F(150000000, P_GPLL0, 4, 0, 0),
 572         F(228570000, P_MMPLL0, 3.5, 0, 0),
 573         F(266670000, P_MMPLL0, 3, 0, 0),
 574         F(320000000, P_MMPLL0, 2.5, 0, 0),
 575         { }
 576 };
 577
 578 static struct clk_rcg2 jpeg2_clk_src = {
 579         .cmd_rcgr = 0x3540,
 580         .hid_width = 5,
 581         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 582         .freq_tbl = ftbl_jpeg2_clk_src,
 583         .clkr.hw.init = &(struct clk_init_data){
 584                 .name = "jpeg2_clk_src",
 585                 .parent_data = mmcc_xo_gpll0_mmpll0,
 586                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 587                 .ops = &clk_rcg2_ops,
 588         },
 589 };
 590
 591 static const struct freq_tbl ftbl_csi2phytimer_clk_src[] = {
 592         F(50000000, P_GPLL0, 12, 0, 0),
 593         F(100000000, P_GPLL0, 6, 0, 0),
 594         F(200000000, P_MMPLL0, 4, 0, 0),
 595         { }
 596 };
 597
 598 static struct clk_rcg2 csi2phytimer_clk_src = {
 599         .cmd_rcgr = 0x3060,
 600         .hid_width = 5,
 601         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 602         .freq_tbl = ftbl_csi2phytimer_clk_src,
 603         .clkr.hw.init = &(struct clk_init_data){
 604                 .name = "csi2phytimer_clk_src",
 605                 .parent_data = mmcc_xo_gpll0_mmpll0,
 606                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 607                 .ops = &clk_rcg2_ops,
 608         },
 609 };
 610
 611 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
 612         F(60000000, P_GPLL0, 10, 0, 0),
 613         F(200000000, P_GPLL0, 3, 0, 0),
 614         F(320000000, P_MMPLL0, 2.5, 0, 0),
 615         F(400000000, P_MMPLL0, 2, 0, 0),
 616         { }
 617 };
 618
 619 static struct clk_rcg2 fd_core_clk_src = {
 620         .cmd_rcgr = 0x3b00,
 621         .hid_width = 5,
 622         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 623         .freq_tbl = ftbl_fd_core_clk_src,
 624         .clkr.hw.init = &(struct clk_init_data){
 625                 .name = "fd_core_clk_src",
 626                 .parent_data = mmcc_xo_gpll0_mmpll0,
 627                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 628                 .ops = &clk_rcg2_ops,
 629         },
 630 };
 631
 632 static const struct freq_tbl ftbl_mdp_clk_src[] = {
 633         F(85710000, P_GPLL0, 7, 0, 0),
 634         F(100000000, P_GPLL0, 6, 0, 0),
 635         F(120000000, P_GPLL0, 5, 0, 0),
 636         F(150000000, P_GPLL0, 4, 0, 0),
 637         F(171430000, P_GPLL0, 3.5, 0, 0),
 638         F(200000000, P_GPLL0, 3, 0, 0),
 639         F(240000000, P_GPLL0, 2.5, 0, 0),
 640         F(266670000, P_MMPLL0, 3, 0, 0),
 641         F(300000000, P_GPLL0, 2, 0, 0),
 642         F(320000000, P_MMPLL0, 2.5, 0, 0),
 643         F(400000000, P_MMPLL0, 2, 0, 0),
 644         { }
 645 };
 646
 647 static const struct freq_tbl ftbl_mdp_clk_src_8992[] = {
 648         F(85710000, P_GPLL0, 7, 0, 0),
 649         F(171430000, P_GPLL0, 3.5, 0, 0),
 650         F(200000000, P_GPLL0, 3, 0, 0),
 651         F(240000000, P_GPLL0, 2.5, 0, 0),
 652         F(266670000, P_MMPLL0, 3, 0, 0),
 653         F(320000000, P_MMPLL0, 2.5, 0, 0),
 654         F(400000000, P_MMPLL0, 2, 0, 0),
 655         { }
 656 };
 657
 658 static struct clk_rcg2 mdp_clk_src = {
 659         .cmd_rcgr = 0x2040,
 660         .hid_width = 5,
 661         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 662         .freq_tbl = ftbl_mdp_clk_src,
 663         .clkr.hw.init = &(struct clk_init_data){
 664                 .name = "mdp_clk_src",
 665                 .parent_data = mmcc_xo_gpll0_mmpll0,
 666                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 667                 .ops = &clk_rcg2_ops,
 668         },
 669 };
 670
 671 static struct clk_rcg2 pclk0_clk_src = {
 672         .cmd_rcgr = 0x2000,
 673         .mnd_width = 8,
 674         .hid_width = 5,
 675         .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
 676         .clkr.hw.init = &(struct clk_init_data){
 677                 .name = "pclk0_clk_src",
 678                 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
 679                 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
 680                 .ops = &clk_pixel_ops,
 681                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 682         },
 683 };
 684
 685 static struct clk_rcg2 pclk1_clk_src = {
 686         .cmd_rcgr = 0x2020,
 687         .mnd_width = 8,
 688         .hid_width = 5,
 689         .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
 690         .clkr.hw.init = &(struct clk_init_data){
 691                 .name = "pclk1_clk_src",
 692                 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
 693                 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
 694                 .ops = &clk_pixel_ops,
 695                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 696         },
 697 };
 698
 699 static const struct freq_tbl ftbl_ocmemnoc_clk_src[] = {
 700         F(19200000, P_XO, 1, 0, 0),
 701         F(75000000, P_GPLL0, 8, 0, 0),
 702         F(100000000, P_GPLL0, 6, 0, 0),
 703         F(150000000, P_GPLL0, 4, 0, 0),
 704         F(228570000, P_MMPLL0, 3.5, 0, 0),
 705         F(266670000, P_MMPLL0, 3, 0, 0),
 706         F(320000000, P_MMPLL0, 2.5, 0, 0),
 707         F(400000000, P_MMPLL0, 2, 0, 0),
 708         { }
 709 };
 710
 711 static const struct freq_tbl ftbl_ocmemnoc_clk_src_8992[] = {
 712         F(19200000, P_XO, 1, 0, 0),
 713         F(75000000, P_GPLL0, 8, 0, 0),
 714         F(100000000, P_GPLL0, 6, 0, 0),
 715         F(150000000, P_GPLL0, 4, 0, 0),
 716         F(320000000, P_MMPLL0, 2.5, 0, 0),
 717         F(400000000, P_MMPLL0, 2, 0, 0),
 718         { }
 719 };
 720
 721 static struct clk_rcg2 ocmemnoc_clk_src = {
 722         .cmd_rcgr = 0x5090,
 723         .hid_width = 5,
 724         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 725         .freq_tbl = ftbl_ocmemnoc_clk_src,
 726         .clkr.hw.init = &(struct clk_init_data){
 727                 .name = "ocmemnoc_clk_src",
 728                 .parent_data = mmcc_xo_gpll0_mmpll0,
 729                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 730                 .ops = &clk_rcg2_ops,
 731         },
 732 };
 733
 734 static const struct freq_tbl ftbl_cci_clk_src[] = {
 735         F(19200000, P_XO, 1, 0, 0),
 736         F(37500000, P_GPLL0, 16, 0, 0),
 737         F(50000000, P_GPLL0, 12, 0, 0),
 738         F(100000000, P_GPLL0, 6, 0, 0),
 739         { }
 740 };
 741
 742 static struct clk_rcg2 cci_clk_src = {
 743         .cmd_rcgr = 0x3300,
 744         .mnd_width = 8,
 745         .hid_width = 5,
 746         .parent_map = mmcc_xo_gpll0_map,
 747         .freq_tbl = ftbl_cci_clk_src,
 748         .clkr.hw.init = &(struct clk_init_data){
 749                 .name = "cci_clk_src",
 750                 .parent_data = mmcc_xo_gpll0,
 751                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
 752                 .ops = &clk_rcg2_ops,
 753         },
 754 };
 755
 756 static const struct freq_tbl ftbl_mmss_gp0_1_clk_src[] = {
 757         F(10000, P_XO, 16, 10, 120),
 758         F(24000, P_GPLL0, 16, 1, 50),
 759         F(6000000, P_GPLL0, 10, 1, 10),
 760         F(12000000, P_GPLL0, 10, 1, 5),
 761         F(13000000, P_GPLL0, 4, 13, 150),
 762         F(24000000, P_GPLL0, 5, 1, 5),
 763         { }
 764 };
 765
 766 static struct clk_rcg2 mmss_gp0_clk_src = {
 767         .cmd_rcgr = 0x3420,
 768         .mnd_width = 8,
 769         .hid_width = 5,
 770         .parent_map = mmcc_xo_gpll0_map,
 771         .freq_tbl = ftbl_mmss_gp0_1_clk_src,
 772         .clkr.hw.init = &(struct clk_init_data){
 773                 .name = "mmss_gp0_clk_src",
 774                 .parent_data = mmcc_xo_gpll0,
 775                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
 776                 .ops = &clk_rcg2_ops,
 777         },
 778 };
 779
 780 static struct clk_rcg2 mmss_gp1_clk_src = {
 781         .cmd_rcgr = 0x3450,
 782         .mnd_width = 8,
 783         .hid_width = 5,
 784         .parent_map = mmcc_xo_gpll0_map,
 785         .freq_tbl = ftbl_mmss_gp0_1_clk_src,
 786         .clkr.hw.init = &(struct clk_init_data){
 787                 .name = "mmss_gp1_clk_src",
 788                 .parent_data = mmcc_xo_gpll0,
 789                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
 790                 .ops = &clk_rcg2_ops,
 791         },
 792 };
 793
 794 static struct clk_rcg2 jpeg0_clk_src = {
 795         .cmd_rcgr = 0x3500,
 796         .hid_width = 5,
 797         .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 798         .freq_tbl = ftbl_jpeg0_1_clk_src,
 799         .clkr.hw.init = &(struct clk_init_data){
 800                 .name = "jpeg0_clk_src",
 801                 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 802                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 803                 .ops = &clk_rcg2_ops,
 804         },
 805 };
 806
 807 static struct clk_rcg2 jpeg_dma_clk_src = {
 808         .cmd_rcgr = 0x3560,
 809         .hid_width = 5,
 810         .parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 811         .freq_tbl = ftbl_jpeg0_1_clk_src,
 812         .clkr.hw.init = &(struct clk_init_data){
 813                 .name = "jpeg_dma_clk_src",
 814                 .parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 815                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 816                 .ops = &clk_rcg2_ops,
 817         },
 818 };
 819
 820 static const struct freq_tbl ftbl_mclk0_1_2_3_clk_src[] = {
 821         F(4800000, P_XO, 4, 0, 0),
 822         F(6000000, P_GPLL0, 10, 1, 10),
 823         F(8000000, P_GPLL0, 15, 1, 5),
 824         F(9600000, P_XO, 2, 0, 0),
 825         F(16000000, P_MMPLL0, 10, 1, 5),
 826         F(19200000, P_XO, 1, 0, 0),
 827         F(24000000, P_GPLL0, 5, 1, 5),
 828         F(32000000, P_MMPLL0, 5, 1, 5),
 829         F(48000000, P_GPLL0, 12.5, 0, 0),
 830         F(64000000, P_MMPLL0, 12.5, 0, 0),
 831         { }
 832 };
 833
 834 static const struct freq_tbl ftbl_mclk0_clk_src_8992[] = {
 835         F(4800000, P_XO, 4, 0, 0),
 836         F(6000000, P_MMPLL4, 10, 1, 16),
 837         F(8000000, P_MMPLL4, 10, 1, 12),
 838         F(9600000, P_XO, 2, 0, 0),
 839         F(12000000, P_MMPLL4, 10, 1, 8),
 840         F(16000000, P_MMPLL4, 10, 1, 6),
 841         F(19200000, P_XO, 1, 0, 0),
 842         F(24000000, P_MMPLL4, 10, 1, 4),
 843         F(32000000, P_MMPLL4, 10, 1, 3),
 844         F(48000000, P_MMPLL4, 10, 1, 2),
 845         F(64000000, P_MMPLL4, 15, 0, 0),
 846         { }
 847 };
 848
 849 static const struct freq_tbl ftbl_mclk1_2_3_clk_src_8992[] = {
 850         F(4800000, P_XO, 4, 0, 0),
 851         F(6000000, P_MMPLL4, 10, 1, 16),
 852         F(8000000, P_MMPLL4, 10, 1, 12),
 853         F(9600000, P_XO, 2, 0, 0),
 854         F(16000000, P_MMPLL4, 10, 1, 6),
 855         F(19200000, P_XO, 1, 0, 0),
 856         F(24000000, P_MMPLL4, 10, 1, 4),
 857         F(32000000, P_MMPLL4, 10, 1, 3),
 858         F(48000000, P_MMPLL4, 10, 1, 2),
 859         F(64000000, P_MMPLL4, 15, 0, 0),
 860         { }
 861 };
 862
 863 static struct clk_rcg2 mclk0_clk_src = {
 864         .cmd_rcgr = 0x3360,
 865         .mnd_width = 8,
 866         .hid_width = 5,
 867         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 868         .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
 869         .clkr.hw.init = &(struct clk_init_data){
 870                 .name = "mclk0_clk_src",
 871                 .parent_data = mmcc_xo_gpll0_mmpll0,
 872                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 873                 .ops = &clk_rcg2_ops,
 874         },
 875 };
 876
 877 static struct clk_rcg2 mclk1_clk_src = {
 878         .cmd_rcgr = 0x3390,
 879         .mnd_width = 8,
 880         .hid_width = 5,
 881         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 882         .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
 883         .clkr.hw.init = &(struct clk_init_data){
 884                 .name = "mclk1_clk_src",
 885                 .parent_data = mmcc_xo_gpll0_mmpll0,
 886                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 887                 .ops = &clk_rcg2_ops,
 888         },
 889 };
 890
 891 static struct clk_rcg2 mclk2_clk_src = {
 892         .cmd_rcgr = 0x33c0,
 893         .mnd_width = 8,
 894         .hid_width = 5,
 895         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 896         .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
 897         .clkr.hw.init = &(struct clk_init_data){
 898                 .name = "mclk2_clk_src",
 899                 .parent_data = mmcc_xo_gpll0_mmpll0,
 900                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 901                 .ops = &clk_rcg2_ops,
 902         },
 903 };
 904
 905 static struct clk_rcg2 mclk3_clk_src = {
 906         .cmd_rcgr = 0x33f0,
 907         .mnd_width = 8,
 908         .hid_width = 5,
 909         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 910         .freq_tbl = ftbl_mclk0_1_2_3_clk_src,
 911         .clkr.hw.init = &(struct clk_init_data){
 912                 .name = "mclk3_clk_src",
 913                 .parent_data = mmcc_xo_gpll0_mmpll0,
 914                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 915                 .ops = &clk_rcg2_ops,
 916         },
 917 };
 918
 919 static const struct freq_tbl ftbl_csi0_1phytimer_clk_src[] = {
 920         F(50000000, P_GPLL0, 12, 0, 0),
 921         F(100000000, P_GPLL0, 6, 0, 0),
 922         F(200000000, P_MMPLL0, 4, 0, 0),
 923         { }
 924 };
 925
 926 static struct clk_rcg2 csi0phytimer_clk_src = {
 927         .cmd_rcgr = 0x3000,
 928         .hid_width = 5,
 929         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 930         .freq_tbl = ftbl_csi0_1phytimer_clk_src,
 931         .clkr.hw.init = &(struct clk_init_data){
 932                 .name = "csi0phytimer_clk_src",
 933                 .parent_data = mmcc_xo_gpll0_mmpll0,
 934                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 935                 .ops = &clk_rcg2_ops,
 936         },
 937 };
 938
 939 static struct clk_rcg2 csi1phytimer_clk_src = {
 940         .cmd_rcgr = 0x3030,
 941         .hid_width = 5,
 942         .parent_map = mmcc_xo_gpll0_mmpll0_map,
 943         .freq_tbl = ftbl_csi0_1phytimer_clk_src,
 944         .clkr.hw.init = &(struct clk_init_data){
 945                 .name = "csi1phytimer_clk_src",
 946                 .parent_data = mmcc_xo_gpll0_mmpll0,
 947                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 948                 .ops = &clk_rcg2_ops,
 949         },
 950 };
 951
 952 static struct clk_rcg2 byte0_clk_src = {
 953         .cmd_rcgr = 0x2120,
 954         .hid_width = 5,
 955         .parent_map = mmcc_xo_dsibyte_map,
 956         .clkr.hw.init = &(struct clk_init_data){
 957                 .name = "byte0_clk_src",
 958                 .parent_data = mmcc_xo_dsibyte,
 959                 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
 960                 .ops = &clk_byte2_ops,
 961                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 962         },
 963 };
 964
 965 static struct clk_rcg2 byte1_clk_src = {
 966         .cmd_rcgr = 0x2140,
 967         .hid_width = 5,
 968         .parent_map = mmcc_xo_dsibyte_map,
 969         .clkr.hw.init = &(struct clk_init_data){
 970                 .name = "byte1_clk_src",
 971                 .parent_data = mmcc_xo_dsibyte,
 972                 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
 973                 .ops = &clk_byte2_ops,
 974                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 975         },
 976 };
 977
 978 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 979         F(19200000, P_XO, 1, 0, 0),
 980         { }
 981 };
 982
 983 static struct clk_rcg2 esc0_clk_src = {
 984         .cmd_rcgr = 0x2160,
 985         .hid_width = 5,
 986         .parent_map = mmcc_xo_dsibyte_map,
 987         .freq_tbl = ftbl_mdss_esc0_1_clk,
 988         .clkr.hw.init = &(struct clk_init_data){
 989                 .name = "esc0_clk_src",
 990                 .parent_data = mmcc_xo_dsibyte,
 991                 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
 992                 .ops = &clk_rcg2_ops,
 993         },
 994 };
 995
 996 static struct clk_rcg2 esc1_clk_src = {
 997         .cmd_rcgr = 0x2180,
 998         .hid_width = 5,
 999         .parent_map = mmcc_xo_dsibyte_map,
1000         .freq_tbl = ftbl_mdss_esc0_1_clk,
1001         .clkr.hw.init = &(struct clk_init_data){
1002                 .name = "esc1_clk_src",
1003                 .parent_data = mmcc_xo_dsibyte,
1004                 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
1005                 .ops = &clk_rcg2_ops,
1006         },
1007 };
1008
1009 static struct freq_tbl extpclk_freq_tbl[] = {
1010         { .src = P_HDMIPLL },
1011         { }
1012 };
1013
1014 static struct clk_rcg2 extpclk_clk_src = {
1015         .cmd_rcgr = 0x2060,
1016         .hid_width = 5,
1017         .parent_map = mmss_xo_hdmi_map,
1018         .freq_tbl = extpclk_freq_tbl,
1019         .clkr.hw.init = &(struct clk_init_data){
1020                 .name = "extpclk_clk_src",
1021                 .parent_data = mmss_xo_hdmi,
1022                 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
1023                 .ops = &clk_rcg2_ops,
1024                 .flags = CLK_SET_RATE_PARENT,
1025         },
1026 };
1027
1028 static struct freq_tbl ftbl_hdmi_clk_src[] = {
1029         F(19200000, P_XO, 1, 0, 0),
1030         { }
1031 };
1032
1033 static struct clk_rcg2 hdmi_clk_src = {
1034         .cmd_rcgr = 0x2100,
1035         .hid_width = 5,
1036         .parent_map = mmcc_xo_gpll0_map,
1037         .freq_tbl = ftbl_hdmi_clk_src,
1038         .clkr.hw.init = &(struct clk_init_data){
1039                 .name = "hdmi_clk_src",
1040                 .parent_data = mmcc_xo_gpll0,
1041                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1042                 .ops = &clk_rcg2_ops,
1043         },
1044 };
1045
1046 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1047         F(19200000, P_XO, 1, 0, 0),
1048         { }
1049 };
1050
1051 static struct clk_rcg2 vsync_clk_src = {
1052         .cmd_rcgr = 0x2080,
1053         .hid_width = 5,
1054         .parent_map = mmcc_xo_gpll0_map,
1055         .freq_tbl = ftbl_mdss_vsync_clk,
1056         .clkr.hw.init = &(struct clk_init_data){
1057                 .name = "vsync_clk_src",
1058                 .parent_data = mmcc_xo_gpll0,
1059                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1060                 .ops = &clk_rcg2_ops,
1061         },
1062 };
1063
1064 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
1065         F(19200000, P_XO, 1, 0, 0),
1066         { }
1067 };
1068
1069 static struct clk_rcg2 rbbmtimer_clk_src = {
1070         .cmd_rcgr = 0x4090,
1071         .hid_width = 5,
1072         .parent_map = mmcc_xo_gpll0_map,
1073         .freq_tbl = ftbl_rbbmtimer_clk_src,
1074         .clkr.hw.init = &(struct clk_init_data){
1075                 .name = "rbbmtimer_clk_src",
1076                 .parent_data = mmcc_xo_gpll0,
1077                 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1078                 .ops = &clk_rcg2_ops,
1079         },
1080 };
1081
1082 static struct clk_branch camss_ahb_clk = {
1083         .halt_reg = 0x348c,
1084         .clkr = {
1085                 .enable_reg = 0x348c,
1086                 .enable_mask = BIT(0),
1087                 .hw.init = &(struct clk_init_data){
1088                         .name = "camss_ahb_clk",
1089                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1090                         .num_parents = 1,
1091                         .flags = CLK_SET_RATE_PARENT,
1092                         .ops = &clk_branch2_ops,
1093                 },
1094         },
1095 };
1096
1097 static struct clk_branch camss_cci_cci_ahb_clk = {
1098         .halt_reg = 0x3348,
1099         .clkr = {
1100                 .enable_reg = 0x3348,
1101                 .enable_mask = BIT(0),
1102                 .hw.init = &(struct clk_init_data){
1103                         .name = "camss_cci_cci_ahb_clk",
1104                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1105                         .num_parents = 1,
1106                         .flags = CLK_SET_RATE_PARENT,
1107                         .ops = &clk_branch2_ops,
1108                 },
1109         },
1110 };
1111
1112 static struct clk_branch camss_cci_cci_clk = {
1113         .halt_reg = 0x3344,
1114         .clkr = {
1115                 .enable_reg = 0x3344,
1116                 .enable_mask = BIT(0),
1117                 .hw.init = &(struct clk_init_data){
1118                         .name = "camss_cci_cci_clk",
1119                         .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1120                         .num_parents = 1,
1121                         .ops = &clk_branch2_ops,
1122                 },
1123         },
1124 };
1125
1126 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1127         .halt_reg = 0x36b4,
1128         .clkr = {
1129                 .enable_reg = 0x36b4,
1130                 .enable_mask = BIT(0),
1131                 .hw.init = &(struct clk_init_data){
1132                         .name = "camss_vfe_cpp_ahb_clk",
1133                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1134                         .num_parents = 1,
1135                         .flags = CLK_SET_RATE_PARENT,
1136                         .ops = &clk_branch2_ops,
1137                 },
1138         },
1139 };
1140
1141 static struct clk_branch camss_vfe_cpp_axi_clk = {
1142         .halt_reg = 0x36c4,
1143         .clkr = {
1144                 .enable_reg = 0x36c4,
1145                 .enable_mask = BIT(0),
1146                 .hw.init = &(struct clk_init_data){
1147                         .name = "camss_vfe_cpp_axi_clk",
1148                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1149                         .num_parents = 1,
1150                         .ops = &clk_branch2_ops,
1151                 },
1152         },
1153 };
1154
1155 static struct clk_branch camss_vfe_cpp_clk = {
1156         .halt_reg = 0x36b0,
1157         .clkr = {
1158                 .enable_reg = 0x36b0,
1159                 .enable_mask = BIT(0),
1160                 .hw.init = &(struct clk_init_data){
1161                         .name = "camss_vfe_cpp_clk",
1162                         .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1163                         .num_parents = 1,
1164                         .ops = &clk_branch2_ops,
1165                 },
1166         },
1167 };
1168
1169 static struct clk_branch camss_csi0_ahb_clk = {
1170         .halt_reg = 0x30bc,
1171         .clkr = {
1172                 .enable_reg = 0x30bc,
1173                 .enable_mask = BIT(0),
1174                 .hw.init = &(struct clk_init_data){
1175                         .name = "camss_csi0_ahb_clk",
1176                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1177                         .num_parents = 1,
1178                         .flags = CLK_SET_RATE_PARENT,
1179                         .ops = &clk_branch2_ops,
1180                 },
1181         },
1182 };
1183
1184 static struct clk_branch camss_csi0_clk = {
1185         .halt_reg = 0x30b4,
1186         .clkr = {
1187                 .enable_reg = 0x30b4,
1188                 .enable_mask = BIT(0),
1189                 .hw.init = &(struct clk_init_data){
1190                         .name = "camss_csi0_clk",
1191                         .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1192                         .num_parents = 1,
1193                         .ops = &clk_branch2_ops,
1194                 },
1195         },
1196 };
1197
1198 static struct clk_branch camss_csi0phy_clk = {
1199         .halt_reg = 0x30c4,
1200         .clkr = {
1201                 .enable_reg = 0x30c4,
1202                 .enable_mask = BIT(0),
1203                 .hw.init = &(struct clk_init_data){
1204                         .name = "camss_csi0phy_clk",
1205                         .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1206                         .num_parents = 1,
1207                         .ops = &clk_branch2_ops,
1208                 },
1209         },
1210 };
1211
1212 static struct clk_branch camss_csi0pix_clk = {
1213         .halt_reg = 0x30e4,
1214         .clkr = {
1215                 .enable_reg = 0x30e4,
1216                 .enable_mask = BIT(0),
1217                 .hw.init = &(struct clk_init_data){
1218                         .name = "camss_csi0pix_clk",
1219                         .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1220                         .num_parents = 1,
1221                         .ops = &clk_branch2_ops,
1222                 },
1223         },
1224 };
1225
1226 static struct clk_branch camss_csi0rdi_clk = {
1227         .halt_reg = 0x30d4,
1228         .clkr = {
1229                 .enable_reg = 0x30d4,
1230                 .enable_mask = BIT(0),
1231                 .hw.init = &(struct clk_init_data){
1232                         .name = "camss_csi0rdi_clk",
1233                         .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1234                         .num_parents = 1,
1235                         .ops = &clk_branch2_ops,
1236                 },
1237         },
1238 };
1239
1240 static struct clk_branch camss_csi1_ahb_clk = {
1241         .halt_reg = 0x3128,
1242         .clkr = {
1243                 .enable_reg = 0x3128,
1244                 .enable_mask = BIT(0),
1245                 .hw.init = &(struct clk_init_data){
1246                         .name = "camss_csi1_ahb_clk",
1247                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1248                         .num_parents = 1,
1249                         .flags = CLK_SET_RATE_PARENT,
1250                         .ops = &clk_branch2_ops,
1251                 },
1252         },
1253 };
1254
1255 static struct clk_branch camss_csi1_clk = {
1256         .halt_reg = 0x3124,
1257         .clkr = {
1258                 .enable_reg = 0x3124,
1259                 .enable_mask = BIT(0),
1260                 .hw.init = &(struct clk_init_data){
1261                         .name = "camss_csi1_clk",
1262                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1263                         .num_parents = 1,
1264                         .ops = &clk_branch2_ops,
1265                 },
1266         },
1267 };
1268
1269 static struct clk_branch camss_csi1phy_clk = {
1270         .halt_reg = 0x3134,
1271         .clkr = {
1272                 .enable_reg = 0x3134,
1273                 .enable_mask = BIT(0),
1274                 .hw.init = &(struct clk_init_data){
1275                         .name = "camss_csi1phy_clk",
1276                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1277                         .num_parents = 1,
1278                         .ops = &clk_branch2_ops,
1279                 },
1280         },
1281 };
1282
1283 static struct clk_branch camss_csi1pix_clk = {
1284         .halt_reg = 0x3154,
1285         .clkr = {
1286                 .enable_reg = 0x3154,
1287                 .enable_mask = BIT(0),
1288                 .hw.init = &(struct clk_init_data){
1289                         .name = "camss_csi1pix_clk",
1290                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1291                         .num_parents = 1,
1292                         .ops = &clk_branch2_ops,
1293                 },
1294         },
1295 };
1296
1297 static struct clk_branch camss_csi1rdi_clk = {
1298         .halt_reg = 0x3144,
1299         .clkr = {
1300                 .enable_reg = 0x3144,
1301                 .enable_mask = BIT(0),
1302                 .hw.init = &(struct clk_init_data){
1303                         .name = "camss_csi1rdi_clk",
1304                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1305                         .num_parents = 1,
1306                         .ops = &clk_branch2_ops,
1307                 },
1308         },
1309 };
1310
1311 static struct clk_branch camss_csi2_ahb_clk = {
1312         .halt_reg = 0x3188,
1313         .clkr = {
1314                 .enable_reg = 0x3188,
1315                 .enable_mask = BIT(0),
1316                 .hw.init = &(struct clk_init_data){
1317                         .name = "camss_csi2_ahb_clk",
1318                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1319                         .num_parents = 1,
1320                         .flags = CLK_SET_RATE_PARENT,
1321                         .ops = &clk_branch2_ops,
1322                 },
1323         },
1324 };
1325
1326 static struct clk_branch camss_csi2_clk = {
1327         .halt_reg = 0x3184,
1328         .clkr = {
1329                 .enable_reg = 0x3184,
1330                 .enable_mask = BIT(0),
1331                 .hw.init = &(struct clk_init_data){
1332                         .name = "camss_csi2_clk",
1333                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1334                         .num_parents = 1,
1335                         .ops = &clk_branch2_ops,
1336                 },
1337         },
1338 };
1339
1340 static struct clk_branch camss_csi2phy_clk = {
1341         .halt_reg = 0x3194,
1342         .clkr = {
1343                 .enable_reg = 0x3194,
1344                 .enable_mask = BIT(0),
1345                 .hw.init = &(struct clk_init_data){
1346                         .name = "camss_csi2phy_clk",
1347                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1348                         .num_parents = 1,
1349                         .ops = &clk_branch2_ops,
1350                 },
1351         },
1352 };
1353
1354 static struct clk_branch camss_csi2pix_clk = {
1355         .halt_reg = 0x31b4,
1356         .clkr = {
1357                 .enable_reg = 0x31b4,
1358                 .enable_mask = BIT(0),
1359                 .hw.init = &(struct clk_init_data){
1360                         .name = "camss_csi2pix_clk",
1361                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1362                         .num_parents = 1,
1363                         .ops = &clk_branch2_ops,
1364                 },
1365         },
1366 };
1367
1368 static struct clk_branch camss_csi2rdi_clk = {
1369         .halt_reg = 0x31a4,
1370         .clkr = {
1371                 .enable_reg = 0x31a4,
1372                 .enable_mask = BIT(0),
1373                 .hw.init = &(struct clk_init_data){
1374                         .name = "camss_csi2rdi_clk",
1375                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1376                         .num_parents = 1,
1377                         .ops = &clk_branch2_ops,
1378                 },
1379         },
1380 };
1381
1382 static struct clk_branch camss_csi3_ahb_clk = {
1383         .halt_reg = 0x31e8,
1384         .clkr = {
1385                 .enable_reg = 0x31e8,
1386                 .enable_mask = BIT(0),
1387                 .hw.init = &(struct clk_init_data){
1388                         .name = "camss_csi3_ahb_clk",
1389                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1390                         .num_parents = 1,
1391                         .flags = CLK_SET_RATE_PARENT,
1392                         .ops = &clk_branch2_ops,
1393                 },
1394         },
1395 };
1396
1397 static struct clk_branch camss_csi3_clk = {
1398         .halt_reg = 0x31e4,
1399         .clkr = {
1400                 .enable_reg = 0x31e4,
1401                 .enable_mask = BIT(0),
1402                 .hw.init = &(struct clk_init_data){
1403                         .name = "camss_csi3_clk",
1404                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1405                         .num_parents = 1,
1406                         .ops = &clk_branch2_ops,
1407                 },
1408         },
1409 };
1410
1411 static struct clk_branch camss_csi3phy_clk = {
1412         .halt_reg = 0x31f4,
1413         .clkr = {
1414                 .enable_reg = 0x31f4,
1415                 .enable_mask = BIT(0),
1416                 .hw.init = &(struct clk_init_data){
1417                         .name = "camss_csi3phy_clk",
1418                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1419                         .num_parents = 1,
1420                         .ops = &clk_branch2_ops,
1421                 },
1422         },
1423 };
1424
1425 static struct clk_branch camss_csi3pix_clk = {
1426         .halt_reg = 0x3214,
1427         .clkr = {
1428                 .enable_reg = 0x3214,
1429                 .enable_mask = BIT(0),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "camss_csi3pix_clk",
1432                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1433                         .num_parents = 1,
1434                         .ops = &clk_branch2_ops,
1435                 },
1436         },
1437 };
1438
1439 static struct clk_branch camss_csi3rdi_clk = {
1440         .halt_reg = 0x3204,
1441         .clkr = {
1442                 .enable_reg = 0x3204,
1443                 .enable_mask = BIT(0),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "camss_csi3rdi_clk",
1446                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1447                         .num_parents = 1,
1448                         .ops = &clk_branch2_ops,
1449                 },
1450         },
1451 };
1452
1453 static struct clk_branch camss_csi_vfe0_clk = {
1454         .halt_reg = 0x3704,
1455         .clkr = {
1456                 .enable_reg = 0x3704,
1457                 .enable_mask = BIT(0),
1458                 .hw.init = &(struct clk_init_data){
1459                         .name = "camss_csi_vfe0_clk",
1460                         .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1461                         .num_parents = 1,
1462                         .ops = &clk_branch2_ops,
1463                 },
1464         },
1465 };
1466
1467 static struct clk_branch camss_csi_vfe1_clk = {
1468         .halt_reg = 0x3714,
1469         .clkr = {
1470                 .enable_reg = 0x3714,
1471                 .enable_mask = BIT(0),
1472                 .hw.init = &(struct clk_init_data){
1473                         .name = "camss_csi_vfe1_clk",
1474                         .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1475                         .num_parents = 1,
1476                         .ops = &clk_branch2_ops,
1477                 },
1478         },
1479 };
1480
1481 static struct clk_branch camss_gp0_clk = {
1482         .halt_reg = 0x3444,
1483         .clkr = {
1484                 .enable_reg = 0x3444,
1485                 .enable_mask = BIT(0),
1486                 .hw.init = &(struct clk_init_data){
1487                         .name = "camss_gp0_clk",
1488                         .parent_hws = (const struct clk_hw *[]){ &mmss_gp0_clk_src.clkr.hw },
1489                         .num_parents = 1,
1490                         .ops = &clk_branch2_ops,
1491                 },
1492         },
1493 };
1494
1495 static struct clk_branch camss_gp1_clk = {
1496         .halt_reg = 0x3474,
1497         .clkr = {
1498                 .enable_reg = 0x3474,
1499                 .enable_mask = BIT(0),
1500                 .hw.init = &(struct clk_init_data){
1501                         .name = "camss_gp1_clk",
1502                         .parent_hws = (const struct clk_hw *[]){ &mmss_gp1_clk_src.clkr.hw },
1503                         .num_parents = 1,
1504                         .ops = &clk_branch2_ops,
1505                 },
1506         },
1507 };
1508
1509 static struct clk_branch camss_ispif_ahb_clk = {
1510         .halt_reg = 0x3224,
1511         .clkr = {
1512                 .enable_reg = 0x3224,
1513                 .enable_mask = BIT(0),
1514                 .hw.init = &(struct clk_init_data){
1515                         .name = "camss_ispif_ahb_clk",
1516                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1517                         .num_parents = 1,
1518                         .flags = CLK_SET_RATE_PARENT,
1519                         .ops = &clk_branch2_ops,
1520                 },
1521         },
1522 };
1523
1524 static struct clk_branch camss_jpeg_dma_clk = {
1525         .halt_reg = 0x35c0,
1526         .clkr = {
1527                 .enable_reg = 0x35c0,
1528                 .enable_mask = BIT(0),
1529                 .hw.init = &(struct clk_init_data){
1530                         .name = "camss_jpeg_dma_clk",
1531                         .parent_hws = (const struct clk_hw *[]){ &jpeg_dma_clk_src.clkr.hw },
1532                         .num_parents = 1,
1533                         .ops = &clk_branch2_ops,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch camss_jpeg_jpeg0_clk = {
1539         .halt_reg = 0x35a8,
1540         .clkr = {
1541                 .enable_reg = 0x35a8,
1542                 .enable_mask = BIT(0),
1543                 .hw.init = &(struct clk_init_data){
1544                         .name = "camss_jpeg_jpeg0_clk",
1545                         .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1546                         .num_parents = 1,
1547                         .ops = &clk_branch2_ops,
1548                 },
1549         },
1550 };
1551
1552 static struct clk_branch camss_jpeg_jpeg1_clk = {
1553         .halt_reg = 0x35ac,
1554         .clkr = {
1555                 .enable_reg = 0x35ac,
1556                 .enable_mask = BIT(0),
1557                 .hw.init = &(struct clk_init_data){
1558                         .name = "camss_jpeg_jpeg1_clk",
1559                         .parent_hws = (const struct clk_hw *[]){ &jpeg1_clk_src.clkr.hw },
1560                         .num_parents = 1,
1561                         .ops = &clk_branch2_ops,
1562                 },
1563         },
1564 };
1565
1566 static struct clk_branch camss_jpeg_jpeg2_clk = {
1567         .halt_reg = 0x35b0,
1568         .clkr = {
1569                 .enable_reg = 0x35b0,
1570                 .enable_mask = BIT(0),
1571                 .hw.init = &(struct clk_init_data){
1572                         .name = "camss_jpeg_jpeg2_clk",
1573                         .parent_hws = (const struct clk_hw *[]){ &jpeg2_clk_src.clkr.hw },
1574                         .num_parents = 1,
1575                         .ops = &clk_branch2_ops,
1576                 },
1577         },
1578 };
1579
1580 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1581         .halt_reg = 0x35b4,
1582         .clkr = {
1583                 .enable_reg = 0x35b4,
1584                 .enable_mask = BIT(0),
1585                 .hw.init = &(struct clk_init_data){
1586                         .name = "camss_jpeg_jpeg_ahb_clk",
1587                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1588                         .num_parents = 1,
1589                         .flags = CLK_SET_RATE_PARENT,
1590                         .ops = &clk_branch2_ops,
1591                 },
1592         },
1593 };
1594
1595 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1596         .halt_reg = 0x35b8,
1597         .clkr = {
1598                 .enable_reg = 0x35b8,
1599                 .enable_mask = BIT(0),
1600                 .hw.init = &(struct clk_init_data){
1601                         .name = "camss_jpeg_jpeg_axi_clk",
1602                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1603                         .num_parents = 1,
1604                         .ops = &clk_branch2_ops,
1605                 },
1606         },
1607 };
1608
1609 static struct clk_branch camss_mclk0_clk = {
1610         .halt_reg = 0x3384,
1611         .clkr = {
1612                 .enable_reg = 0x3384,
1613                 .enable_mask = BIT(0),
1614                 .hw.init = &(struct clk_init_data){
1615                         .name = "camss_mclk0_clk",
1616                         .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1617                         .num_parents = 1,
1618                         .ops = &clk_branch2_ops,
1619                 },
1620         },
1621 };
1622
1623 static struct clk_branch camss_mclk1_clk = {
1624         .halt_reg = 0x33b4,
1625         .clkr = {
1626                 .enable_reg = 0x33b4,
1627                 .enable_mask = BIT(0),
1628                 .hw.init = &(struct clk_init_data){
1629                         .name = "camss_mclk1_clk",
1630                         .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1631                         .num_parents = 1,
1632                         .ops = &clk_branch2_ops,
1633                 },
1634         },
1635 };
1636
1637 static struct clk_branch camss_mclk2_clk = {
1638         .halt_reg = 0x33e4,
1639         .clkr = {
1640                 .enable_reg = 0x33e4,
1641                 .enable_mask = BIT(0),
1642                 .hw.init = &(struct clk_init_data){
1643                         .name = "camss_mclk2_clk",
1644                         .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1645                         .num_parents = 1,
1646                         .ops = &clk_branch2_ops,
1647                 },
1648         },
1649 };
1650
1651 static struct clk_branch camss_mclk3_clk = {
1652         .halt_reg = 0x3414,
1653         .clkr = {
1654                 .enable_reg = 0x3414,
1655                 .enable_mask = BIT(0),
1656                 .hw.init = &(struct clk_init_data){
1657                         .name = "camss_mclk3_clk",
1658                         .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1659                         .num_parents = 1,
1660                         .ops = &clk_branch2_ops,
1661                 },
1662         },
1663 };
1664
1665 static struct clk_branch camss_micro_ahb_clk = {
1666         .halt_reg = 0x3494,
1667         .clkr = {
1668                 .enable_reg = 0x3494,
1669                 .enable_mask = BIT(0),
1670                 .hw.init = &(struct clk_init_data){
1671                         .name = "camss_micro_ahb_clk",
1672                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1673                         .num_parents = 1,
1674                         .flags = CLK_SET_RATE_PARENT,
1675                         .ops = &clk_branch2_ops,
1676                 },
1677         },
1678 };
1679
1680 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1681         .halt_reg = 0x3024,
1682         .clkr = {
1683                 .enable_reg = 0x3024,
1684                 .enable_mask = BIT(0),
1685                 .hw.init = &(struct clk_init_data){
1686                         .name = "camss_phy0_csi0phytimer_clk",
1687                         .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1688                         .num_parents = 1,
1689                         .ops = &clk_branch2_ops,
1690                 },
1691         },
1692 };
1693
1694 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1695         .halt_reg = 0x3054,
1696         .clkr = {
1697                 .enable_reg = 0x3054,
1698                 .enable_mask = BIT(0),
1699                 .hw.init = &(struct clk_init_data){
1700                         .name = "camss_phy1_csi1phytimer_clk",
1701                         .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1702                         .num_parents = 1,
1703                         .ops = &clk_branch2_ops,
1704                 },
1705         },
1706 };
1707
1708 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1709         .halt_reg = 0x3084,
1710         .clkr = {
1711                 .enable_reg = 0x3084,
1712                 .enable_mask = BIT(0),
1713                 .hw.init = &(struct clk_init_data){
1714                         .name = "camss_phy2_csi2phytimer_clk",
1715                         .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1716                         .num_parents = 1,
1717                         .ops = &clk_branch2_ops,
1718                 },
1719         },
1720 };
1721
1722 static struct clk_branch camss_top_ahb_clk = {
1723         .halt_reg = 0x3484,
1724         .clkr = {
1725                 .enable_reg = 0x3484,
1726                 .enable_mask = BIT(0),
1727                 .hw.init = &(struct clk_init_data){
1728                         .name = "camss_top_ahb_clk",
1729                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1730                         .num_parents = 1,
1731                         .flags = CLK_SET_RATE_PARENT,
1732                         .ops = &clk_branch2_ops,
1733                 },
1734         },
1735 };
1736
1737 static struct clk_branch camss_vfe_vfe0_clk = {
1738         .halt_reg = 0x36a8,
1739         .clkr = {
1740                 .enable_reg = 0x36a8,
1741                 .enable_mask = BIT(0),
1742                 .hw.init = &(struct clk_init_data){
1743                         .name = "camss_vfe_vfe0_clk",
1744                         .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1745                         .num_parents = 1,
1746                         .ops = &clk_branch2_ops,
1747                 },
1748         },
1749 };
1750
1751 static struct clk_branch camss_vfe_vfe1_clk = {
1752         .halt_reg = 0x36ac,
1753         .clkr = {
1754                 .enable_reg = 0x36ac,
1755                 .enable_mask = BIT(0),
1756                 .hw.init = &(struct clk_init_data){
1757                         .name = "camss_vfe_vfe1_clk",
1758                         .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1759                         .num_parents = 1,
1760                         .ops = &clk_branch2_ops,
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1766         .halt_reg = 0x36b8,
1767         .clkr = {
1768                 .enable_reg = 0x36b8,
1769                 .enable_mask = BIT(0),
1770                 .hw.init = &(struct clk_init_data){
1771                         .name = "camss_vfe_vfe_ahb_clk",
1772                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1773                         .num_parents = 1,
1774                         .flags = CLK_SET_RATE_PARENT,
1775                         .ops = &clk_branch2_ops,
1776                 },
1777         },
1778 };
1779
1780 static struct clk_branch camss_vfe_vfe_axi_clk = {
1781         .halt_reg = 0x36bc,
1782         .clkr = {
1783                 .enable_reg = 0x36bc,
1784                 .enable_mask = BIT(0),
1785                 .hw.init = &(struct clk_init_data){
1786                         .name = "camss_vfe_vfe_axi_clk",
1787                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1788                         .num_parents = 1,
1789                         .ops = &clk_branch2_ops,
1790                 },
1791         },
1792 };
1793
1794 static struct clk_branch fd_ahb_clk = {
1795         .halt_reg = 0x3b74,
1796         .clkr = {
1797                 .enable_reg = 0x3b74,
1798                 .enable_mask = BIT(0),
1799                 .hw.init = &(struct clk_init_data){
1800                         .name = "fd_ahb_clk",
1801                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1802                         .num_parents = 1,
1803                         .ops = &clk_branch2_ops,
1804                 },
1805         },
1806 };
1807
1808 static struct clk_branch fd_axi_clk = {
1809         .halt_reg = 0x3b70,
1810         .clkr = {
1811                 .enable_reg = 0x3b70,
1812                 .enable_mask = BIT(0),
1813                 .hw.init = &(struct clk_init_data){
1814                         .name = "fd_axi_clk",
1815                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1816                         .num_parents = 1,
1817                         .ops = &clk_branch2_ops,
1818                 },
1819         },
1820 };
1821
1822 static struct clk_branch fd_core_clk = {
1823         .halt_reg = 0x3b68,
1824         .clkr = {
1825                 .enable_reg = 0x3b68,
1826                 .enable_mask = BIT(0),
1827                 .hw.init = &(struct clk_init_data){
1828                         .name = "fd_core_clk",
1829                         .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1830                         .num_parents = 1,
1831                         .ops = &clk_branch2_ops,
1832                 },
1833         },
1834 };
1835
1836 static struct clk_branch fd_core_uar_clk = {
1837         .halt_reg = 0x3b6c,
1838         .clkr = {
1839                 .enable_reg = 0x3b6c,
1840                 .enable_mask = BIT(0),
1841                 .hw.init = &(struct clk_init_data){
1842                         .name = "fd_core_uar_clk",
1843                         .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1844                         .num_parents = 1,
1845                         .ops = &clk_branch2_ops,
1846                 },
1847         },
1848 };
1849
1850 static struct clk_branch mdss_ahb_clk = {
1851         .halt_reg = 0x2308,
1852         .halt_check = BRANCH_HALT,
1853         .clkr = {
1854                 .enable_reg = 0x2308,
1855                 .enable_mask = BIT(0),
1856                 .hw.init = &(struct clk_init_data){
1857                         .name = "mdss_ahb_clk",
1858                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1859                         .num_parents = 1,
1860                         .flags = CLK_SET_RATE_PARENT,
1861                         .ops = &clk_branch2_ops,
1862                 },
1863         },
1864 };
1865
1866 static struct clk_branch mdss_axi_clk = {
1867         .halt_reg = 0x2310,
1868         .clkr = {
1869                 .enable_reg = 0x2310,
1870                 .enable_mask = BIT(0),
1871                 .hw.init = &(struct clk_init_data){
1872                         .name = "mdss_axi_clk",
1873                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1874                         .num_parents = 1,
1875                         .flags = CLK_SET_RATE_PARENT,
1876                         .ops = &clk_branch2_ops,
1877                 },
1878         },
1879 };
1880
1881 static struct clk_branch mdss_byte0_clk = {
1882         .halt_reg = 0x233c,
1883         .clkr = {
1884                 .enable_reg = 0x233c,
1885                 .enable_mask = BIT(0),
1886                 .hw.init = &(struct clk_init_data){
1887                         .name = "mdss_byte0_clk",
1888                         .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1889                         .num_parents = 1,
1890                         .flags = CLK_SET_RATE_PARENT,
1891                         .ops = &clk_branch2_ops,
1892                 },
1893         },
1894 };
1895
1896 static struct clk_branch mdss_byte1_clk = {
1897         .halt_reg = 0x2340,
1898         .clkr = {
1899                 .enable_reg = 0x2340,
1900                 .enable_mask = BIT(0),
1901                 .hw.init = &(struct clk_init_data){
1902                         .name = "mdss_byte1_clk",
1903                         .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1904                         .num_parents = 1,
1905                         .flags = CLK_SET_RATE_PARENT,
1906                         .ops = &clk_branch2_ops,
1907                 },
1908         },
1909 };
1910
1911 static struct clk_branch mdss_esc0_clk = {
1912         .halt_reg = 0x2344,
1913         .clkr = {
1914                 .enable_reg = 0x2344,
1915                 .enable_mask = BIT(0),
1916                 .hw.init = &(struct clk_init_data){
1917                         .name = "mdss_esc0_clk",
1918                         .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1919                         .num_parents = 1,
1920                         .flags = CLK_SET_RATE_PARENT,
1921                         .ops = &clk_branch2_ops,
1922                 },
1923         },
1924 };
1925
1926 static struct clk_branch mdss_esc1_clk = {
1927         .halt_reg = 0x2348,
1928         .clkr = {
1929                 .enable_reg = 0x2348,
1930                 .enable_mask = BIT(0),
1931                 .hw.init = &(struct clk_init_data){
1932                         .name = "mdss_esc1_clk",
1933                         .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1934                         .num_parents = 1,
1935                         .flags = CLK_SET_RATE_PARENT,
1936                         .ops = &clk_branch2_ops,
1937                 },
1938         },
1939 };
1940
1941 static struct clk_branch mdss_extpclk_clk = {
1942         .halt_reg = 0x2324,
1943         .clkr = {
1944                 .enable_reg = 0x2324,
1945                 .enable_mask = BIT(0),
1946                 .hw.init = &(struct clk_init_data){
1947                         .name = "mdss_extpclk_clk",
1948                         .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1949                         .num_parents = 1,
1950                         .flags = CLK_SET_RATE_PARENT,
1951                         .ops = &clk_branch2_ops,
1952                 },
1953         },
1954 };
1955
1956 static struct clk_branch mdss_hdmi_ahb_clk = {
1957         .halt_reg = 0x230c,
1958         .clkr = {
1959                 .enable_reg = 0x230c,
1960                 .enable_mask = BIT(0),
1961                 .hw.init = &(struct clk_init_data){
1962                         .name = "mdss_hdmi_ahb_clk",
1963                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1964                         .num_parents = 1,
1965                         .flags = CLK_SET_RATE_PARENT,
1966                         .ops = &clk_branch2_ops,
1967                 },
1968         },
1969 };
1970
1971 static struct clk_branch mdss_hdmi_clk = {
1972         .halt_reg = 0x2338,
1973         .clkr = {
1974                 .enable_reg = 0x2338,
1975                 .enable_mask = BIT(0),
1976                 .hw.init = &(struct clk_init_data){
1977                         .name = "mdss_hdmi_clk",
1978                         .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1979                         .num_parents = 1,
1980                         .flags = CLK_SET_RATE_PARENT,
1981                         .ops = &clk_branch2_ops,
1982                 },
1983         },
1984 };
1985
1986 static struct clk_branch mdss_mdp_clk = {
1987         .halt_reg = 0x231c,
1988         .clkr = {
1989                 .enable_reg = 0x231c,
1990                 .enable_mask = BIT(0),
1991                 .hw.init = &(struct clk_init_data){
1992                         .name = "mdss_mdp_clk",
1993                         .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1994                         .num_parents = 1,
1995                         .flags = CLK_SET_RATE_PARENT,
1996                         .ops = &clk_branch2_ops,
1997                 },
1998         },
1999 };
2000
2001 static struct clk_branch mdss_pclk0_clk = {
2002         .halt_reg = 0x2314,
2003         .clkr = {
2004                 .enable_reg = 0x2314,
2005                 .enable_mask = BIT(0),
2006                 .hw.init = &(struct clk_init_data){
2007                         .name = "mdss_pclk0_clk",
2008                         .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
2009                         .num_parents = 1,
2010                         .flags = CLK_SET_RATE_PARENT,
2011                         .ops = &clk_branch2_ops,
2012                 },
2013         },
2014 };
2015
2016 static struct clk_branch mdss_pclk1_clk = {
2017         .halt_reg = 0x2318,
2018         .clkr = {
2019                 .enable_reg = 0x2318,
2020                 .enable_mask = BIT(0),
2021                 .hw.init = &(struct clk_init_data){
2022                         .name = "mdss_pclk1_clk",
2023                         .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
2024                         .num_parents = 1,
2025                         .flags = CLK_SET_RATE_PARENT,
2026                         .ops = &clk_branch2_ops,
2027                 },
2028         },
2029 };
2030
2031 static struct clk_branch mdss_vsync_clk = {
2032         .halt_reg = 0x2328,
2033         .clkr = {
2034                 .enable_reg = 0x2328,
2035                 .enable_mask = BIT(0),
2036                 .hw.init = &(struct clk_init_data){
2037                         .name = "mdss_vsync_clk",
2038                         .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
2039                         .num_parents = 1,
2040                         .flags = CLK_SET_RATE_PARENT,
2041                         .ops = &clk_branch2_ops,
2042                 },
2043         },
2044 };
2045
2046 static struct clk_branch mmss_misc_ahb_clk = {
2047         .halt_reg = 0x502c,
2048         .clkr = {
2049                 .enable_reg = 0x502c,
2050                 .enable_mask = BIT(0),
2051                 .hw.init = &(struct clk_init_data){
2052                         .name = "mmss_misc_ahb_clk",
2053                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2054                         .num_parents = 1,
2055                         .flags = CLK_SET_RATE_PARENT,
2056                         .ops = &clk_branch2_ops,
2057                 },
2058         },
2059 };
2060
2061 static struct clk_branch mmss_mmssnoc_axi_clk = {
2062         .halt_reg = 0x506c,
2063         .clkr = {
2064                 .enable_reg = 0x506c,
2065                 .enable_mask = BIT(0),
2066                 .hw.init = &(struct clk_init_data){
2067                         .name = "mmss_mmssnoc_axi_clk",
2068                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2069                         .num_parents = 1,
2070                         /* Gating this clock will wreck havoc among MMSS! */
2071                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2072                         .ops = &clk_branch2_ops,
2073                 },
2074         },
2075 };
2076
2077 static struct clk_branch mmss_s0_axi_clk = {
2078         .halt_reg = 0x5064,
2079         .clkr = {
2080                 .enable_reg = 0x5064,
2081                 .enable_mask = BIT(0),
2082                 .hw.init = &(struct clk_init_data){
2083                         .name = "mmss_s0_axi_clk",
2084                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw, },
2085                         .num_parents = 1,
2086                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2087                         .ops = &clk_branch2_ops,
2088                 },
2089         },
2090 };
2091
2092 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2093         .halt_reg = 0x4058,
2094         .clkr = {
2095                 .enable_reg = 0x4058,
2096                 .enable_mask = BIT(0),
2097                 .hw.init = &(struct clk_init_data){
2098                         .name = "ocmemcx_ocmemnoc_clk",
2099                         .parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2100                         .num_parents = 1,
2101                         .flags = CLK_SET_RATE_PARENT,
2102                         .ops = &clk_branch2_ops,
2103                 },
2104         },
2105 };
2106
2107 static struct clk_branch oxili_gfx3d_clk = {
2108         .halt_reg = 0x4028,
2109         .clkr = {
2110                 .enable_reg = 0x4028,
2111                 .enable_mask = BIT(0),
2112                 .hw.init = &(struct clk_init_data){
2113                         .name = "oxili_gfx3d_clk",
2114                         .parent_data = &(const struct clk_parent_data){
2115                                 .fw_name = "oxili_gfx3d_clk_src",
2116                                 .name = "oxili_gfx3d_clk_src"
2117                         },
2118                         .num_parents = 1,
2119                         .flags = CLK_SET_RATE_PARENT,
2120                         .ops = &clk_branch2_ops,
2121                 },
2122         },
2123 };
2124
2125 static struct clk_branch oxili_rbbmtimer_clk = {
2126         .halt_reg = 0x40b0,
2127         .clkr = {
2128                 .enable_reg = 0x40b0,
2129                 .enable_mask = BIT(0),
2130                 .hw.init = &(struct clk_init_data){
2131                         .name = "oxili_rbbmtimer_clk",
2132                         .parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
2133                         .num_parents = 1,
2134                         .flags = CLK_SET_RATE_PARENT,
2135                         .ops = &clk_branch2_ops,
2136                 },
2137         },
2138 };
2139
2140 static struct clk_branch oxilicx_ahb_clk = {
2141         .halt_reg = 0x403c,
2142         .clkr = {
2143                 .enable_reg = 0x403c,
2144                 .enable_mask = BIT(0),
2145                 .hw.init = &(struct clk_init_data){
2146                         .name = "oxilicx_ahb_clk",
2147                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2148                         .num_parents = 1,
2149                         .flags = CLK_SET_RATE_PARENT,
2150                         .ops = &clk_branch2_ops,
2151                 },
2152         },
2153 };
2154
2155 static struct clk_branch venus0_ahb_clk = {
2156         .halt_reg = 0x1030,
2157         .clkr = {
2158                 .enable_reg = 0x1030,
2159                 .enable_mask = BIT(0),
2160                 .hw.init = &(struct clk_init_data){
2161                         .name = "venus0_ahb_clk",
2162                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2163                         .num_parents = 1,
2164                         .flags = CLK_SET_RATE_PARENT,
2165                         .ops = &clk_branch2_ops,
2166                 },
2167         },
2168 };
2169
2170 static struct clk_branch venus0_axi_clk = {
2171         .halt_reg = 0x1034,
2172         .clkr = {
2173                 .enable_reg = 0x1034,
2174                 .enable_mask = BIT(0),
2175                 .hw.init = &(struct clk_init_data){
2176                         .name = "venus0_axi_clk",
2177                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2178                         .num_parents = 1,
2179                         .ops = &clk_branch2_ops,
2180                 },
2181         },
2182 };
2183
2184 static struct clk_branch venus0_ocmemnoc_clk = {
2185         .halt_reg = 0x1038,
2186         .clkr = {
2187                 .enable_reg = 0x1038,
2188                 .enable_mask = BIT(0),
2189                 .hw.init = &(struct clk_init_data){
2190                         .name = "venus0_ocmemnoc_clk",
2191                         .parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2192                         .num_parents = 1,
2193                         .flags = CLK_SET_RATE_PARENT,
2194                         .ops = &clk_branch2_ops,
2195                 },
2196         },
2197 };
2198
2199 static struct clk_branch venus0_vcodec0_clk = {
2200         .halt_reg = 0x1028,
2201         .clkr = {
2202                 .enable_reg = 0x1028,
2203                 .enable_mask = BIT(0),
2204                 .hw.init = &(struct clk_init_data){
2205                         .name = "venus0_vcodec0_clk",
2206                         .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2207                         .num_parents = 1,
2208                         .flags = CLK_SET_RATE_PARENT,
2209                         .ops = &clk_branch2_ops,
2210                 },
2211         },
2212 };
2213
2214 static struct clk_branch venus0_core0_vcodec_clk = {
2215         .halt_reg = 0x1048,
2216         .clkr = {
2217                 .enable_reg = 0x1048,
2218                 .enable_mask = BIT(0),
2219                 .hw.init = &(struct clk_init_data){
2220                         .name = "venus0_core0_vcodec_clk",
2221                         .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2222                         .num_parents = 1,
2223                         .flags = CLK_SET_RATE_PARENT,
2224                         .ops = &clk_branch2_ops,
2225                 },
2226         },
2227 };
2228
2229 static struct clk_branch venus0_core1_vcodec_clk = {
2230         .halt_reg = 0x104c,
2231         .clkr = {
2232                 .enable_reg = 0x104c,
2233                 .enable_mask = BIT(0),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "venus0_core1_vcodec_clk",
2236                         .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2237                         .num_parents = 1,
2238                         .flags = CLK_SET_RATE_PARENT,
2239                         .ops = &clk_branch2_ops,
2240                 },
2241         },
2242 };
2243
2244 static struct clk_branch venus0_core2_vcodec_clk = {
2245         .halt_reg = 0x1054,
2246         .clkr = {
2247                 .enable_reg = 0x1054,
2248                 .enable_mask = BIT(0),
2249                 .hw.init = &(struct clk_init_data){
2250                         .name = "venus0_core2_vcodec_clk",
2251                         .parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2252                         .num_parents = 1,
2253                         .flags = CLK_SET_RATE_PARENT,
2254                         .ops = &clk_branch2_ops,
2255                 },
2256         },
2257 };
2258
2259 static struct gdsc venus_gdsc = {
2260         .gdscr = 0x1024,
2261         .cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2262         .cxc_count = 3,
2263         .pd = {
2264                 .name = "venus_gdsc",
2265         },
2266         .pwrsts = PWRSTS_OFF_ON,
2267 };
2268
2269 static struct gdsc venus_core0_gdsc = {
2270         .gdscr = 0x1040,
2271         .cxcs = (unsigned int []){ 0x1048 },
2272         .cxc_count = 1,
2273         .pd = {
2274                 .name = "venus_core0_gdsc",
2275         },
2276         .pwrsts = PWRSTS_OFF_ON,
2277         .flags = HW_CTRL,
2278 };
2279
2280 static struct gdsc venus_core1_gdsc = {
2281         .gdscr = 0x1044,
2282         .cxcs = (unsigned int []){ 0x104c },
2283         .cxc_count = 1,
2284         .pd = {
2285         .name = "venus_core1_gdsc",
2286         },
2287         .pwrsts = PWRSTS_OFF_ON,
2288         .flags = HW_CTRL,
2289 };
2290
2291 static struct gdsc venus_core2_gdsc = {
2292         .gdscr = 0x1050,
2293         .cxcs = (unsigned int []){ 0x1054 },
2294         .cxc_count = 1,
2295         .pd = {
2296                 .name = "venus_core2_gdsc",
2297         },
2298         .pwrsts = PWRSTS_OFF_ON,
2299         .flags = HW_CTRL,
2300 };
2301
2302 static struct gdsc mdss_gdsc = {
2303         .gdscr = 0x2304,
2304         .cxcs = (unsigned int []){ 0x2310, 0x231c },
2305         .cxc_count = 2,
2306         .pd = {
2307                 .name = "mdss_gdsc",
2308         },
2309         .pwrsts = PWRSTS_OFF_ON,
2310 };
2311
2312 static struct gdsc camss_top_gdsc = {
2313         .gdscr = 0x34a0,
2314         .cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2315         .cxc_count = 3,
2316         .pd = {
2317                 .name = "camss_top_gdsc",
2318         },
2319         .pwrsts = PWRSTS_OFF_ON,
2320 };
2321
2322 static struct gdsc jpeg_gdsc = {
2323         .gdscr = 0x35a4,
2324         .cxcs = (unsigned int []){ 0x35a8 },
2325         .cxc_count = 1,
2326         .pd = {
2327                 .name = "jpeg_gdsc",
2328         },
2329         .parent = &camss_top_gdsc.pd,
2330         .pwrsts = PWRSTS_OFF_ON,
2331 };
2332
2333 static struct gdsc vfe_gdsc = {
2334         .gdscr = 0x36a4,
2335         .cxcs = (unsigned int []){ 0x36bc },
2336         .cxc_count = 1,
2337         .pd = {
2338                 .name = "vfe_gdsc",
2339         },
2340         .parent = &camss_top_gdsc.pd,
2341         .pwrsts = PWRSTS_OFF_ON,
2342 };
2343
2344 static struct gdsc cpp_gdsc = {
2345         .gdscr = 0x36d4,
2346         .cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2347         .cxc_count = 2,
2348         .pd = {
2349                 .name = "cpp_gdsc",
2350         },
2351         .parent = &camss_top_gdsc.pd,
2352         .pwrsts = PWRSTS_OFF_ON,
2353 };
2354
2355 static struct gdsc fd_gdsc = {
2356         .gdscr = 0x3b64,
2357         .cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2358         .pd = {
2359                 .name = "fd_gdsc",
2360         },
2361         .pwrsts = PWRSTS_OFF_ON,
2362 };
2363
2364 static struct gdsc oxili_cx_gdsc = {
2365         .gdscr = 0x4034,
2366         .pd = {
2367                 .name = "oxili_cx_gdsc",
2368         },
2369         .pwrsts = PWRSTS_OFF_ON,
2370         .flags = VOTABLE,
2371 };
2372
2373 static struct gdsc oxili_gx_gdsc = {
2374         .gdscr = 0x4024,
2375         .cxcs = (unsigned int []){ 0x4028 },
2376         .cxc_count = 1,
2377         .pd = {
2378                 .name = "oxili_gx_gdsc",
2379         },
2380         .pwrsts = PWRSTS_OFF_ON,
2381         .parent = &oxili_cx_gdsc.pd,
2382         .flags = CLAMP_IO,
2383         .supply = "VDD_GFX",
2384 };
2385
2386 static struct clk_regmap *mmcc_msm8994_clocks[] = {
2387         [MMPLL0_EARLY] = &mmpll0_early.clkr,
2388         [MMPLL0_PLL] = &mmpll0.clkr,
2389         [MMPLL1_EARLY] = &mmpll1_early.clkr,
2390         [MMPLL1_PLL] = &mmpll1.clkr,
2391         [MMPLL3_EARLY] = &mmpll3_early.clkr,
2392         [MMPLL3_PLL] = &mmpll3.clkr,
2393         [MMPLL4_EARLY] = &mmpll4_early.clkr,
2394         [MMPLL4_PLL] = &mmpll4.clkr,
2395         [MMPLL5_EARLY] = &mmpll5_early.clkr,
2396         [MMPLL5_PLL] = &mmpll5.clkr,
2397         [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2398         [AXI_CLK_SRC] = &axi_clk_src.clkr,
2399         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2400         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2401         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2402         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2403         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2404         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2405         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2406         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2407         [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2408         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2409         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2410         [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2411         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2412         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2413         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2414         [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2415         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2416         [MMSS_GP0_CLK_SRC] = &mmss_gp0_clk_src.clkr,
2417         [MMSS_GP1_CLK_SRC] = &mmss_gp1_clk_src.clkr,
2418         [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
2419         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2420         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2421         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2422         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2423         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2424         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2425         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2426         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2427         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2428         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2429         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2430         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2431         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2432         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2433         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2434         [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2435         [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2436         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2437         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2438         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2439         [CAMSS_VFE_CPP_AXI_CLK] = &camss_vfe_cpp_axi_clk.clkr,
2440         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2441         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2442         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2443         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2444         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2445         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2446         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2447         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2448         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2449         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2450         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2451         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2452         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2453         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2454         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2455         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2456         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2457         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2458         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2459         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2460         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2461         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2462         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2463         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2464         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2465         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2466         [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
2467         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2468         [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2469         [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2470         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2471         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2472         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2473         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2474         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2475         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2476         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2477         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2478         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2479         [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2480         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2481         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2482         [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2483         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2484         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2485         [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2486         [FD_AXI_CLK] = &fd_axi_clk.clkr,
2487         [FD_CORE_CLK] = &fd_core_clk.clkr,
2488         [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2489         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2490         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2491         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2492         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2493         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2494         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2495         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2496         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2497         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2498         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2499         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2500         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2501         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2502         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2503         [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2504         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2505         [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
2506         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2507         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2508         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2509         [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2510         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2511         [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
2512         [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
2513         [VENUS0_CORE2_VCODEC_CLK] = &venus0_core2_vcodec_clk.clkr,
2514 };
2515
2516 static struct gdsc *mmcc_msm8994_gdscs[] = {
2517         [VENUS_GDSC] = &venus_gdsc,
2518         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2519         [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
2520         [VENUS_CORE2_GDSC] = &venus_core2_gdsc,
2521         [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2522         [MDSS_GDSC] = &mdss_gdsc,
2523         [JPEG_GDSC] = &jpeg_gdsc,
2524         [VFE_GDSC] = &vfe_gdsc,
2525         [CPP_GDSC] = &cpp_gdsc,
2526         [OXILI_GX_GDSC] = &oxili_gx_gdsc,
2527         [OXILI_CX_GDSC] = &oxili_cx_gdsc,
2528         [FD_GDSC] = &fd_gdsc,
2529 };
2530
2531 static const struct qcom_reset_map mmcc_msm8994_resets[] = {
2532         [CAMSS_MICRO_BCR] = { 0x3490 },
2533 };
2534
2535 static const struct regmap_config mmcc_msm8994_regmap_config = {
2536         .reg_bits       = 32,
2537         .reg_stride     = 4,
2538         .val_bits       = 32,
2539         .max_register   = 0x5200,
2540         .fast_io        = true,
2541 };
2542
2543 static const struct qcom_cc_desc mmcc_msm8994_desc = {
2544         .config = &mmcc_msm8994_regmap_config,
2545         .clks = mmcc_msm8994_clocks,
2546         .num_clks = ARRAY_SIZE(mmcc_msm8994_clocks),
2547         .resets = mmcc_msm8994_resets,
2548         .num_resets = ARRAY_SIZE(mmcc_msm8994_resets),
2549         .gdscs = mmcc_msm8994_gdscs,
2550         .num_gdscs = ARRAY_SIZE(mmcc_msm8994_gdscs),
2551 };
2552
2553 static const struct of_device_id mmcc_msm8994_match_table[] = {
2554         { .compatible = "qcom,mmcc-msm8992" },
2555         { .compatible = "qcom,mmcc-msm8994" }, /* V2 and V2.1 */
2556         { }
2557 };
2558 MODULE_DEVICE_TABLE(of, mmcc_msm8994_match_table);
2559
2560 static int mmcc_msm8994_probe(struct platform_device *pdev)
2561 {
2562         struct regmap *regmap;
2563
2564         if (of_device_is_compatible(pdev->dev.of_node, "qcom,mmcc-msm8992")) {
2565                 /* MSM8992 features less clocks and some have different freq tables */
2566                 mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG1_CLK] = NULL;
2567                 mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG2_CLK] = NULL;
2568                 mmcc_msm8994_desc.clks[FD_CORE_CLK_SRC] = NULL;
2569                 mmcc_msm8994_desc.clks[FD_CORE_CLK] = NULL;
2570                 mmcc_msm8994_desc.clks[FD_CORE_UAR_CLK] = NULL;
2571                 mmcc_msm8994_desc.clks[FD_AXI_CLK] = NULL;
2572                 mmcc_msm8994_desc.clks[FD_AHB_CLK] = NULL;
2573                 mmcc_msm8994_desc.clks[JPEG1_CLK_SRC] = NULL;
2574                 mmcc_msm8994_desc.clks[JPEG2_CLK_SRC] = NULL;
2575                 mmcc_msm8994_desc.clks[VENUS0_CORE2_VCODEC_CLK] = NULL;
2576
2577                 mmcc_msm8994_desc.gdscs[FD_GDSC] = NULL;
2578                 mmcc_msm8994_desc.gdscs[VENUS_CORE2_GDSC] = NULL;
2579
2580                 axi_clk_src.freq_tbl = ftbl_axi_clk_src_8992;
2581                 cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_8992;
2582                 csi0_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2583                 csi1_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2584                 csi2_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2585                 csi3_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2586                 mclk0_clk_src.freq_tbl = ftbl_mclk0_clk_src_8992;
2587                 mclk1_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2588                 mclk2_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2589                 mclk3_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2590                 mdp_clk_src.freq_tbl = ftbl_mdp_clk_src_8992;
2591                 ocmemnoc_clk_src.freq_tbl = ftbl_ocmemnoc_clk_src_8992;
2592                 vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_8992;
2593                 vfe0_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2594                 vfe1_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2595         }
2596
2597         regmap = qcom_cc_map(pdev, &mmcc_msm8994_desc);
2598         if (IS_ERR(regmap))
2599                 return PTR_ERR(regmap);
2600
2601         clk_alpha_pll_configure(&mmpll0_early, regmap, &mmpll_p_config);
2602         clk_alpha_pll_configure(&mmpll1_early, regmap, &mmpll_p_config);
2603         clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
2604         clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
2605
2606         return qcom_cc_really_probe(pdev, &mmcc_msm8994_desc, regmap);
2607 }
2608
2609 static struct platform_driver mmcc_msm8994_driver = {
2610         .probe          = mmcc_msm8994_probe,
2611         .driver         = {
2612                 .name   = "mmcc-msm8994",
2613                 .of_match_table = mmcc_msm8994_match_table,
2614         },
2615 };
2616 module_platform_driver(mmcc_msm8994_driver);
2617
2618 MODULE_DESCRIPTION("QCOM MMCC MSM8994 Driver");
2619 MODULE_LICENSE("GPL v2");
2620 MODULE_ALIAS("platform:mmcc-msm8994");