drivers/clk/qcom/mmcc-msm8974.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
  18 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_MMPLL0,
  31         P_EDPLINK,
  32         P_MMPLL1,
  33         P_HDMIPLL,
  34         P_GPLL0,
  35         P_EDPVCO,
  36         P_GPLL1,
  37         P_DSI0PLL,
  38         P_DSI0PLL_BYTE,
  39         P_MMPLL2,
  40         P_MMPLL3,
  41         P_DSI1PLL,
  42         P_DSI1PLL_BYTE,
  43 };
  44
  45 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
  46         { P_XO, 0 },
  47         { P_MMPLL0, 1 },
  48         { P_MMPLL1, 2 },
  49         { P_GPLL0, 5 }
  50 };
  51
  52 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
  53         "xo",
  54         "mmpll0_vote",
  55         "mmpll1_vote",
  56         "mmss_gpll0_vote",
  57 };
  58
  59 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
  60         { P_XO, 0 },
  61         { P_MMPLL0, 1 },
  62         { P_HDMIPLL, 4 },
  63         { P_GPLL0, 5 },
  64         { P_DSI0PLL, 2 },
  65         { P_DSI1PLL, 3 }
  66 };
  67
  68 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
  69         "xo",
  70         "mmpll0_vote",
  71         "hdmipll",
  72         "mmss_gpll0_vote",
  73         "dsi0pll",
  74         "dsi1pll",
  75 };
  76
  77 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
  78         { P_XO, 0 },
  79         { P_MMPLL0, 1 },
  80         { P_MMPLL1, 2 },
  81         { P_GPLL0, 5 },
  82         { P_MMPLL3, 3 }
  83 };
  84
  85 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
  86         "xo",
  87         "mmpll0_vote",
  88         "mmpll1_vote",
  89         "mmss_gpll0_vote",
  90         "mmpll3",
  91 };
  92
  93 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
  94         { P_XO, 0 },
  95         { P_MMPLL0, 1 },
  96         { P_MMPLL1, 2 },
  97         { P_GPLL0, 5 },
  98         { P_GPLL1, 4 }
  99 };
 100
 101 static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
 102         "xo",
 103         "mmpll0_vote",
 104         "mmpll1_vote",
 105         "mmss_gpll0_vote",
 106         "gpll1_vote",
 107 };
 108
 109 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
 110         { P_XO, 0 },
 111         { P_EDPLINK, 4 },
 112         { P_HDMIPLL, 3 },
 113         { P_EDPVCO, 5 },
 114         { P_DSI0PLL, 1 },
 115         { P_DSI1PLL, 2 }
 116 };
 117
 118 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
 119         "xo",
 120         "edp_link_clk",
 121         "hdmipll",
 122         "edp_vco_div",
 123         "dsi0pll",
 124         "dsi1pll",
 125 };
 126
 127 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
 128         { P_XO, 0 },
 129         { P_EDPLINK, 4 },
 130         { P_HDMIPLL, 3 },
 131         { P_GPLL0, 5 },
 132         { P_DSI0PLL, 1 },
 133         { P_DSI1PLL, 2 }
 134 };
 135
 136 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
 137         "xo",
 138         "edp_link_clk",
 139         "hdmipll",
 140         "gpll0_vote",
 141         "dsi0pll",
 142         "dsi1pll",
 143 };
 144
 145 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
 146         { P_XO, 0 },
 147         { P_EDPLINK, 4 },
 148         { P_HDMIPLL, 3 },
 149         { P_GPLL0, 5 },
 150         { P_DSI0PLL_BYTE, 1 },
 151         { P_DSI1PLL_BYTE, 2 }
 152 };
 153
 154 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
 155         "xo",
 156         "edp_link_clk",
 157         "hdmipll",
 158         "gpll0_vote",
 159         "dsi0pllbyte",
 160         "dsi1pllbyte",
 161 };
 162
 163 static struct clk_pll mmpll0 = {
 164         .l_reg = 0x0004,
 165         .m_reg = 0x0008,
 166         .n_reg = 0x000c,
 167         .config_reg = 0x0014,
 168         .mode_reg = 0x0000,
 169         .status_reg = 0x001c,
 170         .status_bit = 17,
 171         .clkr.hw.init = &(struct clk_init_data){
 172                 .name = "mmpll0",
 173                 .parent_names = (const char *[]){ "xo" },
 174                 .num_parents = 1,
 175                 .ops = &clk_pll_ops,
 176         },
 177 };
 178
 179 static struct clk_regmap mmpll0_vote = {
 180         .enable_reg = 0x0100,
 181         .enable_mask = BIT(0),
 182         .hw.init = &(struct clk_init_data){
 183                 .name = "mmpll0_vote",
 184                 .parent_names = (const char *[]){ "mmpll0" },
 185                 .num_parents = 1,
 186                 .ops = &clk_pll_vote_ops,
 187         },
 188 };
 189
 190 static struct clk_pll mmpll1 = {
 191         .l_reg = 0x0044,
 192         .m_reg = 0x0048,
 193         .n_reg = 0x004c,
 194         .config_reg = 0x0050,
 195         .mode_reg = 0x0040,
 196         .status_reg = 0x005c,
 197         .status_bit = 17,
 198         .clkr.hw.init = &(struct clk_init_data){
 199                 .name = "mmpll1",
 200                 .parent_names = (const char *[]){ "xo" },
 201                 .num_parents = 1,
 202                 .ops = &clk_pll_ops,
 203         },
 204 };
 205
 206 static struct clk_regmap mmpll1_vote = {
 207         .enable_reg = 0x0100,
 208         .enable_mask = BIT(1),
 209         .hw.init = &(struct clk_init_data){
 210                 .name = "mmpll1_vote",
 211                 .parent_names = (const char *[]){ "mmpll1" },
 212                 .num_parents = 1,
 213                 .ops = &clk_pll_vote_ops,
 214         },
 215 };
 216
 217 static struct clk_pll mmpll2 = {
 218         .l_reg = 0x4104,
 219         .m_reg = 0x4108,
 220         .n_reg = 0x410c,
 221         .config_reg = 0x4110,
 222         .mode_reg = 0x4100,
 223         .status_reg = 0x411c,
 224         .clkr.hw.init = &(struct clk_init_data){
 225                 .name = "mmpll2",
 226                 .parent_names = (const char *[]){ "xo" },
 227                 .num_parents = 1,
 228                 .ops = &clk_pll_ops,
 229         },
 230 };
 231
 232 static struct clk_pll mmpll3 = {
 233         .l_reg = 0x0084,
 234         .m_reg = 0x0088,
 235         .n_reg = 0x008c,
 236         .config_reg = 0x0090,
 237         .mode_reg = 0x0080,
 238         .status_reg = 0x009c,
 239         .status_bit = 17,
 240         .clkr.hw.init = &(struct clk_init_data){
 241                 .name = "mmpll3",
 242                 .parent_names = (const char *[]){ "xo" },
 243                 .num_parents = 1,
 244                 .ops = &clk_pll_ops,
 245         },
 246 };
 247
 248 static struct clk_rcg2 mmss_ahb_clk_src = {
 249         .cmd_rcgr = 0x5000,
 250         .hid_width = 5,
 251         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 252         .clkr.hw.init = &(struct clk_init_data){
 253                 .name = "mmss_ahb_clk_src",
 254                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 255                 .num_parents = 4,
 256                 .ops = &clk_rcg2_ops,
 257         },
 258 };
 259
 260 static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = {
 261         F(19200000, P_XO, 1, 0, 0),
 262         F(37500000, P_GPLL0, 16, 0, 0),
 263         F(50000000, P_GPLL0, 12, 0, 0),
 264         F(75000000, P_GPLL0, 8, 0, 0),
 265         F(100000000, P_GPLL0, 6, 0, 0),
 266         F(150000000, P_GPLL0, 4, 0, 0),
 267         F(200000000, P_MMPLL0, 4, 0, 0),
 268         F(266666666, P_MMPLL0, 3, 0, 0),
 269         { }
 270 };
 271
 272 static struct freq_tbl ftbl_mmss_axi_clk[] = {
 273         F( 19200000, P_XO, 1, 0, 0),
 274         F( 37500000, P_GPLL0, 16, 0, 0),
 275         F( 50000000, P_GPLL0, 12, 0, 0),
 276         F( 75000000, P_GPLL0, 8, 0, 0),
 277         F(100000000, P_GPLL0, 6, 0, 0),
 278         F(150000000, P_GPLL0, 4, 0, 0),
 279         F(291750000, P_MMPLL1, 4, 0, 0),
 280         F(400000000, P_MMPLL0, 2, 0, 0),
 281         F(466800000, P_MMPLL1, 2.5, 0, 0),
 282 };
 283
 284 static struct clk_rcg2 mmss_axi_clk_src = {
 285         .cmd_rcgr = 0x5040,
 286         .hid_width = 5,
 287         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 288         .freq_tbl = ftbl_mmss_axi_clk,
 289         .clkr.hw.init = &(struct clk_init_data){
 290                 .name = "mmss_axi_clk_src",
 291                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 292                 .num_parents = 4,
 293                 .ops = &clk_rcg2_ops,
 294         },
 295 };
 296
 297 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
 298         F( 19200000, P_XO, 1, 0, 0),
 299         F( 37500000, P_GPLL0, 16, 0, 0),
 300         F( 50000000, P_GPLL0, 12, 0, 0),
 301         F( 75000000, P_GPLL0, 8, 0, 0),
 302         F(100000000, P_GPLL0, 6, 0, 0),
 303         F(150000000, P_GPLL0, 4, 0, 0),
 304         F(291750000, P_MMPLL1, 4, 0, 0),
 305         F(400000000, P_MMPLL0, 2, 0, 0),
 306 };
 307
 308 static struct clk_rcg2 ocmemnoc_clk_src = {
 309         .cmd_rcgr = 0x5090,
 310         .hid_width = 5,
 311         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 312         .freq_tbl = ftbl_ocmemnoc_clk,
 313         .clkr.hw.init = &(struct clk_init_data){
 314                 .name = "ocmemnoc_clk_src",
 315                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 316                 .num_parents = 4,
 317                 .ops = &clk_rcg2_ops,
 318         },
 319 };
 320
 321 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
 322         F(100000000, P_GPLL0, 6, 0, 0),
 323         F(200000000, P_MMPLL0, 4, 0, 0),
 324         { }
 325 };
 326
 327 static struct clk_rcg2 csi0_clk_src = {
 328         .cmd_rcgr = 0x3090,
 329         .hid_width = 5,
 330         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 331         .freq_tbl = ftbl_camss_csi0_3_clk,
 332         .clkr.hw.init = &(struct clk_init_data){
 333                 .name = "csi0_clk_src",
 334                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 335                 .num_parents = 4,
 336                 .ops = &clk_rcg2_ops,
 337         },
 338 };
 339
 340 static struct clk_rcg2 csi1_clk_src = {
 341         .cmd_rcgr = 0x3100,
 342         .hid_width = 5,
 343         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 344         .freq_tbl = ftbl_camss_csi0_3_clk,
 345         .clkr.hw.init = &(struct clk_init_data){
 346                 .name = "csi1_clk_src",
 347                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 348                 .num_parents = 4,
 349                 .ops = &clk_rcg2_ops,
 350         },
 351 };
 352
 353 static struct clk_rcg2 csi2_clk_src = {
 354         .cmd_rcgr = 0x3160,
 355         .hid_width = 5,
 356         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 357         .freq_tbl = ftbl_camss_csi0_3_clk,
 358         .clkr.hw.init = &(struct clk_init_data){
 359                 .name = "csi2_clk_src",
 360                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 361                 .num_parents = 4,
 362                 .ops = &clk_rcg2_ops,
 363         },
 364 };
 365
 366 static struct clk_rcg2 csi3_clk_src = {
 367         .cmd_rcgr = 0x31c0,
 368         .hid_width = 5,
 369         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 370         .freq_tbl = ftbl_camss_csi0_3_clk,
 371         .clkr.hw.init = &(struct clk_init_data){
 372                 .name = "csi3_clk_src",
 373                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 374                 .num_parents = 4,
 375                 .ops = &clk_rcg2_ops,
 376         },
 377 };
 378
 379 static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = {
 380         F(37500000, P_GPLL0, 16, 0, 0),
 381         F(50000000, P_GPLL0, 12, 0, 0),
 382         F(60000000, P_GPLL0, 10, 0, 0),
 383         F(80000000, P_GPLL0, 7.5, 0, 0),
 384         F(100000000, P_GPLL0, 6, 0, 0),
 385         F(109090000, P_GPLL0, 5.5, 0, 0),
 386         F(133330000, P_GPLL0, 4.5, 0, 0),
 387         F(150000000, P_GPLL0, 4, 0, 0),
 388         F(200000000, P_GPLL0, 3, 0, 0),
 389         F(228570000, P_MMPLL0, 3.5, 0, 0),
 390         F(266670000, P_MMPLL0, 3, 0, 0),
 391         F(320000000, P_MMPLL0, 2.5, 0, 0),
 392         F(400000000, P_MMPLL0, 2, 0, 0),
 393         { }
 394 };
 395
 396 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
 397         F(37500000, P_GPLL0, 16, 0, 0),
 398         F(50000000, P_GPLL0, 12, 0, 0),
 399         F(60000000, P_GPLL0, 10, 0, 0),
 400         F(80000000, P_GPLL0, 7.5, 0, 0),
 401         F(100000000, P_GPLL0, 6, 0, 0),
 402         F(109090000, P_GPLL0, 5.5, 0, 0),
 403         F(133330000, P_GPLL0, 4.5, 0, 0),
 404         F(200000000, P_GPLL0, 3, 0, 0),
 405         F(228570000, P_MMPLL0, 3.5, 0, 0),
 406         F(266670000, P_MMPLL0, 3, 0, 0),
 407         F(320000000, P_MMPLL0, 2.5, 0, 0),
 408         F(400000000, P_MMPLL0, 2, 0, 0),
 409         F(465000000, P_MMPLL3, 2, 0, 0),
 410         { }
 411 };
 412
 413 static struct clk_rcg2 vfe0_clk_src = {
 414         .cmd_rcgr = 0x3600,
 415         .hid_width = 5,
 416         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 417         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 418         .clkr.hw.init = &(struct clk_init_data){
 419                 .name = "vfe0_clk_src",
 420                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 421                 .num_parents = 4,
 422                 .ops = &clk_rcg2_ops,
 423         },
 424 };
 425
 426 static struct clk_rcg2 vfe1_clk_src = {
 427         .cmd_rcgr = 0x3620,
 428         .hid_width = 5,
 429         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 430         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 431         .clkr.hw.init = &(struct clk_init_data){
 432                 .name = "vfe1_clk_src",
 433                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 434                 .num_parents = 4,
 435                 .ops = &clk_rcg2_ops,
 436         },
 437 };
 438
 439 static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = {
 440         F(37500000, P_GPLL0, 16, 0, 0),
 441         F(60000000, P_GPLL0, 10, 0, 0),
 442         F(75000000, P_GPLL0, 8, 0, 0),
 443         F(92310000, P_GPLL0, 6.5, 0, 0),
 444         F(100000000, P_GPLL0, 6, 0, 0),
 445         F(133330000, P_MMPLL0, 6, 0, 0),
 446         F(177780000, P_MMPLL0, 4.5, 0, 0),
 447         F(200000000, P_MMPLL0, 4, 0, 0),
 448         { }
 449 };
 450
 451 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
 452         F(37500000, P_GPLL0, 16, 0, 0),
 453         F(60000000, P_GPLL0, 10, 0, 0),
 454         F(75000000, P_GPLL0, 8, 0, 0),
 455         F(85710000, P_GPLL0, 7, 0, 0),
 456         F(100000000, P_GPLL0, 6, 0, 0),
 457         F(133330000, P_MMPLL0, 6, 0, 0),
 458         F(160000000, P_MMPLL0, 5, 0, 0),
 459         F(200000000, P_MMPLL0, 4, 0, 0),
 460         F(228570000, P_MMPLL0, 3.5, 0, 0),
 461         F(240000000, P_GPLL0, 2.5, 0, 0),
 462         F(266670000, P_MMPLL0, 3, 0, 0),
 463         F(320000000, P_MMPLL0, 2.5, 0, 0),
 464         { }
 465 };
 466
 467 static struct clk_rcg2 mdp_clk_src = {
 468         .cmd_rcgr = 0x2040,
 469         .hid_width = 5,
 470         .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
 471         .freq_tbl = ftbl_mdss_mdp_clk,
 472         .clkr.hw.init = &(struct clk_init_data){
 473                 .name = "mdp_clk_src",
 474                 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
 475                 .num_parents = 6,
 476                 .ops = &clk_rcg2_ops,
 477         },
 478 };
 479
 480 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
 481         F(75000000, P_GPLL0, 8, 0, 0),
 482         F(133330000, P_GPLL0, 4.5, 0, 0),
 483         F(200000000, P_GPLL0, 3, 0, 0),
 484         F(228570000, P_MMPLL0, 3.5, 0, 0),
 485         F(266670000, P_MMPLL0, 3, 0, 0),
 486         F(320000000, P_MMPLL0, 2.5, 0, 0),
 487         { }
 488 };
 489
 490 static struct clk_rcg2 jpeg0_clk_src = {
 491         .cmd_rcgr = 0x3500,
 492         .hid_width = 5,
 493         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 494         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 495         .clkr.hw.init = &(struct clk_init_data){
 496                 .name = "jpeg0_clk_src",
 497                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 498                 .num_parents = 4,
 499                 .ops = &clk_rcg2_ops,
 500         },
 501 };
 502
 503 static struct clk_rcg2 jpeg1_clk_src = {
 504         .cmd_rcgr = 0x3520,
 505         .hid_width = 5,
 506         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 507         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 508         .clkr.hw.init = &(struct clk_init_data){
 509                 .name = "jpeg1_clk_src",
 510                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 511                 .num_parents = 4,
 512                 .ops = &clk_rcg2_ops,
 513         },
 514 };
 515
 516 static struct clk_rcg2 jpeg2_clk_src = {
 517         .cmd_rcgr = 0x3540,
 518         .hid_width = 5,
 519         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 520         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 521         .clkr.hw.init = &(struct clk_init_data){
 522                 .name = "jpeg2_clk_src",
 523                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 524                 .num_parents = 4,
 525                 .ops = &clk_rcg2_ops,
 526         },
 527 };
 528
 529 static struct clk_rcg2 pclk0_clk_src = {
 530         .cmd_rcgr = 0x2000,
 531         .mnd_width = 8,
 532         .hid_width = 5,
 533         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 534         .clkr.hw.init = &(struct clk_init_data){
 535                 .name = "pclk0_clk_src",
 536                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 537                 .num_parents = 6,
 538                 .ops = &clk_pixel_ops,
 539                 .flags = CLK_SET_RATE_PARENT,
 540         },
 541 };
 542
 543 static struct clk_rcg2 pclk1_clk_src = {
 544         .cmd_rcgr = 0x2020,
 545         .mnd_width = 8,
 546         .hid_width = 5,
 547         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 548         .clkr.hw.init = &(struct clk_init_data){
 549                 .name = "pclk1_clk_src",
 550                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 551                 .num_parents = 6,
 552                 .ops = &clk_pixel_ops,
 553                 .flags = CLK_SET_RATE_PARENT,
 554         },
 555 };
 556
 557 static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = {
 558         F(66700000, P_GPLL0, 9, 0, 0),
 559         F(100000000, P_GPLL0, 6, 0, 0),
 560         F(133330000, P_MMPLL0, 6, 0, 0),
 561         F(160000000, P_MMPLL0, 5, 0, 0),
 562         { }
 563 };
 564
 565 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
 566         F(50000000, P_GPLL0, 12, 0, 0),
 567         F(100000000, P_GPLL0, 6, 0, 0),
 568         F(133330000, P_MMPLL0, 6, 0, 0),
 569         F(200000000, P_MMPLL0, 4, 0, 0),
 570         F(266670000, P_MMPLL0, 3, 0, 0),
 571         F(465000000, P_MMPLL3, 2, 0, 0),
 572         { }
 573 };
 574
 575 static struct clk_rcg2 vcodec0_clk_src = {
 576         .cmd_rcgr = 0x1000,
 577         .mnd_width = 8,
 578         .hid_width = 5,
 579         .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
 580         .freq_tbl = ftbl_venus0_vcodec0_clk,
 581         .clkr.hw.init = &(struct clk_init_data){
 582                 .name = "vcodec0_clk_src",
 583                 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
 584                 .num_parents = 5,
 585                 .ops = &clk_rcg2_ops,
 586         },
 587 };
 588
 589 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
 590         F(19200000, P_XO, 1, 0, 0),
 591         { }
 592 };
 593
 594 static struct clk_rcg2 cci_clk_src = {
 595         .cmd_rcgr = 0x3300,
 596         .hid_width = 5,
 597         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 598         .freq_tbl = ftbl_camss_cci_cci_clk,
 599         .clkr.hw.init = &(struct clk_init_data){
 600                 .name = "cci_clk_src",
 601                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 602                 .num_parents = 4,
 603                 .ops = &clk_rcg2_ops,
 604         },
 605 };
 606
 607 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
 608         F(10000, P_XO, 16, 1, 120),
 609         F(24000, P_XO, 16, 1, 50),
 610         F(6000000, P_GPLL0, 10, 1, 10),
 611         F(12000000, P_GPLL0, 10, 1, 5),
 612         F(13000000, P_GPLL0, 4, 13, 150),
 613         F(24000000, P_GPLL0, 5, 1, 5),
 614         { }
 615 };
 616
 617 static struct clk_rcg2 camss_gp0_clk_src = {
 618         .cmd_rcgr = 0x3420,
 619         .mnd_width = 8,
 620         .hid_width = 5,
 621         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 622         .freq_tbl = ftbl_camss_gp0_1_clk,
 623         .clkr.hw.init = &(struct clk_init_data){
 624                 .name = "camss_gp0_clk_src",
 625                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 626                 .num_parents = 5,
 627                 .ops = &clk_rcg2_ops,
 628         },
 629 };
 630
 631 static struct clk_rcg2 camss_gp1_clk_src = {
 632         .cmd_rcgr = 0x3450,
 633         .mnd_width = 8,
 634         .hid_width = 5,
 635         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 636         .freq_tbl = ftbl_camss_gp0_1_clk,
 637         .clkr.hw.init = &(struct clk_init_data){
 638                 .name = "camss_gp1_clk_src",
 639                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 640                 .num_parents = 5,
 641                 .ops = &clk_rcg2_ops,
 642         },
 643 };
 644
 645 static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = {
 646         F(19200000, P_XO, 1, 0, 0),
 647         F(24000000, P_GPLL0, 5, 1, 5),
 648         F(66670000, P_GPLL0, 9, 0, 0),
 649         { }
 650 };
 651
 652 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
 653         F(4800000, P_XO, 4, 0, 0),
 654         F(6000000, P_GPLL0, 10, 1, 10),
 655         F(8000000, P_GPLL0, 15, 1, 5),
 656         F(9600000, P_XO, 2, 0, 0),
 657         F(16000000, P_GPLL0, 12.5, 1, 3),
 658         F(19200000, P_XO, 1, 0, 0),
 659         F(24000000, P_GPLL0, 5, 1, 5),
 660         F(32000000, P_MMPLL0, 5, 1, 5),
 661         F(48000000, P_GPLL0, 12.5, 0, 0),
 662         F(64000000, P_MMPLL0, 12.5, 0, 0),
 663         F(66670000, P_GPLL0, 9, 0, 0),
 664         { }
 665 };
 666
 667 static struct clk_rcg2 mclk0_clk_src = {
 668         .cmd_rcgr = 0x3360,
 669         .hid_width = 5,
 670         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 671         .freq_tbl = ftbl_camss_mclk0_3_clk,
 672         .clkr.hw.init = &(struct clk_init_data){
 673                 .name = "mclk0_clk_src",
 674                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 675                 .num_parents = 4,
 676                 .ops = &clk_rcg2_ops,
 677         },
 678 };
 679
 680 static struct clk_rcg2 mclk1_clk_src = {
 681         .cmd_rcgr = 0x3390,
 682         .hid_width = 5,
 683         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 684         .freq_tbl = ftbl_camss_mclk0_3_clk,
 685         .clkr.hw.init = &(struct clk_init_data){
 686                 .name = "mclk1_clk_src",
 687                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 688                 .num_parents = 4,
 689                 .ops = &clk_rcg2_ops,
 690         },
 691 };
 692
 693 static struct clk_rcg2 mclk2_clk_src = {
 694         .cmd_rcgr = 0x33c0,
 695         .hid_width = 5,
 696         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 697         .freq_tbl = ftbl_camss_mclk0_3_clk,
 698         .clkr.hw.init = &(struct clk_init_data){
 699                 .name = "mclk2_clk_src",
 700                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 701                 .num_parents = 4,
 702                 .ops = &clk_rcg2_ops,
 703         },
 704 };
 705
 706 static struct clk_rcg2 mclk3_clk_src = {
 707         .cmd_rcgr = 0x33f0,
 708         .hid_width = 5,
 709         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 710         .freq_tbl = ftbl_camss_mclk0_3_clk,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "mclk3_clk_src",
 713                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 714                 .num_parents = 4,
 715                 .ops = &clk_rcg2_ops,
 716         },
 717 };
 718
 719 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
 720         F(100000000, P_GPLL0, 6, 0, 0),
 721         F(200000000, P_MMPLL0, 4, 0, 0),
 722         { }
 723 };
 724
 725 static struct clk_rcg2 csi0phytimer_clk_src = {
 726         .cmd_rcgr = 0x3000,
 727         .hid_width = 5,
 728         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 729         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 730         .clkr.hw.init = &(struct clk_init_data){
 731                 .name = "csi0phytimer_clk_src",
 732                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 733                 .num_parents = 4,
 734                 .ops = &clk_rcg2_ops,
 735         },
 736 };
 737
 738 static struct clk_rcg2 csi1phytimer_clk_src = {
 739         .cmd_rcgr = 0x3030,
 740         .hid_width = 5,
 741         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 742         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 743         .clkr.hw.init = &(struct clk_init_data){
 744                 .name = "csi1phytimer_clk_src",
 745                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 746                 .num_parents = 4,
 747                 .ops = &clk_rcg2_ops,
 748         },
 749 };
 750
 751 static struct clk_rcg2 csi2phytimer_clk_src = {
 752         .cmd_rcgr = 0x3060,
 753         .hid_width = 5,
 754         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 755         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 756         .clkr.hw.init = &(struct clk_init_data){
 757                 .name = "csi2phytimer_clk_src",
 758                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 759                 .num_parents = 4,
 760                 .ops = &clk_rcg2_ops,
 761         },
 762 };
 763
 764 static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = {
 765         F(133330000, P_GPLL0, 4.5, 0, 0),
 766         F(150000000, P_GPLL0, 4, 0, 0),
 767         F(266670000, P_MMPLL0, 3, 0, 0),
 768         F(320000000, P_MMPLL0, 2.5, 0, 0),
 769         F(400000000, P_MMPLL0, 2, 0, 0),
 770         { }
 771 };
 772
 773 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
 774         F(133330000, P_GPLL0, 4.5, 0, 0),
 775         F(266670000, P_MMPLL0, 3, 0, 0),
 776         F(320000000, P_MMPLL0, 2.5, 0, 0),
 777         F(400000000, P_MMPLL0, 2, 0, 0),
 778         F(465000000, P_MMPLL3, 2, 0, 0),
 779         { }
 780 };
 781
 782 static struct clk_rcg2 cpp_clk_src = {
 783         .cmd_rcgr = 0x3640,
 784         .hid_width = 5,
 785         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 786         .freq_tbl = ftbl_camss_vfe_cpp_clk,
 787         .clkr.hw.init = &(struct clk_init_data){
 788                 .name = "cpp_clk_src",
 789                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 790                 .num_parents = 4,
 791                 .ops = &clk_rcg2_ops,
 792         },
 793 };
 794
 795 static struct freq_tbl byte_freq_tbl[] = {
 796         { .src = P_DSI0PLL_BYTE },
 797         { }
 798 };
 799
 800 static struct clk_rcg2 byte0_clk_src = {
 801         .cmd_rcgr = 0x2120,
 802         .hid_width = 5,
 803         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 804         .freq_tbl = byte_freq_tbl,
 805         .clkr.hw.init = &(struct clk_init_data){
 806                 .name = "byte0_clk_src",
 807                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 808                 .num_parents = 6,
 809                 .ops = &clk_byte2_ops,
 810                 .flags = CLK_SET_RATE_PARENT,
 811         },
 812 };
 813
 814 static struct clk_rcg2 byte1_clk_src = {
 815         .cmd_rcgr = 0x2140,
 816         .hid_width = 5,
 817         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 818         .freq_tbl = byte_freq_tbl,
 819         .clkr.hw.init = &(struct clk_init_data){
 820                 .name = "byte1_clk_src",
 821                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 822                 .num_parents = 6,
 823                 .ops = &clk_byte2_ops,
 824                 .flags = CLK_SET_RATE_PARENT,
 825         },
 826 };
 827
 828 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
 829         F(19200000, P_XO, 1, 0, 0),
 830         { }
 831 };
 832
 833 static struct clk_rcg2 edpaux_clk_src = {
 834         .cmd_rcgr = 0x20e0,
 835         .hid_width = 5,
 836         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 837         .freq_tbl = ftbl_mdss_edpaux_clk,
 838         .clkr.hw.init = &(struct clk_init_data){
 839                 .name = "edpaux_clk_src",
 840                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 841                 .num_parents = 4,
 842                 .ops = &clk_rcg2_ops,
 843         },
 844 };
 845
 846 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
 847         F(135000000, P_EDPLINK, 2, 0, 0),
 848         F(270000000, P_EDPLINK, 11, 0, 0),
 849         { }
 850 };
 851
 852 static struct clk_rcg2 edplink_clk_src = {
 853         .cmd_rcgr = 0x20c0,
 854         .hid_width = 5,
 855         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 856         .freq_tbl = ftbl_mdss_edplink_clk,
 857         .clkr.hw.init = &(struct clk_init_data){
 858                 .name = "edplink_clk_src",
 859                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 860                 .num_parents = 6,
 861                 .ops = &clk_rcg2_ops,
 862                 .flags = CLK_SET_RATE_PARENT,
 863         },
 864 };
 865
 866 static struct freq_tbl edp_pixel_freq_tbl[] = {
 867         { .src = P_EDPVCO },
 868         { }
 869 };
 870
 871 static struct clk_rcg2 edppixel_clk_src = {
 872         .cmd_rcgr = 0x20a0,
 873         .mnd_width = 8,
 874         .hid_width = 5,
 875         .parent_map = mmcc_xo_dsi_hdmi_edp_map,
 876         .freq_tbl = edp_pixel_freq_tbl,
 877         .clkr.hw.init = &(struct clk_init_data){
 878                 .name = "edppixel_clk_src",
 879                 .parent_names = mmcc_xo_dsi_hdmi_edp,
 880                 .num_parents = 6,
 881                 .ops = &clk_edp_pixel_ops,
 882         },
 883 };
 884
 885 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 886         F(19200000, P_XO, 1, 0, 0),
 887         { }
 888 };
 889
 890 static struct clk_rcg2 esc0_clk_src = {
 891         .cmd_rcgr = 0x2160,
 892         .hid_width = 5,
 893         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 894         .freq_tbl = ftbl_mdss_esc0_1_clk,
 895         .clkr.hw.init = &(struct clk_init_data){
 896                 .name = "esc0_clk_src",
 897                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 898                 .num_parents = 6,
 899                 .ops = &clk_rcg2_ops,
 900         },
 901 };
 902
 903 static struct clk_rcg2 esc1_clk_src = {
 904         .cmd_rcgr = 0x2180,
 905         .hid_width = 5,
 906         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 907         .freq_tbl = ftbl_mdss_esc0_1_clk,
 908         .clkr.hw.init = &(struct clk_init_data){
 909                 .name = "esc1_clk_src",
 910                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 911                 .num_parents = 6,
 912                 .ops = &clk_rcg2_ops,
 913         },
 914 };
 915
 916 static struct freq_tbl extpclk_freq_tbl[] = {
 917         { .src = P_HDMIPLL },
 918         { }
 919 };
 920
 921 static struct clk_rcg2 extpclk_clk_src = {
 922         .cmd_rcgr = 0x2060,
 923         .hid_width = 5,
 924         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 925         .freq_tbl = extpclk_freq_tbl,
 926         .clkr.hw.init = &(struct clk_init_data){
 927                 .name = "extpclk_clk_src",
 928                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 929                 .num_parents = 6,
 930                 .ops = &clk_byte_ops,
 931                 .flags = CLK_SET_RATE_PARENT,
 932         },
 933 };
 934
 935 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 936         F(19200000, P_XO, 1, 0, 0),
 937         { }
 938 };
 939
 940 static struct clk_rcg2 hdmi_clk_src = {
 941         .cmd_rcgr = 0x2100,
 942         .hid_width = 5,
 943         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 944         .freq_tbl = ftbl_mdss_hdmi_clk,
 945         .clkr.hw.init = &(struct clk_init_data){
 946                 .name = "hdmi_clk_src",
 947                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 948                 .num_parents = 4,
 949                 .ops = &clk_rcg2_ops,
 950         },
 951 };
 952
 953 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
 954         F(19200000, P_XO, 1, 0, 0),
 955         { }
 956 };
 957
 958 static struct clk_rcg2 vsync_clk_src = {
 959         .cmd_rcgr = 0x2080,
 960         .hid_width = 5,
 961         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 962         .freq_tbl = ftbl_mdss_vsync_clk,
 963         .clkr.hw.init = &(struct clk_init_data){
 964                 .name = "vsync_clk_src",
 965                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 966                 .num_parents = 4,
 967                 .ops = &clk_rcg2_ops,
 968         },
 969 };
 970
 971 static struct clk_branch camss_cci_cci_ahb_clk = {
 972         .halt_reg = 0x3348,
 973         .clkr = {
 974                 .enable_reg = 0x3348,
 975                 .enable_mask = BIT(0),
 976                 .hw.init = &(struct clk_init_data){
 977                         .name = "camss_cci_cci_ahb_clk",
 978                         .parent_names = (const char *[]){
 979                                 "mmss_ahb_clk_src",
 980                         },
 981                         .num_parents = 1,
 982                         .ops = &clk_branch2_ops,
 983                 },
 984         },
 985 };
 986
 987 static struct clk_branch camss_cci_cci_clk = {
 988         .halt_reg = 0x3344,
 989         .clkr = {
 990                 .enable_reg = 0x3344,
 991                 .enable_mask = BIT(0),
 992                 .hw.init = &(struct clk_init_data){
 993                         .name = "camss_cci_cci_clk",
 994                         .parent_names = (const char *[]){
 995                                 "cci_clk_src",
 996                         },
 997                         .num_parents = 1,
 998                         .flags = CLK_SET_RATE_PARENT,
 999                         .ops = &clk_branch2_ops,
1000                 },
1001         },
1002 };
1003
1004 static struct clk_branch camss_csi0_ahb_clk = {
1005         .halt_reg = 0x30bc,
1006         .clkr = {
1007                 .enable_reg = 0x30bc,
1008                 .enable_mask = BIT(0),
1009                 .hw.init = &(struct clk_init_data){
1010                         .name = "camss_csi0_ahb_clk",
1011                         .parent_names = (const char *[]){
1012                                 "mmss_ahb_clk_src",
1013                         },
1014                         .num_parents = 1,
1015                         .ops = &clk_branch2_ops,
1016                 },
1017         },
1018 };
1019
1020 static struct clk_branch camss_csi0_clk = {
1021         .halt_reg = 0x30b4,
1022         .clkr = {
1023                 .enable_reg = 0x30b4,
1024                 .enable_mask = BIT(0),
1025                 .hw.init = &(struct clk_init_data){
1026                         .name = "camss_csi0_clk",
1027                         .parent_names = (const char *[]){
1028                                 "csi0_clk_src",
1029                         },
1030                         .num_parents = 1,
1031                         .flags = CLK_SET_RATE_PARENT,
1032                         .ops = &clk_branch2_ops,
1033                 },
1034         },
1035 };
1036
1037 static struct clk_branch camss_csi0phy_clk = {
1038         .halt_reg = 0x30c4,
1039         .clkr = {
1040                 .enable_reg = 0x30c4,
1041                 .enable_mask = BIT(0),
1042                 .hw.init = &(struct clk_init_data){
1043                         .name = "camss_csi0phy_clk",
1044                         .parent_names = (const char *[]){
1045                                 "csi0_clk_src",
1046                         },
1047                         .num_parents = 1,
1048                         .flags = CLK_SET_RATE_PARENT,
1049                         .ops = &clk_branch2_ops,
1050                 },
1051         },
1052 };
1053
1054 static struct clk_branch camss_csi0pix_clk = {
1055         .halt_reg = 0x30e4,
1056         .clkr = {
1057                 .enable_reg = 0x30e4,
1058                 .enable_mask = BIT(0),
1059                 .hw.init = &(struct clk_init_data){
1060                         .name = "camss_csi0pix_clk",
1061                         .parent_names = (const char *[]){
1062                                 "csi0_clk_src",
1063                         },
1064                         .num_parents = 1,
1065                         .flags = CLK_SET_RATE_PARENT,
1066                         .ops = &clk_branch2_ops,
1067                 },
1068         },
1069 };
1070
1071 static struct clk_branch camss_csi0rdi_clk = {
1072         .halt_reg = 0x30d4,
1073         .clkr = {
1074                 .enable_reg = 0x30d4,
1075                 .enable_mask = BIT(0),
1076                 .hw.init = &(struct clk_init_data){
1077                         .name = "camss_csi0rdi_clk",
1078                         .parent_names = (const char *[]){
1079                                 "csi0_clk_src",
1080                         },
1081                         .num_parents = 1,
1082                         .flags = CLK_SET_RATE_PARENT,
1083                         .ops = &clk_branch2_ops,
1084                 },
1085         },
1086 };
1087
1088 static struct clk_branch camss_csi1_ahb_clk = {
1089         .halt_reg = 0x3128,
1090         .clkr = {
1091                 .enable_reg = 0x3128,
1092                 .enable_mask = BIT(0),
1093                 .hw.init = &(struct clk_init_data){
1094                         .name = "camss_csi1_ahb_clk",
1095                         .parent_names = (const char *[]){
1096                                 "mmss_ahb_clk_src",
1097                         },
1098                         .num_parents = 1,
1099                         .ops = &clk_branch2_ops,
1100                 },
1101         },
1102 };
1103
1104 static struct clk_branch camss_csi1_clk = {
1105         .halt_reg = 0x3124,
1106         .clkr = {
1107                 .enable_reg = 0x3124,
1108                 .enable_mask = BIT(0),
1109                 .hw.init = &(struct clk_init_data){
1110                         .name = "camss_csi1_clk",
1111                         .parent_names = (const char *[]){
1112                                 "csi1_clk_src",
1113                         },
1114                         .num_parents = 1,
1115                         .flags = CLK_SET_RATE_PARENT,
1116                         .ops = &clk_branch2_ops,
1117                 },
1118         },
1119 };
1120
1121 static struct clk_branch camss_csi1phy_clk = {
1122         .halt_reg = 0x3134,
1123         .clkr = {
1124                 .enable_reg = 0x3134,
1125                 .enable_mask = BIT(0),
1126                 .hw.init = &(struct clk_init_data){
1127                         .name = "camss_csi1phy_clk",
1128                         .parent_names = (const char *[]){
1129                                 "csi1_clk_src",
1130                         },
1131                         .num_parents = 1,
1132                         .flags = CLK_SET_RATE_PARENT,
1133                         .ops = &clk_branch2_ops,
1134                 },
1135         },
1136 };
1137
1138 static struct clk_branch camss_csi1pix_clk = {
1139         .halt_reg = 0x3154,
1140         .clkr = {
1141                 .enable_reg = 0x3154,
1142                 .enable_mask = BIT(0),
1143                 .hw.init = &(struct clk_init_data){
1144                         .name = "camss_csi1pix_clk",
1145                         .parent_names = (const char *[]){
1146                                 "csi1_clk_src",
1147                         },
1148                         .num_parents = 1,
1149                         .flags = CLK_SET_RATE_PARENT,
1150                         .ops = &clk_branch2_ops,
1151                 },
1152         },
1153 };
1154
1155 static struct clk_branch camss_csi1rdi_clk = {
1156         .halt_reg = 0x3144,
1157         .clkr = {
1158                 .enable_reg = 0x3144,
1159                 .enable_mask = BIT(0),
1160                 .hw.init = &(struct clk_init_data){
1161                         .name = "camss_csi1rdi_clk",
1162                         .parent_names = (const char *[]){
1163                                 "csi1_clk_src",
1164                         },
1165                         .num_parents = 1,
1166                         .flags = CLK_SET_RATE_PARENT,
1167                         .ops = &clk_branch2_ops,
1168                 },
1169         },
1170 };
1171
1172 static struct clk_branch camss_csi2_ahb_clk = {
1173         .halt_reg = 0x3188,
1174         .clkr = {
1175                 .enable_reg = 0x3188,
1176                 .enable_mask = BIT(0),
1177                 .hw.init = &(struct clk_init_data){
1178                         .name = "camss_csi2_ahb_clk",
1179                         .parent_names = (const char *[]){
1180                                 "mmss_ahb_clk_src",
1181                         },
1182                         .num_parents = 1,
1183                         .ops = &clk_branch2_ops,
1184                 },
1185         },
1186 };
1187
1188 static struct clk_branch camss_csi2_clk = {
1189         .halt_reg = 0x3184,
1190         .clkr = {
1191                 .enable_reg = 0x3184,
1192                 .enable_mask = BIT(0),
1193                 .hw.init = &(struct clk_init_data){
1194                         .name = "camss_csi2_clk",
1195                         .parent_names = (const char *[]){
1196                                 "csi2_clk_src",
1197                         },
1198                         .num_parents = 1,
1199                         .flags = CLK_SET_RATE_PARENT,
1200                         .ops = &clk_branch2_ops,
1201                 },
1202         },
1203 };
1204
1205 static struct clk_branch camss_csi2phy_clk = {
1206         .halt_reg = 0x3194,
1207         .clkr = {
1208                 .enable_reg = 0x3194,
1209                 .enable_mask = BIT(0),
1210                 .hw.init = &(struct clk_init_data){
1211                         .name = "camss_csi2phy_clk",
1212                         .parent_names = (const char *[]){
1213                                 "csi2_clk_src",
1214                         },
1215                         .num_parents = 1,
1216                         .flags = CLK_SET_RATE_PARENT,
1217                         .ops = &clk_branch2_ops,
1218                 },
1219         },
1220 };
1221
1222 static struct clk_branch camss_csi2pix_clk = {
1223         .halt_reg = 0x31b4,
1224         .clkr = {
1225                 .enable_reg = 0x31b4,
1226                 .enable_mask = BIT(0),
1227                 .hw.init = &(struct clk_init_data){
1228                         .name = "camss_csi2pix_clk",
1229                         .parent_names = (const char *[]){
1230                                 "csi2_clk_src",
1231                         },
1232                         .num_parents = 1,
1233                         .flags = CLK_SET_RATE_PARENT,
1234                         .ops = &clk_branch2_ops,
1235                 },
1236         },
1237 };
1238
1239 static struct clk_branch camss_csi2rdi_clk = {
1240         .halt_reg = 0x31a4,
1241         .clkr = {
1242                 .enable_reg = 0x31a4,
1243                 .enable_mask = BIT(0),
1244                 .hw.init = &(struct clk_init_data){
1245                         .name = "camss_csi2rdi_clk",
1246                         .parent_names = (const char *[]){
1247                                 "csi2_clk_src",
1248                         },
1249                         .num_parents = 1,
1250                         .flags = CLK_SET_RATE_PARENT,
1251                         .ops = &clk_branch2_ops,
1252                 },
1253         },
1254 };
1255
1256 static struct clk_branch camss_csi3_ahb_clk = {
1257         .halt_reg = 0x31e8,
1258         .clkr = {
1259                 .enable_reg = 0x31e8,
1260                 .enable_mask = BIT(0),
1261                 .hw.init = &(struct clk_init_data){
1262                         .name = "camss_csi3_ahb_clk",
1263                         .parent_names = (const char *[]){
1264                                 "mmss_ahb_clk_src",
1265                         },
1266                         .num_parents = 1,
1267                         .ops = &clk_branch2_ops,
1268                 },
1269         },
1270 };
1271
1272 static struct clk_branch camss_csi3_clk = {
1273         .halt_reg = 0x31e4,
1274         .clkr = {
1275                 .enable_reg = 0x31e4,
1276                 .enable_mask = BIT(0),
1277                 .hw.init = &(struct clk_init_data){
1278                         .name = "camss_csi3_clk",
1279                         .parent_names = (const char *[]){
1280                                 "csi3_clk_src",
1281                         },
1282                         .num_parents = 1,
1283                         .flags = CLK_SET_RATE_PARENT,
1284                         .ops = &clk_branch2_ops,
1285                 },
1286         },
1287 };
1288
1289 static struct clk_branch camss_csi3phy_clk = {
1290         .halt_reg = 0x31f4,
1291         .clkr = {
1292                 .enable_reg = 0x31f4,
1293                 .enable_mask = BIT(0),
1294                 .hw.init = &(struct clk_init_data){
1295                         .name = "camss_csi3phy_clk",
1296                         .parent_names = (const char *[]){
1297                                 "csi3_clk_src",
1298                         },
1299                         .num_parents = 1,
1300                         .flags = CLK_SET_RATE_PARENT,
1301                         .ops = &clk_branch2_ops,
1302                 },
1303         },
1304 };
1305
1306 static struct clk_branch camss_csi3pix_clk = {
1307         .halt_reg = 0x3214,
1308         .clkr = {
1309                 .enable_reg = 0x3214,
1310                 .enable_mask = BIT(0),
1311                 .hw.init = &(struct clk_init_data){
1312                         .name = "camss_csi3pix_clk",
1313                         .parent_names = (const char *[]){
1314                                 "csi3_clk_src",
1315                         },
1316                         .num_parents = 1,
1317                         .flags = CLK_SET_RATE_PARENT,
1318                         .ops = &clk_branch2_ops,
1319                 },
1320         },
1321 };
1322
1323 static struct clk_branch camss_csi3rdi_clk = {
1324         .halt_reg = 0x3204,
1325         .clkr = {
1326                 .enable_reg = 0x3204,
1327                 .enable_mask = BIT(0),
1328                 .hw.init = &(struct clk_init_data){
1329                         .name = "camss_csi3rdi_clk",
1330                         .parent_names = (const char *[]){
1331                                 "csi3_clk_src",
1332                         },
1333                         .num_parents = 1,
1334                         .flags = CLK_SET_RATE_PARENT,
1335                         .ops = &clk_branch2_ops,
1336                 },
1337         },
1338 };
1339
1340 static struct clk_branch camss_csi_vfe0_clk = {
1341         .halt_reg = 0x3704,
1342         .clkr = {
1343                 .enable_reg = 0x3704,
1344                 .enable_mask = BIT(0),
1345                 .hw.init = &(struct clk_init_data){
1346                         .name = "camss_csi_vfe0_clk",
1347                         .parent_names = (const char *[]){
1348                                 "vfe0_clk_src",
1349                         },
1350                         .num_parents = 1,
1351                         .flags = CLK_SET_RATE_PARENT,
1352                         .ops = &clk_branch2_ops,
1353                 },
1354         },
1355 };
1356
1357 static struct clk_branch camss_csi_vfe1_clk = {
1358         .halt_reg = 0x3714,
1359         .clkr = {
1360                 .enable_reg = 0x3714,
1361                 .enable_mask = BIT(0),
1362                 .hw.init = &(struct clk_init_data){
1363                         .name = "camss_csi_vfe1_clk",
1364                         .parent_names = (const char *[]){
1365                                 "vfe1_clk_src",
1366                         },
1367                         .num_parents = 1,
1368                         .flags = CLK_SET_RATE_PARENT,
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch camss_gp0_clk = {
1375         .halt_reg = 0x3444,
1376         .clkr = {
1377                 .enable_reg = 0x3444,
1378                 .enable_mask = BIT(0),
1379                 .hw.init = &(struct clk_init_data){
1380                         .name = "camss_gp0_clk",
1381                         .parent_names = (const char *[]){
1382                                 "camss_gp0_clk_src",
1383                         },
1384                         .num_parents = 1,
1385                         .flags = CLK_SET_RATE_PARENT,
1386                         .ops = &clk_branch2_ops,
1387                 },
1388         },
1389 };
1390
1391 static struct clk_branch camss_gp1_clk = {
1392         .halt_reg = 0x3474,
1393         .clkr = {
1394                 .enable_reg = 0x3474,
1395                 .enable_mask = BIT(0),
1396                 .hw.init = &(struct clk_init_data){
1397                         .name = "camss_gp1_clk",
1398                         .parent_names = (const char *[]){
1399                                 "camss_gp1_clk_src",
1400                         },
1401                         .num_parents = 1,
1402                         .flags = CLK_SET_RATE_PARENT,
1403                         .ops = &clk_branch2_ops,
1404                 },
1405         },
1406 };
1407
1408 static struct clk_branch camss_ispif_ahb_clk = {
1409         .halt_reg = 0x3224,
1410         .clkr = {
1411                 .enable_reg = 0x3224,
1412                 .enable_mask = BIT(0),
1413                 .hw.init = &(struct clk_init_data){
1414                         .name = "camss_ispif_ahb_clk",
1415                         .parent_names = (const char *[]){
1416                                 "mmss_ahb_clk_src",
1417                         },
1418                         .num_parents = 1,
1419                         .ops = &clk_branch2_ops,
1420                 },
1421         },
1422 };
1423
1424 static struct clk_branch camss_jpeg_jpeg0_clk = {
1425         .halt_reg = 0x35a8,
1426         .clkr = {
1427                 .enable_reg = 0x35a8,
1428                 .enable_mask = BIT(0),
1429                 .hw.init = &(struct clk_init_data){
1430                         .name = "camss_jpeg_jpeg0_clk",
1431                         .parent_names = (const char *[]){
1432                                 "jpeg0_clk_src",
1433                         },
1434                         .num_parents = 1,
1435                         .flags = CLK_SET_RATE_PARENT,
1436                         .ops = &clk_branch2_ops,
1437                 },
1438         },
1439 };
1440
1441 static struct clk_branch camss_jpeg_jpeg1_clk = {
1442         .halt_reg = 0x35ac,
1443         .clkr = {
1444                 .enable_reg = 0x35ac,
1445                 .enable_mask = BIT(0),
1446                 .hw.init = &(struct clk_init_data){
1447                         .name = "camss_jpeg_jpeg1_clk",
1448                         .parent_names = (const char *[]){
1449                                 "jpeg1_clk_src",
1450                         },
1451                         .num_parents = 1,
1452                         .flags = CLK_SET_RATE_PARENT,
1453                         .ops = &clk_branch2_ops,
1454                 },
1455         },
1456 };
1457
1458 static struct clk_branch camss_jpeg_jpeg2_clk = {
1459         .halt_reg = 0x35b0,
1460         .clkr = {
1461                 .enable_reg = 0x35b0,
1462                 .enable_mask = BIT(0),
1463                 .hw.init = &(struct clk_init_data){
1464                         .name = "camss_jpeg_jpeg2_clk",
1465                         .parent_names = (const char *[]){
1466                                 "jpeg2_clk_src",
1467                         },
1468                         .num_parents = 1,
1469                         .flags = CLK_SET_RATE_PARENT,
1470                         .ops = &clk_branch2_ops,
1471                 },
1472         },
1473 };
1474
1475 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1476         .halt_reg = 0x35b4,
1477         .clkr = {
1478                 .enable_reg = 0x35b4,
1479                 .enable_mask = BIT(0),
1480                 .hw.init = &(struct clk_init_data){
1481                         .name = "camss_jpeg_jpeg_ahb_clk",
1482                         .parent_names = (const char *[]){
1483                                 "mmss_ahb_clk_src",
1484                         },
1485                         .num_parents = 1,
1486                         .ops = &clk_branch2_ops,
1487                 },
1488         },
1489 };
1490
1491 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1492         .halt_reg = 0x35b8,
1493         .clkr = {
1494                 .enable_reg = 0x35b8,
1495                 .enable_mask = BIT(0),
1496                 .hw.init = &(struct clk_init_data){
1497                         .name = "camss_jpeg_jpeg_axi_clk",
1498                         .parent_names = (const char *[]){
1499                                 "mmss_axi_clk_src",
1500                         },
1501                         .num_parents = 1,
1502                         .ops = &clk_branch2_ops,
1503                 },
1504         },
1505 };
1506
1507 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1508         .halt_reg = 0x35bc,
1509         .clkr = {
1510                 .enable_reg = 0x35bc,
1511                 .enable_mask = BIT(0),
1512                 .hw.init = &(struct clk_init_data){
1513                         .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1514                         .parent_names = (const char *[]){
1515                                 "ocmemnoc_clk_src",
1516                         },
1517                         .num_parents = 1,
1518                         .flags = CLK_SET_RATE_PARENT,
1519                         .ops = &clk_branch2_ops,
1520                 },
1521         },
1522 };
1523
1524 static struct clk_branch camss_mclk0_clk = {
1525         .halt_reg = 0x3384,
1526         .clkr = {
1527                 .enable_reg = 0x3384,
1528                 .enable_mask = BIT(0),
1529                 .hw.init = &(struct clk_init_data){
1530                         .name = "camss_mclk0_clk",
1531                         .parent_names = (const char *[]){
1532                                 "mclk0_clk_src",
1533                         },
1534                         .num_parents = 1,
1535                         .flags = CLK_SET_RATE_PARENT,
1536                         .ops = &clk_branch2_ops,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_branch camss_mclk1_clk = {
1542         .halt_reg = 0x33b4,
1543         .clkr = {
1544                 .enable_reg = 0x33b4,
1545                 .enable_mask = BIT(0),
1546                 .hw.init = &(struct clk_init_data){
1547                         .name = "camss_mclk1_clk",
1548                         .parent_names = (const char *[]){
1549                                 "mclk1_clk_src",
1550                         },
1551                         .num_parents = 1,
1552                         .flags = CLK_SET_RATE_PARENT,
1553                         .ops = &clk_branch2_ops,
1554                 },
1555         },
1556 };
1557
1558 static struct clk_branch camss_mclk2_clk = {
1559         .halt_reg = 0x33e4,
1560         .clkr = {
1561                 .enable_reg = 0x33e4,
1562                 .enable_mask = BIT(0),
1563                 .hw.init = &(struct clk_init_data){
1564                         .name = "camss_mclk2_clk",
1565                         .parent_names = (const char *[]){
1566                                 "mclk2_clk_src",
1567                         },
1568                         .num_parents = 1,
1569                         .flags = CLK_SET_RATE_PARENT,
1570                         .ops = &clk_branch2_ops,
1571                 },
1572         },
1573 };
1574
1575 static struct clk_branch camss_mclk3_clk = {
1576         .halt_reg = 0x3414,
1577         .clkr = {
1578                 .enable_reg = 0x3414,
1579                 .enable_mask = BIT(0),
1580                 .hw.init = &(struct clk_init_data){
1581                         .name = "camss_mclk3_clk",
1582                         .parent_names = (const char *[]){
1583                                 "mclk3_clk_src",
1584                         },
1585                         .num_parents = 1,
1586                         .flags = CLK_SET_RATE_PARENT,
1587                         .ops = &clk_branch2_ops,
1588                 },
1589         },
1590 };
1591
1592 static struct clk_branch camss_micro_ahb_clk = {
1593         .halt_reg = 0x3494,
1594         .clkr = {
1595                 .enable_reg = 0x3494,
1596                 .enable_mask = BIT(0),
1597                 .hw.init = &(struct clk_init_data){
1598                         .name = "camss_micro_ahb_clk",
1599                         .parent_names = (const char *[]){
1600                                 "mmss_ahb_clk_src",
1601                         },
1602                         .num_parents = 1,
1603                         .ops = &clk_branch2_ops,
1604                 },
1605         },
1606 };
1607
1608 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1609         .halt_reg = 0x3024,
1610         .clkr = {
1611                 .enable_reg = 0x3024,
1612                 .enable_mask = BIT(0),
1613                 .hw.init = &(struct clk_init_data){
1614                         .name = "camss_phy0_csi0phytimer_clk",
1615                         .parent_names = (const char *[]){
1616                                 "csi0phytimer_clk_src",
1617                         },
1618                         .num_parents = 1,
1619                         .flags = CLK_SET_RATE_PARENT,
1620                         .ops = &clk_branch2_ops,
1621                 },
1622         },
1623 };
1624
1625 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1626         .halt_reg = 0x3054,
1627         .clkr = {
1628                 .enable_reg = 0x3054,
1629                 .enable_mask = BIT(0),
1630                 .hw.init = &(struct clk_init_data){
1631                         .name = "camss_phy1_csi1phytimer_clk",
1632                         .parent_names = (const char *[]){
1633                                 "csi1phytimer_clk_src",
1634                         },
1635                         .num_parents = 1,
1636                         .flags = CLK_SET_RATE_PARENT,
1637                         .ops = &clk_branch2_ops,
1638                 },
1639         },
1640 };
1641
1642 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1643         .halt_reg = 0x3084,
1644         .clkr = {
1645                 .enable_reg = 0x3084,
1646                 .enable_mask = BIT(0),
1647                 .hw.init = &(struct clk_init_data){
1648                         .name = "camss_phy2_csi2phytimer_clk",
1649                         .parent_names = (const char *[]){
1650                                 "csi2phytimer_clk_src",
1651                         },
1652                         .num_parents = 1,
1653                         .flags = CLK_SET_RATE_PARENT,
1654                         .ops = &clk_branch2_ops,
1655                 },
1656         },
1657 };
1658
1659 static struct clk_branch camss_top_ahb_clk = {
1660         .halt_reg = 0x3484,
1661         .clkr = {
1662                 .enable_reg = 0x3484,
1663                 .enable_mask = BIT(0),
1664                 .hw.init = &(struct clk_init_data){
1665                         .name = "camss_top_ahb_clk",
1666                         .parent_names = (const char *[]){
1667                                 "mmss_ahb_clk_src",
1668                         },
1669                         .num_parents = 1,
1670                         .ops = &clk_branch2_ops,
1671                 },
1672         },
1673 };
1674
1675 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1676         .halt_reg = 0x36b4,
1677         .clkr = {
1678                 .enable_reg = 0x36b4,
1679                 .enable_mask = BIT(0),
1680                 .hw.init = &(struct clk_init_data){
1681                         .name = "camss_vfe_cpp_ahb_clk",
1682                         .parent_names = (const char *[]){
1683                                 "mmss_ahb_clk_src",
1684                         },
1685                         .num_parents = 1,
1686                         .ops = &clk_branch2_ops,
1687                 },
1688         },
1689 };
1690
1691 static struct clk_branch camss_vfe_cpp_clk = {
1692         .halt_reg = 0x36b0,
1693         .clkr = {
1694                 .enable_reg = 0x36b0,
1695                 .enable_mask = BIT(0),
1696                 .hw.init = &(struct clk_init_data){
1697                         .name = "camss_vfe_cpp_clk",
1698                         .parent_names = (const char *[]){
1699                                 "cpp_clk_src",
1700                         },
1701                         .num_parents = 1,
1702                         .flags = CLK_SET_RATE_PARENT,
1703                         .ops = &clk_branch2_ops,
1704                 },
1705         },
1706 };
1707
1708 static struct clk_branch camss_vfe_vfe0_clk = {
1709         .halt_reg = 0x36a8,
1710         .clkr = {
1711                 .enable_reg = 0x36a8,
1712                 .enable_mask = BIT(0),
1713                 .hw.init = &(struct clk_init_data){
1714                         .name = "camss_vfe_vfe0_clk",
1715                         .parent_names = (const char *[]){
1716                                 "vfe0_clk_src",
1717                         },
1718                         .num_parents = 1,
1719                         .flags = CLK_SET_RATE_PARENT,
1720                         .ops = &clk_branch2_ops,
1721                 },
1722         },
1723 };
1724
1725 static struct clk_branch camss_vfe_vfe1_clk = {
1726         .halt_reg = 0x36ac,
1727         .clkr = {
1728                 .enable_reg = 0x36ac,
1729                 .enable_mask = BIT(0),
1730                 .hw.init = &(struct clk_init_data){
1731                         .name = "camss_vfe_vfe1_clk",
1732                         .parent_names = (const char *[]){
1733                                 "vfe1_clk_src",
1734                         },
1735                         .num_parents = 1,
1736                         .flags = CLK_SET_RATE_PARENT,
1737                         .ops = &clk_branch2_ops,
1738                 },
1739         },
1740 };
1741
1742 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1743         .halt_reg = 0x36b8,
1744         .clkr = {
1745                 .enable_reg = 0x36b8,
1746                 .enable_mask = BIT(0),
1747                 .hw.init = &(struct clk_init_data){
1748                         .name = "camss_vfe_vfe_ahb_clk",
1749                         .parent_names = (const char *[]){
1750                                 "mmss_ahb_clk_src",
1751                         },
1752                         .num_parents = 1,
1753                         .ops = &clk_branch2_ops,
1754                 },
1755         },
1756 };
1757
1758 static struct clk_branch camss_vfe_vfe_axi_clk = {
1759         .halt_reg = 0x36bc,
1760         .clkr = {
1761                 .enable_reg = 0x36bc,
1762                 .enable_mask = BIT(0),
1763                 .hw.init = &(struct clk_init_data){
1764                         .name = "camss_vfe_vfe_axi_clk",
1765                         .parent_names = (const char *[]){
1766                                 "mmss_axi_clk_src",
1767                         },
1768                         .num_parents = 1,
1769                         .ops = &clk_branch2_ops,
1770                 },
1771         },
1772 };
1773
1774 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1775         .halt_reg = 0x36c0,
1776         .clkr = {
1777                 .enable_reg = 0x36c0,
1778                 .enable_mask = BIT(0),
1779                 .hw.init = &(struct clk_init_data){
1780                         .name = "camss_vfe_vfe_ocmemnoc_clk",
1781                         .parent_names = (const char *[]){
1782                                 "ocmemnoc_clk_src",
1783                         },
1784                         .num_parents = 1,
1785                         .flags = CLK_SET_RATE_PARENT,
1786                         .ops = &clk_branch2_ops,
1787                 },
1788         },
1789 };
1790
1791 static struct clk_branch mdss_ahb_clk = {
1792         .halt_reg = 0x2308,
1793         .clkr = {
1794                 .enable_reg = 0x2308,
1795                 .enable_mask = BIT(0),
1796                 .hw.init = &(struct clk_init_data){
1797                         .name = "mdss_ahb_clk",
1798                         .parent_names = (const char *[]){
1799                                 "mmss_ahb_clk_src",
1800                         },
1801                         .num_parents = 1,
1802                         .ops = &clk_branch2_ops,
1803                 },
1804         },
1805 };
1806
1807 static struct clk_branch mdss_axi_clk = {
1808         .halt_reg = 0x2310,
1809         .clkr = {
1810                 .enable_reg = 0x2310,
1811                 .enable_mask = BIT(0),
1812                 .hw.init = &(struct clk_init_data){
1813                         .name = "mdss_axi_clk",
1814                         .parent_names = (const char *[]){
1815                                 "mmss_axi_clk_src",
1816                         },
1817                         .num_parents = 1,
1818                         .flags = CLK_SET_RATE_PARENT,
1819                         .ops = &clk_branch2_ops,
1820                 },
1821         },
1822 };
1823
1824 static struct clk_branch mdss_byte0_clk = {
1825         .halt_reg = 0x233c,
1826         .clkr = {
1827                 .enable_reg = 0x233c,
1828                 .enable_mask = BIT(0),
1829                 .hw.init = &(struct clk_init_data){
1830                         .name = "mdss_byte0_clk",
1831                         .parent_names = (const char *[]){
1832                                 "byte0_clk_src",
1833                         },
1834                         .num_parents = 1,
1835                         .flags = CLK_SET_RATE_PARENT,
1836                         .ops = &clk_branch2_ops,
1837                 },
1838         },
1839 };
1840
1841 static struct clk_branch mdss_byte1_clk = {
1842         .halt_reg = 0x2340,
1843         .clkr = {
1844                 .enable_reg = 0x2340,
1845                 .enable_mask = BIT(0),
1846                 .hw.init = &(struct clk_init_data){
1847                         .name = "mdss_byte1_clk",
1848                         .parent_names = (const char *[]){
1849                                 "byte1_clk_src",
1850                         },
1851                         .num_parents = 1,
1852                         .flags = CLK_SET_RATE_PARENT,
1853                         .ops = &clk_branch2_ops,
1854                 },
1855         },
1856 };
1857
1858 static struct clk_branch mdss_edpaux_clk = {
1859         .halt_reg = 0x2334,
1860         .clkr = {
1861                 .enable_reg = 0x2334,
1862                 .enable_mask = BIT(0),
1863                 .hw.init = &(struct clk_init_data){
1864                         .name = "mdss_edpaux_clk",
1865                         .parent_names = (const char *[]){
1866                                 "edpaux_clk_src",
1867                         },
1868                         .num_parents = 1,
1869                         .flags = CLK_SET_RATE_PARENT,
1870                         .ops = &clk_branch2_ops,
1871                 },
1872         },
1873 };
1874
1875 static struct clk_branch mdss_edplink_clk = {
1876         .halt_reg = 0x2330,
1877         .clkr = {
1878                 .enable_reg = 0x2330,
1879                 .enable_mask = BIT(0),
1880                 .hw.init = &(struct clk_init_data){
1881                         .name = "mdss_edplink_clk",
1882                         .parent_names = (const char *[]){
1883                                 "edplink_clk_src",
1884                         },
1885                         .num_parents = 1,
1886                         .flags = CLK_SET_RATE_PARENT,
1887                         .ops = &clk_branch2_ops,
1888                 },
1889         },
1890 };
1891
1892 static struct clk_branch mdss_edppixel_clk = {
1893         .halt_reg = 0x232c,
1894         .clkr = {
1895                 .enable_reg = 0x232c,
1896                 .enable_mask = BIT(0),
1897                 .hw.init = &(struct clk_init_data){
1898                         .name = "mdss_edppixel_clk",
1899                         .parent_names = (const char *[]){
1900                                 "edppixel_clk_src",
1901                         },
1902                         .num_parents = 1,
1903                         .flags = CLK_SET_RATE_PARENT,
1904                         .ops = &clk_branch2_ops,
1905                 },
1906         },
1907 };
1908
1909 static struct clk_branch mdss_esc0_clk = {
1910         .halt_reg = 0x2344,
1911         .clkr = {
1912                 .enable_reg = 0x2344,
1913                 .enable_mask = BIT(0),
1914                 .hw.init = &(struct clk_init_data){
1915                         .name = "mdss_esc0_clk",
1916                         .parent_names = (const char *[]){
1917                                 "esc0_clk_src",
1918                         },
1919                         .num_parents = 1,
1920                         .flags = CLK_SET_RATE_PARENT,
1921                         .ops = &clk_branch2_ops,
1922                 },
1923         },
1924 };
1925
1926 static struct clk_branch mdss_esc1_clk = {
1927         .halt_reg = 0x2348,
1928         .clkr = {
1929                 .enable_reg = 0x2348,
1930                 .enable_mask = BIT(0),
1931                 .hw.init = &(struct clk_init_data){
1932                         .name = "mdss_esc1_clk",
1933                         .parent_names = (const char *[]){
1934                                 "esc1_clk_src",
1935                         },
1936                         .num_parents = 1,
1937                         .flags = CLK_SET_RATE_PARENT,
1938                         .ops = &clk_branch2_ops,
1939                 },
1940         },
1941 };
1942
1943 static struct clk_branch mdss_extpclk_clk = {
1944         .halt_reg = 0x2324,
1945         .clkr = {
1946                 .enable_reg = 0x2324,
1947                 .enable_mask = BIT(0),
1948                 .hw.init = &(struct clk_init_data){
1949                         .name = "mdss_extpclk_clk",
1950                         .parent_names = (const char *[]){
1951                                 "extpclk_clk_src",
1952                         },
1953                         .num_parents = 1,
1954                         .flags = CLK_SET_RATE_PARENT,
1955                         .ops = &clk_branch2_ops,
1956                 },
1957         },
1958 };
1959
1960 static struct clk_branch mdss_hdmi_ahb_clk = {
1961         .halt_reg = 0x230c,
1962         .clkr = {
1963                 .enable_reg = 0x230c,
1964                 .enable_mask = BIT(0),
1965                 .hw.init = &(struct clk_init_data){
1966                         .name = "mdss_hdmi_ahb_clk",
1967                         .parent_names = (const char *[]){
1968                                 "mmss_ahb_clk_src",
1969                         },
1970                         .num_parents = 1,
1971                         .ops = &clk_branch2_ops,
1972                 },
1973         },
1974 };
1975
1976 static struct clk_branch mdss_hdmi_clk = {
1977         .halt_reg = 0x2338,
1978         .clkr = {
1979                 .enable_reg = 0x2338,
1980                 .enable_mask = BIT(0),
1981                 .hw.init = &(struct clk_init_data){
1982                         .name = "mdss_hdmi_clk",
1983                         .parent_names = (const char *[]){
1984                                 "hdmi_clk_src",
1985                         },
1986                         .num_parents = 1,
1987                         .flags = CLK_SET_RATE_PARENT,
1988                         .ops = &clk_branch2_ops,
1989                 },
1990         },
1991 };
1992
1993 static struct clk_branch mdss_mdp_clk = {
1994         .halt_reg = 0x231c,
1995         .clkr = {
1996                 .enable_reg = 0x231c,
1997                 .enable_mask = BIT(0),
1998                 .hw.init = &(struct clk_init_data){
1999                         .name = "mdss_mdp_clk",
2000                         .parent_names = (const char *[]){
2001                                 "mdp_clk_src",
2002                         },
2003                         .num_parents = 1,
2004                         .flags = CLK_SET_RATE_PARENT,
2005                         .ops = &clk_branch2_ops,
2006                 },
2007         },
2008 };
2009
2010 static struct clk_branch mdss_mdp_lut_clk = {
2011         .halt_reg = 0x2320,
2012         .clkr = {
2013                 .enable_reg = 0x2320,
2014                 .enable_mask = BIT(0),
2015                 .hw.init = &(struct clk_init_data){
2016                         .name = "mdss_mdp_lut_clk",
2017                         .parent_names = (const char *[]){
2018                                 "mdp_clk_src",
2019                         },
2020                         .num_parents = 1,
2021                         .flags = CLK_SET_RATE_PARENT,
2022                         .ops = &clk_branch2_ops,
2023                 },
2024         },
2025 };
2026
2027 static struct clk_branch mdss_pclk0_clk = {
2028         .halt_reg = 0x2314,
2029         .clkr = {
2030                 .enable_reg = 0x2314,
2031                 .enable_mask = BIT(0),
2032                 .hw.init = &(struct clk_init_data){
2033                         .name = "mdss_pclk0_clk",
2034                         .parent_names = (const char *[]){
2035                                 "pclk0_clk_src",
2036                         },
2037                         .num_parents = 1,
2038                         .flags = CLK_SET_RATE_PARENT,
2039                         .ops = &clk_branch2_ops,
2040                 },
2041         },
2042 };
2043
2044 static struct clk_branch mdss_pclk1_clk = {
2045         .halt_reg = 0x2318,
2046         .clkr = {
2047                 .enable_reg = 0x2318,
2048                 .enable_mask = BIT(0),
2049                 .hw.init = &(struct clk_init_data){
2050                         .name = "mdss_pclk1_clk",
2051                         .parent_names = (const char *[]){
2052                                 "pclk1_clk_src",
2053                         },
2054                         .num_parents = 1,
2055                         .flags = CLK_SET_RATE_PARENT,
2056                         .ops = &clk_branch2_ops,
2057                 },
2058         },
2059 };
2060
2061 static struct clk_branch mdss_vsync_clk = {
2062         .halt_reg = 0x2328,
2063         .clkr = {
2064                 .enable_reg = 0x2328,
2065                 .enable_mask = BIT(0),
2066                 .hw.init = &(struct clk_init_data){
2067                         .name = "mdss_vsync_clk",
2068                         .parent_names = (const char *[]){
2069                                 "vsync_clk_src",
2070                         },
2071                         .num_parents = 1,
2072                         .flags = CLK_SET_RATE_PARENT,
2073                         .ops = &clk_branch2_ops,
2074                 },
2075         },
2076 };
2077
2078 static struct clk_branch mmss_misc_ahb_clk = {
2079         .halt_reg = 0x502c,
2080         .clkr = {
2081                 .enable_reg = 0x502c,
2082                 .enable_mask = BIT(0),
2083                 .hw.init = &(struct clk_init_data){
2084                         .name = "mmss_misc_ahb_clk",
2085                         .parent_names = (const char *[]){
2086                                 "mmss_ahb_clk_src",
2087                         },
2088                         .num_parents = 1,
2089                         .ops = &clk_branch2_ops,
2090                 },
2091         },
2092 };
2093
2094 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2095         .halt_reg = 0x5024,
2096         .clkr = {
2097                 .enable_reg = 0x5024,
2098                 .enable_mask = BIT(0),
2099                 .hw.init = &(struct clk_init_data){
2100                         .name = "mmss_mmssnoc_ahb_clk",
2101                         .parent_names = (const char *[]){
2102                                 "mmss_ahb_clk_src",
2103                         },
2104                         .num_parents = 1,
2105                         .ops = &clk_branch2_ops,
2106                         .flags = CLK_IGNORE_UNUSED,
2107                 },
2108         },
2109 };
2110
2111 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2112         .halt_reg = 0x5028,
2113         .clkr = {
2114                 .enable_reg = 0x5028,
2115                 .enable_mask = BIT(0),
2116                 .hw.init = &(struct clk_init_data){
2117                         .name = "mmss_mmssnoc_bto_ahb_clk",
2118                         .parent_names = (const char *[]){
2119                                 "mmss_ahb_clk_src",
2120                         },
2121                         .num_parents = 1,
2122                         .ops = &clk_branch2_ops,
2123                         .flags = CLK_IGNORE_UNUSED,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch mmss_mmssnoc_axi_clk = {
2129         .halt_reg = 0x506c,
2130         .clkr = {
2131                 .enable_reg = 0x506c,
2132                 .enable_mask = BIT(0),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "mmss_mmssnoc_axi_clk",
2135                         .parent_names = (const char *[]){
2136                                 "mmss_axi_clk_src",
2137                         },
2138                         .num_parents = 1,
2139                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2140                         .ops = &clk_branch2_ops,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_branch mmss_s0_axi_clk = {
2146         .halt_reg = 0x5064,
2147         .clkr = {
2148                 .enable_reg = 0x5064,
2149                 .enable_mask = BIT(0),
2150                 .hw.init = &(struct clk_init_data){
2151                         .name = "mmss_s0_axi_clk",
2152                         .parent_names = (const char *[]){
2153                                 "mmss_axi_clk_src",
2154                         },
2155                         .num_parents = 1,
2156                         .ops = &clk_branch2_ops,
2157                         .flags = CLK_IGNORE_UNUSED,
2158                 },
2159         },
2160 };
2161
2162 static struct clk_branch ocmemcx_ahb_clk = {
2163         .halt_reg = 0x405c,
2164         .clkr = {
2165                 .enable_reg = 0x405c,
2166                 .enable_mask = BIT(0),
2167                 .hw.init = &(struct clk_init_data){
2168                         .name = "ocmemcx_ahb_clk",
2169                         .parent_names = (const char *[]){
2170                                 "mmss_ahb_clk_src",
2171                         },
2172                         .num_parents = 1,
2173                         .ops = &clk_branch2_ops,
2174                 },
2175         },
2176 };
2177
2178 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2179         .halt_reg = 0x4058,
2180         .clkr = {
2181                 .enable_reg = 0x4058,
2182                 .enable_mask = BIT(0),
2183                 .hw.init = &(struct clk_init_data){
2184                         .name = "ocmemcx_ocmemnoc_clk",
2185                         .parent_names = (const char *[]){
2186                                 "ocmemnoc_clk_src",
2187                         },
2188                         .num_parents = 1,
2189                         .flags = CLK_SET_RATE_PARENT,
2190                         .ops = &clk_branch2_ops,
2191                 },
2192         },
2193 };
2194
2195 static struct clk_branch oxili_ocmemgx_clk = {
2196         .halt_reg = 0x402c,
2197         .clkr = {
2198                 .enable_reg = 0x402c,
2199                 .enable_mask = BIT(0),
2200                 .hw.init = &(struct clk_init_data){
2201                         .name = "oxili_ocmemgx_clk",
2202                         .parent_names = (const char *[]){
2203                                 "gfx3d_clk_src",
2204                         },
2205                         .num_parents = 1,
2206                         .flags = CLK_SET_RATE_PARENT,
2207                         .ops = &clk_branch2_ops,
2208                 },
2209         },
2210 };
2211
2212 static struct clk_branch ocmemnoc_clk = {
2213         .halt_reg = 0x50b4,
2214         .clkr = {
2215                 .enable_reg = 0x50b4,
2216                 .enable_mask = BIT(0),
2217                 .hw.init = &(struct clk_init_data){
2218                         .name = "ocmemnoc_clk",
2219                         .parent_names = (const char *[]){
2220                                 "ocmemnoc_clk_src",
2221                         },
2222                         .num_parents = 1,
2223                         .flags = CLK_SET_RATE_PARENT,
2224                         .ops = &clk_branch2_ops,
2225                 },
2226         },
2227 };
2228
2229 static struct clk_branch oxili_gfx3d_clk = {
2230         .halt_reg = 0x4028,
2231         .clkr = {
2232                 .enable_reg = 0x4028,
2233                 .enable_mask = BIT(0),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "oxili_gfx3d_clk",
2236                         .parent_names = (const char *[]){
2237                                 "gfx3d_clk_src",
2238                         },
2239                         .num_parents = 1,
2240                         .flags = CLK_SET_RATE_PARENT,
2241                         .ops = &clk_branch2_ops,
2242                 },
2243         },
2244 };
2245
2246 static struct clk_branch oxilicx_ahb_clk = {
2247         .halt_reg = 0x403c,
2248         .clkr = {
2249                 .enable_reg = 0x403c,
2250                 .enable_mask = BIT(0),
2251                 .hw.init = &(struct clk_init_data){
2252                         .name = "oxilicx_ahb_clk",
2253                         .parent_names = (const char *[]){
2254                                 "mmss_ahb_clk_src",
2255                         },
2256                         .num_parents = 1,
2257                         .ops = &clk_branch2_ops,
2258                 },
2259         },
2260 };
2261
2262 static struct clk_branch oxilicx_axi_clk = {
2263         .halt_reg = 0x4038,
2264         .clkr = {
2265                 .enable_reg = 0x4038,
2266                 .enable_mask = BIT(0),
2267                 .hw.init = &(struct clk_init_data){
2268                         .name = "oxilicx_axi_clk",
2269                         .parent_names = (const char *[]){
2270                                 "mmss_axi_clk_src",
2271                         },
2272                         .num_parents = 1,
2273                         .ops = &clk_branch2_ops,
2274                 },
2275         },
2276 };
2277
2278 static struct clk_branch venus0_ahb_clk = {
2279         .halt_reg = 0x1030,
2280         .clkr = {
2281                 .enable_reg = 0x1030,
2282                 .enable_mask = BIT(0),
2283                 .hw.init = &(struct clk_init_data){
2284                         .name = "venus0_ahb_clk",
2285                         .parent_names = (const char *[]){
2286                                 "mmss_ahb_clk_src",
2287                         },
2288                         .num_parents = 1,
2289                         .ops = &clk_branch2_ops,
2290                 },
2291         },
2292 };
2293
2294 static struct clk_branch venus0_axi_clk = {
2295         .halt_reg = 0x1034,
2296         .clkr = {
2297                 .enable_reg = 0x1034,
2298                 .enable_mask = BIT(0),
2299                 .hw.init = &(struct clk_init_data){
2300                         .name = "venus0_axi_clk",
2301                         .parent_names = (const char *[]){
2302                                 "mmss_axi_clk_src",
2303                         },
2304                         .num_parents = 1,
2305                         .ops = &clk_branch2_ops,
2306                 },
2307         },
2308 };
2309
2310 static struct clk_branch venus0_ocmemnoc_clk = {
2311         .halt_reg = 0x1038,
2312         .clkr = {
2313                 .enable_reg = 0x1038,
2314                 .enable_mask = BIT(0),
2315                 .hw.init = &(struct clk_init_data){
2316                         .name = "venus0_ocmemnoc_clk",
2317                         .parent_names = (const char *[]){
2318                                 "ocmemnoc_clk_src",
2319                         },
2320                         .num_parents = 1,
2321                         .flags = CLK_SET_RATE_PARENT,
2322                         .ops = &clk_branch2_ops,
2323                 },
2324         },
2325 };
2326
2327 static struct clk_branch venus0_vcodec0_clk = {
2328         .halt_reg = 0x1028,
2329         .clkr = {
2330                 .enable_reg = 0x1028,
2331                 .enable_mask = BIT(0),
2332                 .hw.init = &(struct clk_init_data){
2333                         .name = "venus0_vcodec0_clk",
2334                         .parent_names = (const char *[]){
2335                                 "vcodec0_clk_src",
2336                         },
2337                         .num_parents = 1,
2338                         .flags = CLK_SET_RATE_PARENT,
2339                         .ops = &clk_branch2_ops,
2340                 },
2341         },
2342 };
2343
2344 static const struct pll_config mmpll1_config = {
2345         .l = 60,
2346         .m = 25,
2347         .n = 32,
2348         .vco_val = 0x0,
2349         .vco_mask = 0x3 << 20,
2350         .pre_div_val = 0x0,
2351         .pre_div_mask = 0x7 << 12,
2352         .post_div_val = 0x0,
2353         .post_div_mask = 0x3 << 8,
2354         .mn_ena_mask = BIT(24),
2355         .main_output_mask = BIT(0),
2356 };
2357
2358 static struct pll_config mmpll3_config = {
2359         .l = 48,
2360         .m = 7,
2361         .n = 16,
2362         .vco_val = 0x0,
2363         .vco_mask = 0x3 << 20,
2364         .pre_div_val = 0x0,
2365         .pre_div_mask = 0x7 << 12,
2366         .post_div_val = 0x0,
2367         .post_div_mask = 0x3 << 8,
2368         .mn_ena_mask = BIT(24),
2369         .main_output_mask = BIT(0),
2370         .aux_output_mask = BIT(1),
2371 };
2372
2373 static struct gdsc venus0_gdsc = {
2374         .gdscr = 0x1024,
2375         .cxcs = (unsigned int []){ 0x1028 },
2376         .cxc_count = 1,
2377         .resets = (unsigned int []){ VENUS0_RESET },
2378         .reset_count = 1,
2379         .pd = {
2380                 .name = "venus0",
2381         },
2382         .pwrsts = PWRSTS_ON,
2383 };
2384
2385 static struct gdsc mdss_gdsc = {
2386         .gdscr = 0x2304,
2387         .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2388         .cxc_count = 2,
2389         .pd = {
2390                 .name = "mdss",
2391         },
2392         .pwrsts = PWRSTS_RET_ON,
2393 };
2394
2395 static struct gdsc camss_jpeg_gdsc = {
2396         .gdscr = 0x35a4,
2397         .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2398         .cxc_count = 3,
2399         .pd = {
2400                 .name = "camss_jpeg",
2401         },
2402         .pwrsts = PWRSTS_OFF_ON,
2403 };
2404
2405 static struct gdsc camss_vfe_gdsc = {
2406         .gdscr = 0x36a4,
2407         .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2408         .cxc_count = 5,
2409         .pd = {
2410                 .name = "camss_vfe",
2411         },
2412         .pwrsts = PWRSTS_OFF_ON,
2413 };
2414
2415 static struct gdsc oxili_gdsc = {
2416         .gdscr = 0x4024,
2417         .cxcs = (unsigned int []){ 0x4028 },
2418         .cxc_count = 1,
2419         .pd = {
2420                 .name = "oxili",
2421         },
2422         .pwrsts = PWRSTS_OFF_ON,
2423 };
2424
2425 static struct gdsc oxilicx_gdsc = {
2426         .gdscr = 0x4034,
2427         .pd = {
2428                 .name = "oxilicx",
2429         },
2430         .parent = &oxili_gdsc.pd,
2431         .pwrsts = PWRSTS_OFF_ON,
2432 };
2433
2434 static struct clk_regmap *mmcc_msm8226_clocks[] = {
2435         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2436         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2437         [MMPLL0] = &mmpll0.clkr,
2438         [MMPLL0_VOTE] = &mmpll0_vote,
2439         [MMPLL1] = &mmpll1.clkr,
2440         [MMPLL1_VOTE] = &mmpll1_vote,
2441         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2442         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2443         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2444         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2445         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2446         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2447         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2448         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2449         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2450         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2451         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2452         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2453         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2454         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2455         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2456         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2457         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2458         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2459         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2460         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2461         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2462         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2463         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2464         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2465         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2466         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2467         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2468         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2469         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2470         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2471         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2472         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2473         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2474         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2475         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2476         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2477         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2478         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2479         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2480         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2481         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2482         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2483         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2484         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2485         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2486         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2487         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2488         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2489         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2490         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2491         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2492         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2493         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2494         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2495         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2496         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2497         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2498         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2499         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2500         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2501         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2502         [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2503         [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2504         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2505         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2506         [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2507         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2508         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2509         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2510 };
2511
2512 static const struct qcom_reset_map mmcc_msm8226_resets[] = {
2513         [SPDM_RESET] = { 0x0200 },
2514         [SPDM_RM_RESET] = { 0x0300 },
2515         [VENUS0_RESET] = { 0x1020 },
2516         [MDSS_RESET] = { 0x2300 },
2517 };
2518
2519 static struct gdsc *mmcc_msm8226_gdscs[] = {
2520         [VENUS0_GDSC] = &venus0_gdsc,
2521         [MDSS_GDSC] = &mdss_gdsc,
2522         [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2523         [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2524 };
2525
2526 static const struct regmap_config mmcc_msm8226_regmap_config = {
2527         .reg_bits       = 32,
2528         .reg_stride     = 4,
2529         .val_bits       = 32,
2530         .max_register   = 0x5104,
2531         .fast_io        = true,
2532 };
2533
2534 static const struct qcom_cc_desc mmcc_msm8226_desc = {
2535         .config = &mmcc_msm8226_regmap_config,
2536         .clks = mmcc_msm8226_clocks,
2537         .num_clks = ARRAY_SIZE(mmcc_msm8226_clocks),
2538         .resets = mmcc_msm8226_resets,
2539         .num_resets = ARRAY_SIZE(mmcc_msm8226_resets),
2540         .gdscs = mmcc_msm8226_gdscs,
2541         .num_gdscs = ARRAY_SIZE(mmcc_msm8226_gdscs),
2542 };
2543
2544 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2545         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2546         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2547         [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2548         [MMPLL0] = &mmpll0.clkr,
2549         [MMPLL0_VOTE] = &mmpll0_vote,
2550         [MMPLL1] = &mmpll1.clkr,
2551         [MMPLL1_VOTE] = &mmpll1_vote,
2552         [MMPLL2] = &mmpll2.clkr,
2553         [MMPLL3] = &mmpll3.clkr,
2554         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2555         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2556         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2557         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2558         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2559         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2560         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2561         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2562         [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2563         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2564         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2565         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2566         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2567         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2568         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2569         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2570         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2571         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2572         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2573         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2574         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2575         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2576         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2577         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2578         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2579         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2580         [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2581         [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2582         [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2583         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2584         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2585         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2586         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2587         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2588         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2589         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2590         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2591         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2592         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2593         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2594         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2595         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2596         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2597         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2598         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2599         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2600         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2601         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2602         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2603         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2604         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2605         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2606         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2607         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2608         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2609         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2610         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2611         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2612         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2613         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2614         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2615         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2616         [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2617         [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2618         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2619         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2620         [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2621         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2622         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2623         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2624         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2625         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2626         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2627         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2628         [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2629         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2630         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2631         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2632         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2633         [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2634         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2635         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2636         [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2637         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2638         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2639         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2640         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2641         [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2642         [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2643         [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2644         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2645         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2646         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2647         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2648         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2649         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2650         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2651         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2652         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2653         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2654         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2655         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2656         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2657         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2658         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2659         [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2660         [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2661         [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2662         [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2663         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2664         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2665         [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2666         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2667         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2668         [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2669         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2670 };
2671
2672 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2673         [SPDM_RESET] = { 0x0200 },
2674         [SPDM_RM_RESET] = { 0x0300 },
2675         [VENUS0_RESET] = { 0x1020 },
2676         [MDSS_RESET] = { 0x2300 },
2677         [CAMSS_PHY0_RESET] = { 0x3020 },
2678         [CAMSS_PHY1_RESET] = { 0x3050 },
2679         [CAMSS_PHY2_RESET] = { 0x3080 },
2680         [CAMSS_CSI0_RESET] = { 0x30b0 },
2681         [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2682         [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2683         [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2684         [CAMSS_CSI1_RESET] = { 0x3120 },
2685         [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2686         [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2687         [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2688         [CAMSS_CSI2_RESET] = { 0x3180 },
2689         [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2690         [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2691         [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2692         [CAMSS_CSI3_RESET] = { 0x31e0 },
2693         [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2694         [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2695         [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2696         [CAMSS_ISPIF_RESET] = { 0x3220 },
2697         [CAMSS_CCI_RESET] = { 0x3340 },
2698         [CAMSS_MCLK0_RESET] = { 0x3380 },
2699         [CAMSS_MCLK1_RESET] = { 0x33b0 },
2700         [CAMSS_MCLK2_RESET] = { 0x33e0 },
2701         [CAMSS_MCLK3_RESET] = { 0x3410 },
2702         [CAMSS_GP0_RESET] = { 0x3440 },
2703         [CAMSS_GP1_RESET] = { 0x3470 },
2704         [CAMSS_TOP_RESET] = { 0x3480 },
2705         [CAMSS_MICRO_RESET] = { 0x3490 },
2706         [CAMSS_JPEG_RESET] = { 0x35a0 },
2707         [CAMSS_VFE_RESET] = { 0x36a0 },
2708         [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2709         [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2710         [OXILI_RESET] = { 0x4020 },
2711         [OXILICX_RESET] = { 0x4030 },
2712         [OCMEMCX_RESET] = { 0x4050 },
2713         [MMSS_RBCRP_RESET] = { 0x4080 },
2714         [MMSSNOCAHB_RESET] = { 0x5020 },
2715         [MMSSNOCAXI_RESET] = { 0x5060 },
2716         [OCMEMNOC_RESET] = { 0x50b0 },
2717 };
2718
2719 static struct gdsc *mmcc_msm8974_gdscs[] = {
2720         [VENUS0_GDSC] = &venus0_gdsc,
2721         [MDSS_GDSC] = &mdss_gdsc,
2722         [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2723         [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2724         [OXILI_GDSC] = &oxili_gdsc,
2725         [OXILICX_GDSC] = &oxilicx_gdsc,
2726 };
2727
2728 static const struct regmap_config mmcc_msm8974_regmap_config = {
2729         .reg_bits       = 32,
2730         .reg_stride     = 4,
2731         .val_bits       = 32,
2732         .max_register   = 0x5104,
2733         .fast_io        = true,
2734 };
2735
2736 static const struct qcom_cc_desc mmcc_msm8974_desc = {
2737         .config = &mmcc_msm8974_regmap_config,
2738         .clks = mmcc_msm8974_clocks,
2739         .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2740         .resets = mmcc_msm8974_resets,
2741         .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2742         .gdscs = mmcc_msm8974_gdscs,
2743         .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2744 };
2745
2746 static const struct of_device_id mmcc_msm8974_match_table[] = {
2747         { .compatible = "qcom,mmcc-msm8226", .data = &mmcc_msm8226_desc },
2748         { .compatible = "qcom,mmcc-msm8974", .data = &mmcc_msm8974_desc },
2749         { }
2750 };
2751 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2752
2753 static void msm8226_clock_override(void)
2754 {
2755         mmss_axi_clk_src.freq_tbl = ftbl_mmss_axi_clk_msm8226;
2756         vfe0_clk_src.freq_tbl = ftbl_camss_vfe_vfe0_clk_msm8226;
2757         mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_msm8226;
2758         vcodec0_clk_src.freq_tbl = ftbl_venus0_vcodec0_clk_msm8226;
2759         mclk0_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
2760         mclk1_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226;
2761         cpp_clk_src.freq_tbl = ftbl_camss_vfe_cpp_clk_msm8226;
2762 }
2763
2764 static int mmcc_msm8974_probe(struct platform_device *pdev)
2765 {
2766         struct regmap *regmap;
2767         const struct qcom_cc_desc *desc;
2768
2769         desc = of_device_get_match_data(&pdev->dev);
2770         if (!desc)
2771                 return -EINVAL;
2772
2773         regmap = qcom_cc_map(pdev, desc);
2774         if (IS_ERR(regmap))
2775                 return PTR_ERR(regmap);
2776
2777         if (desc == &mmcc_msm8974_desc) {
2778                 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2779                 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2780         } else {
2781                 msm8226_clock_override();
2782         }
2783
2784         return qcom_cc_really_probe(pdev, desc, regmap);
2785 }
2786
2787 static struct platform_driver mmcc_msm8974_driver = {
2788         .probe          = mmcc_msm8974_probe,
2789         .driver         = {
2790                 .name   = "mmcc-msm8974",
2791                 .of_match_table = mmcc_msm8974_match_table,
2792         },
2793 };
2794 module_platform_driver(mmcc_msm8974_driver);
2795
2796 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2797 MODULE_LICENSE("GPL v2");
2798 MODULE_ALIAS("platform:mmcc-msm8974");