drivers/clk/qcom/mmcc-msm8974.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
  18 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_MMPLL0,
  31         P_EDPLINK,
  32         P_MMPLL1,
  33         P_HDMIPLL,
  34         P_GPLL0,
  35         P_EDPVCO,
  36         P_GPLL1,
  37         P_DSI0PLL,
  38         P_DSI0PLL_BYTE,
  39         P_MMPLL2,
  40         P_MMPLL3,
  41         P_DSI1PLL,
  42         P_DSI1PLL_BYTE,
  43 };
  44
  45 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
  46         { P_XO, 0 },
  47         { P_MMPLL0, 1 },
  48         { P_MMPLL1, 2 },
  49         { P_GPLL0, 5 }
  50 };
  51
  52 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
  53         "xo",
  54         "mmpll0_vote",
  55         "mmpll1_vote",
  56         "mmss_gpll0_vote",
  57 };
  58
  59 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
  60         { P_XO, 0 },
  61         { P_MMPLL0, 1 },
  62         { P_HDMIPLL, 4 },
  63         { P_GPLL0, 5 },
  64         { P_DSI0PLL, 2 },
  65         { P_DSI1PLL, 3 }
  66 };
  67
  68 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
  69         "xo",
  70         "mmpll0_vote",
  71         "hdmipll",
  72         "mmss_gpll0_vote",
  73         "dsi0pll",
  74         "dsi1pll",
  75 };
  76
  77 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
  78         { P_XO, 0 },
  79         { P_MMPLL0, 1 },
  80         { P_MMPLL1, 2 },
  81         { P_GPLL0, 5 },
  82         { P_MMPLL3, 3 }
  83 };
  84
  85 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
  86         "xo",
  87         "mmpll0_vote",
  88         "mmpll1_vote",
  89         "mmss_gpll0_vote",
  90         "mmpll3",
  91 };
  92
  93 static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
  94         { P_XO, 0 },
  95         { P_MMPLL0, 1 },
  96         { P_MMPLL1, 2 },
  97         { P_GPLL0, 5 },
  98         { P_GPLL1, 4 }
  99 };
 100
 101 static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = {
 102         "xo",
 103         "mmpll0_vote",
 104         "mmpll1_vote",
 105         "mmss_gpll0_vote",
 106         "gpll1_vote",
 107 };
 108
 109 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
 110         { P_XO, 0 },
 111         { P_EDPLINK, 4 },
 112         { P_HDMIPLL, 3 },
 113         { P_EDPVCO, 5 },
 114         { P_DSI0PLL, 1 },
 115         { P_DSI1PLL, 2 }
 116 };
 117
 118 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
 119         "xo",
 120         "edp_link_clk",
 121         "hdmipll",
 122         "edp_vco_div",
 123         "dsi0pll",
 124         "dsi1pll",
 125 };
 126
 127 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
 128         { P_XO, 0 },
 129         { P_EDPLINK, 4 },
 130         { P_HDMIPLL, 3 },
 131         { P_GPLL0, 5 },
 132         { P_DSI0PLL, 1 },
 133         { P_DSI1PLL, 2 }
 134 };
 135
 136 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
 137         "xo",
 138         "edp_link_clk",
 139         "hdmipll",
 140         "gpll0_vote",
 141         "dsi0pll",
 142         "dsi1pll",
 143 };
 144
 145 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
 146         { P_XO, 0 },
 147         { P_EDPLINK, 4 },
 148         { P_HDMIPLL, 3 },
 149         { P_GPLL0, 5 },
 150         { P_DSI0PLL_BYTE, 1 },
 151         { P_DSI1PLL_BYTE, 2 }
 152 };
 153
 154 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
 155         "xo",
 156         "edp_link_clk",
 157         "hdmipll",
 158         "gpll0_vote",
 159         "dsi0pllbyte",
 160         "dsi1pllbyte",
 161 };
 162
 163 static struct clk_pll mmpll0 = {
 164         .l_reg = 0x0004,
 165         .m_reg = 0x0008,
 166         .n_reg = 0x000c,
 167         .config_reg = 0x0014,
 168         .mode_reg = 0x0000,
 169         .status_reg = 0x001c,
 170         .status_bit = 17,
 171         .clkr.hw.init = &(struct clk_init_data){
 172                 .name = "mmpll0",
 173                 .parent_names = (const char *[]){ "xo" },
 174                 .num_parents = 1,
 175                 .ops = &clk_pll_ops,
 176         },
 177 };
 178
 179 static struct clk_regmap mmpll0_vote = {
 180         .enable_reg = 0x0100,
 181         .enable_mask = BIT(0),
 182         .hw.init = &(struct clk_init_data){
 183                 .name = "mmpll0_vote",
 184                 .parent_names = (const char *[]){ "mmpll0" },
 185                 .num_parents = 1,
 186                 .ops = &clk_pll_vote_ops,
 187         },
 188 };
 189
 190 static struct clk_pll mmpll1 = {
 191         .l_reg = 0x0044,
 192         .m_reg = 0x0048,
 193         .n_reg = 0x004c,
 194         .config_reg = 0x0050,
 195         .mode_reg = 0x0040,
 196         .status_reg = 0x005c,
 197         .status_bit = 17,
 198         .clkr.hw.init = &(struct clk_init_data){
 199                 .name = "mmpll1",
 200                 .parent_names = (const char *[]){ "xo" },
 201                 .num_parents = 1,
 202                 .ops = &clk_pll_ops,
 203         },
 204 };
 205
 206 static struct clk_regmap mmpll1_vote = {
 207         .enable_reg = 0x0100,
 208         .enable_mask = BIT(1),
 209         .hw.init = &(struct clk_init_data){
 210                 .name = "mmpll1_vote",
 211                 .parent_names = (const char *[]){ "mmpll1" },
 212                 .num_parents = 1,
 213                 .ops = &clk_pll_vote_ops,
 214         },
 215 };
 216
 217 static struct clk_pll mmpll2 = {
 218         .l_reg = 0x4104,
 219         .m_reg = 0x4108,
 220         .n_reg = 0x410c,
 221         .config_reg = 0x4110,
 222         .mode_reg = 0x4100,
 223         .status_reg = 0x411c,
 224         .clkr.hw.init = &(struct clk_init_data){
 225                 .name = "mmpll2",
 226                 .parent_names = (const char *[]){ "xo" },
 227                 .num_parents = 1,
 228                 .ops = &clk_pll_ops,
 229         },
 230 };
 231
 232 static struct clk_pll mmpll3 = {
 233         .l_reg = 0x0084,
 234         .m_reg = 0x0088,
 235         .n_reg = 0x008c,
 236         .config_reg = 0x0090,
 237         .mode_reg = 0x0080,
 238         .status_reg = 0x009c,
 239         .status_bit = 17,
 240         .clkr.hw.init = &(struct clk_init_data){
 241                 .name = "mmpll3",
 242                 .parent_names = (const char *[]){ "xo" },
 243                 .num_parents = 1,
 244                 .ops = &clk_pll_ops,
 245         },
 246 };
 247
 248 static struct clk_rcg2 mmss_ahb_clk_src = {
 249         .cmd_rcgr = 0x5000,
 250         .hid_width = 5,
 251         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 252         .clkr.hw.init = &(struct clk_init_data){
 253                 .name = "mmss_ahb_clk_src",
 254                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 255                 .num_parents = 4,
 256                 .ops = &clk_rcg2_ops,
 257         },
 258 };
 259
 260 static struct freq_tbl ftbl_mmss_axi_clk[] = {
 261         F( 19200000, P_XO, 1, 0, 0),
 262         F( 37500000, P_GPLL0, 16, 0, 0),
 263         F( 50000000, P_GPLL0, 12, 0, 0),
 264         F( 75000000, P_GPLL0, 8, 0, 0),
 265         F(100000000, P_GPLL0, 6, 0, 0),
 266         F(150000000, P_GPLL0, 4, 0, 0),
 267         F(291750000, P_MMPLL1, 4, 0, 0),
 268         F(400000000, P_MMPLL0, 2, 0, 0),
 269         F(466800000, P_MMPLL1, 2.5, 0, 0),
 270 };
 271
 272 static struct clk_rcg2 mmss_axi_clk_src = {
 273         .cmd_rcgr = 0x5040,
 274         .hid_width = 5,
 275         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 276         .freq_tbl = ftbl_mmss_axi_clk,
 277         .clkr.hw.init = &(struct clk_init_data){
 278                 .name = "mmss_axi_clk_src",
 279                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 280                 .num_parents = 4,
 281                 .ops = &clk_rcg2_ops,
 282         },
 283 };
 284
 285 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
 286         F( 19200000, P_XO, 1, 0, 0),
 287         F( 37500000, P_GPLL0, 16, 0, 0),
 288         F( 50000000, P_GPLL0, 12, 0, 0),
 289         F( 75000000, P_GPLL0, 8, 0, 0),
 290         F(100000000, P_GPLL0, 6, 0, 0),
 291         F(150000000, P_GPLL0, 4, 0, 0),
 292         F(291750000, P_MMPLL1, 4, 0, 0),
 293         F(400000000, P_MMPLL0, 2, 0, 0),
 294 };
 295
 296 static struct clk_rcg2 ocmemnoc_clk_src = {
 297         .cmd_rcgr = 0x5090,
 298         .hid_width = 5,
 299         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 300         .freq_tbl = ftbl_ocmemnoc_clk,
 301         .clkr.hw.init = &(struct clk_init_data){
 302                 .name = "ocmemnoc_clk_src",
 303                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 304                 .num_parents = 4,
 305                 .ops = &clk_rcg2_ops,
 306         },
 307 };
 308
 309 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
 310         F(100000000, P_GPLL0, 6, 0, 0),
 311         F(200000000, P_MMPLL0, 4, 0, 0),
 312         { }
 313 };
 314
 315 static struct clk_rcg2 csi0_clk_src = {
 316         .cmd_rcgr = 0x3090,
 317         .hid_width = 5,
 318         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 319         .freq_tbl = ftbl_camss_csi0_3_clk,
 320         .clkr.hw.init = &(struct clk_init_data){
 321                 .name = "csi0_clk_src",
 322                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 323                 .num_parents = 4,
 324                 .ops = &clk_rcg2_ops,
 325         },
 326 };
 327
 328 static struct clk_rcg2 csi1_clk_src = {
 329         .cmd_rcgr = 0x3100,
 330         .hid_width = 5,
 331         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 332         .freq_tbl = ftbl_camss_csi0_3_clk,
 333         .clkr.hw.init = &(struct clk_init_data){
 334                 .name = "csi1_clk_src",
 335                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 336                 .num_parents = 4,
 337                 .ops = &clk_rcg2_ops,
 338         },
 339 };
 340
 341 static struct clk_rcg2 csi2_clk_src = {
 342         .cmd_rcgr = 0x3160,
 343         .hid_width = 5,
 344         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 345         .freq_tbl = ftbl_camss_csi0_3_clk,
 346         .clkr.hw.init = &(struct clk_init_data){
 347                 .name = "csi2_clk_src",
 348                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 349                 .num_parents = 4,
 350                 .ops = &clk_rcg2_ops,
 351         },
 352 };
 353
 354 static struct clk_rcg2 csi3_clk_src = {
 355         .cmd_rcgr = 0x31c0,
 356         .hid_width = 5,
 357         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 358         .freq_tbl = ftbl_camss_csi0_3_clk,
 359         .clkr.hw.init = &(struct clk_init_data){
 360                 .name = "csi3_clk_src",
 361                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 362                 .num_parents = 4,
 363                 .ops = &clk_rcg2_ops,
 364         },
 365 };
 366
 367 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
 368         F(37500000, P_GPLL0, 16, 0, 0),
 369         F(50000000, P_GPLL0, 12, 0, 0),
 370         F(60000000, P_GPLL0, 10, 0, 0),
 371         F(80000000, P_GPLL0, 7.5, 0, 0),
 372         F(100000000, P_GPLL0, 6, 0, 0),
 373         F(109090000, P_GPLL0, 5.5, 0, 0),
 374         F(133330000, P_GPLL0, 4.5, 0, 0),
 375         F(200000000, P_GPLL0, 3, 0, 0),
 376         F(228570000, P_MMPLL0, 3.5, 0, 0),
 377         F(266670000, P_MMPLL0, 3, 0, 0),
 378         F(320000000, P_MMPLL0, 2.5, 0, 0),
 379         F(400000000, P_MMPLL0, 2, 0, 0),
 380         F(465000000, P_MMPLL3, 2, 0, 0),
 381         { }
 382 };
 383
 384 static struct clk_rcg2 vfe0_clk_src = {
 385         .cmd_rcgr = 0x3600,
 386         .hid_width = 5,
 387         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 388         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 389         .clkr.hw.init = &(struct clk_init_data){
 390                 .name = "vfe0_clk_src",
 391                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 392                 .num_parents = 4,
 393                 .ops = &clk_rcg2_ops,
 394         },
 395 };
 396
 397 static struct clk_rcg2 vfe1_clk_src = {
 398         .cmd_rcgr = 0x3620,
 399         .hid_width = 5,
 400         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 401         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 402         .clkr.hw.init = &(struct clk_init_data){
 403                 .name = "vfe1_clk_src",
 404                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 405                 .num_parents = 4,
 406                 .ops = &clk_rcg2_ops,
 407         },
 408 };
 409
 410 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
 411         F(37500000, P_GPLL0, 16, 0, 0),
 412         F(60000000, P_GPLL0, 10, 0, 0),
 413         F(75000000, P_GPLL0, 8, 0, 0),
 414         F(85710000, P_GPLL0, 7, 0, 0),
 415         F(100000000, P_GPLL0, 6, 0, 0),
 416         F(133330000, P_MMPLL0, 6, 0, 0),
 417         F(160000000, P_MMPLL0, 5, 0, 0),
 418         F(200000000, P_MMPLL0, 4, 0, 0),
 419         F(228570000, P_MMPLL0, 3.5, 0, 0),
 420         F(240000000, P_GPLL0, 2.5, 0, 0),
 421         F(266670000, P_MMPLL0, 3, 0, 0),
 422         F(320000000, P_MMPLL0, 2.5, 0, 0),
 423         { }
 424 };
 425
 426 static struct clk_rcg2 mdp_clk_src = {
 427         .cmd_rcgr = 0x2040,
 428         .hid_width = 5,
 429         .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
 430         .freq_tbl = ftbl_mdss_mdp_clk,
 431         .clkr.hw.init = &(struct clk_init_data){
 432                 .name = "mdp_clk_src",
 433                 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
 434                 .num_parents = 6,
 435                 .ops = &clk_rcg2_ops,
 436         },
 437 };
 438
 439 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
 440         F(75000000, P_GPLL0, 8, 0, 0),
 441         F(133330000, P_GPLL0, 4.5, 0, 0),
 442         F(200000000, P_GPLL0, 3, 0, 0),
 443         F(228570000, P_MMPLL0, 3.5, 0, 0),
 444         F(266670000, P_MMPLL0, 3, 0, 0),
 445         F(320000000, P_MMPLL0, 2.5, 0, 0),
 446         { }
 447 };
 448
 449 static struct clk_rcg2 jpeg0_clk_src = {
 450         .cmd_rcgr = 0x3500,
 451         .hid_width = 5,
 452         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 453         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 454         .clkr.hw.init = &(struct clk_init_data){
 455                 .name = "jpeg0_clk_src",
 456                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 457                 .num_parents = 4,
 458                 .ops = &clk_rcg2_ops,
 459         },
 460 };
 461
 462 static struct clk_rcg2 jpeg1_clk_src = {
 463         .cmd_rcgr = 0x3520,
 464         .hid_width = 5,
 465         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 466         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 467         .clkr.hw.init = &(struct clk_init_data){
 468                 .name = "jpeg1_clk_src",
 469                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 470                 .num_parents = 4,
 471                 .ops = &clk_rcg2_ops,
 472         },
 473 };
 474
 475 static struct clk_rcg2 jpeg2_clk_src = {
 476         .cmd_rcgr = 0x3540,
 477         .hid_width = 5,
 478         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 479         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 480         .clkr.hw.init = &(struct clk_init_data){
 481                 .name = "jpeg2_clk_src",
 482                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 483                 .num_parents = 4,
 484                 .ops = &clk_rcg2_ops,
 485         },
 486 };
 487
 488 static struct clk_rcg2 pclk0_clk_src = {
 489         .cmd_rcgr = 0x2000,
 490         .mnd_width = 8,
 491         .hid_width = 5,
 492         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 493         .clkr.hw.init = &(struct clk_init_data){
 494                 .name = "pclk0_clk_src",
 495                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 496                 .num_parents = 6,
 497                 .ops = &clk_pixel_ops,
 498                 .flags = CLK_SET_RATE_PARENT,
 499         },
 500 };
 501
 502 static struct clk_rcg2 pclk1_clk_src = {
 503         .cmd_rcgr = 0x2020,
 504         .mnd_width = 8,
 505         .hid_width = 5,
 506         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 507         .clkr.hw.init = &(struct clk_init_data){
 508                 .name = "pclk1_clk_src",
 509                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 510                 .num_parents = 6,
 511                 .ops = &clk_pixel_ops,
 512                 .flags = CLK_SET_RATE_PARENT,
 513         },
 514 };
 515
 516 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
 517         F(50000000, P_GPLL0, 12, 0, 0),
 518         F(100000000, P_GPLL0, 6, 0, 0),
 519         F(133330000, P_MMPLL0, 6, 0, 0),
 520         F(200000000, P_MMPLL0, 4, 0, 0),
 521         F(266670000, P_MMPLL0, 3, 0, 0),
 522         F(465000000, P_MMPLL3, 2, 0, 0),
 523         { }
 524 };
 525
 526 static struct clk_rcg2 vcodec0_clk_src = {
 527         .cmd_rcgr = 0x1000,
 528         .mnd_width = 8,
 529         .hid_width = 5,
 530         .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
 531         .freq_tbl = ftbl_venus0_vcodec0_clk,
 532         .clkr.hw.init = &(struct clk_init_data){
 533                 .name = "vcodec0_clk_src",
 534                 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
 535                 .num_parents = 5,
 536                 .ops = &clk_rcg2_ops,
 537         },
 538 };
 539
 540 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
 541         F(19200000, P_XO, 1, 0, 0),
 542         { }
 543 };
 544
 545 static struct clk_rcg2 cci_clk_src = {
 546         .cmd_rcgr = 0x3300,
 547         .hid_width = 5,
 548         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 549         .freq_tbl = ftbl_camss_cci_cci_clk,
 550         .clkr.hw.init = &(struct clk_init_data){
 551                 .name = "cci_clk_src",
 552                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 553                 .num_parents = 4,
 554                 .ops = &clk_rcg2_ops,
 555         },
 556 };
 557
 558 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
 559         F(10000, P_XO, 16, 1, 120),
 560         F(24000, P_XO, 16, 1, 50),
 561         F(6000000, P_GPLL0, 10, 1, 10),
 562         F(12000000, P_GPLL0, 10, 1, 5),
 563         F(13000000, P_GPLL0, 4, 13, 150),
 564         F(24000000, P_GPLL0, 5, 1, 5),
 565         { }
 566 };
 567
 568 static struct clk_rcg2 camss_gp0_clk_src = {
 569         .cmd_rcgr = 0x3420,
 570         .mnd_width = 8,
 571         .hid_width = 5,
 572         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 573         .freq_tbl = ftbl_camss_gp0_1_clk,
 574         .clkr.hw.init = &(struct clk_init_data){
 575                 .name = "camss_gp0_clk_src",
 576                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 577                 .num_parents = 5,
 578                 .ops = &clk_rcg2_ops,
 579         },
 580 };
 581
 582 static struct clk_rcg2 camss_gp1_clk_src = {
 583         .cmd_rcgr = 0x3450,
 584         .mnd_width = 8,
 585         .hid_width = 5,
 586         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 587         .freq_tbl = ftbl_camss_gp0_1_clk,
 588         .clkr.hw.init = &(struct clk_init_data){
 589                 .name = "camss_gp1_clk_src",
 590                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 591                 .num_parents = 5,
 592                 .ops = &clk_rcg2_ops,
 593         },
 594 };
 595
 596 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
 597         F(4800000, P_XO, 4, 0, 0),
 598         F(6000000, P_GPLL0, 10, 1, 10),
 599         F(8000000, P_GPLL0, 15, 1, 5),
 600         F(9600000, P_XO, 2, 0, 0),
 601         F(16000000, P_GPLL0, 12.5, 1, 3),
 602         F(19200000, P_XO, 1, 0, 0),
 603         F(24000000, P_GPLL0, 5, 1, 5),
 604         F(32000000, P_MMPLL0, 5, 1, 5),
 605         F(48000000, P_GPLL0, 12.5, 0, 0),
 606         F(64000000, P_MMPLL0, 12.5, 0, 0),
 607         F(66670000, P_GPLL0, 9, 0, 0),
 608         { }
 609 };
 610
 611 static struct clk_rcg2 mclk0_clk_src = {
 612         .cmd_rcgr = 0x3360,
 613         .hid_width = 5,
 614         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 615         .freq_tbl = ftbl_camss_mclk0_3_clk,
 616         .clkr.hw.init = &(struct clk_init_data){
 617                 .name = "mclk0_clk_src",
 618                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 619                 .num_parents = 4,
 620                 .ops = &clk_rcg2_ops,
 621         },
 622 };
 623
 624 static struct clk_rcg2 mclk1_clk_src = {
 625         .cmd_rcgr = 0x3390,
 626         .hid_width = 5,
 627         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 628         .freq_tbl = ftbl_camss_mclk0_3_clk,
 629         .clkr.hw.init = &(struct clk_init_data){
 630                 .name = "mclk1_clk_src",
 631                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 632                 .num_parents = 4,
 633                 .ops = &clk_rcg2_ops,
 634         },
 635 };
 636
 637 static struct clk_rcg2 mclk2_clk_src = {
 638         .cmd_rcgr = 0x33c0,
 639         .hid_width = 5,
 640         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 641         .freq_tbl = ftbl_camss_mclk0_3_clk,
 642         .clkr.hw.init = &(struct clk_init_data){
 643                 .name = "mclk2_clk_src",
 644                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 645                 .num_parents = 4,
 646                 .ops = &clk_rcg2_ops,
 647         },
 648 };
 649
 650 static struct clk_rcg2 mclk3_clk_src = {
 651         .cmd_rcgr = 0x33f0,
 652         .hid_width = 5,
 653         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 654         .freq_tbl = ftbl_camss_mclk0_3_clk,
 655         .clkr.hw.init = &(struct clk_init_data){
 656                 .name = "mclk3_clk_src",
 657                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 658                 .num_parents = 4,
 659                 .ops = &clk_rcg2_ops,
 660         },
 661 };
 662
 663 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
 664         F(100000000, P_GPLL0, 6, 0, 0),
 665         F(200000000, P_MMPLL0, 4, 0, 0),
 666         { }
 667 };
 668
 669 static struct clk_rcg2 csi0phytimer_clk_src = {
 670         .cmd_rcgr = 0x3000,
 671         .hid_width = 5,
 672         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 673         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 674         .clkr.hw.init = &(struct clk_init_data){
 675                 .name = "csi0phytimer_clk_src",
 676                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 677                 .num_parents = 4,
 678                 .ops = &clk_rcg2_ops,
 679         },
 680 };
 681
 682 static struct clk_rcg2 csi1phytimer_clk_src = {
 683         .cmd_rcgr = 0x3030,
 684         .hid_width = 5,
 685         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 686         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 687         .clkr.hw.init = &(struct clk_init_data){
 688                 .name = "csi1phytimer_clk_src",
 689                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 690                 .num_parents = 4,
 691                 .ops = &clk_rcg2_ops,
 692         },
 693 };
 694
 695 static struct clk_rcg2 csi2phytimer_clk_src = {
 696         .cmd_rcgr = 0x3060,
 697         .hid_width = 5,
 698         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 699         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 700         .clkr.hw.init = &(struct clk_init_data){
 701                 .name = "csi2phytimer_clk_src",
 702                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 703                 .num_parents = 4,
 704                 .ops = &clk_rcg2_ops,
 705         },
 706 };
 707
 708 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
 709         F(133330000, P_GPLL0, 4.5, 0, 0),
 710         F(266670000, P_MMPLL0, 3, 0, 0),
 711         F(320000000, P_MMPLL0, 2.5, 0, 0),
 712         F(400000000, P_MMPLL0, 2, 0, 0),
 713         F(465000000, P_MMPLL3, 2, 0, 0),
 714         { }
 715 };
 716
 717 static struct clk_rcg2 cpp_clk_src = {
 718         .cmd_rcgr = 0x3640,
 719         .hid_width = 5,
 720         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 721         .freq_tbl = ftbl_camss_vfe_cpp_clk,
 722         .clkr.hw.init = &(struct clk_init_data){
 723                 .name = "cpp_clk_src",
 724                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 725                 .num_parents = 4,
 726                 .ops = &clk_rcg2_ops,
 727         },
 728 };
 729
 730 static struct freq_tbl byte_freq_tbl[] = {
 731         { .src = P_DSI0PLL_BYTE },
 732         { }
 733 };
 734
 735 static struct clk_rcg2 byte0_clk_src = {
 736         .cmd_rcgr = 0x2120,
 737         .hid_width = 5,
 738         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 739         .freq_tbl = byte_freq_tbl,
 740         .clkr.hw.init = &(struct clk_init_data){
 741                 .name = "byte0_clk_src",
 742                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 743                 .num_parents = 6,
 744                 .ops = &clk_byte2_ops,
 745                 .flags = CLK_SET_RATE_PARENT,
 746         },
 747 };
 748
 749 static struct clk_rcg2 byte1_clk_src = {
 750         .cmd_rcgr = 0x2140,
 751         .hid_width = 5,
 752         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 753         .freq_tbl = byte_freq_tbl,
 754         .clkr.hw.init = &(struct clk_init_data){
 755                 .name = "byte1_clk_src",
 756                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 757                 .num_parents = 6,
 758                 .ops = &clk_byte2_ops,
 759                 .flags = CLK_SET_RATE_PARENT,
 760         },
 761 };
 762
 763 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
 764         F(19200000, P_XO, 1, 0, 0),
 765         { }
 766 };
 767
 768 static struct clk_rcg2 edpaux_clk_src = {
 769         .cmd_rcgr = 0x20e0,
 770         .hid_width = 5,
 771         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 772         .freq_tbl = ftbl_mdss_edpaux_clk,
 773         .clkr.hw.init = &(struct clk_init_data){
 774                 .name = "edpaux_clk_src",
 775                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 776                 .num_parents = 4,
 777                 .ops = &clk_rcg2_ops,
 778         },
 779 };
 780
 781 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
 782         F(135000000, P_EDPLINK, 2, 0, 0),
 783         F(270000000, P_EDPLINK, 11, 0, 0),
 784         { }
 785 };
 786
 787 static struct clk_rcg2 edplink_clk_src = {
 788         .cmd_rcgr = 0x20c0,
 789         .hid_width = 5,
 790         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 791         .freq_tbl = ftbl_mdss_edplink_clk,
 792         .clkr.hw.init = &(struct clk_init_data){
 793                 .name = "edplink_clk_src",
 794                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 795                 .num_parents = 6,
 796                 .ops = &clk_rcg2_ops,
 797                 .flags = CLK_SET_RATE_PARENT,
 798         },
 799 };
 800
 801 static struct freq_tbl edp_pixel_freq_tbl[] = {
 802         { .src = P_EDPVCO },
 803         { }
 804 };
 805
 806 static struct clk_rcg2 edppixel_clk_src = {
 807         .cmd_rcgr = 0x20a0,
 808         .mnd_width = 8,
 809         .hid_width = 5,
 810         .parent_map = mmcc_xo_dsi_hdmi_edp_map,
 811         .freq_tbl = edp_pixel_freq_tbl,
 812         .clkr.hw.init = &(struct clk_init_data){
 813                 .name = "edppixel_clk_src",
 814                 .parent_names = mmcc_xo_dsi_hdmi_edp,
 815                 .num_parents = 6,
 816                 .ops = &clk_edp_pixel_ops,
 817         },
 818 };
 819
 820 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 821         F(19200000, P_XO, 1, 0, 0),
 822         { }
 823 };
 824
 825 static struct clk_rcg2 esc0_clk_src = {
 826         .cmd_rcgr = 0x2160,
 827         .hid_width = 5,
 828         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 829         .freq_tbl = ftbl_mdss_esc0_1_clk,
 830         .clkr.hw.init = &(struct clk_init_data){
 831                 .name = "esc0_clk_src",
 832                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 833                 .num_parents = 6,
 834                 .ops = &clk_rcg2_ops,
 835         },
 836 };
 837
 838 static struct clk_rcg2 esc1_clk_src = {
 839         .cmd_rcgr = 0x2180,
 840         .hid_width = 5,
 841         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 842         .freq_tbl = ftbl_mdss_esc0_1_clk,
 843         .clkr.hw.init = &(struct clk_init_data){
 844                 .name = "esc1_clk_src",
 845                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 846                 .num_parents = 6,
 847                 .ops = &clk_rcg2_ops,
 848         },
 849 };
 850
 851 static struct freq_tbl extpclk_freq_tbl[] = {
 852         { .src = P_HDMIPLL },
 853         { }
 854 };
 855
 856 static struct clk_rcg2 extpclk_clk_src = {
 857         .cmd_rcgr = 0x2060,
 858         .hid_width = 5,
 859         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 860         .freq_tbl = extpclk_freq_tbl,
 861         .clkr.hw.init = &(struct clk_init_data){
 862                 .name = "extpclk_clk_src",
 863                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 864                 .num_parents = 6,
 865                 .ops = &clk_byte_ops,
 866                 .flags = CLK_SET_RATE_PARENT,
 867         },
 868 };
 869
 870 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 871         F(19200000, P_XO, 1, 0, 0),
 872         { }
 873 };
 874
 875 static struct clk_rcg2 hdmi_clk_src = {
 876         .cmd_rcgr = 0x2100,
 877         .hid_width = 5,
 878         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 879         .freq_tbl = ftbl_mdss_hdmi_clk,
 880         .clkr.hw.init = &(struct clk_init_data){
 881                 .name = "hdmi_clk_src",
 882                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 883                 .num_parents = 4,
 884                 .ops = &clk_rcg2_ops,
 885         },
 886 };
 887
 888 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
 889         F(19200000, P_XO, 1, 0, 0),
 890         { }
 891 };
 892
 893 static struct clk_rcg2 vsync_clk_src = {
 894         .cmd_rcgr = 0x2080,
 895         .hid_width = 5,
 896         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 897         .freq_tbl = ftbl_mdss_vsync_clk,
 898         .clkr.hw.init = &(struct clk_init_data){
 899                 .name = "vsync_clk_src",
 900                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 901                 .num_parents = 4,
 902                 .ops = &clk_rcg2_ops,
 903         },
 904 };
 905
 906 static struct clk_branch camss_cci_cci_ahb_clk = {
 907         .halt_reg = 0x3348,
 908         .clkr = {
 909                 .enable_reg = 0x3348,
 910                 .enable_mask = BIT(0),
 911                 .hw.init = &(struct clk_init_data){
 912                         .name = "camss_cci_cci_ahb_clk",
 913                         .parent_names = (const char *[]){
 914                                 "mmss_ahb_clk_src",
 915                         },
 916                         .num_parents = 1,
 917                         .ops = &clk_branch2_ops,
 918                 },
 919         },
 920 };
 921
 922 static struct clk_branch camss_cci_cci_clk = {
 923         .halt_reg = 0x3344,
 924         .clkr = {
 925                 .enable_reg = 0x3344,
 926                 .enable_mask = BIT(0),
 927                 .hw.init = &(struct clk_init_data){
 928                         .name = "camss_cci_cci_clk",
 929                         .parent_names = (const char *[]){
 930                                 "cci_clk_src",
 931                         },
 932                         .num_parents = 1,
 933                         .flags = CLK_SET_RATE_PARENT,
 934                         .ops = &clk_branch2_ops,
 935                 },
 936         },
 937 };
 938
 939 static struct clk_branch camss_csi0_ahb_clk = {
 940         .halt_reg = 0x30bc,
 941         .clkr = {
 942                 .enable_reg = 0x30bc,
 943                 .enable_mask = BIT(0),
 944                 .hw.init = &(struct clk_init_data){
 945                         .name = "camss_csi0_ahb_clk",
 946                         .parent_names = (const char *[]){
 947                                 "mmss_ahb_clk_src",
 948                         },
 949                         .num_parents = 1,
 950                         .ops = &clk_branch2_ops,
 951                 },
 952         },
 953 };
 954
 955 static struct clk_branch camss_csi0_clk = {
 956         .halt_reg = 0x30b4,
 957         .clkr = {
 958                 .enable_reg = 0x30b4,
 959                 .enable_mask = BIT(0),
 960                 .hw.init = &(struct clk_init_data){
 961                         .name = "camss_csi0_clk",
 962                         .parent_names = (const char *[]){
 963                                 "csi0_clk_src",
 964                         },
 965                         .num_parents = 1,
 966                         .flags = CLK_SET_RATE_PARENT,
 967                         .ops = &clk_branch2_ops,
 968                 },
 969         },
 970 };
 971
 972 static struct clk_branch camss_csi0phy_clk = {
 973         .halt_reg = 0x30c4,
 974         .clkr = {
 975                 .enable_reg = 0x30c4,
 976                 .enable_mask = BIT(0),
 977                 .hw.init = &(struct clk_init_data){
 978                         .name = "camss_csi0phy_clk",
 979                         .parent_names = (const char *[]){
 980                                 "csi0_clk_src",
 981                         },
 982                         .num_parents = 1,
 983                         .flags = CLK_SET_RATE_PARENT,
 984                         .ops = &clk_branch2_ops,
 985                 },
 986         },
 987 };
 988
 989 static struct clk_branch camss_csi0pix_clk = {
 990         .halt_reg = 0x30e4,
 991         .clkr = {
 992                 .enable_reg = 0x30e4,
 993                 .enable_mask = BIT(0),
 994                 .hw.init = &(struct clk_init_data){
 995                         .name = "camss_csi0pix_clk",
 996                         .parent_names = (const char *[]){
 997                                 "csi0_clk_src",
 998                         },
 999                         .num_parents = 1,
1000                         .flags = CLK_SET_RATE_PARENT,
1001                         .ops = &clk_branch2_ops,
1002                 },
1003         },
1004 };
1005
1006 static struct clk_branch camss_csi0rdi_clk = {
1007         .halt_reg = 0x30d4,
1008         .clkr = {
1009                 .enable_reg = 0x30d4,
1010                 .enable_mask = BIT(0),
1011                 .hw.init = &(struct clk_init_data){
1012                         .name = "camss_csi0rdi_clk",
1013                         .parent_names = (const char *[]){
1014                                 "csi0_clk_src",
1015                         },
1016                         .num_parents = 1,
1017                         .flags = CLK_SET_RATE_PARENT,
1018                         .ops = &clk_branch2_ops,
1019                 },
1020         },
1021 };
1022
1023 static struct clk_branch camss_csi1_ahb_clk = {
1024         .halt_reg = 0x3128,
1025         .clkr = {
1026                 .enable_reg = 0x3128,
1027                 .enable_mask = BIT(0),
1028                 .hw.init = &(struct clk_init_data){
1029                         .name = "camss_csi1_ahb_clk",
1030                         .parent_names = (const char *[]){
1031                                 "mmss_ahb_clk_src",
1032                         },
1033                         .num_parents = 1,
1034                         .ops = &clk_branch2_ops,
1035                 },
1036         },
1037 };
1038
1039 static struct clk_branch camss_csi1_clk = {
1040         .halt_reg = 0x3124,
1041         .clkr = {
1042                 .enable_reg = 0x3124,
1043                 .enable_mask = BIT(0),
1044                 .hw.init = &(struct clk_init_data){
1045                         .name = "camss_csi1_clk",
1046                         .parent_names = (const char *[]){
1047                                 "csi1_clk_src",
1048                         },
1049                         .num_parents = 1,
1050                         .flags = CLK_SET_RATE_PARENT,
1051                         .ops = &clk_branch2_ops,
1052                 },
1053         },
1054 };
1055
1056 static struct clk_branch camss_csi1phy_clk = {
1057         .halt_reg = 0x3134,
1058         .clkr = {
1059                 .enable_reg = 0x3134,
1060                 .enable_mask = BIT(0),
1061                 .hw.init = &(struct clk_init_data){
1062                         .name = "camss_csi1phy_clk",
1063                         .parent_names = (const char *[]){
1064                                 "csi1_clk_src",
1065                         },
1066                         .num_parents = 1,
1067                         .flags = CLK_SET_RATE_PARENT,
1068                         .ops = &clk_branch2_ops,
1069                 },
1070         },
1071 };
1072
1073 static struct clk_branch camss_csi1pix_clk = {
1074         .halt_reg = 0x3154,
1075         .clkr = {
1076                 .enable_reg = 0x3154,
1077                 .enable_mask = BIT(0),
1078                 .hw.init = &(struct clk_init_data){
1079                         .name = "camss_csi1pix_clk",
1080                         .parent_names = (const char *[]){
1081                                 "csi1_clk_src",
1082                         },
1083                         .num_parents = 1,
1084                         .flags = CLK_SET_RATE_PARENT,
1085                         .ops = &clk_branch2_ops,
1086                 },
1087         },
1088 };
1089
1090 static struct clk_branch camss_csi1rdi_clk = {
1091         .halt_reg = 0x3144,
1092         .clkr = {
1093                 .enable_reg = 0x3144,
1094                 .enable_mask = BIT(0),
1095                 .hw.init = &(struct clk_init_data){
1096                         .name = "camss_csi1rdi_clk",
1097                         .parent_names = (const char *[]){
1098                                 "csi1_clk_src",
1099                         },
1100                         .num_parents = 1,
1101                         .flags = CLK_SET_RATE_PARENT,
1102                         .ops = &clk_branch2_ops,
1103                 },
1104         },
1105 };
1106
1107 static struct clk_branch camss_csi2_ahb_clk = {
1108         .halt_reg = 0x3188,
1109         .clkr = {
1110                 .enable_reg = 0x3188,
1111                 .enable_mask = BIT(0),
1112                 .hw.init = &(struct clk_init_data){
1113                         .name = "camss_csi2_ahb_clk",
1114                         .parent_names = (const char *[]){
1115                                 "mmss_ahb_clk_src",
1116                         },
1117                         .num_parents = 1,
1118                         .ops = &clk_branch2_ops,
1119                 },
1120         },
1121 };
1122
1123 static struct clk_branch camss_csi2_clk = {
1124         .halt_reg = 0x3184,
1125         .clkr = {
1126                 .enable_reg = 0x3184,
1127                 .enable_mask = BIT(0),
1128                 .hw.init = &(struct clk_init_data){
1129                         .name = "camss_csi2_clk",
1130                         .parent_names = (const char *[]){
1131                                 "csi2_clk_src",
1132                         },
1133                         .num_parents = 1,
1134                         .flags = CLK_SET_RATE_PARENT,
1135                         .ops = &clk_branch2_ops,
1136                 },
1137         },
1138 };
1139
1140 static struct clk_branch camss_csi2phy_clk = {
1141         .halt_reg = 0x3194,
1142         .clkr = {
1143                 .enable_reg = 0x3194,
1144                 .enable_mask = BIT(0),
1145                 .hw.init = &(struct clk_init_data){
1146                         .name = "camss_csi2phy_clk",
1147                         .parent_names = (const char *[]){
1148                                 "csi2_clk_src",
1149                         },
1150                         .num_parents = 1,
1151                         .flags = CLK_SET_RATE_PARENT,
1152                         .ops = &clk_branch2_ops,
1153                 },
1154         },
1155 };
1156
1157 static struct clk_branch camss_csi2pix_clk = {
1158         .halt_reg = 0x31b4,
1159         .clkr = {
1160                 .enable_reg = 0x31b4,
1161                 .enable_mask = BIT(0),
1162                 .hw.init = &(struct clk_init_data){
1163                         .name = "camss_csi2pix_clk",
1164                         .parent_names = (const char *[]){
1165                                 "csi2_clk_src",
1166                         },
1167                         .num_parents = 1,
1168                         .flags = CLK_SET_RATE_PARENT,
1169                         .ops = &clk_branch2_ops,
1170                 },
1171         },
1172 };
1173
1174 static struct clk_branch camss_csi2rdi_clk = {
1175         .halt_reg = 0x31a4,
1176         .clkr = {
1177                 .enable_reg = 0x31a4,
1178                 .enable_mask = BIT(0),
1179                 .hw.init = &(struct clk_init_data){
1180                         .name = "camss_csi2rdi_clk",
1181                         .parent_names = (const char *[]){
1182                                 "csi2_clk_src",
1183                         },
1184                         .num_parents = 1,
1185                         .flags = CLK_SET_RATE_PARENT,
1186                         .ops = &clk_branch2_ops,
1187                 },
1188         },
1189 };
1190
1191 static struct clk_branch camss_csi3_ahb_clk = {
1192         .halt_reg = 0x31e8,
1193         .clkr = {
1194                 .enable_reg = 0x31e8,
1195                 .enable_mask = BIT(0),
1196                 .hw.init = &(struct clk_init_data){
1197                         .name = "camss_csi3_ahb_clk",
1198                         .parent_names = (const char *[]){
1199                                 "mmss_ahb_clk_src",
1200                         },
1201                         .num_parents = 1,
1202                         .ops = &clk_branch2_ops,
1203                 },
1204         },
1205 };
1206
1207 static struct clk_branch camss_csi3_clk = {
1208         .halt_reg = 0x31e4,
1209         .clkr = {
1210                 .enable_reg = 0x31e4,
1211                 .enable_mask = BIT(0),
1212                 .hw.init = &(struct clk_init_data){
1213                         .name = "camss_csi3_clk",
1214                         .parent_names = (const char *[]){
1215                                 "csi3_clk_src",
1216                         },
1217                         .num_parents = 1,
1218                         .flags = CLK_SET_RATE_PARENT,
1219                         .ops = &clk_branch2_ops,
1220                 },
1221         },
1222 };
1223
1224 static struct clk_branch camss_csi3phy_clk = {
1225         .halt_reg = 0x31f4,
1226         .clkr = {
1227                 .enable_reg = 0x31f4,
1228                 .enable_mask = BIT(0),
1229                 .hw.init = &(struct clk_init_data){
1230                         .name = "camss_csi3phy_clk",
1231                         .parent_names = (const char *[]){
1232                                 "csi3_clk_src",
1233                         },
1234                         .num_parents = 1,
1235                         .flags = CLK_SET_RATE_PARENT,
1236                         .ops = &clk_branch2_ops,
1237                 },
1238         },
1239 };
1240
1241 static struct clk_branch camss_csi3pix_clk = {
1242         .halt_reg = 0x3214,
1243         .clkr = {
1244                 .enable_reg = 0x3214,
1245                 .enable_mask = BIT(0),
1246                 .hw.init = &(struct clk_init_data){
1247                         .name = "camss_csi3pix_clk",
1248                         .parent_names = (const char *[]){
1249                                 "csi3_clk_src",
1250                         },
1251                         .num_parents = 1,
1252                         .flags = CLK_SET_RATE_PARENT,
1253                         .ops = &clk_branch2_ops,
1254                 },
1255         },
1256 };
1257
1258 static struct clk_branch camss_csi3rdi_clk = {
1259         .halt_reg = 0x3204,
1260         .clkr = {
1261                 .enable_reg = 0x3204,
1262                 .enable_mask = BIT(0),
1263                 .hw.init = &(struct clk_init_data){
1264                         .name = "camss_csi3rdi_clk",
1265                         .parent_names = (const char *[]){
1266                                 "csi3_clk_src",
1267                         },
1268                         .num_parents = 1,
1269                         .flags = CLK_SET_RATE_PARENT,
1270                         .ops = &clk_branch2_ops,
1271                 },
1272         },
1273 };
1274
1275 static struct clk_branch camss_csi_vfe0_clk = {
1276         .halt_reg = 0x3704,
1277         .clkr = {
1278                 .enable_reg = 0x3704,
1279                 .enable_mask = BIT(0),
1280                 .hw.init = &(struct clk_init_data){
1281                         .name = "camss_csi_vfe0_clk",
1282                         .parent_names = (const char *[]){
1283                                 "vfe0_clk_src",
1284                         },
1285                         .num_parents = 1,
1286                         .flags = CLK_SET_RATE_PARENT,
1287                         .ops = &clk_branch2_ops,
1288                 },
1289         },
1290 };
1291
1292 static struct clk_branch camss_csi_vfe1_clk = {
1293         .halt_reg = 0x3714,
1294         .clkr = {
1295                 .enable_reg = 0x3714,
1296                 .enable_mask = BIT(0),
1297                 .hw.init = &(struct clk_init_data){
1298                         .name = "camss_csi_vfe1_clk",
1299                         .parent_names = (const char *[]){
1300                                 "vfe1_clk_src",
1301                         },
1302                         .num_parents = 1,
1303                         .flags = CLK_SET_RATE_PARENT,
1304                         .ops = &clk_branch2_ops,
1305                 },
1306         },
1307 };
1308
1309 static struct clk_branch camss_gp0_clk = {
1310         .halt_reg = 0x3444,
1311         .clkr = {
1312                 .enable_reg = 0x3444,
1313                 .enable_mask = BIT(0),
1314                 .hw.init = &(struct clk_init_data){
1315                         .name = "camss_gp0_clk",
1316                         .parent_names = (const char *[]){
1317                                 "camss_gp0_clk_src",
1318                         },
1319                         .num_parents = 1,
1320                         .flags = CLK_SET_RATE_PARENT,
1321                         .ops = &clk_branch2_ops,
1322                 },
1323         },
1324 };
1325
1326 static struct clk_branch camss_gp1_clk = {
1327         .halt_reg = 0x3474,
1328         .clkr = {
1329                 .enable_reg = 0x3474,
1330                 .enable_mask = BIT(0),
1331                 .hw.init = &(struct clk_init_data){
1332                         .name = "camss_gp1_clk",
1333                         .parent_names = (const char *[]){
1334                                 "camss_gp1_clk_src",
1335                         },
1336                         .num_parents = 1,
1337                         .flags = CLK_SET_RATE_PARENT,
1338                         .ops = &clk_branch2_ops,
1339                 },
1340         },
1341 };
1342
1343 static struct clk_branch camss_ispif_ahb_clk = {
1344         .halt_reg = 0x3224,
1345         .clkr = {
1346                 .enable_reg = 0x3224,
1347                 .enable_mask = BIT(0),
1348                 .hw.init = &(struct clk_init_data){
1349                         .name = "camss_ispif_ahb_clk",
1350                         .parent_names = (const char *[]){
1351                                 "mmss_ahb_clk_src",
1352                         },
1353                         .num_parents = 1,
1354                         .ops = &clk_branch2_ops,
1355                 },
1356         },
1357 };
1358
1359 static struct clk_branch camss_jpeg_jpeg0_clk = {
1360         .halt_reg = 0x35a8,
1361         .clkr = {
1362                 .enable_reg = 0x35a8,
1363                 .enable_mask = BIT(0),
1364                 .hw.init = &(struct clk_init_data){
1365                         .name = "camss_jpeg_jpeg0_clk",
1366                         .parent_names = (const char *[]){
1367                                 "jpeg0_clk_src",
1368                         },
1369                         .num_parents = 1,
1370                         .flags = CLK_SET_RATE_PARENT,
1371                         .ops = &clk_branch2_ops,
1372                 },
1373         },
1374 };
1375
1376 static struct clk_branch camss_jpeg_jpeg1_clk = {
1377         .halt_reg = 0x35ac,
1378         .clkr = {
1379                 .enable_reg = 0x35ac,
1380                 .enable_mask = BIT(0),
1381                 .hw.init = &(struct clk_init_data){
1382                         .name = "camss_jpeg_jpeg1_clk",
1383                         .parent_names = (const char *[]){
1384                                 "jpeg1_clk_src",
1385                         },
1386                         .num_parents = 1,
1387                         .flags = CLK_SET_RATE_PARENT,
1388                         .ops = &clk_branch2_ops,
1389                 },
1390         },
1391 };
1392
1393 static struct clk_branch camss_jpeg_jpeg2_clk = {
1394         .halt_reg = 0x35b0,
1395         .clkr = {
1396                 .enable_reg = 0x35b0,
1397                 .enable_mask = BIT(0),
1398                 .hw.init = &(struct clk_init_data){
1399                         .name = "camss_jpeg_jpeg2_clk",
1400                         .parent_names = (const char *[]){
1401                                 "jpeg2_clk_src",
1402                         },
1403                         .num_parents = 1,
1404                         .flags = CLK_SET_RATE_PARENT,
1405                         .ops = &clk_branch2_ops,
1406                 },
1407         },
1408 };
1409
1410 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1411         .halt_reg = 0x35b4,
1412         .clkr = {
1413                 .enable_reg = 0x35b4,
1414                 .enable_mask = BIT(0),
1415                 .hw.init = &(struct clk_init_data){
1416                         .name = "camss_jpeg_jpeg_ahb_clk",
1417                         .parent_names = (const char *[]){
1418                                 "mmss_ahb_clk_src",
1419                         },
1420                         .num_parents = 1,
1421                         .ops = &clk_branch2_ops,
1422                 },
1423         },
1424 };
1425
1426 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1427         .halt_reg = 0x35b8,
1428         .clkr = {
1429                 .enable_reg = 0x35b8,
1430                 .enable_mask = BIT(0),
1431                 .hw.init = &(struct clk_init_data){
1432                         .name = "camss_jpeg_jpeg_axi_clk",
1433                         .parent_names = (const char *[]){
1434                                 "mmss_axi_clk_src",
1435                         },
1436                         .num_parents = 1,
1437                         .ops = &clk_branch2_ops,
1438                 },
1439         },
1440 };
1441
1442 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1443         .halt_reg = 0x35bc,
1444         .clkr = {
1445                 .enable_reg = 0x35bc,
1446                 .enable_mask = BIT(0),
1447                 .hw.init = &(struct clk_init_data){
1448                         .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1449                         .parent_names = (const char *[]){
1450                                 "ocmemnoc_clk_src",
1451                         },
1452                         .num_parents = 1,
1453                         .flags = CLK_SET_RATE_PARENT,
1454                         .ops = &clk_branch2_ops,
1455                 },
1456         },
1457 };
1458
1459 static struct clk_branch camss_mclk0_clk = {
1460         .halt_reg = 0x3384,
1461         .clkr = {
1462                 .enable_reg = 0x3384,
1463                 .enable_mask = BIT(0),
1464                 .hw.init = &(struct clk_init_data){
1465                         .name = "camss_mclk0_clk",
1466                         .parent_names = (const char *[]){
1467                                 "mclk0_clk_src",
1468                         },
1469                         .num_parents = 1,
1470                         .flags = CLK_SET_RATE_PARENT,
1471                         .ops = &clk_branch2_ops,
1472                 },
1473         },
1474 };
1475
1476 static struct clk_branch camss_mclk1_clk = {
1477         .halt_reg = 0x33b4,
1478         .clkr = {
1479                 .enable_reg = 0x33b4,
1480                 .enable_mask = BIT(0),
1481                 .hw.init = &(struct clk_init_data){
1482                         .name = "camss_mclk1_clk",
1483                         .parent_names = (const char *[]){
1484                                 "mclk1_clk_src",
1485                         },
1486                         .num_parents = 1,
1487                         .flags = CLK_SET_RATE_PARENT,
1488                         .ops = &clk_branch2_ops,
1489                 },
1490         },
1491 };
1492
1493 static struct clk_branch camss_mclk2_clk = {
1494         .halt_reg = 0x33e4,
1495         .clkr = {
1496                 .enable_reg = 0x33e4,
1497                 .enable_mask = BIT(0),
1498                 .hw.init = &(struct clk_init_data){
1499                         .name = "camss_mclk2_clk",
1500                         .parent_names = (const char *[]){
1501                                 "mclk2_clk_src",
1502                         },
1503                         .num_parents = 1,
1504                         .flags = CLK_SET_RATE_PARENT,
1505                         .ops = &clk_branch2_ops,
1506                 },
1507         },
1508 };
1509
1510 static struct clk_branch camss_mclk3_clk = {
1511         .halt_reg = 0x3414,
1512         .clkr = {
1513                 .enable_reg = 0x3414,
1514                 .enable_mask = BIT(0),
1515                 .hw.init = &(struct clk_init_data){
1516                         .name = "camss_mclk3_clk",
1517                         .parent_names = (const char *[]){
1518                                 "mclk3_clk_src",
1519                         },
1520                         .num_parents = 1,
1521                         .flags = CLK_SET_RATE_PARENT,
1522                         .ops = &clk_branch2_ops,
1523                 },
1524         },
1525 };
1526
1527 static struct clk_branch camss_micro_ahb_clk = {
1528         .halt_reg = 0x3494,
1529         .clkr = {
1530                 .enable_reg = 0x3494,
1531                 .enable_mask = BIT(0),
1532                 .hw.init = &(struct clk_init_data){
1533                         .name = "camss_micro_ahb_clk",
1534                         .parent_names = (const char *[]){
1535                                 "mmss_ahb_clk_src",
1536                         },
1537                         .num_parents = 1,
1538                         .ops = &clk_branch2_ops,
1539                 },
1540         },
1541 };
1542
1543 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1544         .halt_reg = 0x3024,
1545         .clkr = {
1546                 .enable_reg = 0x3024,
1547                 .enable_mask = BIT(0),
1548                 .hw.init = &(struct clk_init_data){
1549                         .name = "camss_phy0_csi0phytimer_clk",
1550                         .parent_names = (const char *[]){
1551                                 "csi0phytimer_clk_src",
1552                         },
1553                         .num_parents = 1,
1554                         .flags = CLK_SET_RATE_PARENT,
1555                         .ops = &clk_branch2_ops,
1556                 },
1557         },
1558 };
1559
1560 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1561         .halt_reg = 0x3054,
1562         .clkr = {
1563                 .enable_reg = 0x3054,
1564                 .enable_mask = BIT(0),
1565                 .hw.init = &(struct clk_init_data){
1566                         .name = "camss_phy1_csi1phytimer_clk",
1567                         .parent_names = (const char *[]){
1568                                 "csi1phytimer_clk_src",
1569                         },
1570                         .num_parents = 1,
1571                         .flags = CLK_SET_RATE_PARENT,
1572                         .ops = &clk_branch2_ops,
1573                 },
1574         },
1575 };
1576
1577 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1578         .halt_reg = 0x3084,
1579         .clkr = {
1580                 .enable_reg = 0x3084,
1581                 .enable_mask = BIT(0),
1582                 .hw.init = &(struct clk_init_data){
1583                         .name = "camss_phy2_csi2phytimer_clk",
1584                         .parent_names = (const char *[]){
1585                                 "csi2phytimer_clk_src",
1586                         },
1587                         .num_parents = 1,
1588                         .flags = CLK_SET_RATE_PARENT,
1589                         .ops = &clk_branch2_ops,
1590                 },
1591         },
1592 };
1593
1594 static struct clk_branch camss_top_ahb_clk = {
1595         .halt_reg = 0x3484,
1596         .clkr = {
1597                 .enable_reg = 0x3484,
1598                 .enable_mask = BIT(0),
1599                 .hw.init = &(struct clk_init_data){
1600                         .name = "camss_top_ahb_clk",
1601                         .parent_names = (const char *[]){
1602                                 "mmss_ahb_clk_src",
1603                         },
1604                         .num_parents = 1,
1605                         .ops = &clk_branch2_ops,
1606                 },
1607         },
1608 };
1609
1610 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1611         .halt_reg = 0x36b4,
1612         .clkr = {
1613                 .enable_reg = 0x36b4,
1614                 .enable_mask = BIT(0),
1615                 .hw.init = &(struct clk_init_data){
1616                         .name = "camss_vfe_cpp_ahb_clk",
1617                         .parent_names = (const char *[]){
1618                                 "mmss_ahb_clk_src",
1619                         },
1620                         .num_parents = 1,
1621                         .ops = &clk_branch2_ops,
1622                 },
1623         },
1624 };
1625
1626 static struct clk_branch camss_vfe_cpp_clk = {
1627         .halt_reg = 0x36b0,
1628         .clkr = {
1629                 .enable_reg = 0x36b0,
1630                 .enable_mask = BIT(0),
1631                 .hw.init = &(struct clk_init_data){
1632                         .name = "camss_vfe_cpp_clk",
1633                         .parent_names = (const char *[]){
1634                                 "cpp_clk_src",
1635                         },
1636                         .num_parents = 1,
1637                         .flags = CLK_SET_RATE_PARENT,
1638                         .ops = &clk_branch2_ops,
1639                 },
1640         },
1641 };
1642
1643 static struct clk_branch camss_vfe_vfe0_clk = {
1644         .halt_reg = 0x36a8,
1645         .clkr = {
1646                 .enable_reg = 0x36a8,
1647                 .enable_mask = BIT(0),
1648                 .hw.init = &(struct clk_init_data){
1649                         .name = "camss_vfe_vfe0_clk",
1650                         .parent_names = (const char *[]){
1651                                 "vfe0_clk_src",
1652                         },
1653                         .num_parents = 1,
1654                         .flags = CLK_SET_RATE_PARENT,
1655                         .ops = &clk_branch2_ops,
1656                 },
1657         },
1658 };
1659
1660 static struct clk_branch camss_vfe_vfe1_clk = {
1661         .halt_reg = 0x36ac,
1662         .clkr = {
1663                 .enable_reg = 0x36ac,
1664                 .enable_mask = BIT(0),
1665                 .hw.init = &(struct clk_init_data){
1666                         .name = "camss_vfe_vfe1_clk",
1667                         .parent_names = (const char *[]){
1668                                 "vfe1_clk_src",
1669                         },
1670                         .num_parents = 1,
1671                         .flags = CLK_SET_RATE_PARENT,
1672                         .ops = &clk_branch2_ops,
1673                 },
1674         },
1675 };
1676
1677 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1678         .halt_reg = 0x36b8,
1679         .clkr = {
1680                 .enable_reg = 0x36b8,
1681                 .enable_mask = BIT(0),
1682                 .hw.init = &(struct clk_init_data){
1683                         .name = "camss_vfe_vfe_ahb_clk",
1684                         .parent_names = (const char *[]){
1685                                 "mmss_ahb_clk_src",
1686                         },
1687                         .num_parents = 1,
1688                         .ops = &clk_branch2_ops,
1689                 },
1690         },
1691 };
1692
1693 static struct clk_branch camss_vfe_vfe_axi_clk = {
1694         .halt_reg = 0x36bc,
1695         .clkr = {
1696                 .enable_reg = 0x36bc,
1697                 .enable_mask = BIT(0),
1698                 .hw.init = &(struct clk_init_data){
1699                         .name = "camss_vfe_vfe_axi_clk",
1700                         .parent_names = (const char *[]){
1701                                 "mmss_axi_clk_src",
1702                         },
1703                         .num_parents = 1,
1704                         .ops = &clk_branch2_ops,
1705                 },
1706         },
1707 };
1708
1709 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1710         .halt_reg = 0x36c0,
1711         .clkr = {
1712                 .enable_reg = 0x36c0,
1713                 .enable_mask = BIT(0),
1714                 .hw.init = &(struct clk_init_data){
1715                         .name = "camss_vfe_vfe_ocmemnoc_clk",
1716                         .parent_names = (const char *[]){
1717                                 "ocmemnoc_clk_src",
1718                         },
1719                         .num_parents = 1,
1720                         .flags = CLK_SET_RATE_PARENT,
1721                         .ops = &clk_branch2_ops,
1722                 },
1723         },
1724 };
1725
1726 static struct clk_branch mdss_ahb_clk = {
1727         .halt_reg = 0x2308,
1728         .clkr = {
1729                 .enable_reg = 0x2308,
1730                 .enable_mask = BIT(0),
1731                 .hw.init = &(struct clk_init_data){
1732                         .name = "mdss_ahb_clk",
1733                         .parent_names = (const char *[]){
1734                                 "mmss_ahb_clk_src",
1735                         },
1736                         .num_parents = 1,
1737                         .ops = &clk_branch2_ops,
1738                 },
1739         },
1740 };
1741
1742 static struct clk_branch mdss_axi_clk = {
1743         .halt_reg = 0x2310,
1744         .clkr = {
1745                 .enable_reg = 0x2310,
1746                 .enable_mask = BIT(0),
1747                 .hw.init = &(struct clk_init_data){
1748                         .name = "mdss_axi_clk",
1749                         .parent_names = (const char *[]){
1750                                 "mmss_axi_clk_src",
1751                         },
1752                         .num_parents = 1,
1753                         .flags = CLK_SET_RATE_PARENT,
1754                         .ops = &clk_branch2_ops,
1755                 },
1756         },
1757 };
1758
1759 static struct clk_branch mdss_byte0_clk = {
1760         .halt_reg = 0x233c,
1761         .clkr = {
1762                 .enable_reg = 0x233c,
1763                 .enable_mask = BIT(0),
1764                 .hw.init = &(struct clk_init_data){
1765                         .name = "mdss_byte0_clk",
1766                         .parent_names = (const char *[]){
1767                                 "byte0_clk_src",
1768                         },
1769                         .num_parents = 1,
1770                         .flags = CLK_SET_RATE_PARENT,
1771                         .ops = &clk_branch2_ops,
1772                 },
1773         },
1774 };
1775
1776 static struct clk_branch mdss_byte1_clk = {
1777         .halt_reg = 0x2340,
1778         .clkr = {
1779                 .enable_reg = 0x2340,
1780                 .enable_mask = BIT(0),
1781                 .hw.init = &(struct clk_init_data){
1782                         .name = "mdss_byte1_clk",
1783                         .parent_names = (const char *[]){
1784                                 "byte1_clk_src",
1785                         },
1786                         .num_parents = 1,
1787                         .flags = CLK_SET_RATE_PARENT,
1788                         .ops = &clk_branch2_ops,
1789                 },
1790         },
1791 };
1792
1793 static struct clk_branch mdss_edpaux_clk = {
1794         .halt_reg = 0x2334,
1795         .clkr = {
1796                 .enable_reg = 0x2334,
1797                 .enable_mask = BIT(0),
1798                 .hw.init = &(struct clk_init_data){
1799                         .name = "mdss_edpaux_clk",
1800                         .parent_names = (const char *[]){
1801                                 "edpaux_clk_src",
1802                         },
1803                         .num_parents = 1,
1804                         .flags = CLK_SET_RATE_PARENT,
1805                         .ops = &clk_branch2_ops,
1806                 },
1807         },
1808 };
1809
1810 static struct clk_branch mdss_edplink_clk = {
1811         .halt_reg = 0x2330,
1812         .clkr = {
1813                 .enable_reg = 0x2330,
1814                 .enable_mask = BIT(0),
1815                 .hw.init = &(struct clk_init_data){
1816                         .name = "mdss_edplink_clk",
1817                         .parent_names = (const char *[]){
1818                                 "edplink_clk_src",
1819                         },
1820                         .num_parents = 1,
1821                         .flags = CLK_SET_RATE_PARENT,
1822                         .ops = &clk_branch2_ops,
1823                 },
1824         },
1825 };
1826
1827 static struct clk_branch mdss_edppixel_clk = {
1828         .halt_reg = 0x232c,
1829         .clkr = {
1830                 .enable_reg = 0x232c,
1831                 .enable_mask = BIT(0),
1832                 .hw.init = &(struct clk_init_data){
1833                         .name = "mdss_edppixel_clk",
1834                         .parent_names = (const char *[]){
1835                                 "edppixel_clk_src",
1836                         },
1837                         .num_parents = 1,
1838                         .flags = CLK_SET_RATE_PARENT,
1839                         .ops = &clk_branch2_ops,
1840                 },
1841         },
1842 };
1843
1844 static struct clk_branch mdss_esc0_clk = {
1845         .halt_reg = 0x2344,
1846         .clkr = {
1847                 .enable_reg = 0x2344,
1848                 .enable_mask = BIT(0),
1849                 .hw.init = &(struct clk_init_data){
1850                         .name = "mdss_esc0_clk",
1851                         .parent_names = (const char *[]){
1852                                 "esc0_clk_src",
1853                         },
1854                         .num_parents = 1,
1855                         .flags = CLK_SET_RATE_PARENT,
1856                         .ops = &clk_branch2_ops,
1857                 },
1858         },
1859 };
1860
1861 static struct clk_branch mdss_esc1_clk = {
1862         .halt_reg = 0x2348,
1863         .clkr = {
1864                 .enable_reg = 0x2348,
1865                 .enable_mask = BIT(0),
1866                 .hw.init = &(struct clk_init_data){
1867                         .name = "mdss_esc1_clk",
1868                         .parent_names = (const char *[]){
1869                                 "esc1_clk_src",
1870                         },
1871                         .num_parents = 1,
1872                         .flags = CLK_SET_RATE_PARENT,
1873                         .ops = &clk_branch2_ops,
1874                 },
1875         },
1876 };
1877
1878 static struct clk_branch mdss_extpclk_clk = {
1879         .halt_reg = 0x2324,
1880         .clkr = {
1881                 .enable_reg = 0x2324,
1882                 .enable_mask = BIT(0),
1883                 .hw.init = &(struct clk_init_data){
1884                         .name = "mdss_extpclk_clk",
1885                         .parent_names = (const char *[]){
1886                                 "extpclk_clk_src",
1887                         },
1888                         .num_parents = 1,
1889                         .flags = CLK_SET_RATE_PARENT,
1890                         .ops = &clk_branch2_ops,
1891                 },
1892         },
1893 };
1894
1895 static struct clk_branch mdss_hdmi_ahb_clk = {
1896         .halt_reg = 0x230c,
1897         .clkr = {
1898                 .enable_reg = 0x230c,
1899                 .enable_mask = BIT(0),
1900                 .hw.init = &(struct clk_init_data){
1901                         .name = "mdss_hdmi_ahb_clk",
1902                         .parent_names = (const char *[]){
1903                                 "mmss_ahb_clk_src",
1904                         },
1905                         .num_parents = 1,
1906                         .ops = &clk_branch2_ops,
1907                 },
1908         },
1909 };
1910
1911 static struct clk_branch mdss_hdmi_clk = {
1912         .halt_reg = 0x2338,
1913         .clkr = {
1914                 .enable_reg = 0x2338,
1915                 .enable_mask = BIT(0),
1916                 .hw.init = &(struct clk_init_data){
1917                         .name = "mdss_hdmi_clk",
1918                         .parent_names = (const char *[]){
1919                                 "hdmi_clk_src",
1920                         },
1921                         .num_parents = 1,
1922                         .flags = CLK_SET_RATE_PARENT,
1923                         .ops = &clk_branch2_ops,
1924                 },
1925         },
1926 };
1927
1928 static struct clk_branch mdss_mdp_clk = {
1929         .halt_reg = 0x231c,
1930         .clkr = {
1931                 .enable_reg = 0x231c,
1932                 .enable_mask = BIT(0),
1933                 .hw.init = &(struct clk_init_data){
1934                         .name = "mdss_mdp_clk",
1935                         .parent_names = (const char *[]){
1936                                 "mdp_clk_src",
1937                         },
1938                         .num_parents = 1,
1939                         .flags = CLK_SET_RATE_PARENT,
1940                         .ops = &clk_branch2_ops,
1941                 },
1942         },
1943 };
1944
1945 static struct clk_branch mdss_mdp_lut_clk = {
1946         .halt_reg = 0x2320,
1947         .clkr = {
1948                 .enable_reg = 0x2320,
1949                 .enable_mask = BIT(0),
1950                 .hw.init = &(struct clk_init_data){
1951                         .name = "mdss_mdp_lut_clk",
1952                         .parent_names = (const char *[]){
1953                                 "mdp_clk_src",
1954                         },
1955                         .num_parents = 1,
1956                         .flags = CLK_SET_RATE_PARENT,
1957                         .ops = &clk_branch2_ops,
1958                 },
1959         },
1960 };
1961
1962 static struct clk_branch mdss_pclk0_clk = {
1963         .halt_reg = 0x2314,
1964         .clkr = {
1965                 .enable_reg = 0x2314,
1966                 .enable_mask = BIT(0),
1967                 .hw.init = &(struct clk_init_data){
1968                         .name = "mdss_pclk0_clk",
1969                         .parent_names = (const char *[]){
1970                                 "pclk0_clk_src",
1971                         },
1972                         .num_parents = 1,
1973                         .flags = CLK_SET_RATE_PARENT,
1974                         .ops = &clk_branch2_ops,
1975                 },
1976         },
1977 };
1978
1979 static struct clk_branch mdss_pclk1_clk = {
1980         .halt_reg = 0x2318,
1981         .clkr = {
1982                 .enable_reg = 0x2318,
1983                 .enable_mask = BIT(0),
1984                 .hw.init = &(struct clk_init_data){
1985                         .name = "mdss_pclk1_clk",
1986                         .parent_names = (const char *[]){
1987                                 "pclk1_clk_src",
1988                         },
1989                         .num_parents = 1,
1990                         .flags = CLK_SET_RATE_PARENT,
1991                         .ops = &clk_branch2_ops,
1992                 },
1993         },
1994 };
1995
1996 static struct clk_branch mdss_vsync_clk = {
1997         .halt_reg = 0x2328,
1998         .clkr = {
1999                 .enable_reg = 0x2328,
2000                 .enable_mask = BIT(0),
2001                 .hw.init = &(struct clk_init_data){
2002                         .name = "mdss_vsync_clk",
2003                         .parent_names = (const char *[]){
2004                                 "vsync_clk_src",
2005                         },
2006                         .num_parents = 1,
2007                         .flags = CLK_SET_RATE_PARENT,
2008                         .ops = &clk_branch2_ops,
2009                 },
2010         },
2011 };
2012
2013 static struct clk_branch mmss_misc_ahb_clk = {
2014         .halt_reg = 0x502c,
2015         .clkr = {
2016                 .enable_reg = 0x502c,
2017                 .enable_mask = BIT(0),
2018                 .hw.init = &(struct clk_init_data){
2019                         .name = "mmss_misc_ahb_clk",
2020                         .parent_names = (const char *[]){
2021                                 "mmss_ahb_clk_src",
2022                         },
2023                         .num_parents = 1,
2024                         .ops = &clk_branch2_ops,
2025                 },
2026         },
2027 };
2028
2029 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2030         .halt_reg = 0x5024,
2031         .clkr = {
2032                 .enable_reg = 0x5024,
2033                 .enable_mask = BIT(0),
2034                 .hw.init = &(struct clk_init_data){
2035                         .name = "mmss_mmssnoc_ahb_clk",
2036                         .parent_names = (const char *[]){
2037                                 "mmss_ahb_clk_src",
2038                         },
2039                         .num_parents = 1,
2040                         .ops = &clk_branch2_ops,
2041                         .flags = CLK_IGNORE_UNUSED,
2042                 },
2043         },
2044 };
2045
2046 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2047         .halt_reg = 0x5028,
2048         .clkr = {
2049                 .enable_reg = 0x5028,
2050                 .enable_mask = BIT(0),
2051                 .hw.init = &(struct clk_init_data){
2052                         .name = "mmss_mmssnoc_bto_ahb_clk",
2053                         .parent_names = (const char *[]){
2054                                 "mmss_ahb_clk_src",
2055                         },
2056                         .num_parents = 1,
2057                         .ops = &clk_branch2_ops,
2058                         .flags = CLK_IGNORE_UNUSED,
2059                 },
2060         },
2061 };
2062
2063 static struct clk_branch mmss_mmssnoc_axi_clk = {
2064         .halt_reg = 0x506c,
2065         .clkr = {
2066                 .enable_reg = 0x506c,
2067                 .enable_mask = BIT(0),
2068                 .hw.init = &(struct clk_init_data){
2069                         .name = "mmss_mmssnoc_axi_clk",
2070                         .parent_names = (const char *[]){
2071                                 "mmss_axi_clk_src",
2072                         },
2073                         .num_parents = 1,
2074                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2075                         .ops = &clk_branch2_ops,
2076                 },
2077         },
2078 };
2079
2080 static struct clk_branch mmss_s0_axi_clk = {
2081         .halt_reg = 0x5064,
2082         .clkr = {
2083                 .enable_reg = 0x5064,
2084                 .enable_mask = BIT(0),
2085                 .hw.init = &(struct clk_init_data){
2086                         .name = "mmss_s0_axi_clk",
2087                         .parent_names = (const char *[]){
2088                                 "mmss_axi_clk_src",
2089                         },
2090                         .num_parents = 1,
2091                         .ops = &clk_branch2_ops,
2092                         .flags = CLK_IGNORE_UNUSED,
2093                 },
2094         },
2095 };
2096
2097 static struct clk_branch ocmemcx_ahb_clk = {
2098         .halt_reg = 0x405c,
2099         .clkr = {
2100                 .enable_reg = 0x405c,
2101                 .enable_mask = BIT(0),
2102                 .hw.init = &(struct clk_init_data){
2103                         .name = "ocmemcx_ahb_clk",
2104                         .parent_names = (const char *[]){
2105                                 "mmss_ahb_clk_src",
2106                         },
2107                         .num_parents = 1,
2108                         .ops = &clk_branch2_ops,
2109                 },
2110         },
2111 };
2112
2113 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2114         .halt_reg = 0x4058,
2115         .clkr = {
2116                 .enable_reg = 0x4058,
2117                 .enable_mask = BIT(0),
2118                 .hw.init = &(struct clk_init_data){
2119                         .name = "ocmemcx_ocmemnoc_clk",
2120                         .parent_names = (const char *[]){
2121                                 "ocmemnoc_clk_src",
2122                         },
2123                         .num_parents = 1,
2124                         .flags = CLK_SET_RATE_PARENT,
2125                         .ops = &clk_branch2_ops,
2126                 },
2127         },
2128 };
2129
2130 static struct clk_branch oxili_ocmemgx_clk = {
2131         .halt_reg = 0x402c,
2132         .clkr = {
2133                 .enable_reg = 0x402c,
2134                 .enable_mask = BIT(0),
2135                 .hw.init = &(struct clk_init_data){
2136                         .name = "oxili_ocmemgx_clk",
2137                         .parent_names = (const char *[]){
2138                                 "gfx3d_clk_src",
2139                         },
2140                         .num_parents = 1,
2141                         .flags = CLK_SET_RATE_PARENT,
2142                         .ops = &clk_branch2_ops,
2143                 },
2144         },
2145 };
2146
2147 static struct clk_branch ocmemnoc_clk = {
2148         .halt_reg = 0x50b4,
2149         .clkr = {
2150                 .enable_reg = 0x50b4,
2151                 .enable_mask = BIT(0),
2152                 .hw.init = &(struct clk_init_data){
2153                         .name = "ocmemnoc_clk",
2154                         .parent_names = (const char *[]){
2155                                 "ocmemnoc_clk_src",
2156                         },
2157                         .num_parents = 1,
2158                         .flags = CLK_SET_RATE_PARENT,
2159                         .ops = &clk_branch2_ops,
2160                 },
2161         },
2162 };
2163
2164 static struct clk_branch oxili_gfx3d_clk = {
2165         .halt_reg = 0x4028,
2166         .clkr = {
2167                 .enable_reg = 0x4028,
2168                 .enable_mask = BIT(0),
2169                 .hw.init = &(struct clk_init_data){
2170                         .name = "oxili_gfx3d_clk",
2171                         .parent_names = (const char *[]){
2172                                 "gfx3d_clk_src",
2173                         },
2174                         .num_parents = 1,
2175                         .flags = CLK_SET_RATE_PARENT,
2176                         .ops = &clk_branch2_ops,
2177                 },
2178         },
2179 };
2180
2181 static struct clk_branch oxilicx_ahb_clk = {
2182         .halt_reg = 0x403c,
2183         .clkr = {
2184                 .enable_reg = 0x403c,
2185                 .enable_mask = BIT(0),
2186                 .hw.init = &(struct clk_init_data){
2187                         .name = "oxilicx_ahb_clk",
2188                         .parent_names = (const char *[]){
2189                                 "mmss_ahb_clk_src",
2190                         },
2191                         .num_parents = 1,
2192                         .ops = &clk_branch2_ops,
2193                 },
2194         },
2195 };
2196
2197 static struct clk_branch oxilicx_axi_clk = {
2198         .halt_reg = 0x4038,
2199         .clkr = {
2200                 .enable_reg = 0x4038,
2201                 .enable_mask = BIT(0),
2202                 .hw.init = &(struct clk_init_data){
2203                         .name = "oxilicx_axi_clk",
2204                         .parent_names = (const char *[]){
2205                                 "mmss_axi_clk_src",
2206                         },
2207                         .num_parents = 1,
2208                         .ops = &clk_branch2_ops,
2209                 },
2210         },
2211 };
2212
2213 static struct clk_branch venus0_ahb_clk = {
2214         .halt_reg = 0x1030,
2215         .clkr = {
2216                 .enable_reg = 0x1030,
2217                 .enable_mask = BIT(0),
2218                 .hw.init = &(struct clk_init_data){
2219                         .name = "venus0_ahb_clk",
2220                         .parent_names = (const char *[]){
2221                                 "mmss_ahb_clk_src",
2222                         },
2223                         .num_parents = 1,
2224                         .ops = &clk_branch2_ops,
2225                 },
2226         },
2227 };
2228
2229 static struct clk_branch venus0_axi_clk = {
2230         .halt_reg = 0x1034,
2231         .clkr = {
2232                 .enable_reg = 0x1034,
2233                 .enable_mask = BIT(0),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "venus0_axi_clk",
2236                         .parent_names = (const char *[]){
2237                                 "mmss_axi_clk_src",
2238                         },
2239                         .num_parents = 1,
2240                         .ops = &clk_branch2_ops,
2241                 },
2242         },
2243 };
2244
2245 static struct clk_branch venus0_ocmemnoc_clk = {
2246         .halt_reg = 0x1038,
2247         .clkr = {
2248                 .enable_reg = 0x1038,
2249                 .enable_mask = BIT(0),
2250                 .hw.init = &(struct clk_init_data){
2251                         .name = "venus0_ocmemnoc_clk",
2252                         .parent_names = (const char *[]){
2253                                 "ocmemnoc_clk_src",
2254                         },
2255                         .num_parents = 1,
2256                         .flags = CLK_SET_RATE_PARENT,
2257                         .ops = &clk_branch2_ops,
2258                 },
2259         },
2260 };
2261
2262 static struct clk_branch venus0_vcodec0_clk = {
2263         .halt_reg = 0x1028,
2264         .clkr = {
2265                 .enable_reg = 0x1028,
2266                 .enable_mask = BIT(0),
2267                 .hw.init = &(struct clk_init_data){
2268                         .name = "venus0_vcodec0_clk",
2269                         .parent_names = (const char *[]){
2270                                 "vcodec0_clk_src",
2271                         },
2272                         .num_parents = 1,
2273                         .flags = CLK_SET_RATE_PARENT,
2274                         .ops = &clk_branch2_ops,
2275                 },
2276         },
2277 };
2278
2279 static const struct pll_config mmpll1_config = {
2280         .l = 60,
2281         .m = 25,
2282         .n = 32,
2283         .vco_val = 0x0,
2284         .vco_mask = 0x3 << 20,
2285         .pre_div_val = 0x0,
2286         .pre_div_mask = 0x7 << 12,
2287         .post_div_val = 0x0,
2288         .post_div_mask = 0x3 << 8,
2289         .mn_ena_mask = BIT(24),
2290         .main_output_mask = BIT(0),
2291 };
2292
2293 static struct pll_config mmpll3_config = {
2294         .l = 48,
2295         .m = 7,
2296         .n = 16,
2297         .vco_val = 0x0,
2298         .vco_mask = 0x3 << 20,
2299         .pre_div_val = 0x0,
2300         .pre_div_mask = 0x7 << 12,
2301         .post_div_val = 0x0,
2302         .post_div_mask = 0x3 << 8,
2303         .mn_ena_mask = BIT(24),
2304         .main_output_mask = BIT(0),
2305         .aux_output_mask = BIT(1),
2306 };
2307
2308 static struct gdsc venus0_gdsc = {
2309         .gdscr = 0x1024,
2310         .cxcs = (unsigned int []){ 0x1028 },
2311         .cxc_count = 1,
2312         .resets = (unsigned int []){ VENUS0_RESET },
2313         .reset_count = 1,
2314         .pd = {
2315                 .name = "venus0",
2316         },
2317         .pwrsts = PWRSTS_ON,
2318 };
2319
2320 static struct gdsc mdss_gdsc = {
2321         .gdscr = 0x2304,
2322         .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2323         .cxc_count = 2,
2324         .pd = {
2325                 .name = "mdss",
2326         },
2327         .pwrsts = PWRSTS_RET_ON,
2328 };
2329
2330 static struct gdsc camss_jpeg_gdsc = {
2331         .gdscr = 0x35a4,
2332         .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 },
2333         .cxc_count = 3,
2334         .pd = {
2335                 .name = "camss_jpeg",
2336         },
2337         .pwrsts = PWRSTS_OFF_ON,
2338 };
2339
2340 static struct gdsc camss_vfe_gdsc = {
2341         .gdscr = 0x36a4,
2342         .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 },
2343         .cxc_count = 5,
2344         .pd = {
2345                 .name = "camss_vfe",
2346         },
2347         .pwrsts = PWRSTS_OFF_ON,
2348 };
2349
2350 static struct gdsc oxili_gdsc = {
2351         .gdscr = 0x4024,
2352         .cxcs = (unsigned int []){ 0x4028 },
2353         .cxc_count = 1,
2354         .pd = {
2355                 .name = "oxili",
2356         },
2357         .pwrsts = PWRSTS_OFF_ON,
2358 };
2359
2360 static struct gdsc oxilicx_gdsc = {
2361         .gdscr = 0x4034,
2362         .pd = {
2363                 .name = "oxilicx",
2364         },
2365         .parent = &oxili_gdsc.pd,
2366         .pwrsts = PWRSTS_OFF_ON,
2367 };
2368
2369 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2370         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2371         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2372         [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2373         [MMPLL0] = &mmpll0.clkr,
2374         [MMPLL0_VOTE] = &mmpll0_vote,
2375         [MMPLL1] = &mmpll1.clkr,
2376         [MMPLL1_VOTE] = &mmpll1_vote,
2377         [MMPLL2] = &mmpll2.clkr,
2378         [MMPLL3] = &mmpll3.clkr,
2379         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2380         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2381         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2382         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2383         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2384         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2385         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2386         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2387         [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2388         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2389         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2390         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2391         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2392         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2393         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2394         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2395         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2396         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2397         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2398         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2399         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2400         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2401         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2402         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2403         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2404         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2405         [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2406         [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2407         [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2408         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2409         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2410         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2411         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2412         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2413         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2414         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2415         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2416         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2417         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2418         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2419         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2420         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2421         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2422         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2423         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2424         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2425         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2426         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2427         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2428         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2429         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2430         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2431         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2432         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2433         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2434         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2435         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2436         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2437         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2438         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2439         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2440         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2441         [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2442         [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2443         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2444         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2445         [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2446         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2447         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2448         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2449         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2450         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2451         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2452         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2453         [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2454         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2455         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2456         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2457         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2458         [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2459         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2460         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2461         [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2462         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2463         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2464         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2465         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2466         [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2467         [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2468         [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2469         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2470         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2471         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2472         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2473         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2474         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2475         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2476         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2477         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2478         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2479         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2480         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2481         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2482         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2483         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2484         [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2485         [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2486         [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2487         [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2488         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2489         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2490         [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2491         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2492         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2493         [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2494         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2495 };
2496
2497 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2498         [SPDM_RESET] = { 0x0200 },
2499         [SPDM_RM_RESET] = { 0x0300 },
2500         [VENUS0_RESET] = { 0x1020 },
2501         [MDSS_RESET] = { 0x2300 },
2502         [CAMSS_PHY0_RESET] = { 0x3020 },
2503         [CAMSS_PHY1_RESET] = { 0x3050 },
2504         [CAMSS_PHY2_RESET] = { 0x3080 },
2505         [CAMSS_CSI0_RESET] = { 0x30b0 },
2506         [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2507         [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2508         [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2509         [CAMSS_CSI1_RESET] = { 0x3120 },
2510         [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2511         [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2512         [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2513         [CAMSS_CSI2_RESET] = { 0x3180 },
2514         [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2515         [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2516         [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2517         [CAMSS_CSI3_RESET] = { 0x31e0 },
2518         [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2519         [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2520         [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2521         [CAMSS_ISPIF_RESET] = { 0x3220 },
2522         [CAMSS_CCI_RESET] = { 0x3340 },
2523         [CAMSS_MCLK0_RESET] = { 0x3380 },
2524         [CAMSS_MCLK1_RESET] = { 0x33b0 },
2525         [CAMSS_MCLK2_RESET] = { 0x33e0 },
2526         [CAMSS_MCLK3_RESET] = { 0x3410 },
2527         [CAMSS_GP0_RESET] = { 0x3440 },
2528         [CAMSS_GP1_RESET] = { 0x3470 },
2529         [CAMSS_TOP_RESET] = { 0x3480 },
2530         [CAMSS_MICRO_RESET] = { 0x3490 },
2531         [CAMSS_JPEG_RESET] = { 0x35a0 },
2532         [CAMSS_VFE_RESET] = { 0x36a0 },
2533         [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2534         [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2535         [OXILI_RESET] = { 0x4020 },
2536         [OXILICX_RESET] = { 0x4030 },
2537         [OCMEMCX_RESET] = { 0x4050 },
2538         [MMSS_RBCRP_RESET] = { 0x4080 },
2539         [MMSSNOCAHB_RESET] = { 0x5020 },
2540         [MMSSNOCAXI_RESET] = { 0x5060 },
2541         [OCMEMNOC_RESET] = { 0x50b0 },
2542 };
2543
2544 static struct gdsc *mmcc_msm8974_gdscs[] = {
2545         [VENUS0_GDSC] = &venus0_gdsc,
2546         [MDSS_GDSC] = &mdss_gdsc,
2547         [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
2548         [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
2549         [OXILI_GDSC] = &oxili_gdsc,
2550         [OXILICX_GDSC] = &oxilicx_gdsc,
2551 };
2552
2553 static const struct regmap_config mmcc_msm8974_regmap_config = {
2554         .reg_bits       = 32,
2555         .reg_stride     = 4,
2556         .val_bits       = 32,
2557         .max_register   = 0x5104,
2558         .fast_io        = true,
2559 };
2560
2561 static const struct qcom_cc_desc mmcc_msm8974_desc = {
2562         .config = &mmcc_msm8974_regmap_config,
2563         .clks = mmcc_msm8974_clocks,
2564         .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks),
2565         .resets = mmcc_msm8974_resets,
2566         .num_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2567         .gdscs = mmcc_msm8974_gdscs,
2568         .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs),
2569 };
2570
2571 static const struct of_device_id mmcc_msm8974_match_table[] = {
2572         { .compatible = "qcom,mmcc-msm8974" },
2573         { }
2574 };
2575 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2576
2577 static int mmcc_msm8974_probe(struct platform_device *pdev)
2578 {
2579         struct regmap *regmap;
2580
2581         regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
2582         if (IS_ERR(regmap))
2583                 return PTR_ERR(regmap);
2584
2585         clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2586         clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2587
2588         return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
2589 }
2590
2591 static struct platform_driver mmcc_msm8974_driver = {
2592         .probe          = mmcc_msm8974_probe,
2593         .driver         = {
2594                 .name   = "mmcc-msm8974",
2595                 .of_match_table = mmcc_msm8974_match_table,
2596         },
2597 };
2598 module_platform_driver(mmcc_msm8974_driver);
2599
2600 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2601 MODULE_LICENSE("GPL v2");
2602 MODULE_ALIAS("platform:mmcc-msm8974");