1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
16 #include "clk-regmap.h"
17 #include "clk-regmap-divider.h"
18 #include "clk-regmap-mux.h"
33 static struct clk_alpha_pll gpll0 = {
35 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
37 .enable_reg = 0x52010,
38 .enable_mask = BIT(0),
39 .hw.init = &(struct clk_init_data){
41 .parent_data = &(const struct clk_parent_data){
45 .ops = &clk_alpha_pll_fixed_fabia_ops,
50 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
55 static struct clk_alpha_pll_postdiv gpll0_out_even = {
58 .post_div_table = post_div_table_gpll0_out_even,
59 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
62 .clkr.hw.init = &(struct clk_init_data){
63 .name = "gpll0_out_even",
64 .parent_hws = (const struct clk_hw*[]){
68 .ops = &clk_alpha_pll_postdiv_fabia_ops,
72 static const struct clk_div_table post_div_table_gpll0_out_odd[] = {
77 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
80 .post_div_table = post_div_table_gpll0_out_odd,
81 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd),
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
84 .clkr.hw.init = &(struct clk_init_data){
85 .name = "gpll0_out_odd",
86 .parent_hws = (const struct clk_hw*[]){
90 .ops = &clk_alpha_pll_postdiv_fabia_ops,
94 static struct clk_alpha_pll gpll6 = {
96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
98 .enable_reg = 0x52010,
99 .enable_mask = BIT(6),
100 .hw.init = &(struct clk_init_data){
102 .parent_hws = (const struct clk_hw*[]){
106 .ops = &clk_alpha_pll_fixed_fabia_ops,
111 static const struct clk_div_table post_div_table_gpll6_out_even[] = {
116 static struct clk_alpha_pll_postdiv gpll6_out_even = {
119 .post_div_table = post_div_table_gpll6_out_even,
120 .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
123 .clkr.hw.init = &(struct clk_init_data){
124 .name = "gpll6_out_even",
125 .parent_hws = (const struct clk_hw*[]){
129 .ops = &clk_alpha_pll_postdiv_fabia_ops,
133 static struct clk_alpha_pll gpll7 = {
135 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
137 .enable_reg = 0x52010,
138 .enable_mask = BIT(7),
139 .hw.init = &(struct clk_init_data){
141 .parent_hws = (const struct clk_hw*[]){
145 .ops = &clk_alpha_pll_fixed_fabia_ops,
150 static const struct parent_map gcc_parent_map_0[] = {
152 { P_GPLL0_OUT_MAIN, 1 },
153 { P_GPLL6_OUT_EVEN, 2 },
154 { P_GPLL0_OUT_EVEN, 6 },
157 static const struct clk_parent_data gcc_parent_data_0[] = {
158 { .fw_name = "bi_tcxo" },
159 { .hw = &gpll0.clkr.hw },
160 { .hw = &gpll6_out_even.clkr.hw },
161 { .hw = &gpll0_out_even.clkr.hw },
164 static const struct parent_map gcc_parent_map_1[] = {
166 { P_GPLL0_OUT_EVEN, 6 },
169 static const struct clk_parent_data gcc_parent_data_1[] = {
170 { .fw_name = "bi_tcxo" },
171 { .hw = &gpll0_out_even.clkr.hw },
174 static const struct parent_map gcc_parent_map_2[] = {
176 { P_GPLL0_OUT_ODD, 2 },
179 static const struct clk_parent_data gcc_parent_data_2[] = {
180 { .fw_name = "bi_tcxo" },
181 { .hw = &gpll0_out_odd.clkr.hw },
183 static const struct clk_parent_data gcc_parent_data_2_ao[] = {
184 { .fw_name = "bi_tcxo_ao" },
185 { .hw = &gpll0_out_odd.clkr.hw },
188 static const struct parent_map gcc_parent_map_4[] = {
190 { P_GPLL0_OUT_MAIN, 1 },
191 { P_GPLL0_OUT_ODD, 2 },
194 static const struct clk_parent_data gcc_parent_data_4[] = {
195 { .fw_name = "bi_tcxo" },
196 { .hw = &gpll0.clkr.hw },
197 { .hw = &gpll0_out_odd.clkr.hw },
200 static const struct parent_map gcc_parent_map_5[] = {
202 { P_GPLL0_OUT_ODD, 2 },
204 { P_GPLL0_OUT_EVEN, 6 },
207 static const struct clk_parent_data gcc_parent_data_5[] = {
208 { .fw_name = "bi_tcxo" },
209 { .hw = &gpll0_out_odd.clkr.hw },
210 { .fw_name = "sleep_clk" },
211 { .hw = &gpll0_out_even.clkr.hw },
214 static const struct parent_map gcc_parent_map_6[] = {
219 static const struct clk_parent_data gcc_parent_data_6[] = {
220 { .fw_name = "bi_tcxo" },
221 { .fw_name = "sleep_clk" }
224 static const struct parent_map gcc_parent_map_7[] = {
226 { P_GPLL6_OUT_EVEN, 2 },
227 { P_GPLL0_OUT_EVEN, 6 },
230 static const struct clk_parent_data gcc_parent_data_7[] = {
231 { .fw_name = "bi_tcxo" },
232 { .hw = &gpll6_out_even.clkr.hw },
233 { .hw = &gpll0_out_even.clkr.hw },
236 static const struct parent_map gcc_parent_map_8[] = {
238 { P_GPLL0_OUT_ODD, 2 },
239 { P_GPLL7_OUT_MAIN, 3 },
242 static const struct clk_parent_data gcc_parent_data_8[] = {
243 { .fw_name = "bi_tcxo" },
244 { .hw = &gpll0_out_odd.clkr.hw },
245 { .hw = &gpll7.clkr.hw },
248 static struct clk_regmap_div gcc_gpu_gpll0_main_div_clk_src = {
252 .clkr.hw.init = &(struct clk_init_data) {
253 .name = "gcc_gpu_gpll0_main_div_clk_src",
254 .parent_hws = (const struct clk_hw*[]){
258 .ops = &clk_regmap_div_ro_ops,
262 static struct clk_regmap_div gcc_npu_pll0_main_div_clk_src = {
266 .clkr.hw.init = &(struct clk_init_data) {
267 .name = "gcc_npu_pll0_main_div_clk_src",
268 .parent_hws = (const struct clk_hw*[]){
272 .ops = &clk_regmap_div_ro_ops,
276 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
277 F(19200000, P_BI_TCXO, 1, 0, 0),
281 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
285 .parent_map = gcc_parent_map_2,
286 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
287 .clkr.hw.init = &(struct clk_init_data){
288 .name = "gcc_cpuss_ahb_clk_src",
289 .parent_data = gcc_parent_data_2_ao,
290 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
291 .ops = &clk_rcg2_ops,
295 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
296 F(19200000, P_BI_TCXO, 1, 0, 0),
297 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
298 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
299 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
300 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
304 static struct clk_rcg2 gcc_gp1_clk_src = {
308 .parent_map = gcc_parent_map_5,
309 .freq_tbl = ftbl_gcc_gp1_clk_src,
310 .clkr.hw.init = &(struct clk_init_data){
311 .name = "gcc_gp1_clk_src",
312 .parent_data = gcc_parent_data_5,
313 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
314 .ops = &clk_rcg2_ops,
318 static struct clk_rcg2 gcc_gp2_clk_src = {
322 .parent_map = gcc_parent_map_5,
323 .freq_tbl = ftbl_gcc_gp1_clk_src,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "gcc_gp2_clk_src",
326 .parent_data = gcc_parent_data_5,
327 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
328 .ops = &clk_rcg2_ops,
332 static struct clk_rcg2 gcc_gp3_clk_src = {
336 .parent_map = gcc_parent_map_5,
337 .freq_tbl = ftbl_gcc_gp1_clk_src,
338 .clkr.hw.init = &(struct clk_init_data){
339 .name = "gcc_gp3_clk_src",
340 .parent_data = gcc_parent_data_5,
341 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
342 .ops = &clk_rcg2_ops,
346 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
347 F(19200000, P_BI_TCXO, 1, 0, 0),
348 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
352 static struct clk_rcg2 gcc_pdm2_clk_src = {
356 .parent_map = gcc_parent_map_1,
357 .freq_tbl = ftbl_gcc_pdm2_clk_src,
358 .clkr.hw.init = &(struct clk_init_data){
359 .name = "gcc_pdm2_clk_src",
360 .parent_data = gcc_parent_data_1,
361 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
362 .ops = &clk_rcg2_ops,
366 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
367 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
368 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
369 F(19200000, P_BI_TCXO, 1, 0, 0),
370 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
371 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
372 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
373 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
374 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
375 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
376 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
377 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
378 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
379 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
380 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
381 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
382 F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
386 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
387 .name = "gcc_qupv3_wrap0_s0_clk_src",
388 .parent_data = gcc_parent_data_0,
389 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
390 .ops = &clk_rcg2_ops,
393 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
397 .parent_map = gcc_parent_map_0,
398 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
399 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
402 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
403 .name = "gcc_qupv3_wrap0_s1_clk_src",
404 .parent_data = gcc_parent_data_0,
405 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
406 .ops = &clk_rcg2_ops,
409 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
413 .parent_map = gcc_parent_map_0,
414 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
415 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
418 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
419 .name = "gcc_qupv3_wrap0_s2_clk_src",
420 .parent_data = gcc_parent_data_0,
421 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
422 .ops = &clk_rcg2_ops,
425 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
429 .parent_map = gcc_parent_map_0,
430 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
431 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
434 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
435 .name = "gcc_qupv3_wrap0_s3_clk_src",
436 .parent_data = gcc_parent_data_0,
437 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
438 .ops = &clk_rcg2_ops,
441 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
445 .parent_map = gcc_parent_map_0,
446 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
447 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
450 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
451 .name = "gcc_qupv3_wrap0_s4_clk_src",
452 .parent_data = gcc_parent_data_0,
453 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
454 .ops = &clk_rcg2_ops,
457 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
461 .parent_map = gcc_parent_map_0,
462 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
463 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
466 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
467 .name = "gcc_qupv3_wrap0_s5_clk_src",
468 .parent_data = gcc_parent_data_0,
469 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
470 .ops = &clk_rcg2_ops,
473 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
477 .parent_map = gcc_parent_map_0,
478 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
479 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
482 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
483 .name = "gcc_qupv3_wrap1_s0_clk_src",
484 .parent_data = gcc_parent_data_0,
485 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
486 .ops = &clk_rcg2_ops,
489 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
493 .parent_map = gcc_parent_map_0,
494 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
495 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
498 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
499 .name = "gcc_qupv3_wrap1_s1_clk_src",
500 .parent_data = gcc_parent_data_0,
501 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
502 .ops = &clk_rcg2_ops,
505 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
509 .parent_map = gcc_parent_map_0,
510 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
511 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
514 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
515 .name = "gcc_qupv3_wrap1_s2_clk_src",
516 .parent_data = gcc_parent_data_0,
517 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
518 .ops = &clk_rcg2_ops,
521 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
525 .parent_map = gcc_parent_map_0,
526 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
527 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
530 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
531 .name = "gcc_qupv3_wrap1_s3_clk_src",
532 .parent_data = gcc_parent_data_0,
533 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
534 .ops = &clk_rcg2_ops,
537 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
541 .parent_map = gcc_parent_map_0,
542 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
543 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
546 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
547 .name = "gcc_qupv3_wrap1_s4_clk_src",
548 .parent_data = gcc_parent_data_0,
549 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
550 .ops = &clk_rcg2_ops,
553 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
557 .parent_map = gcc_parent_map_0,
558 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
559 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
562 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
563 .name = "gcc_qupv3_wrap1_s5_clk_src",
564 .parent_data = gcc_parent_data_0,
565 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
566 .ops = &clk_rcg2_ops,
569 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
573 .parent_map = gcc_parent_map_0,
574 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
575 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
578 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
579 F(144000, P_BI_TCXO, 16, 3, 25),
580 F(400000, P_BI_TCXO, 12, 1, 4),
581 F(19200000, P_BI_TCXO, 1, 0, 0),
582 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
583 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
584 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
585 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
586 F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
587 F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
591 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
595 .parent_map = gcc_parent_map_7,
596 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "gcc_sdcc1_apps_clk_src",
599 .parent_data = gcc_parent_data_7,
600 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
601 .ops = &clk_rcg2_ops,
605 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
606 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
607 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
608 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
612 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
616 .parent_map = gcc_parent_map_1,
617 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
618 .clkr.hw.init = &(struct clk_init_data){
619 .name = "gcc_sdcc1_ice_core_clk_src",
620 .parent_data = gcc_parent_data_1,
621 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
622 .ops = &clk_rcg2_ops,
626 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
627 F(400000, P_BI_TCXO, 12, 1, 4),
628 F(9600000, P_BI_TCXO, 2, 0, 0),
629 F(19200000, P_BI_TCXO, 1, 0, 0),
630 F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
631 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
632 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
633 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
637 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
641 .parent_map = gcc_parent_map_8,
642 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
643 .clkr.hw.init = &(struct clk_init_data){
644 .name = "gcc_sdcc2_apps_clk_src",
645 .parent_data = gcc_parent_data_8,
646 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
647 .ops = &clk_rcg2_floor_ops,
651 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
652 F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
653 F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
654 F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
655 F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
656 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
660 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
664 .parent_map = gcc_parent_map_4,
665 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
666 .clkr.hw.init = &(struct clk_init_data){
667 .name = "gcc_ufs_phy_axi_clk_src",
668 .parent_data = gcc_parent_data_4,
669 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
670 .ops = &clk_rcg2_ops,
674 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
675 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
676 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
677 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
678 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
682 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
686 .parent_map = gcc_parent_map_1,
687 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
688 .clkr.hw.init = &(struct clk_init_data){
689 .name = "gcc_ufs_phy_ice_core_clk_src",
690 .parent_data = gcc_parent_data_1,
691 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
692 .ops = &clk_rcg2_ops,
696 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
697 F(9600000, P_BI_TCXO, 2, 0, 0),
698 F(19200000, P_BI_TCXO, 1, 0, 0),
702 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
706 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
707 .clkr.hw.init = &(struct clk_init_data){
708 .name = "gcc_ufs_phy_phy_aux_clk_src",
709 .parent_data = &(const struct clk_parent_data){
710 .fw_name = "bi_tcxo",
713 .ops = &clk_rcg2_ops,
717 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
718 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
719 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
720 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
724 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
728 .parent_map = gcc_parent_map_1,
729 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "gcc_ufs_phy_unipro_core_clk_src",
732 .parent_data = gcc_parent_data_1,
733 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
734 .ops = &clk_rcg2_ops,
738 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
739 F(66666667, P_GPLL0_OUT_ODD, 3, 0, 0),
740 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
741 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
742 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
746 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
750 .parent_map = gcc_parent_map_4,
751 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
752 .clkr.hw.init = &(struct clk_init_data){
753 .name = "gcc_usb30_prim_master_clk_src",
754 .parent_data = gcc_parent_data_4,
755 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
756 .ops = &clk_rcg2_ops,
760 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
761 F(19200000, P_BI_TCXO, 1, 0, 0),
765 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
769 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
770 .clkr.hw.init = &(struct clk_init_data){
771 .name = "gcc_usb30_prim_mock_utmi_clk_src",
772 .parent_data = &(const struct clk_parent_data){
773 .fw_name = "bi_tcxo",
776 .ops = &clk_rcg2_ops,
780 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
784 .parent_map = gcc_parent_map_6,
785 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
786 .clkr.hw.init = &(struct clk_init_data){
787 .name = "gcc_usb3_prim_phy_aux_clk_src",
788 .parent_data = gcc_parent_data_6,
789 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
790 .ops = &clk_rcg2_ops,
794 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
796 .halt_check = BRANCH_HALT_DELAY,
800 .enable_reg = 0x3e014,
801 .enable_mask = BIT(0),
802 .hw.init = &(struct clk_init_data){
803 .name = "gcc_aggre_ufs_phy_axi_clk",
804 .parent_hws = (const struct clk_hw*[]){
805 &gcc_ufs_phy_axi_clk_src.clkr.hw,
808 .flags = CLK_SET_RATE_PARENT,
809 .ops = &clk_branch2_ops,
814 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
816 .halt_check = BRANCH_HALT,
820 .enable_reg = 0x3e014,
821 .enable_mask = BIT(1),
822 .hw.init = &(struct clk_init_data){
823 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
824 .parent_hws = (const struct clk_hw*[]){
825 &gcc_ufs_phy_axi_clk_src.clkr.hw,
828 .flags = CLK_SET_RATE_PARENT,
829 .ops = &clk_branch2_ops,
834 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
836 .halt_check = BRANCH_HALT,
840 .enable_reg = 0x3e014,
841 .enable_mask = BIT(1),
842 .hw.init = &(struct clk_init_data){
843 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
844 .parent_hws = (const struct clk_hw*[]){
845 &gcc_ufs_phy_axi_clk_src.clkr.hw,
848 .flags = CLK_SET_RATE_PARENT,
849 .ops = &clk_branch2_ops,
854 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
856 .halt_check = BRANCH_HALT,
860 .enable_reg = 0x3e010,
861 .enable_mask = BIT(0),
862 .hw.init = &(struct clk_init_data){
863 .name = "gcc_aggre_usb3_prim_axi_clk",
864 .parent_hws = (const struct clk_hw*[]){
865 &gcc_usb30_prim_master_clk_src.clkr.hw,
868 .flags = CLK_SET_RATE_PARENT,
869 .ops = &clk_branch2_ops,
874 static struct clk_branch gcc_boot_rom_ahb_clk = {
876 .halt_check = BRANCH_HALT_VOTED,
880 .enable_reg = 0x52000,
881 .enable_mask = BIT(28),
882 .hw.init = &(struct clk_init_data){
883 .name = "gcc_boot_rom_ahb_clk",
884 .ops = &clk_branch2_ops,
889 static struct clk_branch gcc_camera_ahb_clk = {
891 .halt_check = BRANCH_HALT,
895 .enable_reg = 0x17008,
896 .enable_mask = BIT(0),
897 .hw.init = &(struct clk_init_data){
898 .name = "gcc_camera_ahb_clk",
899 .flags = CLK_IS_CRITICAL,
900 .ops = &clk_branch2_ops,
905 static struct clk_branch gcc_camera_axi_clk = {
907 .halt_check = BRANCH_HALT,
911 .enable_reg = 0x17018,
912 .enable_mask = BIT(0),
913 .hw.init = &(struct clk_init_data){
914 .name = "gcc_camera_axi_clk",
915 .ops = &clk_branch2_ops,
920 static struct clk_branch gcc_camera_throttle_nrt_axi_clk = {
922 .halt_check = BRANCH_VOTED,
926 .enable_reg = 0x17078,
927 .enable_mask = BIT(0),
928 .hw.init = &(struct clk_init_data){
929 .name = "gcc_camera_throttle_nrt_axi_clk",
930 .ops = &clk_branch2_ops,
935 static struct clk_branch gcc_camera_throttle_rt_axi_clk = {
937 .halt_check = BRANCH_VOTED,
941 .enable_reg = 0x17024,
942 .enable_mask = BIT(0),
943 .hw.init = &(struct clk_init_data){
944 .name = "gcc_camera_throttle_rt_axi_clk",
945 .ops = &clk_branch2_ops,
950 static struct clk_branch gcc_camera_xo_clk = {
952 .halt_check = BRANCH_HALT,
954 .enable_reg = 0x17030,
955 .enable_mask = BIT(0),
956 .hw.init = &(struct clk_init_data){
957 .name = "gcc_camera_xo_clk",
958 .flags = CLK_IS_CRITICAL,
959 .ops = &clk_branch2_ops,
964 static struct clk_branch gcc_ce1_ahb_clk = {
966 .halt_check = BRANCH_HALT_VOTED,
970 .enable_reg = 0x52008,
971 .enable_mask = BIT(3),
972 .hw.init = &(struct clk_init_data){
973 .name = "gcc_ce1_ahb_clk",
974 .ops = &clk_branch2_ops,
979 static struct clk_branch gcc_ce1_axi_clk = {
981 .halt_check = BRANCH_HALT_VOTED,
983 .enable_reg = 0x52008,
984 .enable_mask = BIT(2),
985 .hw.init = &(struct clk_init_data){
986 .name = "gcc_ce1_axi_clk",
987 .ops = &clk_branch2_ops,
992 static struct clk_branch gcc_ce1_clk = {
994 .halt_check = BRANCH_HALT_VOTED,
996 .enable_reg = 0x52008,
997 .enable_mask = BIT(1),
998 .hw.init = &(struct clk_init_data){
999 .name = "gcc_ce1_clk",
1000 .ops = &clk_branch2_ops,
1005 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1006 .halt_reg = 0x1101c,
1007 .halt_check = BRANCH_HALT,
1008 .hwcg_reg = 0x1101c,
1011 .enable_reg = 0x1101c,
1012 .enable_mask = BIT(0),
1013 .hw.init = &(struct clk_init_data){
1014 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1015 .parent_hws = (const struct clk_hw*[]){
1016 &gcc_usb30_prim_master_clk_src.clkr.hw,
1019 .flags = CLK_SET_RATE_PARENT,
1020 .ops = &clk_branch2_ops,
1025 static struct clk_branch gcc_cpuss_ahb_clk = {
1026 .halt_reg = 0x30000,
1027 .halt_check = BRANCH_HALT_VOTED,
1028 .hwcg_reg = 0x30000,
1031 .enable_reg = 0x52008,
1032 .enable_mask = BIT(4),
1033 .hw.init = &(struct clk_init_data){
1034 .name = "gcc_cpuss_ahb_clk",
1035 .parent_hws = (const struct clk_hw*[]){
1036 &gcc_cpuss_ahb_clk_src.clkr.hw,
1039 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1040 .ops = &clk_branch2_ops,
1045 static struct clk_branch gcc_cpuss_gnoc_clk = {
1046 .halt_reg = 0x30004,
1047 .halt_check = BRANCH_HALT_VOTED,
1048 .hwcg_reg = 0x30004,
1051 .enable_reg = 0x52008,
1052 .enable_mask = BIT(5),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "gcc_cpuss_gnoc_clk",
1055 .flags = CLK_IS_CRITICAL,
1056 .ops = &clk_branch2_ops,
1061 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1062 .halt_reg = 0x30008,
1063 .halt_check = BRANCH_HALT,
1065 .enable_reg = 0x30008,
1066 .enable_mask = BIT(0),
1067 .hw.init = &(struct clk_init_data){
1068 .name = "gcc_cpuss_rbcpr_clk",
1069 .ops = &clk_branch2_ops,
1074 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1075 .halt_reg = 0x2d038,
1076 .halt_check = BRANCH_VOTED,
1077 .hwcg_reg = 0x2d038,
1080 .enable_reg = 0x2d038,
1081 .enable_mask = BIT(0),
1082 .hw.init = &(struct clk_init_data){
1083 .name = "gcc_ddrss_gpu_axi_clk",
1084 .ops = &clk_branch2_ops,
1089 static struct clk_branch gcc_disp_ahb_clk = {
1090 .halt_reg = 0x1700c,
1091 .halt_check = BRANCH_HALT,
1092 .hwcg_reg = 0x1700c,
1095 .enable_reg = 0x1700c,
1096 .enable_mask = BIT(0),
1097 .hw.init = &(struct clk_init_data){
1098 .name = "gcc_disp_ahb_clk",
1099 .flags = CLK_IS_CRITICAL,
1100 .ops = &clk_branch2_ops,
1105 static struct clk_branch gcc_disp_axi_clk = {
1106 .halt_reg = 0x1701c,
1107 .halt_check = BRANCH_HALT,
1108 .hwcg_reg = 0x1701c,
1111 .enable_reg = 0x1701c,
1112 .enable_mask = BIT(0),
1113 .hw.init = &(struct clk_init_data){
1114 .name = "gcc_disp_axi_clk",
1115 .ops = &clk_branch2_ops,
1120 static struct clk_branch gcc_disp_cc_sleep_clk = {
1121 .halt_reg = 0x17074,
1122 .halt_check = BRANCH_HALT_DELAY,
1123 .hwcg_reg = 0x17074,
1126 .enable_reg = 0x17074,
1127 .enable_mask = BIT(0),
1128 .hw.init = &(struct clk_init_data){
1129 .name = "gcc_disp_cc_sleep_clk",
1130 .ops = &clk_branch2_ops,
1135 static struct clk_branch gcc_disp_cc_xo_clk = {
1136 .halt_reg = 0x17070,
1137 .halt_check = BRANCH_HALT,
1138 .hwcg_reg = 0x17070,
1141 .enable_reg = 0x17070,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "gcc_disp_cc_xo_clk",
1145 .flags = CLK_IS_CRITICAL,
1146 .ops = &clk_branch2_ops,
1151 static struct clk_branch gcc_disp_gpll0_clk = {
1152 .halt_check = BRANCH_HALT_DELAY,
1154 .enable_reg = 0x52000,
1155 .enable_mask = BIT(2),
1156 .hw.init = &(struct clk_init_data){
1157 .name = "gcc_disp_gpll0_clk",
1158 .parent_hws = (const struct clk_hw*[]){
1162 .ops = &clk_branch2_ops,
1167 static struct clk_branch gcc_disp_throttle_axi_clk = {
1168 .halt_reg = 0x17028,
1169 .halt_check = BRANCH_HALT,
1170 .hwcg_reg = 0x17028,
1173 .enable_reg = 0x17028,
1174 .enable_mask = BIT(0),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "gcc_disp_throttle_axi_clk",
1177 .ops = &clk_branch2_ops,
1182 static struct clk_branch gcc_disp_xo_clk = {
1183 .halt_reg = 0x17034,
1184 .halt_check = BRANCH_HALT,
1186 .enable_reg = 0x17034,
1187 .enable_mask = BIT(0),
1188 .hw.init = &(struct clk_init_data){
1189 .name = "gcc_disp_xo_clk",
1190 .ops = &clk_branch2_ops,
1195 static struct clk_branch gcc_gp1_clk = {
1196 .halt_reg = 0x37000,
1197 .halt_check = BRANCH_HALT,
1199 .enable_reg = 0x37000,
1200 .enable_mask = BIT(0),
1201 .hw.init = &(struct clk_init_data){
1202 .name = "gcc_gp1_clk",
1203 .parent_hws = (const struct clk_hw*[]){
1204 &gcc_gp1_clk_src.clkr.hw,
1207 .flags = CLK_SET_RATE_PARENT,
1208 .ops = &clk_branch2_ops,
1213 static struct clk_branch gcc_gp2_clk = {
1214 .halt_reg = 0x38000,
1215 .halt_check = BRANCH_HALT,
1217 .enable_reg = 0x38000,
1218 .enable_mask = BIT(0),
1219 .hw.init = &(struct clk_init_data){
1220 .name = "gcc_gp2_clk",
1221 .parent_hws = (const struct clk_hw*[]){
1222 &gcc_gp2_clk_src.clkr.hw,
1225 .flags = CLK_SET_RATE_PARENT,
1226 .ops = &clk_branch2_ops,
1231 static struct clk_branch gcc_gp3_clk = {
1232 .halt_reg = 0x39000,
1233 .halt_check = BRANCH_HALT,
1235 .enable_reg = 0x39000,
1236 .enable_mask = BIT(0),
1237 .hw.init = &(struct clk_init_data){
1238 .name = "gcc_gp3_clk",
1239 .parent_hws = (const struct clk_hw*[]){
1240 &gcc_gp3_clk_src.clkr.hw,
1243 .flags = CLK_SET_RATE_PARENT,
1244 .ops = &clk_branch2_ops,
1249 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1250 .halt_reg = 0x45004,
1251 .halt_check = BRANCH_HALT,
1252 .hwcg_reg = 0x45004,
1255 .enable_reg = 0x45004,
1256 .enable_mask = BIT(0),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "gcc_gpu_cfg_ahb_clk",
1259 .flags = CLK_IS_CRITICAL,
1260 .ops = &clk_branch2_ops,
1265 static struct clk_branch gcc_gpu_gpll0_clk = {
1266 .halt_check = BRANCH_HALT_DELAY,
1268 .enable_reg = 0x52008,
1269 .enable_mask = BIT(7),
1270 .hw.init = &(struct clk_init_data){
1271 .name = "gcc_gpu_gpll0_clk",
1272 .parent_hws = (const struct clk_hw*[]){
1276 .ops = &clk_branch2_ops,
1281 static struct clk_branch gcc_gpu_gpll0_div_clk = {
1282 .halt_check = BRANCH_HALT_DELAY,
1284 .enable_reg = 0x52008,
1285 .enable_mask = BIT(8),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "gcc_gpu_gpll0_div_clk",
1288 .parent_hws = (const struct clk_hw*[]){
1289 &gcc_gpu_gpll0_main_div_clk_src.clkr.hw,
1292 .ops = &clk_branch2_ops,
1297 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1298 .halt_reg = 0x4500c,
1299 .halt_check = BRANCH_VOTED,
1300 .hwcg_reg = 0x4500c,
1303 .enable_reg = 0x4500c,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "gcc_gpu_memnoc_gfx_clk",
1307 .ops = &clk_branch2_ops,
1312 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1313 .halt_reg = 0x45014,
1314 .halt_check = BRANCH_HALT,
1315 .hwcg_reg = 0x45014,
1318 .enable_reg = 0x45014,
1319 .enable_mask = BIT(0),
1320 .hw.init = &(struct clk_init_data){
1321 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1322 .ops = &clk_branch2_ops,
1327 static struct clk_branch gcc_npu_axi_clk = {
1328 .halt_reg = 0x4c008,
1329 .halt_check = BRANCH_VOTED,
1330 .hwcg_reg = 0x4c008,
1333 .enable_reg = 0x4c008,
1334 .enable_mask = BIT(0),
1335 .hw.init = &(struct clk_init_data){
1336 .name = "gcc_npu_axi_clk",
1337 .ops = &clk_branch2_ops,
1342 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1343 .halt_reg = 0x4d004,
1344 .halt_check = BRANCH_HALT_DELAY,
1345 .hwcg_reg = 0x4d004,
1348 .enable_reg = 0x4d004,
1349 .enable_mask = BIT(0),
1350 .hw.init = &(struct clk_init_data){
1351 .name = "gcc_npu_bwmon_axi_clk",
1352 .ops = &clk_branch2_ops,
1357 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1358 .halt_reg = 0x4d008,
1359 .halt_check = BRANCH_HALT,
1361 .enable_reg = 0x4d008,
1362 .enable_mask = BIT(0),
1363 .hw.init = &(struct clk_init_data){
1364 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1365 .ops = &clk_branch2_ops,
1370 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1371 .halt_reg = 0x4d00c,
1372 .halt_check = BRANCH_HALT,
1374 .enable_reg = 0x4d00c,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data){
1377 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1378 .ops = &clk_branch2_ops,
1383 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1384 .halt_reg = 0x4c004,
1385 .halt_check = BRANCH_HALT,
1386 .hwcg_reg = 0x4c004,
1389 .enable_reg = 0x4c004,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "gcc_npu_cfg_ahb_clk",
1393 .flags = CLK_IS_CRITICAL,
1394 .ops = &clk_branch2_ops,
1399 static struct clk_branch gcc_npu_dma_clk = {
1400 .halt_reg = 0x4c140,
1401 .halt_check = BRANCH_VOTED,
1402 .hwcg_reg = 0x4c140,
1405 .enable_reg = 0x4c140,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "gcc_npu_dma_clk",
1409 .ops = &clk_branch2_ops,
1414 static struct clk_branch gcc_npu_gpll0_clk = {
1415 .halt_check = BRANCH_HALT_DELAY,
1417 .enable_reg = 0x52008,
1418 .enable_mask = BIT(9),
1419 .hw.init = &(struct clk_init_data){
1420 .name = "gcc_npu_gpll0_clk",
1421 .parent_hws = (const struct clk_hw*[]){
1425 .ops = &clk_branch2_ops,
1430 static struct clk_branch gcc_npu_gpll0_div_clk = {
1431 .halt_check = BRANCH_HALT_DELAY,
1433 .enable_reg = 0x52008,
1434 .enable_mask = BIT(10),
1435 .hw.init = &(struct clk_init_data){
1436 .name = "gcc_npu_gpll0_div_clk",
1437 .parent_hws = (const struct clk_hw*[]){
1438 &gcc_npu_pll0_main_div_clk_src.clkr.hw,
1441 .ops = &clk_branch2_ops,
1446 static struct clk_branch gcc_pdm2_clk = {
1447 .halt_reg = 0x2300c,
1448 .halt_check = BRANCH_HALT,
1450 .enable_reg = 0x2300c,
1451 .enable_mask = BIT(0),
1452 .hw.init = &(struct clk_init_data){
1453 .name = "gcc_pdm2_clk",
1454 .parent_hws = (const struct clk_hw*[]){
1455 &gcc_pdm2_clk_src.clkr.hw,
1458 .flags = CLK_SET_RATE_PARENT,
1459 .ops = &clk_branch2_ops,
1464 static struct clk_branch gcc_pdm_ahb_clk = {
1465 .halt_reg = 0x23004,
1466 .halt_check = BRANCH_HALT,
1467 .hwcg_reg = 0x23004,
1470 .enable_reg = 0x23004,
1471 .enable_mask = BIT(0),
1472 .hw.init = &(struct clk_init_data){
1473 .name = "gcc_pdm_ahb_clk",
1474 .ops = &clk_branch2_ops,
1479 static struct clk_branch gcc_pdm_xo4_clk = {
1480 .halt_reg = 0x23008,
1481 .halt_check = BRANCH_HALT,
1483 .enable_reg = 0x23008,
1484 .enable_mask = BIT(0),
1485 .hw.init = &(struct clk_init_data){
1486 .name = "gcc_pdm_xo4_clk",
1487 .ops = &clk_branch2_ops,
1492 static struct clk_branch gcc_prng_ahb_clk = {
1493 .halt_reg = 0x24004,
1494 .halt_check = BRANCH_HALT_VOTED,
1495 .hwcg_reg = 0x24004,
1498 .enable_reg = 0x52000,
1499 .enable_mask = BIT(26),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "gcc_prng_ahb_clk",
1502 .ops = &clk_branch2_ops,
1507 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1508 .halt_reg = 0x21014,
1509 .halt_check = BRANCH_HALT_VOTED,
1511 .enable_reg = 0x52000,
1512 .enable_mask = BIT(9),
1513 .hw.init = &(struct clk_init_data){
1514 .name = "gcc_qupv3_wrap0_core_2x_clk",
1515 .ops = &clk_branch2_ops,
1520 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1521 .halt_reg = 0x2100c,
1522 .halt_check = BRANCH_HALT_VOTED,
1524 .enable_reg = 0x52000,
1525 .enable_mask = BIT(8),
1526 .hw.init = &(struct clk_init_data){
1527 .name = "gcc_qupv3_wrap0_core_clk",
1528 .ops = &clk_branch2_ops,
1533 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1534 .halt_reg = 0x21144,
1535 .halt_check = BRANCH_HALT_VOTED,
1537 .enable_reg = 0x52000,
1538 .enable_mask = BIT(10),
1539 .hw.init = &(struct clk_init_data){
1540 .name = "gcc_qupv3_wrap0_s0_clk",
1541 .parent_hws = (const struct clk_hw*[]){
1542 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1545 .flags = CLK_SET_RATE_PARENT,
1546 .ops = &clk_branch2_ops,
1551 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1552 .halt_reg = 0x21274,
1553 .halt_check = BRANCH_HALT_VOTED,
1555 .enable_reg = 0x52000,
1556 .enable_mask = BIT(11),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gcc_qupv3_wrap0_s1_clk",
1559 .parent_hws = (const struct clk_hw*[]){
1560 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1569 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1570 .halt_reg = 0x213a4,
1571 .halt_check = BRANCH_HALT_VOTED,
1573 .enable_reg = 0x52000,
1574 .enable_mask = BIT(12),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "gcc_qupv3_wrap0_s2_clk",
1577 .parent_hws = (const struct clk_hw*[]){
1578 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1581 .flags = CLK_SET_RATE_PARENT,
1582 .ops = &clk_branch2_ops,
1587 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1588 .halt_reg = 0x214d4,
1589 .halt_check = BRANCH_HALT_VOTED,
1591 .enable_reg = 0x52000,
1592 .enable_mask = BIT(13),
1593 .hw.init = &(struct clk_init_data){
1594 .name = "gcc_qupv3_wrap0_s3_clk",
1595 .parent_hws = (const struct clk_hw*[]){
1596 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1605 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1606 .halt_reg = 0x21604,
1607 .halt_check = BRANCH_HALT_VOTED,
1609 .enable_reg = 0x52000,
1610 .enable_mask = BIT(14),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "gcc_qupv3_wrap0_s4_clk",
1613 .parent_hws = (const struct clk_hw*[]){
1614 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1617 .flags = CLK_SET_RATE_PARENT,
1618 .ops = &clk_branch2_ops,
1623 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1624 .halt_reg = 0x21734,
1625 .halt_check = BRANCH_HALT_VOTED,
1627 .enable_reg = 0x52000,
1628 .enable_mask = BIT(15),
1629 .hw.init = &(struct clk_init_data){
1630 .name = "gcc_qupv3_wrap0_s5_clk",
1631 .parent_hws = (const struct clk_hw*[]){
1632 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1635 .flags = CLK_SET_RATE_PARENT,
1636 .ops = &clk_branch2_ops,
1641 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1642 .halt_reg = 0x22004,
1643 .halt_check = BRANCH_HALT_VOTED,
1645 .enable_reg = 0x52000,
1646 .enable_mask = BIT(16),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "gcc_qupv3_wrap1_core_2x_clk",
1649 .ops = &clk_branch2_ops,
1654 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1655 .halt_reg = 0x22008,
1656 .halt_check = BRANCH_HALT_VOTED,
1658 .enable_reg = 0x52000,
1659 .enable_mask = BIT(17),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "gcc_qupv3_wrap1_core_clk",
1662 .ops = &clk_branch2_ops,
1667 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1668 .halt_reg = 0x22014,
1669 .halt_check = BRANCH_HALT_VOTED,
1671 .enable_reg = 0x52000,
1672 .enable_mask = BIT(20),
1673 .hw.init = &(struct clk_init_data){
1674 .name = "gcc_qupv3_wrap1_s0_clk",
1675 .parent_hws = (const struct clk_hw*[]){
1676 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1679 .flags = CLK_SET_RATE_PARENT,
1680 .ops = &clk_branch2_ops,
1685 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1686 .halt_reg = 0x22144,
1687 .halt_check = BRANCH_HALT_VOTED,
1689 .enable_reg = 0x52000,
1690 .enable_mask = BIT(21),
1691 .hw.init = &(struct clk_init_data){
1692 .name = "gcc_qupv3_wrap1_s1_clk",
1693 .parent_hws = (const struct clk_hw*[]){
1694 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1697 .flags = CLK_SET_RATE_PARENT,
1698 .ops = &clk_branch2_ops,
1703 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1704 .halt_reg = 0x22274,
1705 .halt_check = BRANCH_HALT_VOTED,
1707 .enable_reg = 0x52000,
1708 .enable_mask = BIT(22),
1709 .hw.init = &(struct clk_init_data){
1710 .name = "gcc_qupv3_wrap1_s2_clk",
1711 .parent_hws = (const struct clk_hw*[]){
1712 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1715 .flags = CLK_SET_RATE_PARENT,
1716 .ops = &clk_branch2_ops,
1721 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1722 .halt_reg = 0x223a4,
1723 .halt_check = BRANCH_HALT_VOTED,
1725 .enable_reg = 0x52000,
1726 .enable_mask = BIT(23),
1727 .hw.init = &(struct clk_init_data){
1728 .name = "gcc_qupv3_wrap1_s3_clk",
1729 .parent_hws = (const struct clk_hw*[]){
1730 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1733 .flags = CLK_SET_RATE_PARENT,
1734 .ops = &clk_branch2_ops,
1739 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1740 .halt_reg = 0x224d4,
1741 .halt_check = BRANCH_HALT_VOTED,
1743 .enable_reg = 0x52000,
1744 .enable_mask = BIT(24),
1745 .hw.init = &(struct clk_init_data){
1746 .name = "gcc_qupv3_wrap1_s4_clk",
1747 .parent_hws = (const struct clk_hw*[]){
1748 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1751 .flags = CLK_SET_RATE_PARENT,
1752 .ops = &clk_branch2_ops,
1757 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1758 .halt_reg = 0x22604,
1759 .halt_check = BRANCH_HALT_VOTED,
1761 .enable_reg = 0x52000,
1762 .enable_mask = BIT(25),
1763 .hw.init = &(struct clk_init_data){
1764 .name = "gcc_qupv3_wrap1_s5_clk",
1765 .parent_hws = (const struct clk_hw*[]){
1766 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1769 .flags = CLK_SET_RATE_PARENT,
1770 .ops = &clk_branch2_ops,
1775 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1776 .halt_reg = 0x21004,
1777 .halt_check = BRANCH_HALT_VOTED,
1778 .hwcg_reg = 0x21004,
1781 .enable_reg = 0x52000,
1782 .enable_mask = BIT(6),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1785 .ops = &clk_branch2_ops,
1790 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1791 .halt_reg = 0x21008,
1792 .halt_check = BRANCH_HALT_VOTED,
1793 .hwcg_reg = 0x21008,
1796 .enable_reg = 0x52000,
1797 .enable_mask = BIT(7),
1798 .hw.init = &(struct clk_init_data){
1799 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1800 .ops = &clk_branch2_ops,
1805 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1806 .halt_reg = 0x2200c,
1807 .halt_check = BRANCH_HALT_VOTED,
1808 .hwcg_reg = 0x2200c,
1811 .enable_reg = 0x52000,
1812 .enable_mask = BIT(18),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1815 .ops = &clk_branch2_ops,
1820 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1821 .halt_reg = 0x22010,
1822 .halt_check = BRANCH_HALT_VOTED,
1823 .hwcg_reg = 0x22010,
1826 .enable_reg = 0x52000,
1827 .enable_mask = BIT(19),
1828 .hw.init = &(struct clk_init_data){
1829 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1830 .ops = &clk_branch2_ops,
1835 static struct clk_branch gcc_sdcc1_ahb_clk = {
1836 .halt_reg = 0x4b004,
1837 .halt_check = BRANCH_HALT,
1839 .enable_reg = 0x4b004,
1840 .enable_mask = BIT(0),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_sdcc1_ahb_clk",
1843 .ops = &clk_branch2_ops,
1848 static struct clk_branch gcc_sdcc1_apps_clk = {
1849 .halt_reg = 0x4b008,
1850 .halt_check = BRANCH_HALT,
1852 .enable_reg = 0x4b008,
1853 .enable_mask = BIT(0),
1854 .hw.init = &(struct clk_init_data){
1855 .name = "gcc_sdcc1_apps_clk",
1856 .parent_hws = (const struct clk_hw*[]){
1857 &gcc_sdcc1_apps_clk_src.clkr.hw,
1860 .flags = CLK_SET_RATE_PARENT,
1861 .ops = &clk_branch2_ops,
1866 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1867 .halt_reg = 0x4b03c,
1868 .halt_check = BRANCH_HALT,
1869 .hwcg_reg = 0x4b03c,
1872 .enable_reg = 0x4b03c,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "gcc_sdcc1_ice_core_clk",
1876 .parent_hws = (const struct clk_hw*[]){
1877 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1880 .flags = CLK_SET_RATE_PARENT,
1881 .ops = &clk_branch2_ops,
1886 static struct clk_branch gcc_sdcc2_ahb_clk = {
1887 .halt_reg = 0x20008,
1888 .halt_check = BRANCH_HALT,
1890 .enable_reg = 0x20008,
1891 .enable_mask = BIT(0),
1892 .hw.init = &(struct clk_init_data){
1893 .name = "gcc_sdcc2_ahb_clk",
1894 .ops = &clk_branch2_ops,
1899 static struct clk_branch gcc_sdcc2_apps_clk = {
1900 .halt_reg = 0x20004,
1901 .halt_check = BRANCH_HALT,
1903 .enable_reg = 0x20004,
1904 .enable_mask = BIT(0),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "gcc_sdcc2_apps_clk",
1907 .parent_hws = (const struct clk_hw*[]){
1908 &gcc_sdcc2_apps_clk_src.clkr.hw,
1911 .flags = CLK_SET_RATE_PARENT,
1912 .ops = &clk_branch2_ops,
1917 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1918 .halt_reg = 0x10140,
1919 .halt_check = BRANCH_HALT_VOTED,
1920 .hwcg_reg = 0x10140,
1923 .enable_reg = 0x52000,
1924 .enable_mask = BIT(0),
1925 .hw.init = &(struct clk_init_data){
1926 .name = "gcc_sys_noc_cpuss_ahb_clk",
1927 .parent_hws = (const struct clk_hw*[]){
1928 &gcc_cpuss_ahb_clk_src.clkr.hw,
1931 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1932 .ops = &clk_branch2_ops,
1937 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1938 .halt_reg = 0x8c000,
1939 .halt_check = BRANCH_HALT,
1941 .enable_reg = 0x8c000,
1942 .enable_mask = BIT(0),
1943 .hw.init = &(struct clk_init_data){
1944 .name = "gcc_ufs_mem_clkref_clk",
1945 .ops = &clk_branch2_ops,
1950 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1951 .halt_reg = 0x3a00c,
1952 .halt_check = BRANCH_HALT,
1953 .hwcg_reg = 0x3a00c,
1956 .enable_reg = 0x3a00c,
1957 .enable_mask = BIT(0),
1958 .hw.init = &(struct clk_init_data){
1959 .name = "gcc_ufs_phy_ahb_clk",
1960 .ops = &clk_branch2_ops,
1965 static struct clk_branch gcc_ufs_phy_axi_clk = {
1966 .halt_reg = 0x3a034,
1967 .halt_check = BRANCH_HALT,
1968 .hwcg_reg = 0x3a034,
1971 .enable_reg = 0x3a034,
1972 .enable_mask = BIT(0),
1973 .hw.init = &(struct clk_init_data){
1974 .name = "gcc_ufs_phy_axi_clk",
1975 .parent_hws = (const struct clk_hw*[]){
1976 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1979 .flags = CLK_SET_RATE_PARENT,
1980 .ops = &clk_branch2_ops,
1985 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1986 .halt_reg = 0x3a0a4,
1987 .halt_check = BRANCH_HALT,
1988 .hwcg_reg = 0x3a0a4,
1991 .enable_reg = 0x3a0a4,
1992 .enable_mask = BIT(0),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "gcc_ufs_phy_ice_core_clk",
1995 .parent_hws = (const struct clk_hw*[]){
1996 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1999 .flags = CLK_SET_RATE_PARENT,
2000 .ops = &clk_branch2_ops,
2005 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2006 .halt_reg = 0x3a0a4,
2007 .halt_check = BRANCH_HALT,
2008 .hwcg_reg = 0x3a0a4,
2011 .enable_reg = 0x3a0a4,
2012 .enable_mask = BIT(1),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2015 .parent_hws = (const struct clk_hw*[]){
2016 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2019 .flags = CLK_SET_RATE_PARENT,
2020 .ops = &clk_branch2_ops,
2025 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2026 .halt_reg = 0x3a0ac,
2027 .halt_check = BRANCH_HALT,
2028 .hwcg_reg = 0x3a0ac,
2031 .enable_reg = 0x3a0ac,
2032 .enable_mask = BIT(0),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "gcc_ufs_phy_phy_aux_clk",
2035 .parent_hws = (const struct clk_hw*[]){
2036 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2039 .flags = CLK_SET_RATE_PARENT,
2040 .ops = &clk_branch2_ops,
2045 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2046 .halt_reg = 0x3a0ac,
2047 .halt_check = BRANCH_HALT,
2048 .hwcg_reg = 0x3a0ac,
2051 .enable_reg = 0x3a0ac,
2052 .enable_mask = BIT(1),
2053 .hw.init = &(struct clk_init_data){
2054 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2055 .parent_hws = (const struct clk_hw*[]){
2056 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2059 .flags = CLK_SET_RATE_PARENT,
2060 .ops = &clk_branch2_ops,
2065 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2066 .halt_reg = 0x3a014,
2067 .halt_check = BRANCH_HALT_SKIP,
2069 .enable_reg = 0x3a014,
2070 .enable_mask = BIT(0),
2071 .hw.init = &(struct clk_init_data){
2072 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2073 .ops = &clk_branch2_ops,
2078 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2079 .halt_reg = 0x3a018,
2080 .halt_check = BRANCH_HALT_SKIP,
2082 .enable_reg = 0x3a018,
2083 .enable_mask = BIT(0),
2084 .hw.init = &(struct clk_init_data){
2085 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2086 .ops = &clk_branch2_ops,
2091 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2092 .halt_reg = 0x3a010,
2093 .halt_check = BRANCH_HALT_SKIP,
2095 .enable_reg = 0x3a010,
2096 .enable_mask = BIT(0),
2097 .hw.init = &(struct clk_init_data){
2098 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2099 .ops = &clk_branch2_ops,
2104 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2105 .halt_reg = 0x3a09c,
2106 .halt_check = BRANCH_HALT,
2107 .hwcg_reg = 0x3a09c,
2110 .enable_reg = 0x3a09c,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "gcc_ufs_phy_unipro_core_clk",
2114 .parent_hws = (const struct clk_hw*[]){
2115 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2118 .flags = CLK_SET_RATE_PARENT,
2119 .ops = &clk_branch2_ops,
2124 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2125 .halt_reg = 0x3a09c,
2126 .halt_check = BRANCH_HALT,
2127 .hwcg_reg = 0x3a09c,
2130 .enable_reg = 0x3a09c,
2131 .enable_mask = BIT(1),
2132 .hw.init = &(struct clk_init_data){
2133 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2134 .parent_hws = (const struct clk_hw*[]){
2135 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2138 .flags = CLK_SET_RATE_PARENT,
2139 .ops = &clk_branch2_ops,
2144 static struct clk_branch gcc_usb30_prim_master_clk = {
2145 .halt_reg = 0x1a00c,
2146 .halt_check = BRANCH_HALT,
2148 .enable_reg = 0x1a00c,
2149 .enable_mask = BIT(0),
2150 .hw.init = &(struct clk_init_data){
2151 .name = "gcc_usb30_prim_master_clk",
2152 .parent_hws = (const struct clk_hw*[]){
2153 &gcc_usb30_prim_master_clk_src.clkr.hw,
2156 .flags = CLK_SET_RATE_PARENT,
2157 .ops = &clk_branch2_ops,
2162 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2163 .halt_reg = 0x1a018,
2164 .halt_check = BRANCH_HALT,
2166 .enable_reg = 0x1a018,
2167 .enable_mask = BIT(0),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "gcc_usb30_prim_mock_utmi_clk",
2170 .parent_hws = (const struct clk_hw*[]){
2171 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2174 .flags = CLK_SET_RATE_PARENT,
2175 .ops = &clk_branch2_ops,
2180 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2181 .halt_reg = 0x1a014,
2182 .halt_check = BRANCH_HALT,
2184 .enable_reg = 0x1a014,
2185 .enable_mask = BIT(0),
2186 .hw.init = &(struct clk_init_data){
2187 .name = "gcc_usb30_prim_sleep_clk",
2188 .ops = &clk_branch2_ops,
2193 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2194 .halt_reg = 0x8c010,
2195 .halt_check = BRANCH_HALT,
2197 .enable_reg = 0x8c010,
2198 .enable_mask = BIT(0),
2199 .hw.init = &(struct clk_init_data){
2200 .name = "gcc_usb3_prim_clkref_clk",
2201 .ops = &clk_branch2_ops,
2206 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2207 .halt_reg = 0x1a050,
2208 .halt_check = BRANCH_HALT,
2210 .enable_reg = 0x1a050,
2211 .enable_mask = BIT(0),
2212 .hw.init = &(struct clk_init_data){
2213 .name = "gcc_usb3_prim_phy_aux_clk",
2214 .parent_hws = (const struct clk_hw*[]){
2215 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2218 .flags = CLK_SET_RATE_PARENT,
2219 .ops = &clk_branch2_ops,
2224 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2225 .halt_reg = 0x1a054,
2226 .halt_check = BRANCH_HALT,
2228 .enable_reg = 0x1a054,
2229 .enable_mask = BIT(0),
2230 .hw.init = &(struct clk_init_data){
2231 .name = "gcc_usb3_prim_phy_com_aux_clk",
2232 .parent_hws = (const struct clk_hw*[]){
2233 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_branch2_ops,
2242 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2243 .halt_reg = 0x1a058,
2244 .halt_check = BRANCH_HALT_SKIP,
2245 .hwcg_reg = 0x1a058,
2248 .enable_reg = 0x1a058,
2249 .enable_mask = BIT(0),
2250 .hw.init = &(struct clk_init_data){
2251 .name = "gcc_usb3_prim_phy_pipe_clk",
2252 .ops = &clk_branch2_ops,
2257 static struct clk_branch gcc_video_ahb_clk = {
2258 .halt_reg = 0x17004,
2259 .halt_check = BRANCH_HALT,
2260 .hwcg_reg = 0x17004,
2263 .enable_reg = 0x17004,
2264 .enable_mask = BIT(0),
2265 .hw.init = &(struct clk_init_data){
2266 .name = "gcc_video_ahb_clk",
2267 .flags = CLK_IS_CRITICAL,
2268 .ops = &clk_branch2_ops,
2273 static struct clk_branch gcc_video_axi_clk = {
2274 .halt_reg = 0x17014,
2275 .halt_check = BRANCH_HALT,
2276 .hwcg_reg = 0x17014,
2279 .enable_reg = 0x17014,
2280 .enable_mask = BIT(0),
2281 .hw.init = &(struct clk_init_data){
2282 .name = "gcc_video_axi_clk",
2283 .ops = &clk_branch2_ops,
2288 static struct clk_branch gcc_video_throttle_axi_clk = {
2289 .halt_reg = 0x17020,
2290 .halt_check = BRANCH_HALT,
2291 .hwcg_reg = 0x17020,
2294 .enable_reg = 0x17020,
2295 .enable_mask = BIT(0),
2296 .hw.init = &(struct clk_init_data){
2297 .name = "gcc_video_throttle_axi_clk",
2298 .ops = &clk_branch2_ops,
2303 static struct clk_branch gcc_video_xo_clk = {
2304 .halt_reg = 0x1702c,
2305 .halt_check = BRANCH_HALT,
2307 .enable_reg = 0x1702c,
2308 .enable_mask = BIT(0),
2309 .hw.init = &(struct clk_init_data){
2310 .name = "gcc_video_xo_clk",
2311 .flags = CLK_IS_CRITICAL,
2312 .ops = &clk_branch2_ops,
2317 static struct gdsc usb30_prim_gdsc = {
2320 .name = "usb30_prim_gdsc",
2322 .pwrsts = PWRSTS_OFF_ON,
2325 static struct gdsc ufs_phy_gdsc = {
2328 .name = "ufs_phy_gdsc",
2330 .pwrsts = PWRSTS_OFF_ON,
2333 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2336 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2338 .pwrsts = PWRSTS_OFF_ON,
2342 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
2345 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
2347 .pwrsts = PWRSTS_OFF_ON,
2351 static struct clk_regmap *gcc_sm6350_clocks[] = {
2352 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2353 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2354 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2355 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
2356 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
2357 [GCC_CAMERA_THROTTLE_NRT_AXI_CLK] =
2358 &gcc_camera_throttle_nrt_axi_clk.clkr,
2359 [GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr,
2360 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
2361 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2362 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2363 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2364 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2365 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2366 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2367 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
2368 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2369 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2370 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
2371 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
2372 [GCC_DISP_CC_SLEEP_CLK] = &gcc_disp_cc_sleep_clk.clkr,
2373 [GCC_DISP_CC_XO_CLK] = &gcc_disp_cc_xo_clk.clkr,
2374 [GCC_DISP_GPLL0_CLK] = &gcc_disp_gpll0_clk.clkr,
2375 [GCC_DISP_THROTTLE_AXI_CLK] = &gcc_disp_throttle_axi_clk.clkr,
2376 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
2377 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2378 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2379 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2380 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2381 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2382 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2383 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2384 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
2385 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
2386 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2387 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2388 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2389 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2390 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2391 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2392 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2393 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2394 [GCC_NPU_GPLL0_CLK] = &gcc_npu_gpll0_clk.clkr,
2395 [GCC_NPU_GPLL0_DIV_CLK] = &gcc_npu_gpll0_div_clk.clkr,
2396 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2397 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2398 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2399 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2400 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2401 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2402 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2403 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2404 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2405 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2406 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2407 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2408 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2409 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2410 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2411 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2412 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2413 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2414 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2415 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2416 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2417 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2418 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2419 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2420 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2421 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2422 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2423 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2424 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2425 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2426 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2427 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2428 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2429 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2430 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2431 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2432 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2433 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2434 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2435 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2436 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2437 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2438 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2439 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2440 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2441 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2442 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2443 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2444 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2445 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2446 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2447 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2448 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2449 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2450 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2451 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
2452 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2453 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2454 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2455 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2456 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2457 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2458 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2459 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2460 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2461 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2462 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2463 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2464 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2465 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2466 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2467 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
2468 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2469 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2470 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
2471 [GPLL0] = &gpll0.clkr,
2472 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2473 [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2474 [GPLL6] = &gpll6.clkr,
2475 [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
2476 [GPLL7] = &gpll7.clkr,
2477 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
2478 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
2479 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
2480 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2481 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
2482 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
2483 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
2484 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
2485 [GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_gpu_gpll0_main_div_clk_src.clkr,
2486 [GCC_NPU_PLL0_MAIN_DIV_CLK_SRC] = &gcc_npu_pll0_main_div_clk_src.clkr,
2489 static struct gdsc *gcc_sm6350_gdscs[] = {
2490 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2491 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2492 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2493 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
2496 static const struct qcom_reset_map gcc_sm6350_resets[] = {
2497 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1d000 },
2498 [GCC_QUSB2PHY_SEC_BCR] = { 0x1e000 },
2499 [GCC_SDCC1_BCR] = { 0x4b000 },
2500 [GCC_SDCC2_BCR] = { 0x20000 },
2501 [GCC_UFS_PHY_BCR] = { 0x3a000 },
2502 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
2503 [GCC_USB3_PHY_PRIM_BCR] = { 0x1c000 },
2504 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1c008 },
2507 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2508 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2509 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2510 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2511 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2512 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2513 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2514 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2515 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2516 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2517 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2518 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2519 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2522 static const struct regmap_config gcc_sm6350_regmap_config = {
2526 .max_register = 0xbf030,
2530 static const struct qcom_cc_desc gcc_sm6350_desc = {
2531 .config = &gcc_sm6350_regmap_config,
2532 .clks = gcc_sm6350_clocks,
2533 .num_clks = ARRAY_SIZE(gcc_sm6350_clocks),
2534 .resets = gcc_sm6350_resets,
2535 .num_resets = ARRAY_SIZE(gcc_sm6350_resets),
2536 .gdscs = gcc_sm6350_gdscs,
2537 .num_gdscs = ARRAY_SIZE(gcc_sm6350_gdscs),
2540 static const struct of_device_id gcc_sm6350_match_table[] = {
2541 { .compatible = "qcom,gcc-sm6350" },
2544 MODULE_DEVICE_TABLE(of, gcc_sm6350_match_table);
2546 static int gcc_sm6350_probe(struct platform_device *pdev)
2548 struct regmap *regmap;
2551 regmap = qcom_cc_map(pdev, &gcc_sm6350_desc);
2553 return PTR_ERR(regmap);
2555 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
2556 regmap_update_bits(regmap, 0x4cf00, 0x3, 0x3);
2557 regmap_update_bits(regmap, 0x45f00, 0x3, 0x3);
2559 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2560 ARRAY_SIZE(gcc_dfs_clocks));
2564 return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);;
2567 static struct platform_driver gcc_sm6350_driver = {
2568 .probe = gcc_sm6350_probe,
2570 .name = "gcc-sm6350",
2571 .of_match_table = gcc_sm6350_match_table,
2575 static int __init gcc_sm6350_init(void)
2577 return platform_driver_register(&gcc_sm6350_driver);
2579 core_initcall(gcc_sm6350_init);
2581 static void __exit gcc_sm6350_exit(void)
2583 platform_driver_unregister(&gcc_sm6350_driver);
2585 module_exit(gcc_sm6350_exit);
2587 MODULE_DESCRIPTION("QTI GCC SM6350 Driver");
2588 MODULE_LICENSE("GPL v2");