drivers/clk/qcom/gcc-msm8996.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  26
  27 #include "common.h"
  28 #include "clk-regmap.h"
  29 #include "clk-alpha-pll.h"
  30 #include "clk-rcg.h"
  31 #include "clk-branch.h"
  32 #include "reset.h"
  33 #include "gdsc.h"
  34
  35 enum {
  36         P_XO,
  37         P_GPLL0,
  38         P_GPLL2,
  39         P_GPLL3,
  40         P_GPLL1,
  41         P_GPLL2_EARLY,
  42         P_GPLL0_EARLY_DIV,
  43         P_SLEEP_CLK,
  44         P_GPLL4,
  45         P_AUD_REF_CLK,
  46         P_GPLL1_EARLY_DIV
  47 };
  48
  49 static const struct parent_map gcc_sleep_clk_map[] = {
  50         { P_SLEEP_CLK, 5 }
  51 };
  52
  53 static const char * const gcc_sleep_clk[] = {
  54         "sleep_clk"
  55 };
  56
  57 static const struct parent_map gcc_xo_gpll0_map[] = {
  58         { P_XO, 0 },
  59         { P_GPLL0, 1 }
  60 };
  61
  62 static const char * const gcc_xo_gpll0[] = {
  63         "xo",
  64         "gpll0"
  65 };
  66
  67 static const struct parent_map gcc_xo_sleep_clk_map[] = {
  68         { P_XO, 0 },
  69         { P_SLEEP_CLK, 5 }
  70 };
  71
  72 static const char * const gcc_xo_sleep_clk[] = {
  73         "xo",
  74         "sleep_clk"
  75 };
  76
  77 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
  78         { P_XO, 0 },
  79         { P_GPLL0, 1 },
  80         { P_GPLL0_EARLY_DIV, 6 }
  81 };
  82
  83 static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
  84         "xo",
  85         "gpll0",
  86         "gpll0_early_div"
  87 };
  88
  89 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  90         { P_XO, 0 },
  91         { P_GPLL0, 1 },
  92         { P_GPLL4, 5 }
  93 };
  94
  95 static const char * const gcc_xo_gpll0_gpll4[] = {
  96         "xo",
  97         "gpll0",
  98         "gpll4"
  99 };
 100
 101 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
 102         { P_XO, 0 },
 103         { P_GPLL0, 1 },
 104         { P_AUD_REF_CLK, 2 }
 105 };
 106
 107 static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
 108         "xo",
 109         "gpll0",
 110         "aud_ref_clk"
 111 };
 112
 113 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 114         { P_XO, 0 },
 115         { P_GPLL0, 1 },
 116         { P_SLEEP_CLK, 5 },
 117         { P_GPLL0_EARLY_DIV, 6 }
 118 };
 119
 120 static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
 121         "xo",
 122         "gpll0",
 123         "sleep_clk",
 124         "gpll0_early_div"
 125 };
 126
 127 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 128         { P_XO, 0 },
 129         { P_GPLL0, 1 },
 130         { P_GPLL4, 5 },
 131         { P_GPLL0_EARLY_DIV, 6 }
 132 };
 133
 134 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 135         "xo",
 136         "gpll0",
 137         "gpll4",
 138         "gpll0_early_div"
 139 };
 140
 141 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] = {
 142         { P_XO, 0 },
 143         { P_GPLL0, 1 },
 144         { P_GPLL2, 2 },
 145         { P_GPLL3, 3 },
 146         { P_GPLL0_EARLY_DIV, 6 }
 147 };
 148
 149 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = {
 150         "xo",
 151         "gpll0",
 152         "gpll2",
 153         "gpll3",
 154         "gpll0_early_div"
 155 };
 156
 157 static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
 158         { P_XO, 0 },
 159         { P_GPLL0, 1 },
 160         { P_GPLL1_EARLY_DIV, 3 },
 161         { P_GPLL1, 4 },
 162         { P_GPLL4, 5 },
 163         { P_GPLL0_EARLY_DIV, 6 }
 164 };
 165
 166 static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
 167         "xo",
 168         "gpll0",
 169         "gpll1_early_div",
 170         "gpll1",
 171         "gpll4",
 172         "gpll0_early_div"
 173 };
 174
 175 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
 176         { P_XO, 0 },
 177         { P_GPLL0, 1 },
 178         { P_GPLL2, 2 },
 179         { P_GPLL3, 3 },
 180         { P_GPLL1, 4 },
 181         { P_GPLL2_EARLY, 5 },
 182         { P_GPLL0_EARLY_DIV, 6 }
 183 };
 184
 185 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
 186         "xo",
 187         "gpll0",
 188         "gpll2",
 189         "gpll3",
 190         "gpll1",
 191         "gpll2_early",
 192         "gpll0_early_div"
 193 };
 194
 195 static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = {
 196         { P_XO, 0 },
 197         { P_GPLL0, 1 },
 198         { P_GPLL2, 2 },
 199         { P_GPLL3, 3 },
 200         { P_GPLL1, 4 },
 201         { P_GPLL4, 5 },
 202         { P_GPLL0_EARLY_DIV, 6 }
 203 };
 204
 205 static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {
 206         "xo",
 207         "gpll0",
 208         "gpll2",
 209         "gpll3",
 210         "gpll1",
 211         "gpll4",
 212         "gpll0_early_div"
 213 };
 214
 215 static struct clk_fixed_factor xo = {
 216         .mult = 1,
 217         .div = 1,
 218         .hw.init = &(struct clk_init_data){
 219                 .name = "xo",
 220                 .parent_names = (const char *[]){ "xo_board" },
 221                 .num_parents = 1,
 222                 .ops = &clk_fixed_factor_ops,
 223         },
 224 };
 225
 226 static struct clk_alpha_pll gpll0_early = {
 227         .offset = 0x00000,
 228         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 229         .clkr = {
 230                 .enable_reg = 0x52000,
 231                 .enable_mask = BIT(0),
 232                 .hw.init = &(struct clk_init_data){
 233                         .name = "gpll0_early",
 234                         .parent_names = (const char *[]){ "xo" },
 235                         .num_parents = 1,
 236                         .ops = &clk_alpha_pll_ops,
 237                 },
 238         },
 239 };
 240
 241 static struct clk_fixed_factor gpll0_early_div = {
 242         .mult = 1,
 243         .div = 2,
 244         .hw.init = &(struct clk_init_data){
 245                 .name = "gpll0_early_div",
 246                 .parent_names = (const char *[]){ "gpll0_early" },
 247                 .num_parents = 1,
 248                 .ops = &clk_fixed_factor_ops,
 249         },
 250 };
 251
 252 static struct clk_alpha_pll_postdiv gpll0 = {
 253         .offset = 0x00000,
 254         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 255         .clkr.hw.init = &(struct clk_init_data){
 256                 .name = "gpll0",
 257                 .parent_names = (const char *[]){ "gpll0_early" },
 258                 .num_parents = 1,
 259                 .ops = &clk_alpha_pll_postdiv_ops,
 260         },
 261 };
 262
 263 static struct clk_branch gcc_mmss_gpll0_div_clk = {
 264         .halt_check = BRANCH_HALT_DELAY,
 265         .clkr = {
 266                 .enable_reg = 0x5200c,
 267                 .enable_mask = BIT(0),
 268                 .hw.init = &(struct clk_init_data){
 269                         .name = "gcc_mmss_gpll0_div_clk",
 270                         .parent_names = (const char *[]){ "gpll0" },
 271                         .num_parents = 1,
 272                         .flags = CLK_SET_RATE_PARENT,
 273                         .ops = &clk_branch2_ops,
 274                 },
 275         },
 276 };
 277
 278 static struct clk_branch gcc_mss_gpll0_div_clk = {
 279         .halt_check = BRANCH_HALT_DELAY,
 280         .clkr = {
 281                 .enable_reg = 0x5200c,
 282                 .enable_mask = BIT(2),
 283                 .hw.init = &(struct clk_init_data){
 284                         .name = "gcc_mss_gpll0_div_clk",
 285                         .parent_names = (const char *[]){ "gpll0" },
 286                         .num_parents = 1,
 287                         .flags = CLK_SET_RATE_PARENT,
 288                         .ops = &clk_branch2_ops
 289                 },
 290         },
 291 };
 292
 293 static struct clk_alpha_pll gpll4_early = {
 294         .offset = 0x77000,
 295         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 296         .clkr = {
 297                 .enable_reg = 0x52000,
 298                 .enable_mask = BIT(4),
 299                 .hw.init = &(struct clk_init_data){
 300                         .name = "gpll4_early",
 301                         .parent_names = (const char *[]){ "xo" },
 302                         .num_parents = 1,
 303                         .ops = &clk_alpha_pll_ops,
 304                 },
 305         },
 306 };
 307
 308 static struct clk_alpha_pll_postdiv gpll4 = {
 309         .offset = 0x77000,
 310         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 311         .clkr.hw.init = &(struct clk_init_data){
 312                 .name = "gpll4",
 313                 .parent_names = (const char *[]){ "gpll4_early" },
 314                 .num_parents = 1,
 315                 .ops = &clk_alpha_pll_postdiv_ops,
 316         },
 317 };
 318
 319 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 320         F(19200000, P_XO, 1, 0, 0),
 321         F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
 322         F(100000000, P_GPLL0, 6, 0, 0),
 323         F(150000000, P_GPLL0, 4, 0, 0),
 324         F(200000000, P_GPLL0, 3, 0, 0),
 325         F(240000000, P_GPLL0, 2.5, 0, 0),
 326         { }
 327 };
 328
 329 static struct clk_rcg2 system_noc_clk_src = {
 330         .cmd_rcgr = 0x0401c,
 331         .hid_width = 5,
 332         .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
 333         .freq_tbl = ftbl_system_noc_clk_src,
 334         .clkr.hw.init = &(struct clk_init_data){
 335                 .name = "system_noc_clk_src",
 336                 .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
 337                 .num_parents = 7,
 338                 .ops = &clk_rcg2_ops,
 339         },
 340 };
 341
 342 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
 343         F(19200000, P_XO, 1, 0, 0),
 344         F(37500000, P_GPLL0, 16, 0, 0),
 345         F(75000000, P_GPLL0, 8, 0, 0),
 346         { }
 347 };
 348
 349 static struct clk_rcg2 config_noc_clk_src = {
 350         .cmd_rcgr = 0x0500c,
 351         .hid_width = 5,
 352         .parent_map = gcc_xo_gpll0_map,
 353         .freq_tbl = ftbl_config_noc_clk_src,
 354         .clkr.hw.init = &(struct clk_init_data){
 355                 .name = "config_noc_clk_src",
 356                 .parent_names = gcc_xo_gpll0,
 357                 .num_parents = 2,
 358                 .ops = &clk_rcg2_ops,
 359         },
 360 };
 361
 362 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
 363         F(19200000, P_XO, 1, 0, 0),
 364         F(37500000, P_GPLL0, 16, 0, 0),
 365         F(50000000, P_GPLL0, 12, 0, 0),
 366         F(75000000, P_GPLL0, 8, 0, 0),
 367         F(100000000, P_GPLL0, 6, 0, 0),
 368         { }
 369 };
 370
 371 static struct clk_rcg2 periph_noc_clk_src = {
 372         .cmd_rcgr = 0x06014,
 373         .hid_width = 5,
 374         .parent_map = gcc_xo_gpll0_map,
 375         .freq_tbl = ftbl_periph_noc_clk_src,
 376         .clkr.hw.init = &(struct clk_init_data){
 377                 .name = "periph_noc_clk_src",
 378                 .parent_names = gcc_xo_gpll0,
 379                 .num_parents = 2,
 380                 .ops = &clk_rcg2_ops,
 381         },
 382 };
 383
 384 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
 385         F(19200000, P_XO, 1, 0, 0),
 386         F(120000000, P_GPLL0, 5, 0, 0),
 387         F(150000000, P_GPLL0, 4, 0, 0),
 388         { }
 389 };
 390
 391 static struct clk_rcg2 usb30_master_clk_src = {
 392         .cmd_rcgr = 0x0f014,
 393         .mnd_width = 8,
 394         .hid_width = 5,
 395         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 396         .freq_tbl = ftbl_usb30_master_clk_src,
 397         .clkr.hw.init = &(struct clk_init_data){
 398                 .name = "usb30_master_clk_src",
 399                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 400                 .num_parents = 3,
 401                 .ops = &clk_rcg2_ops,
 402         },
 403 };
 404
 405 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 406         F(19200000, P_XO, 1, 0, 0),
 407         { }
 408 };
 409
 410 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 411         .cmd_rcgr = 0x0f028,
 412         .hid_width = 5,
 413         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 414         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 415         .clkr.hw.init = &(struct clk_init_data){
 416                 .name = "usb30_mock_utmi_clk_src",
 417                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 418                 .num_parents = 3,
 419                 .ops = &clk_rcg2_ops,
 420         },
 421 };
 422
 423 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
 424         F(1200000, P_XO, 16, 0, 0),
 425         { }
 426 };
 427
 428 static struct clk_rcg2 usb3_phy_aux_clk_src = {
 429         .cmd_rcgr = 0x5000c,
 430         .hid_width = 5,
 431         .parent_map = gcc_xo_sleep_clk_map,
 432         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
 433         .clkr.hw.init = &(struct clk_init_data){
 434                 .name = "usb3_phy_aux_clk_src",
 435                 .parent_names = gcc_xo_sleep_clk,
 436                 .num_parents = 2,
 437                 .ops = &clk_rcg2_ops,
 438         },
 439 };
 440
 441 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
 442         F(120000000, P_GPLL0, 5, 0, 0),
 443         { }
 444 };
 445
 446 static struct clk_rcg2 usb20_master_clk_src = {
 447         .cmd_rcgr = 0x12010,
 448         .mnd_width = 8,
 449         .hid_width = 5,
 450         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 451         .freq_tbl = ftbl_usb20_master_clk_src,
 452         .clkr.hw.init = &(struct clk_init_data){
 453                 .name = "usb20_master_clk_src",
 454                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 455                 .num_parents = 3,
 456                 .ops = &clk_rcg2_ops,
 457         },
 458 };
 459
 460 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 461         .cmd_rcgr = 0x12024,
 462         .hid_width = 5,
 463         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 464         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 465         .clkr.hw.init = &(struct clk_init_data){
 466                 .name = "usb20_mock_utmi_clk_src",
 467                 .parent_names = gcc_xo_gpll0_gpll0_early_div,
 468                 .num_parents = 3,
 469                 .ops = &clk_rcg2_ops,
 470         },
 471 };
 472
 473 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 474         F(144000, P_XO, 16, 3, 25),
 475         F(400000, P_XO, 12, 1, 4),
 476         F(20000000, P_GPLL0, 15, 1, 2),
 477         F(25000000, P_GPLL0, 12, 1, 2),
 478         F(50000000, P_GPLL0, 12, 0, 0),
 479         F(96000000, P_GPLL4, 4, 0, 0),
 480         F(192000000, P_GPLL4, 2, 0, 0),
 481         F(384000000, P_GPLL4, 1, 0, 0),
 482         { }
 483 };
 484
 485 static struct clk_rcg2 sdcc1_apps_clk_src = {
 486         .cmd_rcgr = 0x13010,
 487         .mnd_width = 8,
 488         .hid_width = 5,
 489         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 490         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 491         .clkr.hw.init = &(struct clk_init_data){
 492                 .name = "sdcc1_apps_clk_src",
 493                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 494                 .num_parents = 4,
 495                 .ops = &clk_rcg2_floor_ops,
 496         },
 497 };
 498
 499 static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
 500         F(19200000, P_XO, 1, 0, 0),
 501         F(150000000, P_GPLL0, 4, 0, 0),
 502         F(300000000, P_GPLL0, 2, 0, 0),
 503         { }
 504 };
 505
 506 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 507         .cmd_rcgr = 0x13024,
 508         .hid_width = 5,
 509         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 510         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 511         .clkr.hw.init = &(struct clk_init_data){
 512                 .name = "sdcc1_ice_core_clk_src",
 513                 .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 514                 .num_parents = 4,
 515                 .ops = &clk_rcg2_ops,
 516         },
 517 };
 518
 519 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
 520         F(144000, P_XO, 16, 3, 25),
 521         F(400000, P_XO, 12, 1, 4),
 522         F(20000000, P_GPLL0, 15, 1, 2),
 523         F(25000000, P_GPLL0, 12, 1, 2),
 524         F(50000000, P_GPLL0, 12, 0, 0),
 525         F(100000000, P_GPLL0, 6, 0, 0),
 526         F(200000000, P_GPLL0, 3, 0, 0),
 527         { }
 528 };
 529
 530 static struct clk_rcg2 sdcc2_apps_clk_src = {
 531         .cmd_rcgr = 0x14010,
 532         .mnd_width = 8,
 533         .hid_width = 5,
 534         .parent_map = gcc_xo_gpll0_gpll4_map,
 535         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 536         .clkr.hw.init = &(struct clk_init_data){
 537                 .name = "sdcc2_apps_clk_src",
 538                 .parent_names = gcc_xo_gpll0_gpll4,
 539                 .num_parents = 3,
 540                 .ops = &clk_rcg2_floor_ops,
 541         },
 542 };
 543
 544 static struct clk_rcg2 sdcc3_apps_clk_src = {
 545         .cmd_rcgr = 0x15010,
 546         .mnd_width = 8,
 547         .hid_width = 5,
 548         .parent_map = gcc_xo_gpll0_gpll4_map,
 549         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 550         .clkr.hw.init = &(struct clk_init_data){
 551                 .name = "sdcc3_apps_clk_src",
 552                 .parent_names = gcc_xo_gpll0_gpll4,
 553                 .num_parents = 3,
 554                 .ops = &clk_rcg2_floor_ops,
 555         },
 556 };
 557
 558 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
 559         F(144000, P_XO, 16, 3, 25),
 560         F(400000, P_XO, 12, 1, 4),
 561         F(20000000, P_GPLL0, 15, 1, 2),
 562         F(25000000, P_GPLL0, 12, 1, 2),
 563         F(50000000, P_GPLL0, 12, 0, 0),
 564         F(100000000, P_GPLL0, 6, 0, 0),
 565         { }
 566 };
 567
 568 static struct clk_rcg2 sdcc4_apps_clk_src = {
 569         .cmd_rcgr = 0x16010,
 570         .mnd_width = 8,
 571         .hid_width = 5,
 572         .parent_map = gcc_xo_gpll0_map,
 573         .freq_tbl = ftbl_sdcc4_apps_clk_src,
 574         .clkr.hw.init = &(struct clk_init_data){
 575                 .name = "sdcc4_apps_clk_src",
 576                 .parent_names = gcc_xo_gpll0,
 577                 .num_parents = 2,
 578                 .ops = &clk_rcg2_floor_ops,
 579         },
 580 };
 581
 582 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 583         F(960000, P_XO, 10, 1, 2),
 584         F(4800000, P_XO, 4, 0, 0),
 585         F(9600000, P_XO, 2, 0, 0),
 586         F(15000000, P_GPLL0, 10, 1, 4),
 587         F(19200000, P_XO, 1, 0, 0),
 588         F(25000000, P_GPLL0, 12, 1, 2),
 589         F(50000000, P_GPLL0, 12, 0, 0),
 590         { }
 591 };
 592
 593 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 594         .cmd_rcgr = 0x1900c,
 595         .mnd_width = 8,
 596         .hid_width = 5,
 597         .parent_map = gcc_xo_gpll0_map,
 598         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 599         .clkr.hw.init = &(struct clk_init_data){
 600                 .name = "blsp1_qup1_spi_apps_clk_src",
 601                 .parent_names = gcc_xo_gpll0,
 602                 .num_parents = 2,
 603                 .ops = &clk_rcg2_ops,
 604         },
 605 };
 606
 607 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 608         F(19200000, P_XO, 1, 0, 0),
 609         F(50000000, P_GPLL0, 12, 0, 0),
 610         { }
 611 };
 612
 613 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 614         .cmd_rcgr = 0x19020,
 615         .hid_width = 5,
 616         .parent_map = gcc_xo_gpll0_map,
 617         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 618         .clkr.hw.init = &(struct clk_init_data){
 619                 .name = "blsp1_qup1_i2c_apps_clk_src",
 620                 .parent_names = gcc_xo_gpll0,
 621                 .num_parents = 2,
 622                 .ops = &clk_rcg2_ops,
 623         },
 624 };
 625
 626 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 627         F(3686400, P_GPLL0, 1, 96, 15625),
 628         F(7372800, P_GPLL0, 1, 192, 15625),
 629         F(14745600, P_GPLL0, 1, 384, 15625),
 630         F(16000000, P_GPLL0, 5, 2, 15),
 631         F(19200000, P_XO, 1, 0, 0),
 632         F(24000000, P_GPLL0, 5, 1, 5),
 633         F(32000000, P_GPLL0, 1, 4, 75),
 634         F(40000000, P_GPLL0, 15, 0, 0),
 635         F(46400000, P_GPLL0, 1, 29, 375),
 636         F(48000000, P_GPLL0, 12.5, 0, 0),
 637         F(51200000, P_GPLL0, 1, 32, 375),
 638         F(56000000, P_GPLL0, 1, 7, 75),
 639         F(58982400, P_GPLL0, 1, 1536, 15625),
 640         F(60000000, P_GPLL0, 10, 0, 0),
 641         F(63157895, P_GPLL0, 9.5, 0, 0),
 642         { }
 643 };
 644
 645 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 646         .cmd_rcgr = 0x1a00c,
 647         .mnd_width = 16,
 648         .hid_width = 5,
 649         .parent_map = gcc_xo_gpll0_map,
 650         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 651         .clkr.hw.init = &(struct clk_init_data){
 652                 .name = "blsp1_uart1_apps_clk_src",
 653                 .parent_names = gcc_xo_gpll0,
 654                 .num_parents = 2,
 655                 .ops = &clk_rcg2_ops,
 656         },
 657 };
 658
 659 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 660         .cmd_rcgr = 0x1b00c,
 661         .mnd_width = 8,
 662         .hid_width = 5,
 663         .parent_map = gcc_xo_gpll0_map,
 664         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 665         .clkr.hw.init = &(struct clk_init_data){
 666                 .name = "blsp1_qup2_spi_apps_clk_src",
 667                 .parent_names = gcc_xo_gpll0,
 668                 .num_parents = 2,
 669                 .ops = &clk_rcg2_ops,
 670         },
 671 };
 672
 673 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 674         .cmd_rcgr = 0x1b020,
 675         .hid_width = 5,
 676         .parent_map = gcc_xo_gpll0_map,
 677         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 678         .clkr.hw.init = &(struct clk_init_data){
 679                 .name = "blsp1_qup2_i2c_apps_clk_src",
 680                 .parent_names = gcc_xo_gpll0,
 681                 .num_parents = 2,
 682                 .ops = &clk_rcg2_ops,
 683         },
 684 };
 685
 686 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 687         .cmd_rcgr = 0x1c00c,
 688         .mnd_width = 16,
 689         .hid_width = 5,
 690         .parent_map = gcc_xo_gpll0_map,
 691         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "blsp1_uart2_apps_clk_src",
 694                 .parent_names = gcc_xo_gpll0,
 695                 .num_parents = 2,
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 701         .cmd_rcgr = 0x1d00c,
 702         .mnd_width = 8,
 703         .hid_width = 5,
 704         .parent_map = gcc_xo_gpll0_map,
 705         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 706         .clkr.hw.init = &(struct clk_init_data){
 707                 .name = "blsp1_qup3_spi_apps_clk_src",
 708                 .parent_names = gcc_xo_gpll0,
 709                 .num_parents = 2,
 710                 .ops = &clk_rcg2_ops,
 711         },
 712 };
 713
 714 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 715         .cmd_rcgr = 0x1d020,
 716         .hid_width = 5,
 717         .parent_map = gcc_xo_gpll0_map,
 718         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 719         .clkr.hw.init = &(struct clk_init_data){
 720                 .name = "blsp1_qup3_i2c_apps_clk_src",
 721                 .parent_names = gcc_xo_gpll0,
 722                 .num_parents = 2,
 723                 .ops = &clk_rcg2_ops,
 724         },
 725 };
 726
 727 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 728         .cmd_rcgr = 0x1e00c,
 729         .mnd_width = 16,
 730         .hid_width = 5,
 731         .parent_map = gcc_xo_gpll0_map,
 732         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 733         .clkr.hw.init = &(struct clk_init_data){
 734                 .name = "blsp1_uart3_apps_clk_src",
 735                 .parent_names = gcc_xo_gpll0,
 736                 .num_parents = 2,
 737                 .ops = &clk_rcg2_ops,
 738         },
 739 };
 740
 741 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 742         .cmd_rcgr = 0x1f00c,
 743         .mnd_width = 8,
 744         .hid_width = 5,
 745         .parent_map = gcc_xo_gpll0_map,
 746         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 747         .clkr.hw.init = &(struct clk_init_data){
 748                 .name = "blsp1_qup4_spi_apps_clk_src",
 749                 .parent_names = gcc_xo_gpll0,
 750                 .num_parents = 2,
 751                 .ops = &clk_rcg2_ops,
 752         },
 753 };
 754
 755 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 756         .cmd_rcgr = 0x1f020,
 757         .hid_width = 5,
 758         .parent_map = gcc_xo_gpll0_map,
 759         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 760         .clkr.hw.init = &(struct clk_init_data){
 761                 .name = "blsp1_qup4_i2c_apps_clk_src",
 762                 .parent_names = gcc_xo_gpll0,
 763                 .num_parents = 2,
 764                 .ops = &clk_rcg2_ops,
 765         },
 766 };
 767
 768 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 769         .cmd_rcgr = 0x2000c,
 770         .mnd_width = 16,
 771         .hid_width = 5,
 772         .parent_map = gcc_xo_gpll0_map,
 773         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 774         .clkr.hw.init = &(struct clk_init_data){
 775                 .name = "blsp1_uart4_apps_clk_src",
 776                 .parent_names = gcc_xo_gpll0,
 777                 .num_parents = 2,
 778                 .ops = &clk_rcg2_ops,
 779         },
 780 };
 781
 782 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 783         .cmd_rcgr = 0x2100c,
 784         .mnd_width = 8,
 785         .hid_width = 5,
 786         .parent_map = gcc_xo_gpll0_map,
 787         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 788         .clkr.hw.init = &(struct clk_init_data){
 789                 .name = "blsp1_qup5_spi_apps_clk_src",
 790                 .parent_names = gcc_xo_gpll0,
 791                 .num_parents = 2,
 792                 .ops = &clk_rcg2_ops,
 793         },
 794 };
 795
 796 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 797         .cmd_rcgr = 0x21020,
 798         .hid_width = 5,
 799         .parent_map = gcc_xo_gpll0_map,
 800         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "blsp1_qup5_i2c_apps_clk_src",
 803                 .parent_names = gcc_xo_gpll0,
 804                 .num_parents = 2,
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 810         .cmd_rcgr = 0x2200c,
 811         .mnd_width = 16,
 812         .hid_width = 5,
 813         .parent_map = gcc_xo_gpll0_map,
 814         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 815         .clkr.hw.init = &(struct clk_init_data){
 816                 .name = "blsp1_uart5_apps_clk_src",
 817                 .parent_names = gcc_xo_gpll0,
 818                 .num_parents = 2,
 819                 .ops = &clk_rcg2_ops,
 820         },
 821 };
 822
 823 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 824         .cmd_rcgr = 0x2300c,
 825         .mnd_width = 8,
 826         .hid_width = 5,
 827         .parent_map = gcc_xo_gpll0_map,
 828         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 829         .clkr.hw.init = &(struct clk_init_data){
 830                 .name = "blsp1_qup6_spi_apps_clk_src",
 831                 .parent_names = gcc_xo_gpll0,
 832                 .num_parents = 2,
 833                 .ops = &clk_rcg2_ops,
 834         },
 835 };
 836
 837 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 838         .cmd_rcgr = 0x23020,
 839         .hid_width = 5,
 840         .parent_map = gcc_xo_gpll0_map,
 841         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 842         .clkr.hw.init = &(struct clk_init_data){
 843                 .name = "blsp1_qup6_i2c_apps_clk_src",
 844                 .parent_names = gcc_xo_gpll0,
 845                 .num_parents = 2,
 846                 .ops = &clk_rcg2_ops,
 847         },
 848 };
 849
 850 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 851         .cmd_rcgr = 0x2400c,
 852         .mnd_width = 16,
 853         .hid_width = 5,
 854         .parent_map = gcc_xo_gpll0_map,
 855         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 856         .clkr.hw.init = &(struct clk_init_data){
 857                 .name = "blsp1_uart6_apps_clk_src",
 858                 .parent_names = gcc_xo_gpll0,
 859                 .num_parents = 2,
 860                 .ops = &clk_rcg2_ops,
 861         },
 862 };
 863
 864 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 865         .cmd_rcgr = 0x2600c,
 866         .mnd_width = 8,
 867         .hid_width = 5,
 868         .parent_map = gcc_xo_gpll0_map,
 869         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 870         .clkr.hw.init = &(struct clk_init_data){
 871                 .name = "blsp2_qup1_spi_apps_clk_src",
 872                 .parent_names = gcc_xo_gpll0,
 873                 .num_parents = 2,
 874                 .ops = &clk_rcg2_ops,
 875         },
 876 };
 877
 878 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 879         .cmd_rcgr = 0x26020,
 880         .hid_width = 5,
 881         .parent_map = gcc_xo_gpll0_map,
 882         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 883         .clkr.hw.init = &(struct clk_init_data){
 884                 .name = "blsp2_qup1_i2c_apps_clk_src",
 885                 .parent_names = gcc_xo_gpll0,
 886                 .num_parents = 2,
 887                 .ops = &clk_rcg2_ops,
 888         },
 889 };
 890
 891 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 892         .cmd_rcgr = 0x2700c,
 893         .mnd_width = 16,
 894         .hid_width = 5,
 895         .parent_map = gcc_xo_gpll0_map,
 896         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 897         .clkr.hw.init = &(struct clk_init_data){
 898                 .name = "blsp2_uart1_apps_clk_src",
 899                 .parent_names = gcc_xo_gpll0,
 900                 .num_parents = 2,
 901                 .ops = &clk_rcg2_ops,
 902         },
 903 };
 904
 905 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 906         .cmd_rcgr = 0x2800c,
 907         .mnd_width = 8,
 908         .hid_width = 5,
 909         .parent_map = gcc_xo_gpll0_map,
 910         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 911         .clkr.hw.init = &(struct clk_init_data){
 912                 .name = "blsp2_qup2_spi_apps_clk_src",
 913                 .parent_names = gcc_xo_gpll0,
 914                 .num_parents = 2,
 915                 .ops = &clk_rcg2_ops,
 916         },
 917 };
 918
 919 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 920         .cmd_rcgr = 0x28020,
 921         .hid_width = 5,
 922         .parent_map = gcc_xo_gpll0_map,
 923         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 924         .clkr.hw.init = &(struct clk_init_data){
 925                 .name = "blsp2_qup2_i2c_apps_clk_src",
 926                 .parent_names = gcc_xo_gpll0,
 927                 .num_parents = 2,
 928                 .ops = &clk_rcg2_ops,
 929         },
 930 };
 931
 932 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 933         .cmd_rcgr = 0x2900c,
 934         .mnd_width = 16,
 935         .hid_width = 5,
 936         .parent_map = gcc_xo_gpll0_map,
 937         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 938         .clkr.hw.init = &(struct clk_init_data){
 939                 .name = "blsp2_uart2_apps_clk_src",
 940                 .parent_names = gcc_xo_gpll0,
 941                 .num_parents = 2,
 942                 .ops = &clk_rcg2_ops,
 943         },
 944 };
 945
 946 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 947         .cmd_rcgr = 0x2a00c,
 948         .mnd_width = 8,
 949         .hid_width = 5,
 950         .parent_map = gcc_xo_gpll0_map,
 951         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 952         .clkr.hw.init = &(struct clk_init_data){
 953                 .name = "blsp2_qup3_spi_apps_clk_src",
 954                 .parent_names = gcc_xo_gpll0,
 955                 .num_parents = 2,
 956                 .ops = &clk_rcg2_ops,
 957         },
 958 };
 959
 960 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 961         .cmd_rcgr = 0x2a020,
 962         .hid_width = 5,
 963         .parent_map = gcc_xo_gpll0_map,
 964         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 965         .clkr.hw.init = &(struct clk_init_data){
 966                 .name = "blsp2_qup3_i2c_apps_clk_src",
 967                 .parent_names = gcc_xo_gpll0,
 968                 .num_parents = 2,
 969                 .ops = &clk_rcg2_ops,
 970         },
 971 };
 972
 973 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 974         .cmd_rcgr = 0x2b00c,
 975         .mnd_width = 16,
 976         .hid_width = 5,
 977         .parent_map = gcc_xo_gpll0_map,
 978         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 979         .clkr.hw.init = &(struct clk_init_data){
 980                 .name = "blsp2_uart3_apps_clk_src",
 981                 .parent_names = gcc_xo_gpll0,
 982                 .num_parents = 2,
 983                 .ops = &clk_rcg2_ops,
 984         },
 985 };
 986
 987 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 988         .cmd_rcgr = 0x2c00c,
 989         .mnd_width = 8,
 990         .hid_width = 5,
 991         .parent_map = gcc_xo_gpll0_map,
 992         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 993         .clkr.hw.init = &(struct clk_init_data){
 994                 .name = "blsp2_qup4_spi_apps_clk_src",
 995                 .parent_names = gcc_xo_gpll0,
 996                 .num_parents = 2,
 997                 .ops = &clk_rcg2_ops,
 998         },
 999 };
1000
1001 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
1002         .cmd_rcgr = 0x2c020,
1003         .hid_width = 5,
1004         .parent_map = gcc_xo_gpll0_map,
1005         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1006         .clkr.hw.init = &(struct clk_init_data){
1007                 .name = "blsp2_qup4_i2c_apps_clk_src",
1008                 .parent_names = gcc_xo_gpll0,
1009                 .num_parents = 2,
1010                 .ops = &clk_rcg2_ops,
1011         },
1012 };
1013
1014 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
1015         .cmd_rcgr = 0x2d00c,
1016         .mnd_width = 16,
1017         .hid_width = 5,
1018         .parent_map = gcc_xo_gpll0_map,
1019         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1020         .clkr.hw.init = &(struct clk_init_data){
1021                 .name = "blsp2_uart4_apps_clk_src",
1022                 .parent_names = gcc_xo_gpll0,
1023                 .num_parents = 2,
1024                 .ops = &clk_rcg2_ops,
1025         },
1026 };
1027
1028 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
1029         .cmd_rcgr = 0x2e00c,
1030         .mnd_width = 8,
1031         .hid_width = 5,
1032         .parent_map = gcc_xo_gpll0_map,
1033         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1034         .clkr.hw.init = &(struct clk_init_data){
1035                 .name = "blsp2_qup5_spi_apps_clk_src",
1036                 .parent_names = gcc_xo_gpll0,
1037                 .num_parents = 2,
1038                 .ops = &clk_rcg2_ops,
1039         },
1040 };
1041
1042 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
1043         .cmd_rcgr = 0x2e020,
1044         .hid_width = 5,
1045         .parent_map = gcc_xo_gpll0_map,
1046         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1047         .clkr.hw.init = &(struct clk_init_data){
1048                 .name = "blsp2_qup5_i2c_apps_clk_src",
1049                 .parent_names = gcc_xo_gpll0,
1050                 .num_parents = 2,
1051                 .ops = &clk_rcg2_ops,
1052         },
1053 };
1054
1055 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
1056         .cmd_rcgr = 0x2f00c,
1057         .mnd_width = 16,
1058         .hid_width = 5,
1059         .parent_map = gcc_xo_gpll0_map,
1060         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1061         .clkr.hw.init = &(struct clk_init_data){
1062                 .name = "blsp2_uart5_apps_clk_src",
1063                 .parent_names = gcc_xo_gpll0,
1064                 .num_parents = 2,
1065                 .ops = &clk_rcg2_ops,
1066         },
1067 };
1068
1069 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
1070         .cmd_rcgr = 0x3000c,
1071         .mnd_width = 8,
1072         .hid_width = 5,
1073         .parent_map = gcc_xo_gpll0_map,
1074         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1075         .clkr.hw.init = &(struct clk_init_data){
1076                 .name = "blsp2_qup6_spi_apps_clk_src",
1077                 .parent_names = gcc_xo_gpll0,
1078                 .num_parents = 2,
1079                 .ops = &clk_rcg2_ops,
1080         },
1081 };
1082
1083 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1084         .cmd_rcgr = 0x30020,
1085         .hid_width = 5,
1086         .parent_map = gcc_xo_gpll0_map,
1087         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1088         .clkr.hw.init = &(struct clk_init_data){
1089                 .name = "blsp2_qup6_i2c_apps_clk_src",
1090                 .parent_names = gcc_xo_gpll0,
1091                 .num_parents = 2,
1092                 .ops = &clk_rcg2_ops,
1093         },
1094 };
1095
1096 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1097         .cmd_rcgr = 0x3100c,
1098         .mnd_width = 16,
1099         .hid_width = 5,
1100         .parent_map = gcc_xo_gpll0_map,
1101         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1102         .clkr.hw.init = &(struct clk_init_data){
1103                 .name = "blsp2_uart6_apps_clk_src",
1104                 .parent_names = gcc_xo_gpll0,
1105                 .num_parents = 2,
1106                 .ops = &clk_rcg2_ops,
1107         },
1108 };
1109
1110 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1111         F(60000000, P_GPLL0, 10, 0, 0),
1112         { }
1113 };
1114
1115 static struct clk_rcg2 pdm2_clk_src = {
1116         .cmd_rcgr = 0x33010,
1117         .hid_width = 5,
1118         .parent_map = gcc_xo_gpll0_map,
1119         .freq_tbl = ftbl_pdm2_clk_src,
1120         .clkr.hw.init = &(struct clk_init_data){
1121                 .name = "pdm2_clk_src",
1122                 .parent_names = gcc_xo_gpll0,
1123                 .num_parents = 2,
1124                 .ops = &clk_rcg2_ops,
1125         },
1126 };
1127
1128 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1129         F(105495, P_XO, 1, 1, 182),
1130         { }
1131 };
1132
1133 static struct clk_rcg2 tsif_ref_clk_src = {
1134         .cmd_rcgr = 0x36010,
1135         .mnd_width = 8,
1136         .hid_width = 5,
1137         .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1138         .freq_tbl = ftbl_tsif_ref_clk_src,
1139         .clkr.hw.init = &(struct clk_init_data){
1140                 .name = "tsif_ref_clk_src",
1141                 .parent_names = gcc_xo_gpll0_aud_ref_clk,
1142                 .num_parents = 3,
1143                 .ops = &clk_rcg2_ops,
1144         },
1145 };
1146
1147 static struct clk_rcg2 gcc_sleep_clk_src = {
1148         .cmd_rcgr = 0x43014,
1149         .hid_width = 5,
1150         .parent_map = gcc_sleep_clk_map,
1151         .clkr.hw.init = &(struct clk_init_data){
1152                 .name = "gcc_sleep_clk_src",
1153                 .parent_names = gcc_sleep_clk,
1154                 .num_parents = 1,
1155                 .ops = &clk_rcg2_ops,
1156         },
1157 };
1158
1159 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1160         .cmd_rcgr = 0x48040,
1161         .hid_width = 5,
1162         .parent_map = gcc_xo_gpll0_map,
1163         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1164         .clkr.hw.init = &(struct clk_init_data){
1165                 .name = "hmss_rbcpr_clk_src",
1166                 .parent_names = gcc_xo_gpll0,
1167                 .num_parents = 2,
1168                 .ops = &clk_rcg2_ops,
1169         },
1170 };
1171
1172 static struct clk_rcg2 hmss_gpll0_clk_src = {
1173         .cmd_rcgr = 0x48058,
1174         .hid_width = 5,
1175         .parent_map = gcc_xo_gpll0_map,
1176         .clkr.hw.init = &(struct clk_init_data){
1177                 .name = "hmss_gpll0_clk_src",
1178                 .parent_names = gcc_xo_gpll0,
1179                 .num_parents = 2,
1180                 .ops = &clk_rcg2_ops,
1181         },
1182 };
1183
1184 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1185         F(19200000, P_XO, 1, 0, 0),
1186         F(100000000, P_GPLL0, 6, 0, 0),
1187         F(200000000, P_GPLL0, 3, 0, 0),
1188         { }
1189 };
1190
1191 static struct clk_rcg2 gp1_clk_src = {
1192         .cmd_rcgr = 0x64004,
1193         .mnd_width = 8,
1194         .hid_width = 5,
1195         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1196         .freq_tbl = ftbl_gp1_clk_src,
1197         .clkr.hw.init = &(struct clk_init_data){
1198                 .name = "gp1_clk_src",
1199                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1200                 .num_parents = 4,
1201                 .ops = &clk_rcg2_ops,
1202         },
1203 };
1204
1205 static struct clk_rcg2 gp2_clk_src = {
1206         .cmd_rcgr = 0x65004,
1207         .mnd_width = 8,
1208         .hid_width = 5,
1209         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1210         .freq_tbl = ftbl_gp1_clk_src,
1211         .clkr.hw.init = &(struct clk_init_data){
1212                 .name = "gp2_clk_src",
1213                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1214                 .num_parents = 4,
1215                 .ops = &clk_rcg2_ops,
1216         },
1217 };
1218
1219 static struct clk_rcg2 gp3_clk_src = {
1220         .cmd_rcgr = 0x66004,
1221         .mnd_width = 8,
1222         .hid_width = 5,
1223         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1224         .freq_tbl = ftbl_gp1_clk_src,
1225         .clkr.hw.init = &(struct clk_init_data){
1226                 .name = "gp3_clk_src",
1227                 .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1228                 .num_parents = 4,
1229                 .ops = &clk_rcg2_ops,
1230         },
1231 };
1232
1233 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1234         F(1010526, P_XO, 1, 1, 19),
1235         { }
1236 };
1237
1238 static struct clk_rcg2 pcie_aux_clk_src = {
1239         .cmd_rcgr = 0x6c000,
1240         .mnd_width = 16,
1241         .hid_width = 5,
1242         .parent_map = gcc_xo_sleep_clk_map,
1243         .freq_tbl = ftbl_pcie_aux_clk_src,
1244         .clkr.hw.init = &(struct clk_init_data){
1245                 .name = "pcie_aux_clk_src",
1246                 .parent_names = gcc_xo_sleep_clk,
1247                 .num_parents = 2,
1248                 .ops = &clk_rcg2_ops,
1249         },
1250 };
1251
1252 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1253         F(100000000, P_GPLL0, 6, 0, 0),
1254         F(200000000, P_GPLL0, 3, 0, 0),
1255         F(240000000, P_GPLL0, 2.5, 0, 0),
1256         { }
1257 };
1258
1259 static struct clk_rcg2 ufs_axi_clk_src = {
1260         .cmd_rcgr = 0x75024,
1261         .mnd_width = 8,
1262         .hid_width = 5,
1263         .parent_map = gcc_xo_gpll0_map,
1264         .freq_tbl = ftbl_ufs_axi_clk_src,
1265         .clkr.hw.init = &(struct clk_init_data){
1266                 .name = "ufs_axi_clk_src",
1267                 .parent_names = gcc_xo_gpll0,
1268                 .num_parents = 2,
1269                 .ops = &clk_rcg2_ops,
1270         },
1271 };
1272
1273 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1274         F(19200000, P_XO, 1, 0, 0),
1275         F(150000000, P_GPLL0, 4, 0, 0),
1276         F(300000000, P_GPLL0, 2, 0, 0),
1277         { }
1278 };
1279
1280 static struct clk_rcg2 ufs_ice_core_clk_src = {
1281         .cmd_rcgr = 0x76014,
1282         .hid_width = 5,
1283         .parent_map = gcc_xo_gpll0_map,
1284         .freq_tbl = ftbl_ufs_ice_core_clk_src,
1285         .clkr.hw.init = &(struct clk_init_data){
1286                 .name = "ufs_ice_core_clk_src",
1287                 .parent_names = gcc_xo_gpll0,
1288                 .num_parents = 2,
1289                 .ops = &clk_rcg2_ops,
1290         },
1291 };
1292
1293 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1294         F(75000000, P_GPLL0, 8, 0, 0),
1295         F(150000000, P_GPLL0, 4, 0, 0),
1296         F(256000000, P_GPLL4, 1.5, 0, 0),
1297         F(300000000, P_GPLL0, 2, 0, 0),
1298         { }
1299 };
1300
1301 static struct clk_rcg2 qspi_ser_clk_src = {
1302         .cmd_rcgr = 0x8b00c,
1303         .hid_width = 5,
1304         .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
1305         .freq_tbl = ftbl_qspi_ser_clk_src,
1306         .clkr.hw.init = &(struct clk_init_data){
1307                 .name = "qspi_ser_clk_src",
1308                 .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
1309                 .num_parents = 6,
1310                 .ops = &clk_rcg2_ops,
1311         },
1312 };
1313
1314 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1315         .halt_reg = 0x0f03c,
1316         .clkr = {
1317                 .enable_reg = 0x0f03c,
1318                 .enable_mask = BIT(0),
1319                 .hw.init = &(struct clk_init_data){
1320                         .name = "gcc_sys_noc_usb3_axi_clk",
1321                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1322                         .num_parents = 1,
1323                         .flags = CLK_SET_RATE_PARENT,
1324                         .ops = &clk_branch2_ops,
1325                 },
1326         },
1327 };
1328
1329 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1330         .halt_reg = 0x75038,
1331         .clkr = {
1332                 .enable_reg = 0x75038,
1333                 .enable_mask = BIT(0),
1334                 .hw.init = &(struct clk_init_data){
1335                         .name = "gcc_sys_noc_ufs_axi_clk",
1336                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
1337                         .num_parents = 1,
1338                         .flags = CLK_SET_RATE_PARENT,
1339                         .ops = &clk_branch2_ops,
1340                 },
1341         },
1342 };
1343
1344 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1345         .halt_reg = 0x6010,
1346         .clkr = {
1347                 .enable_reg = 0x6010,
1348                 .enable_mask = BIT(0),
1349                 .hw.init = &(struct clk_init_data){
1350                         .name = "gcc_periph_noc_usb20_ahb_clk",
1351                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1352                         .num_parents = 1,
1353                         .flags = CLK_SET_RATE_PARENT,
1354                         .ops = &clk_branch2_ops,
1355                 },
1356         },
1357 };
1358
1359 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1360         .halt_reg = 0x9008,
1361         .clkr = {
1362                 .enable_reg = 0x9008,
1363                 .enable_mask = BIT(0),
1364                 .hw.init = &(struct clk_init_data){
1365                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1366                         .parent_names = (const char *[]){ "config_noc_clk_src" },
1367                         .num_parents = 1,
1368                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1375         .halt_reg = 0x9010,
1376         .clkr = {
1377                 .enable_reg = 0x9010,
1378                 .enable_mask = BIT(0),
1379                 .hw.init = &(struct clk_init_data){
1380                         .name = "gcc_mmss_bimc_gfx_clk",
1381                         .flags = CLK_SET_RATE_PARENT,
1382                         .ops = &clk_branch2_ops,
1383                 },
1384         },
1385 };
1386
1387 static struct clk_branch gcc_usb30_master_clk = {
1388         .halt_reg = 0x0f008,
1389         .clkr = {
1390                 .enable_reg = 0x0f008,
1391                 .enable_mask = BIT(0),
1392                 .hw.init = &(struct clk_init_data){
1393                         .name = "gcc_usb30_master_clk",
1394                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
1395                         .num_parents = 1,
1396                         .flags = CLK_SET_RATE_PARENT,
1397                         .ops = &clk_branch2_ops,
1398                 },
1399         },
1400 };
1401
1402 static struct clk_branch gcc_usb30_sleep_clk = {
1403         .halt_reg = 0x0f00c,
1404         .clkr = {
1405                 .enable_reg = 0x0f00c,
1406                 .enable_mask = BIT(0),
1407                 .hw.init = &(struct clk_init_data){
1408                         .name = "gcc_usb30_sleep_clk",
1409                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1410                         .num_parents = 1,
1411                         .flags = CLK_SET_RATE_PARENT,
1412                         .ops = &clk_branch2_ops,
1413                 },
1414         },
1415 };
1416
1417 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1418         .halt_reg = 0x0f010,
1419         .clkr = {
1420                 .enable_reg = 0x0f010,
1421                 .enable_mask = BIT(0),
1422                 .hw.init = &(struct clk_init_data){
1423                         .name = "gcc_usb30_mock_utmi_clk",
1424                         .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
1425                         .num_parents = 1,
1426                         .flags = CLK_SET_RATE_PARENT,
1427                         .ops = &clk_branch2_ops,
1428                 },
1429         },
1430 };
1431
1432 static struct clk_branch gcc_usb3_phy_aux_clk = {
1433         .halt_reg = 0x50000,
1434         .clkr = {
1435                 .enable_reg = 0x50000,
1436                 .enable_mask = BIT(0),
1437                 .hw.init = &(struct clk_init_data){
1438                         .name = "gcc_usb3_phy_aux_clk",
1439                         .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
1440                         .num_parents = 1,
1441                         .flags = CLK_SET_RATE_PARENT,
1442                         .ops = &clk_branch2_ops,
1443                 },
1444         },
1445 };
1446
1447 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1448         .halt_reg = 0x50004,
1449         .halt_check = BRANCH_HALT_SKIP,
1450         .clkr = {
1451                 .enable_reg = 0x50004,
1452                 .enable_mask = BIT(0),
1453                 .hw.init = &(struct clk_init_data){
1454                         .name = "gcc_usb3_phy_pipe_clk",
1455                         .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
1456                         .num_parents = 1,
1457                         .flags = CLK_SET_RATE_PARENT,
1458                         .ops = &clk_branch2_ops,
1459                 },
1460         },
1461 };
1462
1463 static struct clk_branch gcc_usb20_master_clk = {
1464         .halt_reg = 0x12004,
1465         .clkr = {
1466                 .enable_reg = 0x12004,
1467                 .enable_mask = BIT(0),
1468                 .hw.init = &(struct clk_init_data){
1469                         .name = "gcc_usb20_master_clk",
1470                         .parent_names = (const char *[]){ "usb20_master_clk_src" },
1471                         .num_parents = 1,
1472                         .flags = CLK_SET_RATE_PARENT,
1473                         .ops = &clk_branch2_ops,
1474                 },
1475         },
1476 };
1477
1478 static struct clk_branch gcc_usb20_sleep_clk = {
1479         .halt_reg = 0x12008,
1480         .clkr = {
1481                 .enable_reg = 0x12008,
1482                 .enable_mask = BIT(0),
1483                 .hw.init = &(struct clk_init_data){
1484                         .name = "gcc_usb20_sleep_clk",
1485                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1486                         .num_parents = 1,
1487                         .flags = CLK_SET_RATE_PARENT,
1488                         .ops = &clk_branch2_ops,
1489                 },
1490         },
1491 };
1492
1493 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1494         .halt_reg = 0x1200c,
1495         .clkr = {
1496                 .enable_reg = 0x1200c,
1497                 .enable_mask = BIT(0),
1498                 .hw.init = &(struct clk_init_data){
1499                         .name = "gcc_usb20_mock_utmi_clk",
1500                         .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
1501                         .num_parents = 1,
1502                         .flags = CLK_SET_RATE_PARENT,
1503                         .ops = &clk_branch2_ops,
1504                 },
1505         },
1506 };
1507
1508 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1509         .halt_reg = 0x6a004,
1510         .clkr = {
1511                 .enable_reg = 0x6a004,
1512                 .enable_mask = BIT(0),
1513                 .hw.init = &(struct clk_init_data){
1514                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1515                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1516                         .num_parents = 1,
1517                         .flags = CLK_SET_RATE_PARENT,
1518                         .ops = &clk_branch2_ops,
1519                 },
1520         },
1521 };
1522
1523 static struct clk_branch gcc_sdcc1_apps_clk = {
1524         .halt_reg = 0x13004,
1525         .clkr = {
1526                 .enable_reg = 0x13004,
1527                 .enable_mask = BIT(0),
1528                 .hw.init = &(struct clk_init_data){
1529                         .name = "gcc_sdcc1_apps_clk",
1530                         .parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
1531                         .num_parents = 1,
1532                         .flags = CLK_SET_RATE_PARENT,
1533                         .ops = &clk_branch2_ops,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch gcc_sdcc1_ahb_clk = {
1539         .halt_reg = 0x13008,
1540         .clkr = {
1541                 .enable_reg = 0x13008,
1542                 .enable_mask = BIT(0),
1543                 .hw.init = &(struct clk_init_data){
1544                         .name = "gcc_sdcc1_ahb_clk",
1545                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1546                         .num_parents = 1,
1547                         .flags = CLK_SET_RATE_PARENT,
1548                         .ops = &clk_branch2_ops,
1549                 },
1550         },
1551 };
1552
1553 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1554         .halt_reg = 0x13038,
1555         .clkr = {
1556                 .enable_reg = 0x13038,
1557                 .enable_mask = BIT(0),
1558                 .hw.init = &(struct clk_init_data){
1559                         .name = "gcc_sdcc1_ice_core_clk",
1560                         .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
1561                         .num_parents = 1,
1562                         .flags = CLK_SET_RATE_PARENT,
1563                         .ops = &clk_branch2_ops,
1564                 },
1565         },
1566 };
1567
1568 static struct clk_branch gcc_sdcc2_apps_clk = {
1569         .halt_reg = 0x14004,
1570         .clkr = {
1571                 .enable_reg = 0x14004,
1572                 .enable_mask = BIT(0),
1573                 .hw.init = &(struct clk_init_data){
1574                         .name = "gcc_sdcc2_apps_clk",
1575                         .parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
1576                         .num_parents = 1,
1577                         .flags = CLK_SET_RATE_PARENT,
1578                         .ops = &clk_branch2_ops,
1579                 },
1580         },
1581 };
1582
1583 static struct clk_branch gcc_sdcc2_ahb_clk = {
1584         .halt_reg = 0x14008,
1585         .clkr = {
1586                 .enable_reg = 0x14008,
1587                 .enable_mask = BIT(0),
1588                 .hw.init = &(struct clk_init_data){
1589                         .name = "gcc_sdcc2_ahb_clk",
1590                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1591                         .num_parents = 1,
1592                         .flags = CLK_SET_RATE_PARENT,
1593                         .ops = &clk_branch2_ops,
1594                 },
1595         },
1596 };
1597
1598 static struct clk_branch gcc_sdcc3_apps_clk = {
1599         .halt_reg = 0x15004,
1600         .clkr = {
1601                 .enable_reg = 0x15004,
1602                 .enable_mask = BIT(0),
1603                 .hw.init = &(struct clk_init_data){
1604                         .name = "gcc_sdcc3_apps_clk",
1605                         .parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
1606                         .num_parents = 1,
1607                         .flags = CLK_SET_RATE_PARENT,
1608                         .ops = &clk_branch2_ops,
1609                 },
1610         },
1611 };
1612
1613 static struct clk_branch gcc_sdcc3_ahb_clk = {
1614         .halt_reg = 0x15008,
1615         .clkr = {
1616                 .enable_reg = 0x15008,
1617                 .enable_mask = BIT(0),
1618                 .hw.init = &(struct clk_init_data){
1619                         .name = "gcc_sdcc3_ahb_clk",
1620                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1621                         .num_parents = 1,
1622                         .flags = CLK_SET_RATE_PARENT,
1623                         .ops = &clk_branch2_ops,
1624                 },
1625         },
1626 };
1627
1628 static struct clk_branch gcc_sdcc4_apps_clk = {
1629         .halt_reg = 0x16004,
1630         .clkr = {
1631                 .enable_reg = 0x16004,
1632                 .enable_mask = BIT(0),
1633                 .hw.init = &(struct clk_init_data){
1634                         .name = "gcc_sdcc4_apps_clk",
1635                         .parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
1636                         .num_parents = 1,
1637                         .flags = CLK_SET_RATE_PARENT,
1638                         .ops = &clk_branch2_ops,
1639                 },
1640         },
1641 };
1642
1643 static struct clk_branch gcc_sdcc4_ahb_clk = {
1644         .halt_reg = 0x16008,
1645         .clkr = {
1646                 .enable_reg = 0x16008,
1647                 .enable_mask = BIT(0),
1648                 .hw.init = &(struct clk_init_data){
1649                         .name = "gcc_sdcc4_ahb_clk",
1650                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1651                         .num_parents = 1,
1652                         .flags = CLK_SET_RATE_PARENT,
1653                         .ops = &clk_branch2_ops,
1654                 },
1655         },
1656 };
1657
1658 static struct clk_branch gcc_blsp1_ahb_clk = {
1659         .halt_reg = 0x17004,
1660         .halt_check = BRANCH_HALT_VOTED,
1661         .clkr = {
1662                 .enable_reg = 0x52004,
1663                 .enable_mask = BIT(17),
1664                 .hw.init = &(struct clk_init_data){
1665                         .name = "gcc_blsp1_ahb_clk",
1666                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1667                         .num_parents = 1,
1668                         .flags = CLK_SET_RATE_PARENT,
1669                         .ops = &clk_branch2_ops,
1670                 },
1671         },
1672 };
1673
1674 static struct clk_branch gcc_blsp1_sleep_clk = {
1675         .halt_reg = 0x17008,
1676         .halt_check = BRANCH_HALT_VOTED,
1677         .clkr = {
1678                 .enable_reg = 0x52004,
1679                 .enable_mask = BIT(16),
1680                 .hw.init = &(struct clk_init_data){
1681                         .name = "gcc_blsp1_sleep_clk",
1682                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1683                         .num_parents = 1,
1684                         .flags = CLK_SET_RATE_PARENT,
1685                         .ops = &clk_branch2_ops,
1686                 },
1687         },
1688 };
1689
1690 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1691         .halt_reg = 0x19004,
1692         .clkr = {
1693                 .enable_reg = 0x19004,
1694                 .enable_mask = BIT(0),
1695                 .hw.init = &(struct clk_init_data){
1696                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1697                         .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
1698                         .num_parents = 1,
1699                         .flags = CLK_SET_RATE_PARENT,
1700                         .ops = &clk_branch2_ops,
1701                 },
1702         },
1703 };
1704
1705 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1706         .halt_reg = 0x19008,
1707         .clkr = {
1708                 .enable_reg = 0x19008,
1709                 .enable_mask = BIT(0),
1710                 .hw.init = &(struct clk_init_data){
1711                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1712                         .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
1713                         .num_parents = 1,
1714                         .flags = CLK_SET_RATE_PARENT,
1715                         .ops = &clk_branch2_ops,
1716                 },
1717         },
1718 };
1719
1720 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1721         .halt_reg = 0x1a004,
1722         .clkr = {
1723                 .enable_reg = 0x1a004,
1724                 .enable_mask = BIT(0),
1725                 .hw.init = &(struct clk_init_data){
1726                         .name = "gcc_blsp1_uart1_apps_clk",
1727                         .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
1728                         .num_parents = 1,
1729                         .flags = CLK_SET_RATE_PARENT,
1730                         .ops = &clk_branch2_ops,
1731                 },
1732         },
1733 };
1734
1735 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1736         .halt_reg = 0x1b004,
1737         .clkr = {
1738                 .enable_reg = 0x1b004,
1739                 .enable_mask = BIT(0),
1740                 .hw.init = &(struct clk_init_data){
1741                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1742                         .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
1743                         .num_parents = 1,
1744                         .flags = CLK_SET_RATE_PARENT,
1745                         .ops = &clk_branch2_ops,
1746                 },
1747         },
1748 };
1749
1750 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1751         .halt_reg = 0x1b008,
1752         .clkr = {
1753                 .enable_reg = 0x1b008,
1754                 .enable_mask = BIT(0),
1755                 .hw.init = &(struct clk_init_data){
1756                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1757                         .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
1758                         .num_parents = 1,
1759                         .flags = CLK_SET_RATE_PARENT,
1760                         .ops = &clk_branch2_ops,
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1766         .halt_reg = 0x1c004,
1767         .clkr = {
1768                 .enable_reg = 0x1c004,
1769                 .enable_mask = BIT(0),
1770                 .hw.init = &(struct clk_init_data){
1771                         .name = "gcc_blsp1_uart2_apps_clk",
1772                         .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
1773                         .num_parents = 1,
1774                         .flags = CLK_SET_RATE_PARENT,
1775                         .ops = &clk_branch2_ops,
1776                 },
1777         },
1778 };
1779
1780 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1781         .halt_reg = 0x1d004,
1782         .clkr = {
1783                 .enable_reg = 0x1d004,
1784                 .enable_mask = BIT(0),
1785                 .hw.init = &(struct clk_init_data){
1786                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1787                         .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
1788                         .num_parents = 1,
1789                         .flags = CLK_SET_RATE_PARENT,
1790                         .ops = &clk_branch2_ops,
1791                 },
1792         },
1793 };
1794
1795 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1796         .halt_reg = 0x1d008,
1797         .clkr = {
1798                 .enable_reg = 0x1d008,
1799                 .enable_mask = BIT(0),
1800                 .hw.init = &(struct clk_init_data){
1801                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1802                         .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
1803                         .num_parents = 1,
1804                         .flags = CLK_SET_RATE_PARENT,
1805                         .ops = &clk_branch2_ops,
1806                 },
1807         },
1808 };
1809
1810 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1811         .halt_reg = 0x1e004,
1812         .clkr = {
1813                 .enable_reg = 0x1e004,
1814                 .enable_mask = BIT(0),
1815                 .hw.init = &(struct clk_init_data){
1816                         .name = "gcc_blsp1_uart3_apps_clk",
1817                         .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
1818                         .num_parents = 1,
1819                         .flags = CLK_SET_RATE_PARENT,
1820                         .ops = &clk_branch2_ops,
1821                 },
1822         },
1823 };
1824
1825 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1826         .halt_reg = 0x1f004,
1827         .clkr = {
1828                 .enable_reg = 0x1f004,
1829                 .enable_mask = BIT(0),
1830                 .hw.init = &(struct clk_init_data){
1831                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1832                         .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
1833                         .num_parents = 1,
1834                         .flags = CLK_SET_RATE_PARENT,
1835                         .ops = &clk_branch2_ops,
1836                 },
1837         },
1838 };
1839
1840 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1841         .halt_reg = 0x1f008,
1842         .clkr = {
1843                 .enable_reg = 0x1f008,
1844                 .enable_mask = BIT(0),
1845                 .hw.init = &(struct clk_init_data){
1846                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1847                         .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
1848                         .num_parents = 1,
1849                         .flags = CLK_SET_RATE_PARENT,
1850                         .ops = &clk_branch2_ops,
1851                 },
1852         },
1853 };
1854
1855 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1856         .halt_reg = 0x20004,
1857         .clkr = {
1858                 .enable_reg = 0x20004,
1859                 .enable_mask = BIT(0),
1860                 .hw.init = &(struct clk_init_data){
1861                         .name = "gcc_blsp1_uart4_apps_clk",
1862                         .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
1863                         .num_parents = 1,
1864                         .flags = CLK_SET_RATE_PARENT,
1865                         .ops = &clk_branch2_ops,
1866                 },
1867         },
1868 };
1869
1870 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1871         .halt_reg = 0x21004,
1872         .clkr = {
1873                 .enable_reg = 0x21004,
1874                 .enable_mask = BIT(0),
1875                 .hw.init = &(struct clk_init_data){
1876                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1877                         .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
1878                         .num_parents = 1,
1879                         .flags = CLK_SET_RATE_PARENT,
1880                         .ops = &clk_branch2_ops,
1881                 },
1882         },
1883 };
1884
1885 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1886         .halt_reg = 0x21008,
1887         .clkr = {
1888                 .enable_reg = 0x21008,
1889                 .enable_mask = BIT(0),
1890                 .hw.init = &(struct clk_init_data){
1891                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1892                         .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
1893                         .num_parents = 1,
1894                         .flags = CLK_SET_RATE_PARENT,
1895                         .ops = &clk_branch2_ops,
1896                 },
1897         },
1898 };
1899
1900 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1901         .halt_reg = 0x22004,
1902         .clkr = {
1903                 .enable_reg = 0x22004,
1904                 .enable_mask = BIT(0),
1905                 .hw.init = &(struct clk_init_data){
1906                         .name = "gcc_blsp1_uart5_apps_clk",
1907                         .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
1908                         .num_parents = 1,
1909                         .flags = CLK_SET_RATE_PARENT,
1910                         .ops = &clk_branch2_ops,
1911                 },
1912         },
1913 };
1914
1915 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1916         .halt_reg = 0x23004,
1917         .clkr = {
1918                 .enable_reg = 0x23004,
1919                 .enable_mask = BIT(0),
1920                 .hw.init = &(struct clk_init_data){
1921                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1922                         .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
1923                         .num_parents = 1,
1924                         .flags = CLK_SET_RATE_PARENT,
1925                         .ops = &clk_branch2_ops,
1926                 },
1927         },
1928 };
1929
1930 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1931         .halt_reg = 0x23008,
1932         .clkr = {
1933                 .enable_reg = 0x23008,
1934                 .enable_mask = BIT(0),
1935                 .hw.init = &(struct clk_init_data){
1936                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1937                         .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
1938                         .num_parents = 1,
1939                         .flags = CLK_SET_RATE_PARENT,
1940                         .ops = &clk_branch2_ops,
1941                 },
1942         },
1943 };
1944
1945 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1946         .halt_reg = 0x24004,
1947         .clkr = {
1948                 .enable_reg = 0x24004,
1949                 .enable_mask = BIT(0),
1950                 .hw.init = &(struct clk_init_data){
1951                         .name = "gcc_blsp1_uart6_apps_clk",
1952                         .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
1953                         .num_parents = 1,
1954                         .flags = CLK_SET_RATE_PARENT,
1955                         .ops = &clk_branch2_ops,
1956                 },
1957         },
1958 };
1959
1960 static struct clk_branch gcc_blsp2_ahb_clk = {
1961         .halt_reg = 0x25004,
1962         .halt_check = BRANCH_HALT_VOTED,
1963         .clkr = {
1964                 .enable_reg = 0x52004,
1965                 .enable_mask = BIT(15),
1966                 .hw.init = &(struct clk_init_data){
1967                         .name = "gcc_blsp2_ahb_clk",
1968                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
1969                         .num_parents = 1,
1970                         .flags = CLK_SET_RATE_PARENT,
1971                         .ops = &clk_branch2_ops,
1972                 },
1973         },
1974 };
1975
1976 static struct clk_branch gcc_blsp2_sleep_clk = {
1977         .halt_reg = 0x25008,
1978         .halt_check = BRANCH_HALT_VOTED,
1979         .clkr = {
1980                 .enable_reg = 0x52004,
1981                 .enable_mask = BIT(14),
1982                 .hw.init = &(struct clk_init_data){
1983                         .name = "gcc_blsp2_sleep_clk",
1984                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
1985                         .num_parents = 1,
1986                         .flags = CLK_SET_RATE_PARENT,
1987                         .ops = &clk_branch2_ops,
1988                 },
1989         },
1990 };
1991
1992 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1993         .halt_reg = 0x26004,
1994         .clkr = {
1995                 .enable_reg = 0x26004,
1996                 .enable_mask = BIT(0),
1997                 .hw.init = &(struct clk_init_data){
1998                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1999                         .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
2000                         .num_parents = 1,
2001                         .flags = CLK_SET_RATE_PARENT,
2002                         .ops = &clk_branch2_ops,
2003                 },
2004         },
2005 };
2006
2007 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
2008         .halt_reg = 0x26008,
2009         .clkr = {
2010                 .enable_reg = 0x26008,
2011                 .enable_mask = BIT(0),
2012                 .hw.init = &(struct clk_init_data){
2013                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
2014                         .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
2015                         .num_parents = 1,
2016                         .flags = CLK_SET_RATE_PARENT,
2017                         .ops = &clk_branch2_ops,
2018                 },
2019         },
2020 };
2021
2022 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
2023         .halt_reg = 0x27004,
2024         .clkr = {
2025                 .enable_reg = 0x27004,
2026                 .enable_mask = BIT(0),
2027                 .hw.init = &(struct clk_init_data){
2028                         .name = "gcc_blsp2_uart1_apps_clk",
2029                         .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
2030                         .num_parents = 1,
2031                         .flags = CLK_SET_RATE_PARENT,
2032                         .ops = &clk_branch2_ops,
2033                 },
2034         },
2035 };
2036
2037 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
2038         .halt_reg = 0x28004,
2039         .clkr = {
2040                 .enable_reg = 0x28004,
2041                 .enable_mask = BIT(0),
2042                 .hw.init = &(struct clk_init_data){
2043                         .name = "gcc_blsp2_qup2_spi_apps_clk",
2044                         .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
2045                         .num_parents = 1,
2046                         .flags = CLK_SET_RATE_PARENT,
2047                         .ops = &clk_branch2_ops,
2048                 },
2049         },
2050 };
2051
2052 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
2053         .halt_reg = 0x28008,
2054         .clkr = {
2055                 .enable_reg = 0x28008,
2056                 .enable_mask = BIT(0),
2057                 .hw.init = &(struct clk_init_data){
2058                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
2059                         .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
2060                         .num_parents = 1,
2061                         .flags = CLK_SET_RATE_PARENT,
2062                         .ops = &clk_branch2_ops,
2063                 },
2064         },
2065 };
2066
2067 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2068         .halt_reg = 0x29004,
2069         .clkr = {
2070                 .enable_reg = 0x29004,
2071                 .enable_mask = BIT(0),
2072                 .hw.init = &(struct clk_init_data){
2073                         .name = "gcc_blsp2_uart2_apps_clk",
2074                         .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
2075                         .num_parents = 1,
2076                         .flags = CLK_SET_RATE_PARENT,
2077                         .ops = &clk_branch2_ops,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2083         .halt_reg = 0x2a004,
2084         .clkr = {
2085                 .enable_reg = 0x2a004,
2086                 .enable_mask = BIT(0),
2087                 .hw.init = &(struct clk_init_data){
2088                         .name = "gcc_blsp2_qup3_spi_apps_clk",
2089                         .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
2090                         .num_parents = 1,
2091                         .flags = CLK_SET_RATE_PARENT,
2092                         .ops = &clk_branch2_ops,
2093                 },
2094         },
2095 };
2096
2097 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2098         .halt_reg = 0x2a008,
2099         .clkr = {
2100                 .enable_reg = 0x2a008,
2101                 .enable_mask = BIT(0),
2102                 .hw.init = &(struct clk_init_data){
2103                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
2104                         .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
2105                         .num_parents = 1,
2106                         .flags = CLK_SET_RATE_PARENT,
2107                         .ops = &clk_branch2_ops,
2108                 },
2109         },
2110 };
2111
2112 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2113         .halt_reg = 0x2b004,
2114         .clkr = {
2115                 .enable_reg = 0x2b004,
2116                 .enable_mask = BIT(0),
2117                 .hw.init = &(struct clk_init_data){
2118                         .name = "gcc_blsp2_uart3_apps_clk",
2119                         .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
2120                         .num_parents = 1,
2121                         .flags = CLK_SET_RATE_PARENT,
2122                         .ops = &clk_branch2_ops,
2123                 },
2124         },
2125 };
2126
2127 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2128         .halt_reg = 0x2c004,
2129         .clkr = {
2130                 .enable_reg = 0x2c004,
2131                 .enable_mask = BIT(0),
2132                 .hw.init = &(struct clk_init_data){
2133                         .name = "gcc_blsp2_qup4_spi_apps_clk",
2134                         .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
2135                         .num_parents = 1,
2136                         .flags = CLK_SET_RATE_PARENT,
2137                         .ops = &clk_branch2_ops,
2138                 },
2139         },
2140 };
2141
2142 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2143         .halt_reg = 0x2c008,
2144         .clkr = {
2145                 .enable_reg = 0x2c008,
2146                 .enable_mask = BIT(0),
2147                 .hw.init = &(struct clk_init_data){
2148                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
2149                         .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
2150                         .num_parents = 1,
2151                         .flags = CLK_SET_RATE_PARENT,
2152                         .ops = &clk_branch2_ops,
2153                 },
2154         },
2155 };
2156
2157 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2158         .halt_reg = 0x2d004,
2159         .clkr = {
2160                 .enable_reg = 0x2d004,
2161                 .enable_mask = BIT(0),
2162                 .hw.init = &(struct clk_init_data){
2163                         .name = "gcc_blsp2_uart4_apps_clk",
2164                         .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
2165                         .num_parents = 1,
2166                         .flags = CLK_SET_RATE_PARENT,
2167                         .ops = &clk_branch2_ops,
2168                 },
2169         },
2170 };
2171
2172 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2173         .halt_reg = 0x2e004,
2174         .clkr = {
2175                 .enable_reg = 0x2e004,
2176                 .enable_mask = BIT(0),
2177                 .hw.init = &(struct clk_init_data){
2178                         .name = "gcc_blsp2_qup5_spi_apps_clk",
2179                         .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
2180                         .num_parents = 1,
2181                         .flags = CLK_SET_RATE_PARENT,
2182                         .ops = &clk_branch2_ops,
2183                 },
2184         },
2185 };
2186
2187 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2188         .halt_reg = 0x2e008,
2189         .clkr = {
2190                 .enable_reg = 0x2e008,
2191                 .enable_mask = BIT(0),
2192                 .hw.init = &(struct clk_init_data){
2193                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
2194                         .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
2195                         .num_parents = 1,
2196                         .flags = CLK_SET_RATE_PARENT,
2197                         .ops = &clk_branch2_ops,
2198                 },
2199         },
2200 };
2201
2202 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2203         .halt_reg = 0x2f004,
2204         .clkr = {
2205                 .enable_reg = 0x2f004,
2206                 .enable_mask = BIT(0),
2207                 .hw.init = &(struct clk_init_data){
2208                         .name = "gcc_blsp2_uart5_apps_clk",
2209                         .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
2210                         .num_parents = 1,
2211                         .flags = CLK_SET_RATE_PARENT,
2212                         .ops = &clk_branch2_ops,
2213                 },
2214         },
2215 };
2216
2217 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2218         .halt_reg = 0x30004,
2219         .clkr = {
2220                 .enable_reg = 0x30004,
2221                 .enable_mask = BIT(0),
2222                 .hw.init = &(struct clk_init_data){
2223                         .name = "gcc_blsp2_qup6_spi_apps_clk",
2224                         .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
2225                         .num_parents = 1,
2226                         .flags = CLK_SET_RATE_PARENT,
2227                         .ops = &clk_branch2_ops,
2228                 },
2229         },
2230 };
2231
2232 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2233         .halt_reg = 0x30008,
2234         .clkr = {
2235                 .enable_reg = 0x30008,
2236                 .enable_mask = BIT(0),
2237                 .hw.init = &(struct clk_init_data){
2238                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
2239                         .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
2240                         .num_parents = 1,
2241                         .flags = CLK_SET_RATE_PARENT,
2242                         .ops = &clk_branch2_ops,
2243                 },
2244         },
2245 };
2246
2247 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2248         .halt_reg = 0x31004,
2249         .clkr = {
2250                 .enable_reg = 0x31004,
2251                 .enable_mask = BIT(0),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "gcc_blsp2_uart6_apps_clk",
2254                         .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
2255                         .num_parents = 1,
2256                         .flags = CLK_SET_RATE_PARENT,
2257                         .ops = &clk_branch2_ops,
2258                 },
2259         },
2260 };
2261
2262 static struct clk_branch gcc_pdm_ahb_clk = {
2263         .halt_reg = 0x33004,
2264         .clkr = {
2265                 .enable_reg = 0x33004,
2266                 .enable_mask = BIT(0),
2267                 .hw.init = &(struct clk_init_data){
2268                         .name = "gcc_pdm_ahb_clk",
2269                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2270                         .num_parents = 1,
2271                         .flags = CLK_SET_RATE_PARENT,
2272                         .ops = &clk_branch2_ops,
2273                 },
2274         },
2275 };
2276
2277 static struct clk_branch gcc_pdm2_clk = {
2278         .halt_reg = 0x3300c,
2279         .clkr = {
2280                 .enable_reg = 0x3300c,
2281                 .enable_mask = BIT(0),
2282                 .hw.init = &(struct clk_init_data){
2283                         .name = "gcc_pdm2_clk",
2284                         .parent_names = (const char *[]){ "pdm2_clk_src" },
2285                         .num_parents = 1,
2286                         .flags = CLK_SET_RATE_PARENT,
2287                         .ops = &clk_branch2_ops,
2288                 },
2289         },
2290 };
2291
2292 static struct clk_branch gcc_prng_ahb_clk = {
2293         .halt_reg = 0x34004,
2294         .halt_check = BRANCH_HALT_VOTED,
2295         .clkr = {
2296                 .enable_reg = 0x52004,
2297                 .enable_mask = BIT(13),
2298                 .hw.init = &(struct clk_init_data){
2299                         .name = "gcc_prng_ahb_clk",
2300                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2301                         .num_parents = 1,
2302                         .flags = CLK_SET_RATE_PARENT,
2303                         .ops = &clk_branch2_ops,
2304                 },
2305         },
2306 };
2307
2308 static struct clk_branch gcc_tsif_ahb_clk = {
2309         .halt_reg = 0x36004,
2310         .clkr = {
2311                 .enable_reg = 0x36004,
2312                 .enable_mask = BIT(0),
2313                 .hw.init = &(struct clk_init_data){
2314                         .name = "gcc_tsif_ahb_clk",
2315                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2316                         .num_parents = 1,
2317                         .flags = CLK_SET_RATE_PARENT,
2318                         .ops = &clk_branch2_ops,
2319                 },
2320         },
2321 };
2322
2323 static struct clk_branch gcc_tsif_ref_clk = {
2324         .halt_reg = 0x36008,
2325         .clkr = {
2326                 .enable_reg = 0x36008,
2327                 .enable_mask = BIT(0),
2328                 .hw.init = &(struct clk_init_data){
2329                         .name = "gcc_tsif_ref_clk",
2330                         .parent_names = (const char *[]){ "tsif_ref_clk_src" },
2331                         .num_parents = 1,
2332                         .flags = CLK_SET_RATE_PARENT,
2333                         .ops = &clk_branch2_ops,
2334                 },
2335         },
2336 };
2337
2338 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2339         .halt_reg = 0x3600c,
2340         .clkr = {
2341                 .enable_reg = 0x3600c,
2342                 .enable_mask = BIT(0),
2343                 .hw.init = &(struct clk_init_data){
2344                         .name = "gcc_tsif_inactivity_timers_clk",
2345                         .parent_names = (const char *[]){ "gcc_sleep_clk_src" },
2346                         .num_parents = 1,
2347                         .flags = CLK_SET_RATE_PARENT,
2348                         .ops = &clk_branch2_ops,
2349                 },
2350         },
2351 };
2352
2353 static struct clk_branch gcc_boot_rom_ahb_clk = {
2354         .halt_reg = 0x38004,
2355         .halt_check = BRANCH_HALT_VOTED,
2356         .clkr = {
2357                 .enable_reg = 0x52004,
2358                 .enable_mask = BIT(10),
2359                 .hw.init = &(struct clk_init_data){
2360                         .name = "gcc_boot_rom_ahb_clk",
2361                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2362                         .num_parents = 1,
2363                         .flags = CLK_SET_RATE_PARENT,
2364                         .ops = &clk_branch2_ops,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_branch gcc_bimc_gfx_clk = {
2370         .halt_reg = 0x46018,
2371         .clkr = {
2372                 .enable_reg = 0x46018,
2373                 .enable_mask = BIT(0),
2374                 .hw.init = &(struct clk_init_data){
2375                         .name = "gcc_bimc_gfx_clk",
2376                         .flags = CLK_SET_RATE_PARENT,
2377                         .ops = &clk_branch2_ops,
2378                 },
2379         },
2380 };
2381
2382 static struct clk_branch gcc_hmss_rbcpr_clk = {
2383         .halt_reg = 0x4800c,
2384         .clkr = {
2385                 .enable_reg = 0x4800c,
2386                 .enable_mask = BIT(0),
2387                 .hw.init = &(struct clk_init_data){
2388                         .name = "gcc_hmss_rbcpr_clk",
2389                         .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
2390                         .num_parents = 1,
2391                         .flags = CLK_SET_RATE_PARENT,
2392                         .ops = &clk_branch2_ops,
2393                 },
2394         },
2395 };
2396
2397 static struct clk_branch gcc_gp1_clk = {
2398         .halt_reg = 0x64000,
2399         .clkr = {
2400                 .enable_reg = 0x64000,
2401                 .enable_mask = BIT(0),
2402                 .hw.init = &(struct clk_init_data){
2403                         .name = "gcc_gp1_clk",
2404                         .parent_names = (const char *[]){ "gp1_clk_src" },
2405                         .num_parents = 1,
2406                         .flags = CLK_SET_RATE_PARENT,
2407                         .ops = &clk_branch2_ops,
2408                 },
2409         },
2410 };
2411
2412 static struct clk_branch gcc_gp2_clk = {
2413         .halt_reg = 0x65000,
2414         .clkr = {
2415                 .enable_reg = 0x65000,
2416                 .enable_mask = BIT(0),
2417                 .hw.init = &(struct clk_init_data){
2418                         .name = "gcc_gp2_clk",
2419                         .parent_names = (const char *[]){ "gp2_clk_src" },
2420                         .num_parents = 1,
2421                         .flags = CLK_SET_RATE_PARENT,
2422                         .ops = &clk_branch2_ops,
2423                 },
2424         },
2425 };
2426
2427 static struct clk_branch gcc_gp3_clk = {
2428         .halt_reg = 0x66000,
2429         .clkr = {
2430                 .enable_reg = 0x66000,
2431                 .enable_mask = BIT(0),
2432                 .hw.init = &(struct clk_init_data){
2433                         .name = "gcc_gp3_clk",
2434                         .parent_names = (const char *[]){ "gp3_clk_src" },
2435                         .num_parents = 1,
2436                         .flags = CLK_SET_RATE_PARENT,
2437                         .ops = &clk_branch2_ops,
2438                 },
2439         },
2440 };
2441
2442 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2443         .halt_reg = 0x6b008,
2444         .clkr = {
2445                 .enable_reg = 0x6b008,
2446                 .enable_mask = BIT(0),
2447                 .hw.init = &(struct clk_init_data){
2448                         .name = "gcc_pcie_0_slv_axi_clk",
2449                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2450                         .num_parents = 1,
2451                         .flags = CLK_SET_RATE_PARENT,
2452                         .ops = &clk_branch2_ops,
2453                 },
2454         },
2455 };
2456
2457 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2458         .halt_reg = 0x6b00c,
2459         .clkr = {
2460                 .enable_reg = 0x6b00c,
2461                 .enable_mask = BIT(0),
2462                 .hw.init = &(struct clk_init_data){
2463                         .name = "gcc_pcie_0_mstr_axi_clk",
2464                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2465                         .num_parents = 1,
2466                         .flags = CLK_SET_RATE_PARENT,
2467                         .ops = &clk_branch2_ops,
2468                 },
2469         },
2470 };
2471
2472 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2473         .halt_reg = 0x6b010,
2474         .clkr = {
2475                 .enable_reg = 0x6b010,
2476                 .enable_mask = BIT(0),
2477                 .hw.init = &(struct clk_init_data){
2478                         .name = "gcc_pcie_0_cfg_ahb_clk",
2479                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2480                         .num_parents = 1,
2481                         .flags = CLK_SET_RATE_PARENT,
2482                         .ops = &clk_branch2_ops,
2483                 },
2484         },
2485 };
2486
2487 static struct clk_branch gcc_pcie_0_aux_clk = {
2488         .halt_reg = 0x6b014,
2489         .clkr = {
2490                 .enable_reg = 0x6b014,
2491                 .enable_mask = BIT(0),
2492                 .hw.init = &(struct clk_init_data){
2493                         .name = "gcc_pcie_0_aux_clk",
2494                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2495                         .num_parents = 1,
2496                         .flags = CLK_SET_RATE_PARENT,
2497                         .ops = &clk_branch2_ops,
2498                 },
2499         },
2500 };
2501
2502 static struct clk_branch gcc_pcie_0_pipe_clk = {
2503         .halt_reg = 0x6b018,
2504         .halt_check = BRANCH_HALT_SKIP,
2505         .clkr = {
2506                 .enable_reg = 0x6b018,
2507                 .enable_mask = BIT(0),
2508                 .hw.init = &(struct clk_init_data){
2509                         .name = "gcc_pcie_0_pipe_clk",
2510                         .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
2511                         .num_parents = 1,
2512                         .flags = CLK_SET_RATE_PARENT,
2513                         .ops = &clk_branch2_ops,
2514                 },
2515         },
2516 };
2517
2518 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2519         .halt_reg = 0x6d008,
2520         .clkr = {
2521                 .enable_reg = 0x6d008,
2522                 .enable_mask = BIT(0),
2523                 .hw.init = &(struct clk_init_data){
2524                         .name = "gcc_pcie_1_slv_axi_clk",
2525                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2526                         .num_parents = 1,
2527                         .flags = CLK_SET_RATE_PARENT,
2528                         .ops = &clk_branch2_ops,
2529                 },
2530         },
2531 };
2532
2533 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2534         .halt_reg = 0x6d00c,
2535         .clkr = {
2536                 .enable_reg = 0x6d00c,
2537                 .enable_mask = BIT(0),
2538                 .hw.init = &(struct clk_init_data){
2539                         .name = "gcc_pcie_1_mstr_axi_clk",
2540                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2541                         .num_parents = 1,
2542                         .flags = CLK_SET_RATE_PARENT,
2543                         .ops = &clk_branch2_ops,
2544                 },
2545         },
2546 };
2547
2548 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2549         .halt_reg = 0x6d010,
2550         .clkr = {
2551                 .enable_reg = 0x6d010,
2552                 .enable_mask = BIT(0),
2553                 .hw.init = &(struct clk_init_data){
2554                         .name = "gcc_pcie_1_cfg_ahb_clk",
2555                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2556                         .num_parents = 1,
2557                         .flags = CLK_SET_RATE_PARENT,
2558                         .ops = &clk_branch2_ops,
2559                 },
2560         },
2561 };
2562
2563 static struct clk_branch gcc_pcie_1_aux_clk = {
2564         .halt_reg = 0x6d014,
2565         .clkr = {
2566                 .enable_reg = 0x6d014,
2567                 .enable_mask = BIT(0),
2568                 .hw.init = &(struct clk_init_data){
2569                         .name = "gcc_pcie_1_aux_clk",
2570                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2571                         .num_parents = 1,
2572                         .flags = CLK_SET_RATE_PARENT,
2573                         .ops = &clk_branch2_ops,
2574                 },
2575         },
2576 };
2577
2578 static struct clk_branch gcc_pcie_1_pipe_clk = {
2579         .halt_reg = 0x6d018,
2580         .halt_check = BRANCH_HALT_SKIP,
2581         .clkr = {
2582                 .enable_reg = 0x6d018,
2583                 .enable_mask = BIT(0),
2584                 .hw.init = &(struct clk_init_data){
2585                         .name = "gcc_pcie_1_pipe_clk",
2586                         .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
2587                         .num_parents = 1,
2588                         .flags = CLK_SET_RATE_PARENT,
2589                         .ops = &clk_branch2_ops,
2590                 },
2591         },
2592 };
2593
2594 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2595         .halt_reg = 0x6e008,
2596         .clkr = {
2597                 .enable_reg = 0x6e008,
2598                 .enable_mask = BIT(0),
2599                 .hw.init = &(struct clk_init_data){
2600                         .name = "gcc_pcie_2_slv_axi_clk",
2601                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2602                         .num_parents = 1,
2603                         .flags = CLK_SET_RATE_PARENT,
2604                         .ops = &clk_branch2_ops,
2605                 },
2606         },
2607 };
2608
2609 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2610         .halt_reg = 0x6e00c,
2611         .clkr = {
2612                 .enable_reg = 0x6e00c,
2613                 .enable_mask = BIT(0),
2614                 .hw.init = &(struct clk_init_data){
2615                         .name = "gcc_pcie_2_mstr_axi_clk",
2616                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2617                         .num_parents = 1,
2618                         .flags = CLK_SET_RATE_PARENT,
2619                         .ops = &clk_branch2_ops,
2620                 },
2621         },
2622 };
2623
2624 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2625         .halt_reg = 0x6e010,
2626         .clkr = {
2627                 .enable_reg = 0x6e010,
2628                 .enable_mask = BIT(0),
2629                 .hw.init = &(struct clk_init_data){
2630                         .name = "gcc_pcie_2_cfg_ahb_clk",
2631                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2632                         .num_parents = 1,
2633                         .flags = CLK_SET_RATE_PARENT,
2634                         .ops = &clk_branch2_ops,
2635                 },
2636         },
2637 };
2638
2639 static struct clk_branch gcc_pcie_2_aux_clk = {
2640         .halt_reg = 0x6e014,
2641         .clkr = {
2642                 .enable_reg = 0x6e014,
2643                 .enable_mask = BIT(0),
2644                 .hw.init = &(struct clk_init_data){
2645                         .name = "gcc_pcie_2_aux_clk",
2646                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2647                         .num_parents = 1,
2648                         .flags = CLK_SET_RATE_PARENT,
2649                         .ops = &clk_branch2_ops,
2650                 },
2651         },
2652 };
2653
2654 static struct clk_branch gcc_pcie_2_pipe_clk = {
2655         .halt_reg = 0x6e018,
2656         .halt_check = BRANCH_HALT_SKIP,
2657         .clkr = {
2658                 .enable_reg = 0x6e018,
2659                 .enable_mask = BIT(0),
2660                 .hw.init = &(struct clk_init_data){
2661                         .name = "gcc_pcie_2_pipe_clk",
2662                         .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
2663                         .num_parents = 1,
2664                         .flags = CLK_SET_RATE_PARENT,
2665                         .ops = &clk_branch2_ops,
2666                 },
2667         },
2668 };
2669
2670 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2671         .halt_reg = 0x6f004,
2672         .clkr = {
2673                 .enable_reg = 0x6f004,
2674                 .enable_mask = BIT(0),
2675                 .hw.init = &(struct clk_init_data){
2676                         .name = "gcc_pcie_phy_cfg_ahb_clk",
2677                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2678                         .num_parents = 1,
2679                         .flags = CLK_SET_RATE_PARENT,
2680                         .ops = &clk_branch2_ops,
2681                 },
2682         },
2683 };
2684
2685 static struct clk_branch gcc_pcie_phy_aux_clk = {
2686         .halt_reg = 0x6f008,
2687         .clkr = {
2688                 .enable_reg = 0x6f008,
2689                 .enable_mask = BIT(0),
2690                 .hw.init = &(struct clk_init_data){
2691                         .name = "gcc_pcie_phy_aux_clk",
2692                         .parent_names = (const char *[]){ "pcie_aux_clk_src" },
2693                         .num_parents = 1,
2694                         .flags = CLK_SET_RATE_PARENT,
2695                         .ops = &clk_branch2_ops,
2696                 },
2697         },
2698 };
2699
2700 static struct clk_branch gcc_ufs_axi_clk = {
2701         .halt_reg = 0x75008,
2702         .clkr = {
2703                 .enable_reg = 0x75008,
2704                 .enable_mask = BIT(0),
2705                 .hw.init = &(struct clk_init_data){
2706                         .name = "gcc_ufs_axi_clk",
2707                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2708                         .num_parents = 1,
2709                         .flags = CLK_SET_RATE_PARENT,
2710                         .ops = &clk_branch2_ops,
2711                 },
2712         },
2713 };
2714
2715 static struct clk_branch gcc_ufs_ahb_clk = {
2716         .halt_reg = 0x7500c,
2717         .clkr = {
2718                 .enable_reg = 0x7500c,
2719                 .enable_mask = BIT(0),
2720                 .hw.init = &(struct clk_init_data){
2721                         .name = "gcc_ufs_ahb_clk",
2722                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2723                         .num_parents = 1,
2724                         .flags = CLK_SET_RATE_PARENT,
2725                         .ops = &clk_branch2_ops,
2726                 },
2727         },
2728 };
2729
2730 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2731         .mult = 1,
2732         .div = 16,
2733         .hw.init = &(struct clk_init_data){
2734                 .name = "ufs_tx_cfg_clk_src",
2735                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2736                 .num_parents = 1,
2737                 .flags = CLK_SET_RATE_PARENT,
2738                 .ops = &clk_fixed_factor_ops,
2739         },
2740 };
2741
2742 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2743         .halt_reg = 0x75010,
2744         .clkr = {
2745                 .enable_reg = 0x75010,
2746                 .enable_mask = BIT(0),
2747                 .hw.init = &(struct clk_init_data){
2748                         .name = "gcc_ufs_tx_cfg_clk",
2749                         .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
2750                         .num_parents = 1,
2751                         .flags = CLK_SET_RATE_PARENT,
2752                         .ops = &clk_branch2_ops,
2753                 },
2754         },
2755 };
2756
2757 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2758         .mult = 1,
2759         .div = 16,
2760         .hw.init = &(struct clk_init_data){
2761                 .name = "ufs_rx_cfg_clk_src",
2762                 .parent_names = (const char *[]){ "ufs_axi_clk_src" },
2763                 .num_parents = 1,
2764                 .flags = CLK_SET_RATE_PARENT,
2765                 .ops = &clk_fixed_factor_ops,
2766         },
2767 };
2768
2769 static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2770         .halt_reg = 0x7d010,
2771         .halt_check = BRANCH_HALT_VOTED,
2772         .clkr = {
2773                 .enable_reg = 0x7d010,
2774                 .enable_mask = BIT(0),
2775                 .hw.init = &(struct clk_init_data){
2776                         .name = "hlos1_vote_lpass_core_smmu_clk",
2777                         .ops = &clk_branch2_ops,
2778                 },
2779         },
2780 };
2781
2782 static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2783         .halt_reg = 0x7d014,
2784         .halt_check = BRANCH_HALT_VOTED,
2785         .clkr = {
2786                 .enable_reg = 0x7d014,
2787                 .enable_mask = BIT(0),
2788                 .hw.init = &(struct clk_init_data){
2789                         .name = "hlos1_vote_lpass_adsp_smmu_clk",
2790                         .ops = &clk_branch2_ops,
2791                 },
2792         },
2793 };
2794
2795 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2796         .halt_reg = 0x75014,
2797         .clkr = {
2798                 .enable_reg = 0x75014,
2799                 .enable_mask = BIT(0),
2800                 .hw.init = &(struct clk_init_data){
2801                         .name = "gcc_ufs_rx_cfg_clk",
2802                         .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
2803                         .num_parents = 1,
2804                         .flags = CLK_SET_RATE_PARENT,
2805                         .ops = &clk_branch2_ops,
2806                 },
2807         },
2808 };
2809
2810 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2811         .halt_reg = 0x75018,
2812         .halt_check = BRANCH_HALT_SKIP,
2813         .clkr = {
2814                 .enable_reg = 0x75018,
2815                 .enable_mask = BIT(0),
2816                 .hw.init = &(struct clk_init_data){
2817                         .name = "gcc_ufs_tx_symbol_0_clk",
2818                         .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
2819                         .num_parents = 1,
2820                         .flags = CLK_SET_RATE_PARENT,
2821                         .ops = &clk_branch2_ops,
2822                 },
2823         },
2824 };
2825
2826 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2827         .halt_reg = 0x7501c,
2828         .halt_check = BRANCH_HALT_SKIP,
2829         .clkr = {
2830                 .enable_reg = 0x7501c,
2831                 .enable_mask = BIT(0),
2832                 .hw.init = &(struct clk_init_data){
2833                         .name = "gcc_ufs_rx_symbol_0_clk",
2834                         .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
2835                         .num_parents = 1,
2836                         .flags = CLK_SET_RATE_PARENT,
2837                         .ops = &clk_branch2_ops,
2838                 },
2839         },
2840 };
2841
2842 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2843         .halt_reg = 0x75020,
2844         .halt_check = BRANCH_HALT_SKIP,
2845         .clkr = {
2846                 .enable_reg = 0x75020,
2847                 .enable_mask = BIT(0),
2848                 .hw.init = &(struct clk_init_data){
2849                         .name = "gcc_ufs_rx_symbol_1_clk",
2850                         .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
2851                         .num_parents = 1,
2852                         .flags = CLK_SET_RATE_PARENT,
2853                         .ops = &clk_branch2_ops,
2854                 },
2855         },
2856 };
2857
2858 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2859         .mult = 1,
2860         .div = 2,
2861         .hw.init = &(struct clk_init_data){
2862                 .name = "ufs_ice_core_postdiv_clk_src",
2863                 .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2864                 .num_parents = 1,
2865                 .flags = CLK_SET_RATE_PARENT,
2866                 .ops = &clk_fixed_factor_ops,
2867         },
2868 };
2869
2870 static struct clk_branch gcc_ufs_unipro_core_clk = {
2871         .halt_reg = 0x7600c,
2872         .clkr = {
2873                 .enable_reg = 0x7600c,
2874                 .enable_mask = BIT(0),
2875                 .hw.init = &(struct clk_init_data){
2876                         .name = "gcc_ufs_unipro_core_clk",
2877                         .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
2878                         .num_parents = 1,
2879                         .flags = CLK_SET_RATE_PARENT,
2880                         .ops = &clk_branch2_ops,
2881                 },
2882         },
2883 };
2884
2885 static struct clk_branch gcc_ufs_ice_core_clk = {
2886         .halt_reg = 0x76010,
2887         .clkr = {
2888                 .enable_reg = 0x76010,
2889                 .enable_mask = BIT(0),
2890                 .hw.init = &(struct clk_init_data){
2891                         .name = "gcc_ufs_ice_core_clk",
2892                         .parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
2893                         .num_parents = 1,
2894                         .flags = CLK_SET_RATE_PARENT,
2895                         .ops = &clk_branch2_ops,
2896                 },
2897         },
2898 };
2899
2900 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
2901         .halt_check = BRANCH_HALT_DELAY,
2902         .clkr = {
2903                 .enable_reg = 0x76030,
2904                 .enable_mask = BIT(0),
2905                 .hw.init = &(struct clk_init_data){
2906                         .name = "gcc_ufs_sys_clk_core_clk",
2907                         .ops = &clk_branch2_ops,
2908                 },
2909         },
2910 };
2911
2912 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
2913         .halt_check = BRANCH_HALT_DELAY,
2914         .clkr = {
2915                 .enable_reg = 0x76034,
2916                 .enable_mask = BIT(0),
2917                 .hw.init = &(struct clk_init_data){
2918                         .name = "gcc_ufs_tx_symbol_clk_core_clk",
2919                         .ops = &clk_branch2_ops,
2920                 },
2921         },
2922 };
2923
2924 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
2925         .halt_reg = 0x81008,
2926         .clkr = {
2927                 .enable_reg = 0x81008,
2928                 .enable_mask = BIT(0),
2929                 .hw.init = &(struct clk_init_data){
2930                         .name = "gcc_aggre0_snoc_axi_clk",
2931                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2932                         .num_parents = 1,
2933                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2934                         .ops = &clk_branch2_ops,
2935                 },
2936         },
2937 };
2938
2939 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
2940         .halt_reg = 0x8100c,
2941         .clkr = {
2942                 .enable_reg = 0x8100c,
2943                 .enable_mask = BIT(0),
2944                 .hw.init = &(struct clk_init_data){
2945                         .name = "gcc_aggre0_cnoc_ahb_clk",
2946                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2947                         .num_parents = 1,
2948                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2949                         .ops = &clk_branch2_ops,
2950                 },
2951         },
2952 };
2953
2954 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
2955         .halt_reg = 0x81014,
2956         .clkr = {
2957                 .enable_reg = 0x81014,
2958                 .enable_mask = BIT(0),
2959                 .hw.init = &(struct clk_init_data){
2960                         .name = "gcc_smmu_aggre0_axi_clk",
2961                         .parent_names = (const char *[]){ "system_noc_clk_src" },
2962                         .num_parents = 1,
2963                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2964                         .ops = &clk_branch2_ops,
2965                 },
2966         },
2967 };
2968
2969 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
2970         .halt_reg = 0x81018,
2971         .clkr = {
2972                 .enable_reg = 0x81018,
2973                 .enable_mask = BIT(0),
2974                 .hw.init = &(struct clk_init_data){
2975                         .name = "gcc_smmu_aggre0_ahb_clk",
2976                         .parent_names = (const char *[]){ "config_noc_clk_src" },
2977                         .num_parents = 1,
2978                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2979                         .ops = &clk_branch2_ops,
2980                 },
2981         },
2982 };
2983
2984 static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
2985         .halt_reg = 0x82014,
2986         .clkr = {
2987                 .enable_reg = 0x82014,
2988                 .enable_mask = BIT(0),
2989                 .hw.init = &(struct clk_init_data){
2990                         .name = "gcc_aggre1_pnoc_ahb_clk",
2991                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
2992                         .num_parents = 1,
2993                         .ops = &clk_branch2_ops,
2994                 },
2995         },
2996 };
2997
2998 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
2999         .halt_reg = 0x83014,
3000         .clkr = {
3001                 .enable_reg = 0x83014,
3002                 .enable_mask = BIT(0),
3003                 .hw.init = &(struct clk_init_data){
3004                         .name = "gcc_aggre2_ufs_axi_clk",
3005                         .parent_names = (const char *[]){ "ufs_axi_clk_src" },
3006                         .num_parents = 1,
3007                         .flags = CLK_SET_RATE_PARENT,
3008                         .ops = &clk_branch2_ops,
3009                 },
3010         },
3011 };
3012
3013 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
3014         .halt_reg = 0x83018,
3015         .clkr = {
3016                 .enable_reg = 0x83018,
3017                 .enable_mask = BIT(0),
3018                 .hw.init = &(struct clk_init_data){
3019                         .name = "gcc_aggre2_usb3_axi_clk",
3020                         .parent_names = (const char *[]){ "usb30_master_clk_src" },
3021                         .num_parents = 1,
3022                         .flags = CLK_SET_RATE_PARENT,
3023                         .ops = &clk_branch2_ops,
3024                 },
3025         },
3026 };
3027
3028 static struct clk_branch gcc_dcc_ahb_clk = {
3029         .halt_reg = 0x84004,
3030         .clkr = {
3031                 .enable_reg = 0x84004,
3032                 .enable_mask = BIT(0),
3033                 .hw.init = &(struct clk_init_data){
3034                         .name = "gcc_dcc_ahb_clk",
3035                         .parent_names = (const char *[]){ "config_noc_clk_src" },
3036                         .num_parents = 1,
3037                         .ops = &clk_branch2_ops,
3038                 },
3039         },
3040 };
3041
3042 static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
3043         .halt_reg = 0x85000,
3044         .clkr = {
3045                 .enable_reg = 0x85000,
3046                 .enable_mask = BIT(0),
3047                 .hw.init = &(struct clk_init_data){
3048                         .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
3049                         .parent_names = (const char *[]){ "config_noc_clk_src" },
3050                         .num_parents = 1,
3051                         .ops = &clk_branch2_ops,
3052                 },
3053         },
3054 };
3055
3056 static struct clk_branch gcc_qspi_ahb_clk = {
3057         .halt_reg = 0x8b004,
3058         .clkr = {
3059                 .enable_reg = 0x8b004,
3060                 .enable_mask = BIT(0),
3061                 .hw.init = &(struct clk_init_data){
3062                         .name = "gcc_qspi_ahb_clk",
3063                         .parent_names = (const char *[]){ "periph_noc_clk_src" },
3064                         .num_parents = 1,
3065                         .flags = CLK_SET_RATE_PARENT,
3066                         .ops = &clk_branch2_ops,
3067                 },
3068         },
3069 };
3070
3071 static struct clk_branch gcc_qspi_ser_clk = {
3072         .halt_reg = 0x8b008,
3073         .clkr = {
3074                 .enable_reg = 0x8b008,
3075                 .enable_mask = BIT(0),
3076                 .hw.init = &(struct clk_init_data){
3077                         .name = "gcc_qspi_ser_clk",
3078                         .parent_names = (const char *[]){ "qspi_ser_clk_src" },
3079                         .num_parents = 1,
3080                         .flags = CLK_SET_RATE_PARENT,
3081                         .ops = &clk_branch2_ops,
3082                 },
3083         },
3084 };
3085
3086 static struct clk_branch gcc_usb3_clkref_clk = {
3087         .halt_reg = 0x8800C,
3088         .clkr = {
3089                 .enable_reg = 0x8800C,
3090                 .enable_mask = BIT(0),
3091                 .hw.init = &(struct clk_init_data){
3092                         .name = "gcc_usb3_clkref_clk",
3093                         .parent_names = (const char *[]){ "xo" },
3094                         .num_parents = 1,
3095                         .ops = &clk_branch2_ops,
3096                 },
3097         },
3098 };
3099
3100 static struct clk_branch gcc_hdmi_clkref_clk = {
3101         .halt_reg = 0x88000,
3102         .clkr = {
3103                 .enable_reg = 0x88000,
3104                 .enable_mask = BIT(0),
3105                 .hw.init = &(struct clk_init_data){
3106                         .name = "gcc_hdmi_clkref_clk",
3107                         .parent_names = (const char *[]){ "xo" },
3108                         .num_parents = 1,
3109                         .ops = &clk_branch2_ops,
3110                 },
3111         },
3112 };
3113
3114 static struct clk_branch gcc_edp_clkref_clk = {
3115         .halt_reg = 0x88004,
3116         .clkr = {
3117                 .enable_reg = 0x88004,
3118                 .enable_mask = BIT(0),
3119                 .hw.init = &(struct clk_init_data){
3120                         .name = "gcc_edp_clkref_clk",
3121                         .parent_names = (const char *[]){ "xo" },
3122                         .num_parents = 1,
3123                         .ops = &clk_branch2_ops,
3124                 },
3125         },
3126 };
3127
3128 static struct clk_branch gcc_ufs_clkref_clk = {
3129         .halt_reg = 0x88008,
3130         .clkr = {
3131                 .enable_reg = 0x88008,
3132                 .enable_mask = BIT(0),
3133                 .hw.init = &(struct clk_init_data){
3134                         .name = "gcc_ufs_clkref_clk",
3135                         .parent_names = (const char *[]){ "xo" },
3136                         .num_parents = 1,
3137                         .ops = &clk_branch2_ops,
3138                 },
3139         },
3140 };
3141
3142 static struct clk_branch gcc_pcie_clkref_clk = {
3143         .halt_reg = 0x88010,
3144         .clkr = {
3145                 .enable_reg = 0x88010,
3146                 .enable_mask = BIT(0),
3147                 .hw.init = &(struct clk_init_data){
3148                         .name = "gcc_pcie_clkref_clk",
3149                         .parent_names = (const char *[]){ "xo" },
3150                         .num_parents = 1,
3151                         .ops = &clk_branch2_ops,
3152                 },
3153         },
3154 };
3155
3156 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3157         .halt_reg = 0x88014,
3158         .clkr = {
3159                 .enable_reg = 0x88014,
3160                 .enable_mask = BIT(0),
3161                 .hw.init = &(struct clk_init_data){
3162                         .name = "gcc_rx2_usb2_clkref_clk",
3163                         .parent_names = (const char *[]){ "xo" },
3164                         .num_parents = 1,
3165                         .ops = &clk_branch2_ops,
3166                 },
3167         },
3168 };
3169
3170 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3171         .halt_reg = 0x88018,
3172         .clkr = {
3173                 .enable_reg = 0x88018,
3174                 .enable_mask = BIT(0),
3175                 .hw.init = &(struct clk_init_data){
3176                         .name = "gcc_rx1_usb2_clkref_clk",
3177                         .parent_names = (const char *[]){ "xo" },
3178                         .num_parents = 1,
3179                         .ops = &clk_branch2_ops,
3180                 },
3181         },
3182 };
3183
3184 static struct clk_branch gcc_mss_cfg_ahb_clk = {
3185         .halt_reg = 0x8a000,
3186         .clkr = {
3187                 .enable_reg = 0x8a000,
3188                 .enable_mask = BIT(0),
3189                 .hw.init = &(struct clk_init_data){
3190                         .name = "gcc_mss_cfg_ahb_clk",
3191                         .parent_names = (const char *[]){ "config_noc_clk_src" },
3192                         .num_parents = 1,
3193                         .ops = &clk_branch2_ops,
3194                 },
3195         },
3196 };
3197
3198 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
3199         .halt_reg = 0x8a004,
3200         .clkr = {
3201                 .enable_reg = 0x8a004,
3202                 .enable_mask = BIT(0),
3203                 .hw.init = &(struct clk_init_data){
3204                         .name = "gcc_mss_mnoc_bimc_axi_clk",
3205                         .parent_names = (const char *[]){ "system_noc_clk_src" },
3206                         .num_parents = 1,
3207                         .ops = &clk_branch2_ops,
3208                 },
3209         },
3210 };
3211
3212 static struct clk_branch gcc_mss_snoc_axi_clk = {
3213         .halt_reg = 0x8a024,
3214         .clkr = {
3215                 .enable_reg = 0x8a024,
3216                 .enable_mask = BIT(0),
3217                 .hw.init = &(struct clk_init_data){
3218                         .name = "gcc_mss_snoc_axi_clk",
3219                         .parent_names = (const char *[]){ "system_noc_clk_src" },
3220                         .num_parents = 1,
3221                         .ops = &clk_branch2_ops,
3222                 },
3223         },
3224 };
3225
3226 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3227         .halt_reg = 0x8a028,
3228         .clkr = {
3229                 .enable_reg = 0x8a028,
3230                 .enable_mask = BIT(0),
3231                 .hw.init = &(struct clk_init_data){
3232                         .name = "gcc_mss_q6_bimc_axi_clk",
3233                         .parent_names = (const char *[]){ "system_noc_clk_src" },
3234                         .num_parents = 1,
3235                         .ops = &clk_branch2_ops,
3236                 },
3237         },
3238 };
3239
3240 static struct clk_hw *gcc_msm8996_hws[] = {
3241         &xo.hw,
3242         &gpll0_early_div.hw,
3243         &ufs_tx_cfg_clk_src.hw,
3244         &ufs_rx_cfg_clk_src.hw,
3245         &ufs_ice_core_postdiv_clk_src.hw,
3246 };
3247
3248 static struct gdsc aggre0_noc_gdsc = {
3249         .gdscr = 0x81004,
3250         .gds_hw_ctrl = 0x81028,
3251         .pd = {
3252                 .name = "aggre0_noc",
3253         },
3254         .pwrsts = PWRSTS_OFF_ON,
3255         .flags = VOTABLE | ALWAYS_ON,
3256 };
3257
3258 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3259         .gdscr = 0x7d024,
3260         .pd = {
3261                 .name = "hlos1_vote_aggre0_noc",
3262         },
3263         .pwrsts = PWRSTS_OFF_ON,
3264         .flags = VOTABLE,
3265 };
3266
3267 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3268         .gdscr = 0x7d034,
3269         .pd = {
3270                 .name = "hlos1_vote_lpass_adsp",
3271         },
3272         .pwrsts = PWRSTS_OFF_ON,
3273         .flags = VOTABLE,
3274 };
3275
3276 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3277         .gdscr = 0x7d038,
3278         .pd = {
3279                 .name = "hlos1_vote_lpass_core",
3280         },
3281         .pwrsts = PWRSTS_OFF_ON,
3282         .flags = VOTABLE,
3283 };
3284
3285 static struct gdsc usb30_gdsc = {
3286         .gdscr = 0xf004,
3287         .pd = {
3288                 .name = "usb30",
3289         },
3290         .pwrsts = PWRSTS_OFF_ON,
3291 };
3292
3293 static struct gdsc pcie0_gdsc = {
3294         .gdscr = 0x6b004,
3295         .pd = {
3296                 .name = "pcie0",
3297         },
3298         .pwrsts = PWRSTS_OFF_ON,
3299 };
3300
3301 static struct gdsc pcie1_gdsc = {
3302         .gdscr = 0x6d004,
3303         .pd = {
3304                 .name = "pcie1",
3305         },
3306         .pwrsts = PWRSTS_OFF_ON,
3307 };
3308
3309 static struct gdsc pcie2_gdsc = {
3310         .gdscr = 0x6e004,
3311         .pd = {
3312                 .name = "pcie2",
3313         },
3314         .pwrsts = PWRSTS_OFF_ON,
3315 };
3316
3317 static struct gdsc ufs_gdsc = {
3318         .gdscr = 0x75004,
3319         .pd = {
3320                 .name = "ufs",
3321         },
3322         .pwrsts = PWRSTS_OFF_ON,
3323 };
3324
3325 static struct clk_regmap *gcc_msm8996_clocks[] = {
3326         [GPLL0_EARLY] = &gpll0_early.clkr,
3327         [GPLL0] = &gpll0.clkr,
3328         [GPLL4_EARLY] = &gpll4_early.clkr,
3329         [GPLL4] = &gpll4.clkr,
3330         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3331         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3332         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3333         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3334         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3335         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3336         [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3337         [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3338         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3339         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3340         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3341         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3342         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3343         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3344         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3345         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3346         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3347         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3348         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3349         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3350         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3351         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3352         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3353         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3354         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3355         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3356         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3357         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3358         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3359         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3360         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3361         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3362         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3363         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3364         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3365         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3366         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3367         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3368         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3369         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3370         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3371         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3372         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3373         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3374         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3375         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3376         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3377         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3378         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3379         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3380         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3381         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3382         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3383         [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3384         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3385         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3386         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3387         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3388         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3389         [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3390         [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3391         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3392         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3393         [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3394         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3395         [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3396         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3397         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3398         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3399         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3400         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3401         [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3402         [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3403         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3404         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3405         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3406         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3407         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3408         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3409         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3410         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3411         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3412         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3413         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3414         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3415         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3416         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3417         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3418         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3419         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3420         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3421         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3422         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3423         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3424         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3425         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3426         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3427         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3428         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3429         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3430         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3431         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3432         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3433         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3434         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3435         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3436         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3437         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3438         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3439         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3440         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3441         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3442         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3443         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3444         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3445         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3446         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3447         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3448         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3449         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3450         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3451         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3452         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3453         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3454         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3455         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3456         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3457         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3458         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3459         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3460         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3461         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3462         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3463         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3464         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3465         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3466         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3467         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3468         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3469         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3470         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3471         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3472         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3473         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3474         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3475         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3476         [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3477         [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3478         [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3479         [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3480         [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3481         [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3482         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3483         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3484         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3485         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3486         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3487         [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3488         [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3489         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3490         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3491         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3492         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3493         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3494         [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3495         [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3496         [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3497         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3498         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3499         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3500         [GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
3501         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3502         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3503         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3504         [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3505         [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3506         [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3507         [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3508         [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3509         [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3510         [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3511         [GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
3512         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3513         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3514         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3515         [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
3516         [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
3517         [GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
3518         [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
3519         [GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
3520 };
3521
3522 static struct gdsc *gcc_msm8996_gdscs[] = {
3523         [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3524         [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3525         [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3526         [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3527         [USB30_GDSC] = &usb30_gdsc,
3528         [PCIE0_GDSC] = &pcie0_gdsc,
3529         [PCIE1_GDSC] = &pcie1_gdsc,
3530         [PCIE2_GDSC] = &pcie2_gdsc,
3531         [UFS_GDSC] = &ufs_gdsc,
3532 };
3533
3534 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3535         [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3536         [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3537         [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3538         [GCC_IMEM_BCR] = { 0x8000 },
3539         [GCC_MMSS_BCR] = { 0x9000 },
3540         [GCC_PIMEM_BCR] = { 0x0a000 },
3541         [GCC_QDSS_BCR] = { 0x0c000 },
3542         [GCC_USB_30_BCR] = { 0x0f000 },
3543         [GCC_USB_20_BCR] = { 0x12000 },
3544         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3545         [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3546         [GCC_USB3_PHY_BCR] = { 0x50020 },
3547         [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3548         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3549         [GCC_SDCC1_BCR] = { 0x13000 },
3550         [GCC_SDCC2_BCR] = { 0x14000 },
3551         [GCC_SDCC3_BCR] = { 0x15000 },
3552         [GCC_SDCC4_BCR] = { 0x16000 },
3553         [GCC_BLSP1_BCR] = { 0x17000 },
3554         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3555         [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3556         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3557         [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3558         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3559         [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3560         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3561         [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3562         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3563         [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3564         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3565         [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3566         [GCC_BLSP2_BCR] = { 0x25000 },
3567         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3568         [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3569         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3570         [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3571         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3572         [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3573         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3574         [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3575         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3576         [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3577         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3578         [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3579         [GCC_PDM_BCR] = { 0x33000 },
3580         [GCC_PRNG_BCR] = { 0x34000 },
3581         [GCC_TSIF_BCR] = { 0x36000 },
3582         [GCC_TCSR_BCR] = { 0x37000 },
3583         [GCC_BOOT_ROM_BCR] = { 0x38000 },
3584         [GCC_MSG_RAM_BCR] = { 0x39000 },
3585         [GCC_TLMM_BCR] = { 0x3a000 },
3586         [GCC_MPM_BCR] = { 0x3b000 },
3587         [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3588         [GCC_SPMI_BCR] = { 0x3f000 },
3589         [GCC_SPDM_BCR] = { 0x40000 },
3590         [GCC_CE1_BCR] = { 0x41000 },
3591         [GCC_BIMC_BCR] = { 0x44000 },
3592         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3593         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3594         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3595         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3596         [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3597         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3598         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3599         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3600         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3601         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3602         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3603         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3604         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3605         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3606         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3607         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3608         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3609         [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3610         [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3611         [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3612         [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3613         [GCC_APB2JTAG_BCR] = { 0x4c000 },
3614         [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3615         [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3616         [GCC_PCIE_0_BCR] = { 0x6b000 },
3617         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3618         [GCC_PCIE_1_BCR] = { 0x6d000 },
3619         [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3620         [GCC_PCIE_2_BCR] = { 0x6e000 },
3621         [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3622         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3623         [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3624         [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3625         [GCC_DCD_BCR] = { 0x70000 },
3626         [GCC_OBT_ODT_BCR] = { 0x73000 },
3627         [GCC_UFS_BCR] = { 0x75000 },
3628         [GCC_SSC_BCR] = { 0x63000 },
3629         [GCC_VS_BCR] = { 0x7a000 },
3630         [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3631         [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3632         [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3633         [GCC_DCC_BCR] = { 0x84000 },
3634         [GCC_IPA_BCR] = { 0x89000 },
3635         [GCC_QSPI_BCR] = { 0x8b000 },
3636         [GCC_SKL_BCR] = { 0x8c000 },
3637         [GCC_MSMPU_BCR] = { 0x8d000 },
3638         [GCC_MSS_Q6_BCR] = { 0x8e000 },
3639         [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3640         [GCC_MSS_RESTART] = { 0x8f008 },
3641 };
3642
3643 static const struct regmap_config gcc_msm8996_regmap_config = {
3644         .reg_bits       = 32,
3645         .reg_stride     = 4,
3646         .val_bits       = 32,
3647         .max_register   = 0x8f010,
3648         .fast_io        = true,
3649 };
3650
3651 static const struct qcom_cc_desc gcc_msm8996_desc = {
3652         .config = &gcc_msm8996_regmap_config,
3653         .clks = gcc_msm8996_clocks,
3654         .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3655         .resets = gcc_msm8996_resets,
3656         .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3657         .gdscs = gcc_msm8996_gdscs,
3658         .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3659 };
3660
3661 static const struct of_device_id gcc_msm8996_match_table[] = {
3662         { .compatible = "qcom,gcc-msm8996" },
3663         { }
3664 };
3665 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3666
3667 static int gcc_msm8996_probe(struct platform_device *pdev)
3668 {
3669         struct device *dev = &pdev->dev;
3670         int i, ret;
3671         struct regmap *regmap;
3672
3673         regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3674         if (IS_ERR(regmap))
3675                 return PTR_ERR(regmap);
3676
3677         /*
3678          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3679          * turned off by hardware during certain apps low power modes.
3680          */
3681         regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3682
3683         for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3684                 ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
3685                 if (ret)
3686                         return ret;
3687         }
3688
3689         return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3690 }
3691
3692 static struct platform_driver gcc_msm8996_driver = {
3693         .probe          = gcc_msm8996_probe,
3694         .driver         = {
3695                 .name   = "gcc-msm8996",
3696                 .of_match_table = gcc_msm8996_match_table,
3697         },
3698 };
3699
3700 static int __init gcc_msm8996_init(void)
3701 {
3702         return platform_driver_register(&gcc_msm8996_driver);
3703 }
3704 core_initcall(gcc_msm8996_init);
3705
3706 static void __exit gcc_msm8996_exit(void)
3707 {
3708         platform_driver_unregister(&gcc_msm8996_driver);
3709 }
3710 module_exit(gcc_msm8996_exit);
3711
3712 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3713 MODULE_LICENSE("GPL v2");
3714 MODULE_ALIAS("platform:gcc-msm8996");