drivers/clk/qcom/gcc-mdm9615.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  * Copyright (c) BayLibre, SAS.
   4  * Author : Neil Armstrong <narmstrong@baylibre.com>
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/bitops.h>
  18 #include <linux/err.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/clk-provider.h>
  24 #include <linux/regmap.h>
  25 #include <linux/reset-controller.h>
  26
  27 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
  28 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
  29
  30 #include "common.h"
  31 #include "clk-regmap.h"
  32 #include "clk-pll.h"
  33 #include "clk-rcg.h"
  34 #include "clk-branch.h"
  35 #include "reset.h"
  36
  37 static struct clk_fixed_factor cxo = {
  38         .mult = 1,
  39         .div = 1,
  40         .hw.init = &(struct clk_init_data){
  41                 .name = "cxo",
  42                 .parent_names = (const char *[]){ "cxo_board" },
  43                 .num_parents = 1,
  44                 .ops = &clk_fixed_factor_ops,
  45         },
  46 };
  47
  48 static struct clk_pll pll0 = {
  49         .l_reg = 0x30c4,
  50         .m_reg = 0x30c8,
  51         .n_reg = 0x30cc,
  52         .config_reg = 0x30d4,
  53         .mode_reg = 0x30c0,
  54         .status_reg = 0x30d8,
  55         .status_bit = 16,
  56         .clkr.hw.init = &(struct clk_init_data){
  57                 .name = "pll0",
  58                 .parent_names = (const char *[]){ "cxo" },
  59                 .num_parents = 1,
  60                 .ops = &clk_pll_ops,
  61         },
  62 };
  63
  64 static struct clk_regmap pll0_vote = {
  65         .enable_reg = 0x34c0,
  66         .enable_mask = BIT(0),
  67         .hw.init = &(struct clk_init_data){
  68                 .name = "pll0_vote",
  69                 .parent_names = (const char *[]){ "pll8" },
  70                 .num_parents = 1,
  71                 .ops = &clk_pll_vote_ops,
  72         },
  73 };
  74
  75 static struct clk_regmap pll4_vote = {
  76         .enable_reg = 0x34c0,
  77         .enable_mask = BIT(4),
  78         .hw.init = &(struct clk_init_data){
  79                 .name = "pll4_vote",
  80                 .parent_names = (const char *[]){ "pll4" },
  81                 .num_parents = 1,
  82                 .ops = &clk_pll_vote_ops,
  83         },
  84 };
  85
  86 static struct clk_pll pll8 = {
  87         .l_reg = 0x3144,
  88         .m_reg = 0x3148,
  89         .n_reg = 0x314c,
  90         .config_reg = 0x3154,
  91         .mode_reg = 0x3140,
  92         .status_reg = 0x3158,
  93         .status_bit = 16,
  94         .clkr.hw.init = &(struct clk_init_data){
  95                 .name = "pll8",
  96                 .parent_names = (const char *[]){ "cxo" },
  97                 .num_parents = 1,
  98                 .ops = &clk_pll_ops,
  99         },
 100 };
 101
 102 static struct clk_regmap pll8_vote = {
 103         .enable_reg = 0x34c0,
 104         .enable_mask = BIT(8),
 105         .hw.init = &(struct clk_init_data){
 106                 .name = "pll8_vote",
 107                 .parent_names = (const char *[]){ "pll8" },
 108                 .num_parents = 1,
 109                 .ops = &clk_pll_vote_ops,
 110         },
 111 };
 112
 113 static struct clk_pll pll14 = {
 114         .l_reg = 0x31c4,
 115         .m_reg = 0x31c8,
 116         .n_reg = 0x31cc,
 117         .config_reg = 0x31d4,
 118         .mode_reg = 0x31c0,
 119         .status_reg = 0x31d8,
 120         .status_bit = 16,
 121         .clkr.hw.init = &(struct clk_init_data){
 122                 .name = "pll14",
 123                 .parent_names = (const char *[]){ "cxo" },
 124                 .num_parents = 1,
 125                 .ops = &clk_pll_ops,
 126         },
 127 };
 128
 129 static struct clk_regmap pll14_vote = {
 130         .enable_reg = 0x34c0,
 131         .enable_mask = BIT(11),
 132         .hw.init = &(struct clk_init_data){
 133                 .name = "pll14_vote",
 134                 .parent_names = (const char *[]){ "pll14" },
 135                 .num_parents = 1,
 136                 .ops = &clk_pll_vote_ops,
 137         },
 138 };
 139
 140 enum {
 141         P_CXO,
 142         P_PLL8,
 143         P_PLL14,
 144 };
 145
 146 static const struct parent_map gcc_cxo_pll8_map[] = {
 147         { P_CXO, 0 },
 148         { P_PLL8, 3 }
 149 };
 150
 151 static const char * const gcc_cxo_pll8[] = {
 152         "cxo",
 153         "pll8_vote",
 154 };
 155
 156 static const struct parent_map gcc_cxo_pll14_map[] = {
 157         { P_CXO, 0 },
 158         { P_PLL14, 4 }
 159 };
 160
 161 static const char * const gcc_cxo_pll14[] = {
 162         "cxo",
 163         "pll14_vote",
 164 };
 165
 166 static const struct parent_map gcc_cxo_map[] = {
 167         { P_CXO, 0 },
 168 };
 169
 170 static const char * const gcc_cxo[] = {
 171         "cxo",
 172 };
 173
 174 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 175         {  1843200, P_PLL8, 2,  6, 625 },
 176         {  3686400, P_PLL8, 2, 12, 625 },
 177         {  7372800, P_PLL8, 2, 24, 625 },
 178         { 14745600, P_PLL8, 2, 48, 625 },
 179         { 16000000, P_PLL8, 4,  1,   6 },
 180         { 24000000, P_PLL8, 4,  1,   4 },
 181         { 32000000, P_PLL8, 4,  1,   3 },
 182         { 40000000, P_PLL8, 1,  5,  48 },
 183         { 46400000, P_PLL8, 1, 29, 240 },
 184         { 48000000, P_PLL8, 4,  1,   2 },
 185         { 51200000, P_PLL8, 1,  2,  15 },
 186         { 56000000, P_PLL8, 1,  7,  48 },
 187         { 58982400, P_PLL8, 1, 96, 625 },
 188         { 64000000, P_PLL8, 2,  1,   3 },
 189         { }
 190 };
 191
 192 static struct clk_rcg gsbi1_uart_src = {
 193         .ns_reg = 0x29d4,
 194         .md_reg = 0x29d0,
 195         .mn = {
 196                 .mnctr_en_bit = 8,
 197                 .mnctr_reset_bit = 7,
 198                 .mnctr_mode_shift = 5,
 199                 .n_val_shift = 16,
 200                 .m_val_shift = 16,
 201                 .width = 16,
 202         },
 203         .p = {
 204                 .pre_div_shift = 3,
 205                 .pre_div_width = 2,
 206         },
 207         .s = {
 208                 .src_sel_shift = 0,
 209                 .parent_map = gcc_cxo_pll8_map,
 210         },
 211         .freq_tbl = clk_tbl_gsbi_uart,
 212         .clkr = {
 213                 .enable_reg = 0x29d4,
 214                 .enable_mask = BIT(11),
 215                 .hw.init = &(struct clk_init_data){
 216                         .name = "gsbi1_uart_src",
 217                         .parent_names = gcc_cxo_pll8,
 218                         .num_parents = 2,
 219                         .ops = &clk_rcg_ops,
 220                         .flags = CLK_SET_PARENT_GATE,
 221                 },
 222         },
 223 };
 224
 225 static struct clk_branch gsbi1_uart_clk = {
 226         .halt_reg = 0x2fcc,
 227         .halt_bit = 10,
 228         .clkr = {
 229                 .enable_reg = 0x29d4,
 230                 .enable_mask = BIT(9),
 231                 .hw.init = &(struct clk_init_data){
 232                         .name = "gsbi1_uart_clk",
 233                         .parent_names = (const char *[]){
 234                                 "gsbi1_uart_src",
 235                         },
 236                         .num_parents = 1,
 237                         .ops = &clk_branch_ops,
 238                         .flags = CLK_SET_RATE_PARENT,
 239                 },
 240         },
 241 };
 242
 243 static struct clk_rcg gsbi2_uart_src = {
 244         .ns_reg = 0x29f4,
 245         .md_reg = 0x29f0,
 246         .mn = {
 247                 .mnctr_en_bit = 8,
 248                 .mnctr_reset_bit = 7,
 249                 .mnctr_mode_shift = 5,
 250                 .n_val_shift = 16,
 251                 .m_val_shift = 16,
 252                 .width = 16,
 253         },
 254         .p = {
 255                 .pre_div_shift = 3,
 256                 .pre_div_width = 2,
 257         },
 258         .s = {
 259                 .src_sel_shift = 0,
 260                 .parent_map = gcc_cxo_pll8_map,
 261         },
 262         .freq_tbl = clk_tbl_gsbi_uart,
 263         .clkr = {
 264                 .enable_reg = 0x29f4,
 265                 .enable_mask = BIT(11),
 266                 .hw.init = &(struct clk_init_data){
 267                         .name = "gsbi2_uart_src",
 268                         .parent_names = gcc_cxo_pll8,
 269                         .num_parents = 2,
 270                         .ops = &clk_rcg_ops,
 271                         .flags = CLK_SET_PARENT_GATE,
 272                 },
 273         },
 274 };
 275
 276 static struct clk_branch gsbi2_uart_clk = {
 277         .halt_reg = 0x2fcc,
 278         .halt_bit = 6,
 279         .clkr = {
 280                 .enable_reg = 0x29f4,
 281                 .enable_mask = BIT(9),
 282                 .hw.init = &(struct clk_init_data){
 283                         .name = "gsbi2_uart_clk",
 284                         .parent_names = (const char *[]){
 285                                 "gsbi2_uart_src",
 286                         },
 287                         .num_parents = 1,
 288                         .ops = &clk_branch_ops,
 289                         .flags = CLK_SET_RATE_PARENT,
 290                 },
 291         },
 292 };
 293
 294 static struct clk_rcg gsbi3_uart_src = {
 295         .ns_reg = 0x2a14,
 296         .md_reg = 0x2a10,
 297         .mn = {
 298                 .mnctr_en_bit = 8,
 299                 .mnctr_reset_bit = 7,
 300                 .mnctr_mode_shift = 5,
 301                 .n_val_shift = 16,
 302                 .m_val_shift = 16,
 303                 .width = 16,
 304         },
 305         .p = {
 306                 .pre_div_shift = 3,
 307                 .pre_div_width = 2,
 308         },
 309         .s = {
 310                 .src_sel_shift = 0,
 311                 .parent_map = gcc_cxo_pll8_map,
 312         },
 313         .freq_tbl = clk_tbl_gsbi_uart,
 314         .clkr = {
 315                 .enable_reg = 0x2a14,
 316                 .enable_mask = BIT(11),
 317                 .hw.init = &(struct clk_init_data){
 318                         .name = "gsbi3_uart_src",
 319                         .parent_names = gcc_cxo_pll8,
 320                         .num_parents = 2,
 321                         .ops = &clk_rcg_ops,
 322                         .flags = CLK_SET_PARENT_GATE,
 323                 },
 324         },
 325 };
 326
 327 static struct clk_branch gsbi3_uart_clk = {
 328         .halt_reg = 0x2fcc,
 329         .halt_bit = 2,
 330         .clkr = {
 331                 .enable_reg = 0x2a14,
 332                 .enable_mask = BIT(9),
 333                 .hw.init = &(struct clk_init_data){
 334                         .name = "gsbi3_uart_clk",
 335                         .parent_names = (const char *[]){
 336                                 "gsbi3_uart_src",
 337                         },
 338                         .num_parents = 1,
 339                         .ops = &clk_branch_ops,
 340                         .flags = CLK_SET_RATE_PARENT,
 341                 },
 342         },
 343 };
 344
 345 static struct clk_rcg gsbi4_uart_src = {
 346         .ns_reg = 0x2a34,
 347         .md_reg = 0x2a30,
 348         .mn = {
 349                 .mnctr_en_bit = 8,
 350                 .mnctr_reset_bit = 7,
 351                 .mnctr_mode_shift = 5,
 352                 .n_val_shift = 16,
 353                 .m_val_shift = 16,
 354                 .width = 16,
 355         },
 356         .p = {
 357                 .pre_div_shift = 3,
 358                 .pre_div_width = 2,
 359         },
 360         .s = {
 361                 .src_sel_shift = 0,
 362                 .parent_map = gcc_cxo_pll8_map,
 363         },
 364         .freq_tbl = clk_tbl_gsbi_uart,
 365         .clkr = {
 366                 .enable_reg = 0x2a34,
 367                 .enable_mask = BIT(11),
 368                 .hw.init = &(struct clk_init_data){
 369                         .name = "gsbi4_uart_src",
 370                         .parent_names = gcc_cxo_pll8,
 371                         .num_parents = 2,
 372                         .ops = &clk_rcg_ops,
 373                         .flags = CLK_SET_PARENT_GATE,
 374                 },
 375         },
 376 };
 377
 378 static struct clk_branch gsbi4_uart_clk = {
 379         .halt_reg = 0x2fd0,
 380         .halt_bit = 26,
 381         .clkr = {
 382                 .enable_reg = 0x2a34,
 383                 .enable_mask = BIT(9),
 384                 .hw.init = &(struct clk_init_data){
 385                         .name = "gsbi4_uart_clk",
 386                         .parent_names = (const char *[]){
 387                                 "gsbi4_uart_src",
 388                         },
 389                         .num_parents = 1,
 390                         .ops = &clk_branch_ops,
 391                         .flags = CLK_SET_RATE_PARENT,
 392                 },
 393         },
 394 };
 395
 396 static struct clk_rcg gsbi5_uart_src = {
 397         .ns_reg = 0x2a54,
 398         .md_reg = 0x2a50,
 399         .mn = {
 400                 .mnctr_en_bit = 8,
 401                 .mnctr_reset_bit = 7,
 402                 .mnctr_mode_shift = 5,
 403                 .n_val_shift = 16,
 404                 .m_val_shift = 16,
 405                 .width = 16,
 406         },
 407         .p = {
 408                 .pre_div_shift = 3,
 409                 .pre_div_width = 2,
 410         },
 411         .s = {
 412                 .src_sel_shift = 0,
 413                 .parent_map = gcc_cxo_pll8_map,
 414         },
 415         .freq_tbl = clk_tbl_gsbi_uart,
 416         .clkr = {
 417                 .enable_reg = 0x2a54,
 418                 .enable_mask = BIT(11),
 419                 .hw.init = &(struct clk_init_data){
 420                         .name = "gsbi5_uart_src",
 421                         .parent_names = gcc_cxo_pll8,
 422                         .num_parents = 2,
 423                         .ops = &clk_rcg_ops,
 424                         .flags = CLK_SET_PARENT_GATE,
 425                 },
 426         },
 427 };
 428
 429 static struct clk_branch gsbi5_uart_clk = {
 430         .halt_reg = 0x2fd0,
 431         .halt_bit = 22,
 432         .clkr = {
 433                 .enable_reg = 0x2a54,
 434                 .enable_mask = BIT(9),
 435                 .hw.init = &(struct clk_init_data){
 436                         .name = "gsbi5_uart_clk",
 437                         .parent_names = (const char *[]){
 438                                 "gsbi5_uart_src",
 439                         },
 440                         .num_parents = 1,
 441                         .ops = &clk_branch_ops,
 442                         .flags = CLK_SET_RATE_PARENT,
 443                 },
 444         },
 445 };
 446
 447 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 448         {   960000, P_CXO,  4, 1,  5 },
 449         {  4800000, P_CXO,  4, 0,  1 },
 450         {  9600000, P_CXO,  2, 0,  1 },
 451         { 15060000, P_PLL8, 1, 2, 51 },
 452         { 24000000, P_PLL8, 4, 1,  4 },
 453         { 25600000, P_PLL8, 1, 1, 15 },
 454         { 48000000, P_PLL8, 4, 1,  2 },
 455         { 51200000, P_PLL8, 1, 2, 15 },
 456         { }
 457 };
 458
 459 static struct clk_rcg gsbi1_qup_src = {
 460         .ns_reg = 0x29cc,
 461         .md_reg = 0x29c8,
 462         .mn = {
 463                 .mnctr_en_bit = 8,
 464                 .mnctr_reset_bit = 7,
 465                 .mnctr_mode_shift = 5,
 466                 .n_val_shift = 16,
 467                 .m_val_shift = 16,
 468                 .width = 8,
 469         },
 470         .p = {
 471                 .pre_div_shift = 3,
 472                 .pre_div_width = 2,
 473         },
 474         .s = {
 475                 .src_sel_shift = 0,
 476                 .parent_map = gcc_cxo_pll8_map,
 477         },
 478         .freq_tbl = clk_tbl_gsbi_qup,
 479         .clkr = {
 480                 .enable_reg = 0x29cc,
 481                 .enable_mask = BIT(11),
 482                 .hw.init = &(struct clk_init_data){
 483                         .name = "gsbi1_qup_src",
 484                         .parent_names = gcc_cxo_pll8,
 485                         .num_parents = 2,
 486                         .ops = &clk_rcg_ops,
 487                         .flags = CLK_SET_PARENT_GATE,
 488                 },
 489         },
 490 };
 491
 492 static struct clk_branch gsbi1_qup_clk = {
 493         .halt_reg = 0x2fcc,
 494         .halt_bit = 9,
 495         .clkr = {
 496                 .enable_reg = 0x29cc,
 497                 .enable_mask = BIT(9),
 498                 .hw.init = &(struct clk_init_data){
 499                         .name = "gsbi1_qup_clk",
 500                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 501                         .num_parents = 1,
 502                         .ops = &clk_branch_ops,
 503                         .flags = CLK_SET_RATE_PARENT,
 504                 },
 505         },
 506 };
 507
 508 static struct clk_rcg gsbi2_qup_src = {
 509         .ns_reg = 0x29ec,
 510         .md_reg = 0x29e8,
 511         .mn = {
 512                 .mnctr_en_bit = 8,
 513                 .mnctr_reset_bit = 7,
 514                 .mnctr_mode_shift = 5,
 515                 .n_val_shift = 16,
 516                 .m_val_shift = 16,
 517                 .width = 8,
 518         },
 519         .p = {
 520                 .pre_div_shift = 3,
 521                 .pre_div_width = 2,
 522         },
 523         .s = {
 524                 .src_sel_shift = 0,
 525                 .parent_map = gcc_cxo_pll8_map,
 526         },
 527         .freq_tbl = clk_tbl_gsbi_qup,
 528         .clkr = {
 529                 .enable_reg = 0x29ec,
 530                 .enable_mask = BIT(11),
 531                 .hw.init = &(struct clk_init_data){
 532                         .name = "gsbi2_qup_src",
 533                         .parent_names = gcc_cxo_pll8,
 534                         .num_parents = 2,
 535                         .ops = &clk_rcg_ops,
 536                         .flags = CLK_SET_PARENT_GATE,
 537                 },
 538         },
 539 };
 540
 541 static struct clk_branch gsbi2_qup_clk = {
 542         .halt_reg = 0x2fcc,
 543         .halt_bit = 4,
 544         .clkr = {
 545                 .enable_reg = 0x29ec,
 546                 .enable_mask = BIT(9),
 547                 .hw.init = &(struct clk_init_data){
 548                         .name = "gsbi2_qup_clk",
 549                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 550                         .num_parents = 1,
 551                         .ops = &clk_branch_ops,
 552                         .flags = CLK_SET_RATE_PARENT,
 553                 },
 554         },
 555 };
 556
 557 static struct clk_rcg gsbi3_qup_src = {
 558         .ns_reg = 0x2a0c,
 559         .md_reg = 0x2a08,
 560         .mn = {
 561                 .mnctr_en_bit = 8,
 562                 .mnctr_reset_bit = 7,
 563                 .mnctr_mode_shift = 5,
 564                 .n_val_shift = 16,
 565                 .m_val_shift = 16,
 566                 .width = 8,
 567         },
 568         .p = {
 569                 .pre_div_shift = 3,
 570                 .pre_div_width = 2,
 571         },
 572         .s = {
 573                 .src_sel_shift = 0,
 574                 .parent_map = gcc_cxo_pll8_map,
 575         },
 576         .freq_tbl = clk_tbl_gsbi_qup,
 577         .clkr = {
 578                 .enable_reg = 0x2a0c,
 579                 .enable_mask = BIT(11),
 580                 .hw.init = &(struct clk_init_data){
 581                         .name = "gsbi3_qup_src",
 582                         .parent_names = gcc_cxo_pll8,
 583                         .num_parents = 2,
 584                         .ops = &clk_rcg_ops,
 585                         .flags = CLK_SET_PARENT_GATE,
 586                 },
 587         },
 588 };
 589
 590 static struct clk_branch gsbi3_qup_clk = {
 591         .halt_reg = 0x2fcc,
 592         .halt_bit = 0,
 593         .clkr = {
 594                 .enable_reg = 0x2a0c,
 595                 .enable_mask = BIT(9),
 596                 .hw.init = &(struct clk_init_data){
 597                         .name = "gsbi3_qup_clk",
 598                         .parent_names = (const char *[]){ "gsbi3_qup_src" },
 599                         .num_parents = 1,
 600                         .ops = &clk_branch_ops,
 601                         .flags = CLK_SET_RATE_PARENT,
 602                 },
 603         },
 604 };
 605
 606 static struct clk_rcg gsbi4_qup_src = {
 607         .ns_reg = 0x2a2c,
 608         .md_reg = 0x2a28,
 609         .mn = {
 610                 .mnctr_en_bit = 8,
 611                 .mnctr_reset_bit = 7,
 612                 .mnctr_mode_shift = 5,
 613                 .n_val_shift = 16,
 614                 .m_val_shift = 16,
 615                 .width = 8,
 616         },
 617         .p = {
 618                 .pre_div_shift = 3,
 619                 .pre_div_width = 2,
 620         },
 621         .s = {
 622                 .src_sel_shift = 0,
 623                 .parent_map = gcc_cxo_pll8_map,
 624         },
 625         .freq_tbl = clk_tbl_gsbi_qup,
 626         .clkr = {
 627                 .enable_reg = 0x2a2c,
 628                 .enable_mask = BIT(11),
 629                 .hw.init = &(struct clk_init_data){
 630                         .name = "gsbi4_qup_src",
 631                         .parent_names = gcc_cxo_pll8,
 632                         .num_parents = 2,
 633                         .ops = &clk_rcg_ops,
 634                         .flags = CLK_SET_PARENT_GATE,
 635                 },
 636         },
 637 };
 638
 639 static struct clk_branch gsbi4_qup_clk = {
 640         .halt_reg = 0x2fd0,
 641         .halt_bit = 24,
 642         .clkr = {
 643                 .enable_reg = 0x2a2c,
 644                 .enable_mask = BIT(9),
 645                 .hw.init = &(struct clk_init_data){
 646                         .name = "gsbi4_qup_clk",
 647                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 648                         .num_parents = 1,
 649                         .ops = &clk_branch_ops,
 650                         .flags = CLK_SET_RATE_PARENT,
 651                 },
 652         },
 653 };
 654
 655 static struct clk_rcg gsbi5_qup_src = {
 656         .ns_reg = 0x2a4c,
 657         .md_reg = 0x2a48,
 658         .mn = {
 659                 .mnctr_en_bit = 8,
 660                 .mnctr_reset_bit = 7,
 661                 .mnctr_mode_shift = 5,
 662                 .n_val_shift = 16,
 663                 .m_val_shift = 16,
 664                 .width = 8,
 665         },
 666         .p = {
 667                 .pre_div_shift = 3,
 668                 .pre_div_width = 2,
 669         },
 670         .s = {
 671                 .src_sel_shift = 0,
 672                 .parent_map = gcc_cxo_pll8_map,
 673         },
 674         .freq_tbl = clk_tbl_gsbi_qup,
 675         .clkr = {
 676                 .enable_reg = 0x2a4c,
 677                 .enable_mask = BIT(11),
 678                 .hw.init = &(struct clk_init_data){
 679                         .name = "gsbi5_qup_src",
 680                         .parent_names = gcc_cxo_pll8,
 681                         .num_parents = 2,
 682                         .ops = &clk_rcg_ops,
 683                         .flags = CLK_SET_PARENT_GATE,
 684                 },
 685         },
 686 };
 687
 688 static struct clk_branch gsbi5_qup_clk = {
 689         .halt_reg = 0x2fd0,
 690         .halt_bit = 20,
 691         .clkr = {
 692                 .enable_reg = 0x2a4c,
 693                 .enable_mask = BIT(9),
 694                 .hw.init = &(struct clk_init_data){
 695                         .name = "gsbi5_qup_clk",
 696                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
 697                         .num_parents = 1,
 698                         .ops = &clk_branch_ops,
 699                         .flags = CLK_SET_RATE_PARENT,
 700                 },
 701         },
 702 };
 703
 704 static const struct freq_tbl clk_tbl_gp[] = {
 705         { 9600000, P_CXO,  2, 0, 0 },
 706         { 19200000, P_CXO,  1, 0, 0 },
 707         { }
 708 };
 709
 710 static struct clk_rcg gp0_src = {
 711         .ns_reg = 0x2d24,
 712         .md_reg = 0x2d00,
 713         .mn = {
 714                 .mnctr_en_bit = 8,
 715                 .mnctr_reset_bit = 7,
 716                 .mnctr_mode_shift = 5,
 717                 .n_val_shift = 16,
 718                 .m_val_shift = 16,
 719                 .width = 8,
 720         },
 721         .p = {
 722                 .pre_div_shift = 3,
 723                 .pre_div_width = 2,
 724         },
 725         .s = {
 726                 .src_sel_shift = 0,
 727                 .parent_map = gcc_cxo_map,
 728         },
 729         .freq_tbl = clk_tbl_gp,
 730         .clkr = {
 731                 .enable_reg = 0x2d24,
 732                 .enable_mask = BIT(11),
 733                 .hw.init = &(struct clk_init_data){
 734                         .name = "gp0_src",
 735                         .parent_names = gcc_cxo,
 736                         .num_parents = 1,
 737                         .ops = &clk_rcg_ops,
 738                         .flags = CLK_SET_PARENT_GATE,
 739                 },
 740         }
 741 };
 742
 743 static struct clk_branch gp0_clk = {
 744         .halt_reg = 0x2fd8,
 745         .halt_bit = 7,
 746         .clkr = {
 747                 .enable_reg = 0x2d24,
 748                 .enable_mask = BIT(9),
 749                 .hw.init = &(struct clk_init_data){
 750                         .name = "gp0_clk",
 751                         .parent_names = (const char *[]){ "gp0_src" },
 752                         .num_parents = 1,
 753                         .ops = &clk_branch_ops,
 754                         .flags = CLK_SET_RATE_PARENT,
 755                 },
 756         },
 757 };
 758
 759 static struct clk_rcg gp1_src = {
 760         .ns_reg = 0x2d44,
 761         .md_reg = 0x2d40,
 762         .mn = {
 763                 .mnctr_en_bit = 8,
 764                 .mnctr_reset_bit = 7,
 765                 .mnctr_mode_shift = 5,
 766                 .n_val_shift = 16,
 767                 .m_val_shift = 16,
 768                 .width = 8,
 769         },
 770         .p = {
 771                 .pre_div_shift = 3,
 772                 .pre_div_width = 2,
 773         },
 774         .s = {
 775                 .src_sel_shift = 0,
 776                 .parent_map = gcc_cxo_map,
 777         },
 778         .freq_tbl = clk_tbl_gp,
 779         .clkr = {
 780                 .enable_reg = 0x2d44,
 781                 .enable_mask = BIT(11),
 782                 .hw.init = &(struct clk_init_data){
 783                         .name = "gp1_src",
 784                         .parent_names = gcc_cxo,
 785                         .num_parents = 1,
 786                         .ops = &clk_rcg_ops,
 787                         .flags = CLK_SET_RATE_GATE,
 788                 },
 789         }
 790 };
 791
 792 static struct clk_branch gp1_clk = {
 793         .halt_reg = 0x2fd8,
 794         .halt_bit = 6,
 795         .clkr = {
 796                 .enable_reg = 0x2d44,
 797                 .enable_mask = BIT(9),
 798                 .hw.init = &(struct clk_init_data){
 799                         .name = "gp1_clk",
 800                         .parent_names = (const char *[]){ "gp1_src" },
 801                         .num_parents = 1,
 802                         .ops = &clk_branch_ops,
 803                         .flags = CLK_SET_RATE_PARENT,
 804                 },
 805         },
 806 };
 807
 808 static struct clk_rcg gp2_src = {
 809         .ns_reg = 0x2d64,
 810         .md_reg = 0x2d60,
 811         .mn = {
 812                 .mnctr_en_bit = 8,
 813                 .mnctr_reset_bit = 7,
 814                 .mnctr_mode_shift = 5,
 815                 .n_val_shift = 16,
 816                 .m_val_shift = 16,
 817                 .width = 8,
 818         },
 819         .p = {
 820                 .pre_div_shift = 3,
 821                 .pre_div_width = 2,
 822         },
 823         .s = {
 824                 .src_sel_shift = 0,
 825                 .parent_map = gcc_cxo_map,
 826         },
 827         .freq_tbl = clk_tbl_gp,
 828         .clkr = {
 829                 .enable_reg = 0x2d64,
 830                 .enable_mask = BIT(11),
 831                 .hw.init = &(struct clk_init_data){
 832                         .name = "gp2_src",
 833                         .parent_names = gcc_cxo,
 834                         .num_parents = 1,
 835                         .ops = &clk_rcg_ops,
 836                         .flags = CLK_SET_RATE_GATE,
 837                 },
 838         }
 839 };
 840
 841 static struct clk_branch gp2_clk = {
 842         .halt_reg = 0x2fd8,
 843         .halt_bit = 5,
 844         .clkr = {
 845                 .enable_reg = 0x2d64,
 846                 .enable_mask = BIT(9),
 847                 .hw.init = &(struct clk_init_data){
 848                         .name = "gp2_clk",
 849                         .parent_names = (const char *[]){ "gp2_src" },
 850                         .num_parents = 1,
 851                         .ops = &clk_branch_ops,
 852                         .flags = CLK_SET_RATE_PARENT,
 853                 },
 854         },
 855 };
 856
 857 static struct clk_branch pmem_clk = {
 858         .hwcg_reg = 0x25a0,
 859         .hwcg_bit = 6,
 860         .halt_reg = 0x2fc8,
 861         .halt_bit = 20,
 862         .clkr = {
 863                 .enable_reg = 0x25a0,
 864                 .enable_mask = BIT(4),
 865                 .hw.init = &(struct clk_init_data){
 866                         .name = "pmem_clk",
 867                         .ops = &clk_branch_ops,
 868                 },
 869         },
 870 };
 871
 872 static struct clk_rcg prng_src = {
 873         .ns_reg = 0x2e80,
 874         .p = {
 875                 .pre_div_shift = 3,
 876                 .pre_div_width = 4,
 877         },
 878         .s = {
 879                 .src_sel_shift = 0,
 880                 .parent_map = gcc_cxo_pll8_map,
 881         },
 882         .clkr = {
 883                 .hw.init = &(struct clk_init_data){
 884                         .name = "prng_src",
 885                         .parent_names = gcc_cxo_pll8,
 886                         .num_parents = 2,
 887                         .ops = &clk_rcg_ops,
 888                 },
 889         },
 890 };
 891
 892 static struct clk_branch prng_clk = {
 893         .halt_reg = 0x2fd8,
 894         .halt_check = BRANCH_HALT_VOTED,
 895         .halt_bit = 10,
 896         .clkr = {
 897                 .enable_reg = 0x3080,
 898                 .enable_mask = BIT(10),
 899                 .hw.init = &(struct clk_init_data){
 900                         .name = "prng_clk",
 901                         .parent_names = (const char *[]){ "prng_src" },
 902                         .num_parents = 1,
 903                         .ops = &clk_branch_ops,
 904                 },
 905         },
 906 };
 907
 908 static const struct freq_tbl clk_tbl_sdc[] = {
 909         {    144000, P_CXO,   1, 1, 133 },
 910         {    400000, P_PLL8,  4, 1, 240 },
 911         {  16000000, P_PLL8,  4, 1,   6 },
 912         {  17070000, P_PLL8,  1, 2,  45 },
 913         {  20210000, P_PLL8,  1, 1,  19 },
 914         {  24000000, P_PLL8,  4, 1,   4 },
 915         {  38400000, P_PLL8,  2, 1,   5 },
 916         {  48000000, P_PLL8,  4, 1,   2 },
 917         {  64000000, P_PLL8,  3, 1,   2 },
 918         {  76800000, P_PLL8,  1, 1,   5 },
 919         { }
 920 };
 921
 922 static struct clk_rcg sdc1_src = {
 923         .ns_reg = 0x282c,
 924         .md_reg = 0x2828,
 925         .mn = {
 926                 .mnctr_en_bit = 8,
 927                 .mnctr_reset_bit = 7,
 928                 .mnctr_mode_shift = 5,
 929                 .n_val_shift = 16,
 930                 .m_val_shift = 16,
 931                 .width = 8,
 932         },
 933         .p = {
 934                 .pre_div_shift = 3,
 935                 .pre_div_width = 2,
 936         },
 937         .s = {
 938                 .src_sel_shift = 0,
 939                 .parent_map = gcc_cxo_pll8_map,
 940         },
 941         .freq_tbl = clk_tbl_sdc,
 942         .clkr = {
 943                 .enable_reg = 0x282c,
 944                 .enable_mask = BIT(11),
 945                 .hw.init = &(struct clk_init_data){
 946                         .name = "sdc1_src",
 947                         .parent_names = gcc_cxo_pll8,
 948                         .num_parents = 2,
 949                         .ops = &clk_rcg_ops,
 950                 },
 951         }
 952 };
 953
 954 static struct clk_branch sdc1_clk = {
 955         .halt_reg = 0x2fc8,
 956         .halt_bit = 6,
 957         .clkr = {
 958                 .enable_reg = 0x282c,
 959                 .enable_mask = BIT(9),
 960                 .hw.init = &(struct clk_init_data){
 961                         .name = "sdc1_clk",
 962                         .parent_names = (const char *[]){ "sdc1_src" },
 963                         .num_parents = 1,
 964                         .ops = &clk_branch_ops,
 965                         .flags = CLK_SET_RATE_PARENT,
 966                 },
 967         },
 968 };
 969
 970 static struct clk_rcg sdc2_src = {
 971         .ns_reg = 0x284c,
 972         .md_reg = 0x2848,
 973         .mn = {
 974                 .mnctr_en_bit = 8,
 975                 .mnctr_reset_bit = 7,
 976                 .mnctr_mode_shift = 5,
 977                 .n_val_shift = 16,
 978                 .m_val_shift = 16,
 979                 .width = 8,
 980         },
 981         .p = {
 982                 .pre_div_shift = 3,
 983                 .pre_div_width = 2,
 984         },
 985         .s = {
 986                 .src_sel_shift = 0,
 987                 .parent_map = gcc_cxo_pll8_map,
 988         },
 989         .freq_tbl = clk_tbl_sdc,
 990         .clkr = {
 991                 .enable_reg = 0x284c,
 992                 .enable_mask = BIT(11),
 993                 .hw.init = &(struct clk_init_data){
 994                         .name = "sdc2_src",
 995                         .parent_names = gcc_cxo_pll8,
 996                         .num_parents = 2,
 997                         .ops = &clk_rcg_ops,
 998                 },
 999         }
1000 };
1001
1002 static struct clk_branch sdc2_clk = {
1003         .halt_reg = 0x2fc8,
1004         .halt_bit = 5,
1005         .clkr = {
1006                 .enable_reg = 0x284c,
1007                 .enable_mask = BIT(9),
1008                 .hw.init = &(struct clk_init_data){
1009                         .name = "sdc2_clk",
1010                         .parent_names = (const char *[]){ "sdc2_src" },
1011                         .num_parents = 1,
1012                         .ops = &clk_branch_ops,
1013                         .flags = CLK_SET_RATE_PARENT,
1014                 },
1015         },
1016 };
1017
1018 static const struct freq_tbl clk_tbl_usb[] = {
1019         { 60000000, P_PLL8, 1, 5, 32 },
1020         { }
1021 };
1022
1023 static struct clk_rcg usb_hs1_xcvr_src = {
1024         .ns_reg = 0x290c,
1025         .md_reg = 0x2908,
1026         .mn = {
1027                 .mnctr_en_bit = 8,
1028                 .mnctr_reset_bit = 7,
1029                 .mnctr_mode_shift = 5,
1030                 .n_val_shift = 16,
1031                 .m_val_shift = 16,
1032                 .width = 8,
1033         },
1034         .p = {
1035                 .pre_div_shift = 3,
1036                 .pre_div_width = 2,
1037         },
1038         .s = {
1039                 .src_sel_shift = 0,
1040                 .parent_map = gcc_cxo_pll8_map,
1041         },
1042         .freq_tbl = clk_tbl_usb,
1043         .clkr = {
1044                 .enable_reg = 0x290c,
1045                 .enable_mask = BIT(11),
1046                 .hw.init = &(struct clk_init_data){
1047                         .name = "usb_hs1_xcvr_src",
1048                         .parent_names = gcc_cxo_pll8,
1049                         .num_parents = 2,
1050                         .ops = &clk_rcg_ops,
1051                         .flags = CLK_SET_RATE_GATE,
1052                 },
1053         }
1054 };
1055
1056 static struct clk_branch usb_hs1_xcvr_clk = {
1057         .halt_reg = 0x2fc8,
1058         .halt_bit = 0,
1059         .clkr = {
1060                 .enable_reg = 0x290c,
1061                 .enable_mask = BIT(9),
1062                 .hw.init = &(struct clk_init_data){
1063                         .name = "usb_hs1_xcvr_clk",
1064                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1065                         .num_parents = 1,
1066                         .ops = &clk_branch_ops,
1067                         .flags = CLK_SET_RATE_PARENT,
1068                 },
1069         },
1070 };
1071
1072 static struct clk_rcg usb_hsic_xcvr_fs_src = {
1073         .ns_reg = 0x2928,
1074         .md_reg = 0x2924,
1075         .mn = {
1076                 .mnctr_en_bit = 8,
1077                 .mnctr_reset_bit = 7,
1078                 .mnctr_mode_shift = 5,
1079                 .n_val_shift = 16,
1080                 .m_val_shift = 16,
1081                 .width = 8,
1082         },
1083         .p = {
1084                 .pre_div_shift = 3,
1085                 .pre_div_width = 2,
1086         },
1087         .s = {
1088                 .src_sel_shift = 0,
1089                 .parent_map = gcc_cxo_pll8_map,
1090         },
1091         .freq_tbl = clk_tbl_usb,
1092         .clkr = {
1093                 .enable_reg = 0x2928,
1094                 .enable_mask = BIT(11),
1095                 .hw.init = &(struct clk_init_data){
1096                         .name = "usb_hsic_xcvr_fs_src",
1097                         .parent_names = gcc_cxo_pll8,
1098                         .num_parents = 2,
1099                         .ops = &clk_rcg_ops,
1100                         .flags = CLK_SET_RATE_GATE,
1101                 },
1102         }
1103 };
1104
1105 static struct clk_branch usb_hsic_xcvr_fs_clk = {
1106         .halt_reg = 0x2fc8,
1107         .halt_bit = 9,
1108         .clkr = {
1109                 .enable_reg = 0x2928,
1110                 .enable_mask = BIT(9),
1111                 .hw.init = &(struct clk_init_data){
1112                         .name = "usb_hsic_xcvr_fs_clk",
1113                         .parent_names =
1114                                 (const char *[]){ "usb_hsic_xcvr_fs_src" },
1115                         .num_parents = 1,
1116                         .ops = &clk_branch_ops,
1117                         .flags = CLK_SET_RATE_PARENT,
1118                 },
1119         },
1120 };
1121
1122 static const struct freq_tbl clk_tbl_usb_hs1_system[] = {
1123         { 60000000, P_PLL8, 1, 5, 32 },
1124         { }
1125 };
1126
1127 static struct clk_rcg usb_hs1_system_src = {
1128         .ns_reg = 0x36a4,
1129         .md_reg = 0x36a0,
1130         .mn = {
1131                 .mnctr_en_bit = 8,
1132                 .mnctr_reset_bit = 7,
1133                 .mnctr_mode_shift = 5,
1134                 .n_val_shift = 16,
1135                 .m_val_shift = 16,
1136                 .width = 8,
1137         },
1138         .p = {
1139                 .pre_div_shift = 3,
1140                 .pre_div_width = 2,
1141         },
1142         .s = {
1143                 .src_sel_shift = 0,
1144                 .parent_map = gcc_cxo_pll8_map,
1145         },
1146         .freq_tbl = clk_tbl_usb_hs1_system,
1147         .clkr = {
1148                 .enable_reg = 0x36a4,
1149                 .enable_mask = BIT(11),
1150                 .hw.init = &(struct clk_init_data){
1151                         .name = "usb_hs1_system_src",
1152                         .parent_names = gcc_cxo_pll8,
1153                         .num_parents = 2,
1154                         .ops = &clk_rcg_ops,
1155                         .flags = CLK_SET_RATE_GATE,
1156                 },
1157         }
1158 };
1159
1160 static struct clk_branch usb_hs1_system_clk = {
1161         .halt_reg = 0x2fc8,
1162         .halt_bit = 4,
1163         .clkr = {
1164                 .enable_reg = 0x36a4,
1165                 .enable_mask = BIT(9),
1166                 .hw.init = &(struct clk_init_data){
1167                         .parent_names =
1168                                 (const char *[]){ "usb_hs1_system_src" },
1169                         .num_parents = 1,
1170                         .name = "usb_hs1_system_clk",
1171                         .ops = &clk_branch_ops,
1172                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1173                 },
1174         },
1175 };
1176
1177 static const struct freq_tbl clk_tbl_usb_hsic_system[] = {
1178         { 64000000, P_PLL8, 1, 1, 6 },
1179         { }
1180 };
1181
1182 static struct clk_rcg usb_hsic_system_src = {
1183         .ns_reg = 0x2b58,
1184         .md_reg = 0x2b54,
1185         .mn = {
1186                 .mnctr_en_bit = 8,
1187                 .mnctr_reset_bit = 7,
1188                 .mnctr_mode_shift = 5,
1189                 .n_val_shift = 16,
1190                 .m_val_shift = 16,
1191                 .width = 8,
1192         },
1193         .p = {
1194                 .pre_div_shift = 3,
1195                 .pre_div_width = 2,
1196         },
1197         .s = {
1198                 .src_sel_shift = 0,
1199                 .parent_map = gcc_cxo_pll8_map,
1200         },
1201         .freq_tbl = clk_tbl_usb_hsic_system,
1202         .clkr = {
1203                 .enable_reg = 0x2b58,
1204                 .enable_mask = BIT(11),
1205                 .hw.init = &(struct clk_init_data){
1206                         .name = "usb_hsic_system_src",
1207                         .parent_names = gcc_cxo_pll8,
1208                         .num_parents = 2,
1209                         .ops = &clk_rcg_ops,
1210                         .flags = CLK_SET_RATE_GATE,
1211                 },
1212         }
1213 };
1214
1215 static struct clk_branch usb_hsic_system_clk = {
1216         .halt_reg = 0x2fc8,
1217         .halt_bit = 7,
1218         .clkr = {
1219                 .enable_reg = 0x2b58,
1220                 .enable_mask = BIT(9),
1221                 .hw.init = &(struct clk_init_data){
1222                         .parent_names =
1223                                 (const char *[]){ "usb_hsic_system_src" },
1224                         .num_parents = 1,
1225                         .name = "usb_hsic_system_clk",
1226                         .ops = &clk_branch_ops,
1227                         .flags = CLK_SET_RATE_PARENT,
1228                 },
1229         },
1230 };
1231
1232 static const struct freq_tbl clk_tbl_usb_hsic_hsic[] = {
1233         { 48000000, P_PLL14, 1, 0, 0 },
1234         { }
1235 };
1236
1237 static struct clk_rcg usb_hsic_hsic_src = {
1238         .ns_reg = 0x2b50,
1239         .md_reg = 0x2b4c,
1240         .mn = {
1241                 .mnctr_en_bit = 8,
1242                 .mnctr_reset_bit = 7,
1243                 .mnctr_mode_shift = 5,
1244                 .n_val_shift = 16,
1245                 .m_val_shift = 16,
1246                 .width = 8,
1247         },
1248         .p = {
1249                 .pre_div_shift = 3,
1250                 .pre_div_width = 2,
1251         },
1252         .s = {
1253                 .src_sel_shift = 0,
1254                 .parent_map = gcc_cxo_pll14_map,
1255         },
1256         .freq_tbl = clk_tbl_usb_hsic_hsic,
1257         .clkr = {
1258                 .enable_reg = 0x2b50,
1259                 .enable_mask = BIT(11),
1260                 .hw.init = &(struct clk_init_data){
1261                         .name = "usb_hsic_hsic_src",
1262                         .parent_names = gcc_cxo_pll14,
1263                         .num_parents = 2,
1264                         .ops = &clk_rcg_ops,
1265                         .flags = CLK_SET_RATE_GATE,
1266                 },
1267         }
1268 };
1269
1270 static struct clk_branch usb_hsic_hsic_clk = {
1271         .halt_check = BRANCH_HALT_DELAY,
1272         .clkr = {
1273                 .enable_reg = 0x2b50,
1274                 .enable_mask = BIT(9),
1275                 .hw.init = &(struct clk_init_data){
1276                         .parent_names = (const char *[]){ "usb_hsic_hsic_src" },
1277                         .num_parents = 1,
1278                         .name = "usb_hsic_hsic_clk",
1279                         .ops = &clk_branch_ops,
1280                         .flags = CLK_SET_RATE_PARENT,
1281                 },
1282         },
1283 };
1284
1285 static struct clk_branch usb_hsic_hsio_cal_clk = {
1286         .halt_reg = 0x2fc8,
1287         .halt_bit = 8,
1288         .clkr = {
1289                 .enable_reg = 0x2b48,
1290                 .enable_mask = BIT(0),
1291                 .hw.init = &(struct clk_init_data){
1292                         .parent_names = (const char *[]){ "cxo" },
1293                         .num_parents = 1,
1294                         .name = "usb_hsic_hsio_cal_clk",
1295                         .ops = &clk_branch_ops,
1296                 },
1297         },
1298 };
1299
1300 static struct clk_branch ce1_core_clk = {
1301         .hwcg_reg = 0x2724,
1302         .hwcg_bit = 6,
1303         .halt_reg = 0x2fd4,
1304         .halt_bit = 27,
1305         .clkr = {
1306                 .enable_reg = 0x2724,
1307                 .enable_mask = BIT(4),
1308                 .hw.init = &(struct clk_init_data){
1309                         .name = "ce1_core_clk",
1310                         .ops = &clk_branch_ops,
1311                 },
1312         },
1313 };
1314
1315 static struct clk_branch ce1_h_clk = {
1316         .halt_reg = 0x2fd4,
1317         .halt_bit = 1,
1318         .clkr = {
1319                 .enable_reg = 0x2720,
1320                 .enable_mask = BIT(4),
1321                 .hw.init = &(struct clk_init_data){
1322                         .name = "ce1_h_clk",
1323                         .ops = &clk_branch_ops,
1324                 },
1325         },
1326 };
1327
1328 static struct clk_branch dma_bam_h_clk = {
1329         .hwcg_reg = 0x25c0,
1330         .hwcg_bit = 6,
1331         .halt_reg = 0x2fc8,
1332         .halt_bit = 12,
1333         .clkr = {
1334                 .enable_reg = 0x25c0,
1335                 .enable_mask = BIT(4),
1336                 .hw.init = &(struct clk_init_data){
1337                         .name = "dma_bam_h_clk",
1338                         .ops = &clk_branch_ops,
1339                 },
1340         },
1341 };
1342
1343 static struct clk_branch gsbi1_h_clk = {
1344         .hwcg_reg = 0x29c0,
1345         .hwcg_bit = 6,
1346         .halt_reg = 0x2fcc,
1347         .halt_bit = 11,
1348         .clkr = {
1349                 .enable_reg = 0x29c0,
1350                 .enable_mask = BIT(4),
1351                 .hw.init = &(struct clk_init_data){
1352                         .name = "gsbi1_h_clk",
1353                         .ops = &clk_branch_ops,
1354                 },
1355         },
1356 };
1357
1358 static struct clk_branch gsbi2_h_clk = {
1359         .hwcg_reg = 0x29e0,
1360         .hwcg_bit = 6,
1361         .halt_reg = 0x2fcc,
1362         .halt_bit = 7,
1363         .clkr = {
1364                 .enable_reg = 0x29e0,
1365                 .enable_mask = BIT(4),
1366                 .hw.init = &(struct clk_init_data){
1367                         .name = "gsbi2_h_clk",
1368                         .ops = &clk_branch_ops,
1369                 },
1370         },
1371 };
1372
1373 static struct clk_branch gsbi3_h_clk = {
1374         .hwcg_reg = 0x2a00,
1375         .hwcg_bit = 6,
1376         .halt_reg = 0x2fcc,
1377         .halt_bit = 3,
1378         .clkr = {
1379                 .enable_reg = 0x2a00,
1380                 .enable_mask = BIT(4),
1381                 .hw.init = &(struct clk_init_data){
1382                         .name = "gsbi3_h_clk",
1383                         .ops = &clk_branch_ops,
1384                 },
1385         },
1386 };
1387
1388 static struct clk_branch gsbi4_h_clk = {
1389         .hwcg_reg = 0x2a20,
1390         .hwcg_bit = 6,
1391         .halt_reg = 0x2fd0,
1392         .halt_bit = 27,
1393         .clkr = {
1394                 .enable_reg = 0x2a20,
1395                 .enable_mask = BIT(4),
1396                 .hw.init = &(struct clk_init_data){
1397                         .name = "gsbi4_h_clk",
1398                         .ops = &clk_branch_ops,
1399                 },
1400         },
1401 };
1402
1403 static struct clk_branch gsbi5_h_clk = {
1404         .hwcg_reg = 0x2a40,
1405         .hwcg_bit = 6,
1406         .halt_reg = 0x2fd0,
1407         .halt_bit = 23,
1408         .clkr = {
1409                 .enable_reg = 0x2a40,
1410                 .enable_mask = BIT(4),
1411                 .hw.init = &(struct clk_init_data){
1412                         .name = "gsbi5_h_clk",
1413                         .ops = &clk_branch_ops,
1414                 },
1415         },
1416 };
1417
1418 static struct clk_branch usb_hs1_h_clk = {
1419         .hwcg_reg = 0x2900,
1420         .hwcg_bit = 6,
1421         .halt_reg = 0x2fc8,
1422         .halt_bit = 1,
1423         .clkr = {
1424                 .enable_reg = 0x2900,
1425                 .enable_mask = BIT(4),
1426                 .hw.init = &(struct clk_init_data){
1427                         .name = "usb_hs1_h_clk",
1428                         .ops = &clk_branch_ops,
1429                 },
1430         },
1431 };
1432
1433 static struct clk_branch usb_hsic_h_clk = {
1434         .halt_reg = 0x2fcc,
1435         .halt_bit = 28,
1436         .clkr = {
1437                 .enable_reg = 0x2920,
1438                 .enable_mask = BIT(4),
1439                 .hw.init = &(struct clk_init_data){
1440                         .name = "usb_hsic_h_clk",
1441                         .ops = &clk_branch_ops,
1442                 },
1443         },
1444 };
1445
1446 static struct clk_branch sdc1_h_clk = {
1447         .hwcg_reg = 0x2820,
1448         .hwcg_bit = 6,
1449         .halt_reg = 0x2fc8,
1450         .halt_bit = 11,
1451         .clkr = {
1452                 .enable_reg = 0x2820,
1453                 .enable_mask = BIT(4),
1454                 .hw.init = &(struct clk_init_data){
1455                         .name = "sdc1_h_clk",
1456                         .ops = &clk_branch_ops,
1457                 },
1458         },
1459 };
1460
1461 static struct clk_branch sdc2_h_clk = {
1462         .hwcg_reg = 0x2840,
1463         .hwcg_bit = 6,
1464         .halt_reg = 0x2fc8,
1465         .halt_bit = 10,
1466         .clkr = {
1467                 .enable_reg = 0x2840,
1468                 .enable_mask = BIT(4),
1469                 .hw.init = &(struct clk_init_data){
1470                         .name = "sdc2_h_clk",
1471                         .ops = &clk_branch_ops,
1472                 },
1473         },
1474 };
1475
1476 static struct clk_branch adm0_clk = {
1477         .halt_reg = 0x2fdc,
1478         .halt_check = BRANCH_HALT_VOTED,
1479         .halt_bit = 14,
1480         .clkr = {
1481                 .enable_reg = 0x3080,
1482                 .enable_mask = BIT(2),
1483                 .hw.init = &(struct clk_init_data){
1484                         .name = "adm0_clk",
1485                         .ops = &clk_branch_ops,
1486                 },
1487         },
1488 };
1489
1490 static struct clk_branch adm0_pbus_clk = {
1491         .hwcg_reg = 0x2208,
1492         .hwcg_bit = 6,
1493         .halt_reg = 0x2fdc,
1494         .halt_check = BRANCH_HALT_VOTED,
1495         .halt_bit = 13,
1496         .clkr = {
1497                 .enable_reg = 0x3080,
1498                 .enable_mask = BIT(3),
1499                 .hw.init = &(struct clk_init_data){
1500                         .name = "adm0_pbus_clk",
1501                         .ops = &clk_branch_ops,
1502                 },
1503         },
1504 };
1505
1506 static struct clk_branch pmic_arb0_h_clk = {
1507         .halt_reg = 0x2fd8,
1508         .halt_check = BRANCH_HALT_VOTED,
1509         .halt_bit = 22,
1510         .clkr = {
1511                 .enable_reg = 0x3080,
1512                 .enable_mask = BIT(8),
1513                 .hw.init = &(struct clk_init_data){
1514                         .name = "pmic_arb0_h_clk",
1515                         .ops = &clk_branch_ops,
1516                 },
1517         },
1518 };
1519
1520 static struct clk_branch pmic_arb1_h_clk = {
1521         .halt_reg = 0x2fd8,
1522         .halt_check = BRANCH_HALT_VOTED,
1523         .halt_bit = 21,
1524         .clkr = {
1525                 .enable_reg = 0x3080,
1526                 .enable_mask = BIT(9),
1527                 .hw.init = &(struct clk_init_data){
1528                         .name = "pmic_arb1_h_clk",
1529                         .ops = &clk_branch_ops,
1530                 },
1531         },
1532 };
1533
1534 static struct clk_branch pmic_ssbi2_clk = {
1535         .halt_reg = 0x2fd8,
1536         .halt_check = BRANCH_HALT_VOTED,
1537         .halt_bit = 23,
1538         .clkr = {
1539                 .enable_reg = 0x3080,
1540                 .enable_mask = BIT(7),
1541                 .hw.init = &(struct clk_init_data){
1542                         .name = "pmic_ssbi2_clk",
1543                         .ops = &clk_branch_ops,
1544                 },
1545         },
1546 };
1547
1548 static struct clk_branch rpm_msg_ram_h_clk = {
1549         .hwcg_reg = 0x27e0,
1550         .hwcg_bit = 6,
1551         .halt_reg = 0x2fd8,
1552         .halt_check = BRANCH_HALT_VOTED,
1553         .halt_bit = 12,
1554         .clkr = {
1555                 .enable_reg = 0x3080,
1556                 .enable_mask = BIT(6),
1557                 .hw.init = &(struct clk_init_data){
1558                         .name = "rpm_msg_ram_h_clk",
1559                         .ops = &clk_branch_ops,
1560                 },
1561         },
1562 };
1563
1564 static struct clk_branch ebi2_clk = {
1565         .hwcg_reg = 0x2664,
1566         .hwcg_bit = 6,
1567         .halt_reg = 0x2fcc,
1568         .halt_bit = 24,
1569         .clkr = {
1570                 .enable_reg = 0x2664,
1571                 .enable_mask = BIT(6) | BIT(4),
1572                 .hw.init = &(struct clk_init_data){
1573                         .name = "ebi2_clk",
1574                         .ops = &clk_branch_ops,
1575                 },
1576         },
1577 };
1578
1579 static struct clk_branch ebi2_aon_clk = {
1580         .halt_reg = 0x2fcc,
1581         .halt_bit = 23,
1582         .clkr = {
1583                 .enable_reg = 0x2664,
1584                 .enable_mask = BIT(8),
1585                 .hw.init = &(struct clk_init_data){
1586                         .name = "ebi2_aon_clk",
1587                         .ops = &clk_branch_ops,
1588                 },
1589         },
1590 };
1591
1592 static struct clk_hw *gcc_mdm9615_hws[] = {
1593         &cxo.hw,
1594 };
1595
1596 static struct clk_regmap *gcc_mdm9615_clks[] = {
1597         [PLL0] = &pll0.clkr,
1598         [PLL0_VOTE] = &pll0_vote,
1599         [PLL4_VOTE] = &pll4_vote,
1600         [PLL8] = &pll8.clkr,
1601         [PLL8_VOTE] = &pll8_vote,
1602         [PLL14] = &pll14.clkr,
1603         [PLL14_VOTE] = &pll14_vote,
1604         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
1605         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
1606         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
1607         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
1608         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
1609         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
1610         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
1611         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
1612         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
1613         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
1614         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
1615         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
1616         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
1617         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
1618         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
1619         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
1620         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
1621         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
1622         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
1623         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
1624         [GP0_SRC] = &gp0_src.clkr,
1625         [GP0_CLK] = &gp0_clk.clkr,
1626         [GP1_SRC] = &gp1_src.clkr,
1627         [GP1_CLK] = &gp1_clk.clkr,
1628         [GP2_SRC] = &gp2_src.clkr,
1629         [GP2_CLK] = &gp2_clk.clkr,
1630         [PMEM_A_CLK] = &pmem_clk.clkr,
1631         [PRNG_SRC] = &prng_src.clkr,
1632         [PRNG_CLK] = &prng_clk.clkr,
1633         [SDC1_SRC] = &sdc1_src.clkr,
1634         [SDC1_CLK] = &sdc1_clk.clkr,
1635         [SDC2_SRC] = &sdc2_src.clkr,
1636         [SDC2_CLK] = &sdc2_clk.clkr,
1637         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
1638         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
1639         [USB_HS1_SYSTEM_CLK_SRC] = &usb_hs1_system_src.clkr,
1640         [USB_HS1_SYSTEM_CLK] = &usb_hs1_system_clk.clkr,
1641         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
1642         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
1643         [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_src.clkr,
1644         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
1645         [USB_HSIC_HSIC_CLK_SRC] = &usb_hsic_hsic_src.clkr,
1646         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
1647         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
1648         [CE1_CORE_CLK] = &ce1_core_clk.clkr,
1649         [CE1_H_CLK] = &ce1_h_clk.clkr,
1650         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
1651         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
1652         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
1653         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
1654         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
1655         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
1656         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
1657         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
1658         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
1659         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
1660         [ADM0_CLK] = &adm0_clk.clkr,
1661         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
1662         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
1663         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
1664         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
1665         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
1666         [EBI2_CLK] = &ebi2_clk.clkr,
1667         [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
1668 };
1669
1670 static const struct qcom_reset_map gcc_mdm9615_resets[] = {
1671         [DMA_BAM_RESET] = { 0x25c0, 7 },
1672         [CE1_H_RESET] = { 0x2720, 7 },
1673         [CE1_CORE_RESET] = { 0x2724, 7 },
1674         [SDC1_RESET] = { 0x2830 },
1675         [SDC2_RESET] = { 0x2850 },
1676         [ADM0_C2_RESET] = { 0x220c, 4 },
1677         [ADM0_C1_RESET] = { 0x220c, 3 },
1678         [ADM0_C0_RESET] = { 0x220c, 2 },
1679         [ADM0_PBUS_RESET] = { 0x220c, 1 },
1680         [ADM0_RESET] = { 0x220c },
1681         [USB_HS1_RESET] = { 0x2910 },
1682         [USB_HSIC_RESET] = { 0x2934 },
1683         [GSBI1_RESET] = { 0x29dc },
1684         [GSBI2_RESET] = { 0x29fc },
1685         [GSBI3_RESET] = { 0x2a1c },
1686         [GSBI4_RESET] = { 0x2a3c },
1687         [GSBI5_RESET] = { 0x2a5c },
1688         [PDM_RESET] = { 0x2CC0, 12 },
1689 };
1690
1691 static const struct regmap_config gcc_mdm9615_regmap_config = {
1692         .reg_bits       = 32,
1693         .reg_stride     = 4,
1694         .val_bits       = 32,
1695         .max_register   = 0x3660,
1696         .fast_io        = true,
1697 };
1698
1699 static const struct qcom_cc_desc gcc_mdm9615_desc = {
1700         .config = &gcc_mdm9615_regmap_config,
1701         .clks = gcc_mdm9615_clks,
1702         .num_clks = ARRAY_SIZE(gcc_mdm9615_clks),
1703         .resets = gcc_mdm9615_resets,
1704         .num_resets = ARRAY_SIZE(gcc_mdm9615_resets),
1705 };
1706
1707 static const struct of_device_id gcc_mdm9615_match_table[] = {
1708         { .compatible = "qcom,gcc-mdm9615" },
1709         { }
1710 };
1711 MODULE_DEVICE_TABLE(of, gcc_mdm9615_match_table);
1712
1713 static int gcc_mdm9615_probe(struct platform_device *pdev)
1714 {
1715         struct device *dev = &pdev->dev;
1716         struct regmap *regmap;
1717         int ret;
1718         int i;
1719
1720         regmap = qcom_cc_map(pdev, &gcc_mdm9615_desc);
1721         if (IS_ERR(regmap))
1722                 return PTR_ERR(regmap);
1723
1724         for (i = 0; i < ARRAY_SIZE(gcc_mdm9615_hws); i++) {
1725                 ret = devm_clk_hw_register(dev, gcc_mdm9615_hws[i]);
1726                 if (ret)
1727                         return ret;
1728         }
1729
1730         return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
1731 }
1732
1733 static struct platform_driver gcc_mdm9615_driver = {
1734         .probe          = gcc_mdm9615_probe,
1735         .driver         = {
1736                 .name   = "gcc-mdm9615",
1737                 .of_match_table = gcc_mdm9615_match_table,
1738         },
1739 };
1740
1741 static int __init gcc_mdm9615_init(void)
1742 {
1743         return platform_driver_register(&gcc_mdm9615_driver);
1744 }
1745 core_initcall(gcc_mdm9615_init);
1746
1747 static void __exit gcc_mdm9615_exit(void)
1748 {
1749         platform_driver_unregister(&gcc_mdm9615_driver);
1750 }
1751 module_exit(gcc_mdm9615_exit);
1752
1753 MODULE_DESCRIPTION("QCOM GCC MDM9615 Driver");
1754 MODULE_LICENSE("GPL v2");
1755 MODULE_ALIAS("platform:gcc-mdm9615");