drivers/clk/mediatek/clk-mux.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Owen Chen <owen.chen@mediatek.com>
   5  */
   6
   7 #ifndef __DRV_CLK_MTK_MUX_H
   8 #define __DRV_CLK_MTK_MUX_H
   9
  10 #include <linux/clk-provider.h>
  11
  12 struct mtk_clk_mux {
  13         struct clk_hw hw;
  14         struct regmap *regmap;
  15         const struct mtk_mux *data;
  16         spinlock_t *lock;
  17         bool reparent;
  18 };
  19
  20 struct mtk_mux {
  21         int id;
  22         const char *name;
  23         const char * const *parent_names;
  24         unsigned int flags;
  25
  26         u32 mux_ofs;
  27         u32 set_ofs;
  28         u32 clr_ofs;
  29         u32 upd_ofs;
  30
  31         u8 mux_shift;
  32         u8 mux_width;
  33         u8 gate_shift;
  34         s8 upd_shift;
  35
  36         signed char num_parents;
  37 };
  38
  39 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,          \
  40                         _mux_set_ofs, _mux_clr_ofs, _shift, _width,     \
  41                         _gate, _upd_ofs, _upd, _flags) {                \
  42                 .id = _id,                                              \
  43                 .name = _name,                                          \
  44                 .mux_ofs = _mux_ofs,                                    \
  45                 .set_ofs = _mux_set_ofs,                                \
  46                 .clr_ofs = _mux_clr_ofs,                                \
  47                 .upd_ofs = _upd_ofs,                                    \
  48                 .mux_shift = _shift,                                    \
  49                 .mux_width = _width,                                    \
  50                 .gate_shift = _gate,                                    \
  51                 .upd_shift = _upd,                                      \
  52                 .parent_names = _parents,                               \
  53                 .num_parents = ARRAY_SIZE(_parents),                    \
  54                 .flags = _flags,                                        \
  55         }
  56
  57 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,      \
  58                         _mux_set_ofs, _mux_clr_ofs, _shift, _width,     \
  59                         _gate, _upd_ofs, _upd, _flags)                  \
  60                 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,  \
  61                         _mux_set_ofs, _mux_clr_ofs, _shift, _width,     \
  62                         _gate, _upd_ofs, _upd, _flags)                  \
  63
  64 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,            \
  65                         _mux_set_ofs, _mux_clr_ofs, _shift, _width,     \
  66                         _gate, _upd_ofs, _upd)                          \
  67                 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents,        \
  68                         _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift,   \
  69                         _width, _gate, _upd_ofs, _upd,                  \
  70                         CLK_SET_RATE_PARENT)
  71
  72 int mtk_clk_register_muxes(const struct mtk_mux *muxes,
  73                            int num, struct device_node *node,
  74                            spinlock_t *lock,
  75                            struct clk_onecell_data *clk_data);
  76
  77 #endif /* __DRV_CLK_MTK_MUX_H */