drivers/clk/mediatek/clk-mt2701.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Shunli Wang <shunli.wang@mediatek.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/of.h>
   9 #include <linux/of_address.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12
  13 #include "clk-mtk.h"
  14 #include "clk-gate.h"
  15 #include "clk-cpumux.h"
  16
  17 #include <dt-bindings/clock/mt2701-clk.h>
  18
  19 /*
  20  * For some clocks, we don't care what their actual rates are. And these
  21  * clocks may change their rate on different products or different scenarios.
  22  * So we model these clocks' rate as 0, to denote it's not an actual rate.
  23  */
  24 #define DUMMY_RATE              0
  25
  26 static DEFINE_SPINLOCK(mt2701_clk_lock);
  27
  28 static const struct mtk_fixed_clk top_fixed_clks[] = {
  29         FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
  30                 108 * MHZ),
  31         FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
  32                 400 * MHZ),
  33         FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
  34                 295750000),
  35         FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
  36                 340 * MHZ),
  37         FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
  38                 340 * MHZ),
  39         FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
  40                 340 * MHZ),
  41         FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
  42                 27 * MHZ),
  43         FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
  44                 416 * MHZ),
  45         FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
  46                 143 * MHZ),
  47         FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
  48                 27 * MHZ),
  49         FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
  50                 DUMMY_RATE),
  51         FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
  52                 DUMMY_RATE),
  53         FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
  54                 DUMMY_RATE),
  55 };
  56
  57 static const struct mtk_fixed_factor top_fixed_divs[] = {
  58         FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
  59         FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  60         FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
  61         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  62         FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
  63         FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
  64         FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
  65         FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
  66         FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
  67         FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
  68         FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
  69         FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
  70         FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
  71         FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
  72         FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
  73         FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
  74
  75         FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
  76         FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  77         FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  78         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  79         FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  80         FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
  81         FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
  82         FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
  83         FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
  84         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
  85         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
  86         FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
  87         FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
  88         FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
  89         FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
  90         FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
  91         FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
  92         FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
  93         FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
  94         FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
  95         FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
  96
  97         FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
  98         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
  99         FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
 100         FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
 101
 102         FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
 103         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
 104
 105         FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
 106         FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
 107         FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
 108
 109         FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
 110         FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
 111         FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
 112
 113         FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
 114         FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
 115         FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
 116
 117         FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
 118         FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
 119         FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
 120
 121         FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
 122         FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
 123         FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
 124
 125         FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
 126
 127         FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
 128         FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
 129         FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
 130         FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
 131         FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
 132
 133         FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
 134         FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
 135         FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
 136         FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
 137         FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
 138         FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
 139         FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
 140         FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
 141         FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
 142 };
 143
 144 static const char * const axi_parents[] = {
 145         "clk26m",
 146         "syspll1_d2",
 147         "syspll_d5",
 148         "syspll1_d4",
 149         "univpll_d5",
 150         "univpll2_d2",
 151         "mmpll_d2",
 152         "dmpll_d2"
 153 };
 154
 155 static const char * const mem_parents[] = {
 156         "clk26m",
 157         "dmpll_ck"
 158 };
 159
 160 static const char * const ddrphycfg_parents[] = {
 161         "clk26m",
 162         "syspll1_d8"
 163 };
 164
 165 static const char * const mm_parents[] = {
 166         "clk26m",
 167         "vencpll_ck",
 168         "syspll1_d2",
 169         "syspll1_d4",
 170         "univpll_d5",
 171         "univpll1_d2",
 172         "univpll2_d2",
 173         "dmpll_ck"
 174 };
 175
 176 static const char * const pwm_parents[] = {
 177         "clk26m",
 178         "univpll2_d4",
 179         "univpll3_d2",
 180         "univpll1_d4",
 181 };
 182
 183 static const char * const vdec_parents[] = {
 184         "clk26m",
 185         "vdecpll_ck",
 186         "syspll_d5",
 187         "syspll1_d4",
 188         "univpll_d5",
 189         "univpll2_d2",
 190         "vencpll_ck",
 191         "msdcpll_d2",
 192         "mmpll_d2"
 193 };
 194
 195 static const char * const mfg_parents[] = {
 196         "clk26m",
 197         "mmpll_ck",
 198         "dmpll_x2_ck",
 199         "msdcpll_ck",
 200         "clk26m",
 201         "syspll_d3",
 202         "univpll_d3",
 203         "univpll1_d2"
 204 };
 205
 206 static const char * const camtg_parents[] = {
 207         "clk26m",
 208         "univpll_d26",
 209         "univpll2_d2",
 210         "syspll3_d2",
 211         "syspll3_d4",
 212         "msdcpll_d2",
 213         "mmpll_d2"
 214 };
 215
 216 static const char * const uart_parents[] = {
 217         "clk26m",
 218         "univpll2_d8"
 219 };
 220
 221 static const char * const spi_parents[] = {
 222         "clk26m",
 223         "syspll3_d2",
 224         "syspll4_d2",
 225         "univpll2_d4",
 226         "univpll1_d8"
 227 };
 228
 229 static const char * const usb20_parents[] = {
 230         "clk26m",
 231         "univpll1_d8",
 232         "univpll3_d4"
 233 };
 234
 235 static const char * const msdc30_parents[] = {
 236         "clk26m",
 237         "msdcpll_d2",
 238         "syspll2_d2",
 239         "syspll1_d4",
 240         "univpll1_d4",
 241         "univpll2_d4"
 242 };
 243
 244 static const char * const aud_intbus_parents[] = {
 245         "clk26m",
 246         "syspll1_d4",
 247         "syspll3_d2",
 248         "syspll4_d2",
 249         "univpll3_d2",
 250         "univpll2_d4"
 251 };
 252
 253 static const char * const pmicspi_parents[] = {
 254         "clk26m",
 255         "syspll1_d8",
 256         "syspll2_d4",
 257         "syspll4_d2",
 258         "syspll3_d4",
 259         "syspll2_d8",
 260         "syspll1_d16",
 261         "univpll3_d4",
 262         "univpll_d26",
 263         "dmpll_d2",
 264         "dmpll_d4"
 265 };
 266
 267 static const char * const scp_parents[] = {
 268         "clk26m",
 269         "syspll1_d8",
 270         "dmpll_d2",
 271         "dmpll_d4"
 272 };
 273
 274 static const char * const dpi0_parents[] = {
 275         "clk26m",
 276         "mipipll",
 277         "mipipll_d2",
 278         "mipipll_d4",
 279         "clk26m",
 280         "tvdpll_ck",
 281         "tvdpll_d2",
 282         "tvdpll_d4"
 283 };
 284
 285 static const char * const dpi1_parents[] = {
 286         "clk26m",
 287         "tvdpll_ck",
 288         "tvdpll_d2",
 289         "tvdpll_d4"
 290 };
 291
 292 static const char * const tve_parents[] = {
 293         "clk26m",
 294         "mipipll",
 295         "mipipll_d2",
 296         "mipipll_d4",
 297         "clk26m",
 298         "tvdpll_ck",
 299         "tvdpll_d2",
 300         "tvdpll_d4"
 301 };
 302
 303 static const char * const hdmi_parents[] = {
 304         "clk26m",
 305         "hdmipll_ck",
 306         "hdmipll_d2",
 307         "hdmipll_d3"
 308 };
 309
 310 static const char * const apll_parents[] = {
 311         "clk26m",
 312         "audpll",
 313         "audpll_d4",
 314         "audpll_d8",
 315         "audpll_d16",
 316         "audpll_d24",
 317         "clk26m",
 318         "clk26m"
 319 };
 320
 321 static const char * const rtc_parents[] = {
 322         "32k_internal",
 323         "32k_external",
 324         "clk26m",
 325         "univpll3_d8"
 326 };
 327
 328 static const char * const nfi2x_parents[] = {
 329         "clk26m",
 330         "syspll2_d2",
 331         "syspll_d7",
 332         "univpll3_d2",
 333         "syspll2_d4",
 334         "univpll3_d4",
 335         "syspll4_d4",
 336         "clk26m"
 337 };
 338
 339 static const char * const emmc_hclk_parents[] = {
 340         "clk26m",
 341         "syspll1_d2",
 342         "syspll1_d4",
 343         "syspll2_d2"
 344 };
 345
 346 static const char * const flash_parents[] = {
 347         "clk26m_d8",
 348         "clk26m",
 349         "syspll2_d8",
 350         "syspll3_d4",
 351         "univpll3_d4",
 352         "syspll4_d2",
 353         "syspll2_d4",
 354         "univpll2_d4"
 355 };
 356
 357 static const char * const di_parents[] = {
 358         "clk26m",
 359         "tvd2pll_ck",
 360         "tvd2pll_d2",
 361         "clk26m"
 362 };
 363
 364 static const char * const nr_osd_parents[] = {
 365         "clk26m",
 366         "vencpll_ck",
 367         "syspll1_d2",
 368         "syspll1_d4",
 369         "univpll_d5",
 370         "univpll1_d2",
 371         "univpll2_d2",
 372         "dmpll_ck"
 373 };
 374
 375 static const char * const hdmirx_bist_parents[] = {
 376         "clk26m",
 377         "syspll_d3",
 378         "clk26m",
 379         "syspll1_d16",
 380         "syspll4_d2",
 381         "syspll1_d4",
 382         "vencpll_ck",
 383         "clk26m"
 384 };
 385
 386 static const char * const intdir_parents[] = {
 387         "clk26m",
 388         "mmpll_ck",
 389         "syspll_d2",
 390         "univpll_d2"
 391 };
 392
 393 static const char * const asm_parents[] = {
 394         "clk26m",
 395         "univpll2_d4",
 396         "univpll2_d2",
 397         "syspll_d5"
 398 };
 399
 400 static const char * const ms_card_parents[] = {
 401         "clk26m",
 402         "univpll3_d8",
 403         "syspll4_d4"
 404 };
 405
 406 static const char * const ethif_parents[] = {
 407         "clk26m",
 408         "syspll1_d2",
 409         "syspll_d5",
 410         "syspll1_d4",
 411         "univpll_d5",
 412         "univpll1_d2",
 413         "dmpll_ck",
 414         "dmpll_d2"
 415 };
 416
 417 static const char * const hdmirx_parents[] = {
 418         "clk26m",
 419         "univpll_d52"
 420 };
 421
 422 static const char * const cmsys_parents[] = {
 423         "clk26m",
 424         "syspll1_d2",
 425         "univpll1_d2",
 426         "univpll_d5",
 427         "syspll_d5",
 428         "syspll2_d2",
 429         "syspll1_d4",
 430         "syspll3_d2",
 431         "syspll2_d4",
 432         "syspll1_d8",
 433         "clk26m",
 434         "clk26m",
 435         "clk26m",
 436         "clk26m",
 437         "clk26m"
 438 };
 439
 440 static const char * const clk_8bdac_parents[] = {
 441         "32k_internal",
 442         "8bdac_ck",
 443         "clk26m",
 444         "clk26m"
 445 };
 446
 447 static const char * const aud2dvd_parents[] = {
 448         "a1sys_hp_ck",
 449         "a2sys_hp_ck"
 450 };
 451
 452 static const char * const padmclk_parents[] = {
 453         "clk26m",
 454         "univpll_d26",
 455         "univpll_d52",
 456         "univpll_d108",
 457         "univpll2_d8",
 458         "univpll2_d16",
 459         "univpll2_d32"
 460 };
 461
 462 static const char * const aud_mux_parents[] = {
 463         "clk26m",
 464         "aud1pll_98m_ck",
 465         "aud2pll_90m_ck",
 466         "hadds2pll_98m",
 467         "audio_ext1_ck",
 468         "audio_ext2_ck"
 469 };
 470
 471 static const char * const aud_src_parents[] = {
 472         "aud_mux1_sel",
 473         "aud_mux2_sel"
 474 };
 475
 476 static const char * const cpu_parents[] = {
 477         "clk26m",
 478         "armpll",
 479         "mainpll",
 480         "mmpll"
 481 };
 482
 483 static const struct mtk_composite cpu_muxes[] __initconst = {
 484         MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
 485 };
 486
 487 static const struct mtk_composite top_muxes[] = {
 488         MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 489                 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
 490         MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
 491                 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
 492         MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
 493                 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
 494         MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
 495                 0x0040, 24, 3, 31),
 496
 497         MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
 498                 0x0050, 0, 2, 7),
 499         MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
 500                 0x0050, 8, 4, 15),
 501         MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
 502                 0x0050, 16, 3, 23),
 503         MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
 504                 0x0050, 24, 3, 31),
 505         MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
 506                 0x0060, 0, 1, 7),
 507
 508         MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
 509                 0x0060, 8, 3, 15),
 510         MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
 511                 0x0060, 16, 2, 23),
 512         MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
 513                 0x0060, 24, 3, 31),
 514
 515         MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
 516                 0x0070, 0, 3, 7),
 517         MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
 518                 0x0070, 8, 3, 15),
 519         MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
 520                 0x0070, 16, 1, 23),
 521         MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
 522                 0x0070, 24, 3, 31),
 523
 524         MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
 525                 0x0080, 0, 4, 7),
 526         MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
 527                 0x0080, 8, 2, 15),
 528         MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
 529                 0x0080, 16, 3, 23),
 530         MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
 531                 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
 532
 533         MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
 534                 0x0090, 0, 3, 7),
 535         MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
 536                 0x0090, 8, 2, 15),
 537         MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
 538                 0x0090, 16, 3, 23),
 539
 540         MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
 541                 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
 542         MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
 543                 0x00A0, 8, 3, 15),
 544         MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
 545                 0x00A0, 24, 2, 31),
 546
 547         MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
 548                 0x00B0, 0, 3, 7),
 549         MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
 550                 0x00B0, 8, 2, 15),
 551         MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
 552                 0x00B0, 16, 3, 23),
 553         MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
 554                 0x00B0, 24, 3, 31),
 555
 556         MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
 557                 hdmirx_bist_parents, 0x00C0, 0, 3, 7),
 558         MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
 559                 0x00C0, 8, 2, 15),
 560         MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
 561                 0x00C0, 16, 2, 23),
 562         MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
 563                 0x00C0, 24, 3, 31),
 564
 565         MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
 566                 0x00D0, 0, 2, 7),
 567         MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
 568                 0x00D0, 16, 2, 23),
 569         MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
 570                 0x00D0, 24, 3, 31),
 571
 572         MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
 573                 0x00E0, 0, 1, 7),
 574         MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
 575                 0x00E0, 8, 3, 15),
 576         MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
 577                 0x00E0, 16, 4, 23),
 578
 579         MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
 580                 0x00E0, 24, 3, 31),
 581         MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
 582                 0x00F0, 0, 3, 7),
 583         MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
 584                 0x00F0, 8, 2, 15),
 585         MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
 586                 0x00F0, 16, 1, 23),
 587
 588         MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
 589                 0x0100, 0, 3),
 590
 591         MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
 592                 0x012c, 0, 3),
 593         MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
 594                 0x012c, 3, 3),
 595         MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
 596                 0x012c, 6, 3),
 597         MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
 598                 0x012c, 15, 1, 23),
 599         MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
 600                 0x012c, 16, 1, 24),
 601         MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
 602                 0x012c, 17, 1, 25),
 603         MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
 604                 0x012c, 18, 1, 26),
 605         MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
 606                 0x012c, 19, 1, 27),
 607         MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
 608                 0x012c, 20, 1, 28),
 609 };
 610
 611 static const struct mtk_clk_divider top_adj_divs[] = {
 612         DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
 613                 0x0120, 0, 8),
 614         DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
 615                 0x0120, 8, 8),
 616         DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
 617                 0x0120, 16, 8),
 618         DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
 619                 0x0120, 24, 8),
 620         DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
 621                 0x0124, 0, 8),
 622         DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
 623                 0x0124, 8, 8),
 624         DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
 625                 0x0124, 16, 8),
 626         DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
 627                 0x0124, 24, 8),
 628         DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
 629                 0x0128, 0, 8),
 630         DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
 631                 0x0128, 8, 8),
 632 };
 633
 634 static const struct mtk_gate_regs top_aud_cg_regs = {
 635         .sta_ofs = 0x012C,
 636 };
 637
 638 #define GATE_TOP_AUD(_id, _name, _parent, _shift) {     \
 639                 .id = _id,                              \
 640                 .name = _name,                          \
 641                 .parent_name = _parent,                 \
 642                 .regs = &top_aud_cg_regs,               \
 643                 .shift = _shift,                        \
 644                 .ops = &mtk_clk_gate_ops_no_setclr,     \
 645         }
 646
 647 static const struct mtk_gate top_clks[] = {
 648         GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
 649                 21),
 650         GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
 651                 22),
 652         GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
 653                 23),
 654         GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
 655                 24),
 656         GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
 657                 25),
 658         GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
 659                 26),
 660         GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
 661                 27),
 662         GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
 663                 28),
 664 };
 665
 666 static int mtk_topckgen_init(struct platform_device *pdev)
 667 {
 668         struct clk_onecell_data *clk_data;
 669         void __iomem *base;
 670         struct device_node *node = pdev->dev.of_node;
 671         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 672
 673         base = devm_ioremap_resource(&pdev->dev, res);
 674         if (IS_ERR(base))
 675                 return PTR_ERR(base);
 676
 677         clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
 678
 679         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
 680                                                                 clk_data);
 681
 682         mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
 683                                                                 clk_data);
 684
 685         mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
 686                                 base, &mt2701_clk_lock, clk_data);
 687
 688         mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
 689                                 base, &mt2701_clk_lock, clk_data);
 690
 691         mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
 692                                                 clk_data);
 693
 694         return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 695 }
 696
 697 static const struct mtk_gate_regs infra_cg_regs = {
 698         .set_ofs = 0x0040,
 699         .clr_ofs = 0x0044,
 700         .sta_ofs = 0x0048,
 701 };
 702
 703 #define GATE_ICG(_id, _name, _parent, _shift) {         \
 704                 .id = _id,                              \
 705                 .name = _name,                          \
 706                 .parent_name = _parent,                 \
 707                 .regs = &infra_cg_regs,                 \
 708                 .shift = _shift,                        \
 709                 .ops = &mtk_clk_gate_ops_setclr,        \
 710         }
 711
 712 static const struct mtk_gate infra_clks[] = {
 713         GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
 714         GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
 715         GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
 716         GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
 717         GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
 718         GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
 719         GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
 720         GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
 721         GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
 722         GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
 723         GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
 724         GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
 725         GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
 726         GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
 727         GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
 728         GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
 729         GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
 730         GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
 731 };
 732
 733 static const struct mtk_fixed_factor infra_fixed_divs[] = {
 734         FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
 735 };
 736
 737 static struct clk_onecell_data *infra_clk_data;
 738
 739 static void __init mtk_infrasys_init_early(struct device_node *node)
 740 {
 741         int r, i;
 742
 743         if (!infra_clk_data) {
 744                 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 745
 746                 for (i = 0; i < CLK_INFRA_NR; i++)
 747                         infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
 748         }
 749
 750         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 751                                                 infra_clk_data);
 752
 753         mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
 754                                   infra_clk_data);
 755
 756         r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
 757         if (r)
 758                 pr_err("%s(): could not register clock provider: %d\n",
 759                         __func__, r);
 760 }
 761 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
 762                         mtk_infrasys_init_early);
 763
 764 static int mtk_infrasys_init(struct platform_device *pdev)
 765 {
 766         int r, i;
 767         struct device_node *node = pdev->dev.of_node;
 768
 769         if (!infra_clk_data) {
 770                 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 771         } else {
 772                 for (i = 0; i < CLK_INFRA_NR; i++) {
 773                         if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
 774                                 infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
 775                 }
 776         }
 777
 778         mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 779                                                 infra_clk_data);
 780         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 781                                                 infra_clk_data);
 782
 783         r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
 784         if (r)
 785                 return r;
 786
 787         mtk_register_reset_controller(node, 2, 0x30);
 788
 789         return 0;
 790 }
 791
 792 static const struct mtk_gate_regs peri0_cg_regs = {
 793         .set_ofs = 0x0008,
 794         .clr_ofs = 0x0010,
 795         .sta_ofs = 0x0018,
 796 };
 797
 798 static const struct mtk_gate_regs peri1_cg_regs = {
 799         .set_ofs = 0x000c,
 800         .clr_ofs = 0x0014,
 801         .sta_ofs = 0x001c,
 802 };
 803
 804 #define GATE_PERI0(_id, _name, _parent, _shift) {       \
 805                 .id = _id,                              \
 806                 .name = _name,                          \
 807                 .parent_name = _parent,                 \
 808                 .regs = &peri0_cg_regs,                 \
 809                 .shift = _shift,                        \
 810                 .ops = &mtk_clk_gate_ops_setclr,        \
 811         }
 812
 813 #define GATE_PERI1(_id, _name, _parent, _shift) {       \
 814                 .id = _id,                              \
 815                 .name = _name,                          \
 816                 .parent_name = _parent,                 \
 817                 .regs = &peri1_cg_regs,                 \
 818                 .shift = _shift,                        \
 819                 .ops = &mtk_clk_gate_ops_setclr,        \
 820         }
 821
 822 static const struct mtk_gate peri_clks[] = {
 823         GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
 824         GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
 825         GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
 826         GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
 827         GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
 828         GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
 829         GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
 830         GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
 831         GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
 832         GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
 833         GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
 834         GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
 835         GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
 836         GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
 837         GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
 838         GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
 839         GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
 840         GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
 841         GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
 842         GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
 843         GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
 844         GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
 845         GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
 846         GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
 847         GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
 848         GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
 849         GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
 850         GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
 851         GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
 852         GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
 853         GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
 854         GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
 855
 856         GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
 857         GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
 858         GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
 859         GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
 860         GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
 861         GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
 862         GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
 863         GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
 864         GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
 865         GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
 866         GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
 867         GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
 868 };
 869
 870 static const char * const uart_ck_sel_parents[] = {
 871         "clk26m",
 872         "uart_sel",
 873 };
 874
 875 static const struct mtk_composite peri_muxs[] = {
 876         MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
 877                 0x40c, 0, 1),
 878         MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
 879                 0x40c, 1, 1),
 880         MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
 881                 0x40c, 2, 1),
 882         MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
 883                 0x40c, 3, 1),
 884 };
 885
 886 static int mtk_pericfg_init(struct platform_device *pdev)
 887 {
 888         struct clk_onecell_data *clk_data;
 889         void __iomem *base;
 890         int r;
 891         struct device_node *node = pdev->dev.of_node;
 892         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 893
 894         base = devm_ioremap_resource(&pdev->dev, res);
 895         if (IS_ERR(base))
 896                 return PTR_ERR(base);
 897
 898         clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
 899
 900         mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
 901                                                 clk_data);
 902
 903         mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
 904                         &mt2701_clk_lock, clk_data);
 905
 906         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 907         if (r)
 908                 return r;
 909
 910         mtk_register_reset_controller(node, 2, 0x0);
 911
 912         return 0;
 913 }
 914
 915 #define MT8590_PLL_FMAX         (2000 * MHZ)
 916 #define CON0_MT8590_RST_BAR     BIT(27)
 917
 918 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
 919                         _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) {  \
 920                 .id = _id,                                              \
 921                 .name = _name,                                          \
 922                 .reg = _reg,                                            \
 923                 .pwr_reg = _pwr_reg,                                    \
 924                 .en_mask = _en_mask,                                    \
 925                 .flags = _flags,                                        \
 926                 .rst_bar_mask = CON0_MT8590_RST_BAR,                    \
 927                 .fmax = MT8590_PLL_FMAX,                                \
 928                 .pcwbits = _pcwbits,                                    \
 929                 .pd_reg = _pd_reg,                                      \
 930                 .pd_shift = _pd_shift,                                  \
 931                 .tuner_reg = _tuner_reg,                                \
 932                 .pcw_reg = _pcw_reg,                                    \
 933                 .pcw_shift = _pcw_shift,                                \
 934         }
 935
 936 static const struct mtk_pll_data apmixed_plls[] = {
 937         PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
 938                         PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
 939         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
 940                   HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
 941         PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
 942                   HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
 943         PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
 944                                 21, 0x230, 4, 0x0, 0x234, 0),
 945         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
 946                                 21, 0x240, 4, 0x0, 0x244, 0),
 947         PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
 948                                 21, 0x250, 4, 0x0, 0x254, 0),
 949         PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
 950                                 31, 0x270, 4, 0x0, 0x274, 0),
 951         PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
 952                                 31, 0x280, 4, 0x0, 0x284, 0),
 953         PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
 954                                 31, 0x290, 4, 0x0, 0x294, 0),
 955         PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
 956                                 31, 0x2a0, 4, 0x0, 0x2a4, 0),
 957         PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
 958                                 31, 0x2b0, 4, 0x0, 0x2b4, 0),
 959         PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
 960                                 31, 0x2c0, 4, 0x0, 0x2c4, 0),
 961         PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
 962                                 21, 0x2d0, 4, 0x0, 0x2d4, 0),
 963 };
 964
 965 static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
 966         FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
 967 };
 968
 969 static int mtk_apmixedsys_init(struct platform_device *pdev)
 970 {
 971         struct clk_onecell_data *clk_data;
 972         struct device_node *node = pdev->dev.of_node;
 973
 974         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
 975         if (!clk_data)
 976                 return -ENOMEM;
 977
 978         mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
 979                                                                 clk_data);
 980         mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
 981                                                                 clk_data);
 982
 983         return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 984 }
 985
 986 static const struct of_device_id of_match_clk_mt2701[] = {
 987         {
 988                 .compatible = "mediatek,mt2701-topckgen",
 989                 .data = mtk_topckgen_init,
 990         }, {
 991                 .compatible = "mediatek,mt2701-infracfg",
 992                 .data = mtk_infrasys_init,
 993         }, {
 994                 .compatible = "mediatek,mt2701-pericfg",
 995                 .data = mtk_pericfg_init,
 996         }, {
 997                 .compatible = "mediatek,mt2701-apmixedsys",
 998                 .data = mtk_apmixedsys_init,
 999         }, {
1000                 /* sentinel */
1001         }
1002 };
1003
1004 static int clk_mt2701_probe(struct platform_device *pdev)
1005 {
1006         int (*clk_init)(struct platform_device *);
1007         int r;
1008
1009         clk_init = of_device_get_match_data(&pdev->dev);
1010         if (!clk_init)
1011                 return -EINVAL;
1012
1013         r = clk_init(pdev);
1014         if (r)
1015                 dev_err(&pdev->dev,
1016                         "could not register clock provider: %s: %d\n",
1017                         pdev->name, r);
1018
1019         return r;
1020 }
1021
1022 static struct platform_driver clk_mt2701_drv = {
1023         .probe = clk_mt2701_probe,
1024         .driver = {
1025                 .name = "clk-mt2701",
1026                 .of_match_table = of_match_clk_mt2701,
1027         },
1028 };
1029
1030 static int __init clk_mt2701_init(void)
1031 {
1032         return platform_driver_register(&clk_mt2701_drv);
1033 }
1034
1035 arch_initcall(clk_mt2701_init);