Merge tag 'leds-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pavel...
[linux-2.6-microblaze.git] / drivers / clk / clk-stm32f4.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Author: Daniel Thompson <daniel.thompson@linaro.org>
4  *
5  * Inspired by clk-asm9260.c .
6  */
7
8 #include <linux/clk-provider.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/ioport.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/regmap.h>
18 #include <linux/mfd/syscon.h>
19
20 /*
21  * Include list of clocks wich are not derived from system clock (SYSCLOCK)
22  * The index of these clocks is the secondary index of DT bindings
23  *
24  */
25 #include <dt-bindings/clock/stm32fx-clock.h>
26
27 #define STM32F4_RCC_CR                  0x00
28 #define STM32F4_RCC_PLLCFGR             0x04
29 #define STM32F4_RCC_CFGR                0x08
30 #define STM32F4_RCC_AHB1ENR             0x30
31 #define STM32F4_RCC_AHB2ENR             0x34
32 #define STM32F4_RCC_AHB3ENR             0x38
33 #define STM32F4_RCC_APB1ENR             0x40
34 #define STM32F4_RCC_APB2ENR             0x44
35 #define STM32F4_RCC_BDCR                0x70
36 #define STM32F4_RCC_CSR                 0x74
37 #define STM32F4_RCC_PLLI2SCFGR          0x84
38 #define STM32F4_RCC_PLLSAICFGR          0x88
39 #define STM32F4_RCC_DCKCFGR             0x8c
40 #define STM32F7_RCC_DCKCFGR2            0x90
41
42 #define NONE -1
43 #define NO_IDX  NONE
44 #define NO_MUX  NONE
45 #define NO_GATE NONE
46
47 struct stm32f4_gate_data {
48         u8      offset;
49         u8      bit_idx;
50         const char *name;
51         const char *parent_name;
52         unsigned long flags;
53 };
54
55 static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
56         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
57         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
58         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
59         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
60         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
61         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
62         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
63         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
64         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
65         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
66         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
67         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
68         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
69         { STM32F4_RCC_AHB1ENR, 20,      "ccmdatam",     "ahb_div" },
70         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
71         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
72         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
73         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
74         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
75         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
76         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
77         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
78         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
79
80         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
81         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
82         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
83         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48" },
84         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48" },
85
86         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
87                 CLK_IGNORE_UNUSED },
88
89         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
90         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
91         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
92         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
93         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
94         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
95         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
96         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
97         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
98         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
99         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
100         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
101         { STM32F4_RCC_APB1ENR, 17,      "uart2",        "apb1_div" },
102         { STM32F4_RCC_APB1ENR, 18,      "uart3",        "apb1_div" },
103         { STM32F4_RCC_APB1ENR, 19,      "uart4",        "apb1_div" },
104         { STM32F4_RCC_APB1ENR, 20,      "uart5",        "apb1_div" },
105         { STM32F4_RCC_APB1ENR, 21,      "i2c1",         "apb1_div" },
106         { STM32F4_RCC_APB1ENR, 22,      "i2c2",         "apb1_div" },
107         { STM32F4_RCC_APB1ENR, 23,      "i2c3",         "apb1_div" },
108         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
109         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
110         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
111         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
112         { STM32F4_RCC_APB1ENR, 30,      "uart7",        "apb1_div" },
113         { STM32F4_RCC_APB1ENR, 31,      "uart8",        "apb1_div" },
114
115         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
116         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
117         { STM32F4_RCC_APB2ENR,  4,      "usart1",       "apb2_div" },
118         { STM32F4_RCC_APB2ENR,  5,      "usart6",       "apb2_div" },
119         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
120         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
121         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
122         { STM32F4_RCC_APB2ENR, 11,      "sdio",         "pll48" },
123         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
124         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
125         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
126         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
127         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
128         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
129         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
130         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
131         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
132 };
133
134 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
135         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
136         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
137         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
138         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
139         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
140         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
141         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
142         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
143         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
144         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
145         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
146         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
147         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
148         { STM32F4_RCC_AHB1ENR, 20,      "ccmdatam",     "ahb_div" },
149         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
150         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
151         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
152         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
153         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
154         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
155         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
156         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
157         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
158
159         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
160         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
161         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
162         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48" },
163         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48" },
164
165         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
166                 CLK_IGNORE_UNUSED },
167         { STM32F4_RCC_AHB3ENR,  1,      "qspi",         "ahb_div",
168                 CLK_IGNORE_UNUSED },
169
170         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
171         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
172         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
173         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
174         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
175         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
176         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
177         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
178         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
179         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
180         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
181         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
182         { STM32F4_RCC_APB1ENR, 17,      "uart2",        "apb1_div" },
183         { STM32F4_RCC_APB1ENR, 18,      "uart3",        "apb1_div" },
184         { STM32F4_RCC_APB1ENR, 19,      "uart4",        "apb1_div" },
185         { STM32F4_RCC_APB1ENR, 20,      "uart5",        "apb1_div" },
186         { STM32F4_RCC_APB1ENR, 21,      "i2c1",         "apb1_div" },
187         { STM32F4_RCC_APB1ENR, 22,      "i2c2",         "apb1_div" },
188         { STM32F4_RCC_APB1ENR, 23,      "i2c3",         "apb1_div" },
189         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
190         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
191         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
192         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
193         { STM32F4_RCC_APB1ENR, 30,      "uart7",        "apb1_div" },
194         { STM32F4_RCC_APB1ENR, 31,      "uart8",        "apb1_div" },
195
196         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
197         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
198         { STM32F4_RCC_APB2ENR,  4,      "usart1",       "apb2_div" },
199         { STM32F4_RCC_APB2ENR,  5,      "usart6",       "apb2_div" },
200         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
201         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
202         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
203         { STM32F4_RCC_APB2ENR, 11,      "sdio",         "sdmux" },
204         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
205         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
206         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
207         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
208         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
209         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
210         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
211         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
212         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
213 };
214
215 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
216         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
217         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
218         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
219         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
220         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
221         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
222         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
223         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
224         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
225         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
226         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
227         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
228         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
229         { STM32F4_RCC_AHB1ENR, 20,      "dtcmram",      "ahb_div" },
230         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
231         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
232         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
233         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
234         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
235         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
236         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
237         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
238         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
239
240         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
241         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
242         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
243         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48"   },
244         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48"   },
245
246         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
247                 CLK_IGNORE_UNUSED },
248         { STM32F4_RCC_AHB3ENR,  1,      "qspi",         "ahb_div",
249                 CLK_IGNORE_UNUSED },
250
251         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
252         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
253         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
254         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
255         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
256         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
257         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
258         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
259         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
260         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
261         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
262         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
263         { STM32F4_RCC_APB1ENR, 16,      "spdifrx",      "apb1_div" },
264         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
265         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
266         { STM32F4_RCC_APB1ENR, 27,      "cec",          "apb1_div" },
267         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
268         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
269
270         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
271         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
272         { STM32F4_RCC_APB2ENR,  7,      "sdmmc2",       "sdmux"    },
273         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
274         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
275         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
276         { STM32F4_RCC_APB2ENR, 11,      "sdmmc",        "sdmux"    },
277         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
278         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
279         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
280         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
281         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
282         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
283         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
284         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
285         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
286         { STM32F4_RCC_APB2ENR, 23,      "sai2",         "apb2_div" },
287 };
288
289 static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
290         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
291         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
292         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
293         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
294         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
295         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
296         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
297         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
298         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
299         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
300         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
301         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
302         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
303         { STM32F4_RCC_AHB1ENR, 20,      "dtcmram",      "ahb_div" },
304         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
305         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
306         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
307         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
308         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
309         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
310         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
311         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
312         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
313
314         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
315         { STM32F4_RCC_AHB2ENR,  1,      "jpeg",         "ahb_div" },
316         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
317         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
318         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48"   },
319         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48"   },
320
321         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
322                 CLK_IGNORE_UNUSED },
323         { STM32F4_RCC_AHB3ENR,  1,      "qspi",         "ahb_div",
324                 CLK_IGNORE_UNUSED },
325
326         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
327         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
328         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
329         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
330         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
331         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
332         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
333         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
334         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
335         { STM32F4_RCC_APB1ENR, 10,      "rtcapb",       "apb1_mul" },
336         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
337         { STM32F4_RCC_APB1ENR, 13,      "can3",         "apb1_div" },
338         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
339         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
340         { STM32F4_RCC_APB1ENR, 16,      "spdifrx",      "apb1_div" },
341         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
342         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
343         { STM32F4_RCC_APB1ENR, 27,      "cec",          "apb1_div" },
344         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
345         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
346
347         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
348         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
349         { STM32F4_RCC_APB2ENR,  7,      "sdmmc2",       "sdmux2" },
350         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
351         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
352         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
353         { STM32F4_RCC_APB2ENR, 11,      "sdmmc1",       "sdmux1" },
354         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
355         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
356         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
357         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
358         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
359         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
360         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
361         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
362         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
363         { STM32F4_RCC_APB2ENR, 23,      "sai2",         "apb2_div" },
364         { STM32F4_RCC_APB2ENR, 30,      "mdio",         "apb2_div" },
365 };
366
367 /*
368  * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
369  * have gate bits associated with them. Its combined hweight is 71.
370  */
371 #define MAX_GATE_MAP 3
372
373 static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
374                                                        0x0000000000000001ull,
375                                                        0x04777f33f6fec9ffull };
376
377 static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
378                                                        0x0000000000000003ull,
379                                                        0x0c777f33f6fec9ffull };
380
381 static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
382                                                       0x0000000000000003ull,
383                                                       0x04f77f833e01c9ffull };
384
385 static const u64 stm32f769_gate_map[MAX_GATE_MAP] = { 0x000000f37ef417ffull,
386                                                       0x0000000000000003ull,
387                                                       0x44F77F833E01EDFFull };
388
389 static const u64 *stm32f4_gate_map;
390
391 static struct clk_hw **clks;
392
393 static DEFINE_SPINLOCK(stm32f4_clk_lock);
394 static void __iomem *base;
395
396 static struct regmap *pdrm;
397
398 static int stm32fx_end_primary_clk;
399
400 /*
401  * "Multiplier" device for APBx clocks.
402  *
403  * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
404  * mode, they also tap out the one of the low order state bits to run the
405  * timers. ST datasheets represent this feature as a (conditional) clock
406  * multiplier.
407  */
408 struct clk_apb_mul {
409         struct clk_hw hw;
410         u8 bit_idx;
411 };
412
413 #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
414
415 static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
416                                              unsigned long parent_rate)
417 {
418         struct clk_apb_mul *am = to_clk_apb_mul(hw);
419
420         if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
421                 return parent_rate * 2;
422
423         return parent_rate;
424 }
425
426 static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
427                                    unsigned long *prate)
428 {
429         struct clk_apb_mul *am = to_clk_apb_mul(hw);
430         unsigned long mult = 1;
431
432         if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
433                 mult = 2;
434
435         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
436                 unsigned long best_parent = rate / mult;
437
438                 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
439         }
440
441         return *prate * mult;
442 }
443
444 static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
445                                 unsigned long parent_rate)
446 {
447         /*
448          * We must report success but we can do so unconditionally because
449          * clk_apb_mul_round_rate returns values that ensure this call is a
450          * nop.
451          */
452
453         return 0;
454 }
455
456 static const struct clk_ops clk_apb_mul_factor_ops = {
457         .round_rate = clk_apb_mul_round_rate,
458         .set_rate = clk_apb_mul_set_rate,
459         .recalc_rate = clk_apb_mul_recalc_rate,
460 };
461
462 static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
463                                         const char *parent_name,
464                                         unsigned long flags, u8 bit_idx)
465 {
466         struct clk_apb_mul *am;
467         struct clk_init_data init;
468         struct clk *clk;
469
470         am = kzalloc(sizeof(*am), GFP_KERNEL);
471         if (!am)
472                 return ERR_PTR(-ENOMEM);
473
474         am->bit_idx = bit_idx;
475         am->hw.init = &init;
476
477         init.name = name;
478         init.ops = &clk_apb_mul_factor_ops;
479         init.flags = flags;
480         init.parent_names = &parent_name;
481         init.num_parents = 1;
482
483         clk = clk_register(dev, &am->hw);
484
485         if (IS_ERR(clk))
486                 kfree(am);
487
488         return clk;
489 }
490
491 enum {
492         PLL,
493         PLL_I2S,
494         PLL_SAI,
495 };
496
497 static const struct clk_div_table pll_divp_table[] = {
498         { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
499 };
500
501 static const struct clk_div_table pll_divq_table[] = {
502         { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
503         { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
504         { 14, 14 }, { 15, 15 },
505         { 0 }
506 };
507
508 static const struct clk_div_table pll_divr_table[] = {
509         { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
510 };
511
512 struct stm32f4_pll {
513         spinlock_t *lock;
514         struct  clk_gate gate;
515         u8 offset;
516         u8 bit_rdy_idx;
517         u8 status;
518         u8 n_start;
519 };
520
521 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
522
523 struct stm32f4_pll_post_div_data {
524         int idx;
525         int pll_idx;
526         const char *name;
527         const char *parent;
528         u8 flag;
529         u8 offset;
530         u8 shift;
531         u8 width;
532         u8 flag_div;
533         const struct clk_div_table *div_table;
534 };
535
536 struct stm32f4_vco_data {
537         const char *vco_name;
538         u8 offset;
539         u8 bit_idx;
540         u8 bit_rdy_idx;
541 };
542
543 static const struct stm32f4_vco_data  vco_data[] = {
544         { "vco",     STM32F4_RCC_PLLCFGR,    24, 25 },
545         { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
546         { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
547 };
548
549
550 static const struct clk_div_table post_divr_table[] = {
551         { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
552 };
553
554 #define MAX_POST_DIV 3
555 static const struct stm32f4_pll_post_div_data  post_div_data[MAX_POST_DIV] = {
556         { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
557                 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
558
559         { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
560                 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
561
562         { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
563                 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
564 };
565
566 struct stm32f4_div_data {
567         u8 shift;
568         u8 width;
569         u8 flag_div;
570         const struct clk_div_table *div_table;
571 };
572
573 #define MAX_PLL_DIV 3
574 static const struct stm32f4_div_data  div_data[MAX_PLL_DIV] = {
575         { 16, 2, 0, pll_divp_table },
576         { 24, 4, 0, pll_divq_table },
577         { 28, 3, 0, pll_divr_table },
578 };
579
580 struct stm32f4_pll_data {
581         u8 pll_num;
582         u8 n_start;
583         const char *div_name[MAX_PLL_DIV];
584 };
585
586 static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
587         { PLL,     192, { "pll", "pll48",    NULL       } },
588         { PLL_I2S, 192, { NULL,  "plli2s-q", "plli2s-r" } },
589         { PLL_SAI,  49, { NULL,  "pllsai-q", "pllsai-r" } },
590 };
591
592 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
593         { PLL,     50, { "pll",      "pll-q",    "pll-r"    } },
594         { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
595         { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
596 };
597
598 static int stm32f4_pll_is_enabled(struct clk_hw *hw)
599 {
600         return clk_gate_ops.is_enabled(hw);
601 }
602
603 #define PLL_TIMEOUT 10000
604
605 static int stm32f4_pll_enable(struct clk_hw *hw)
606 {
607         struct clk_gate *gate = to_clk_gate(hw);
608         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
609         int bit_status;
610         unsigned int timeout = PLL_TIMEOUT;
611
612         if (clk_gate_ops.is_enabled(hw))
613                 return 0;
614
615         clk_gate_ops.enable(hw);
616
617         do {
618                 bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
619
620         } while (bit_status && --timeout);
621
622         return bit_status;
623 }
624
625 static void stm32f4_pll_disable(struct clk_hw *hw)
626 {
627         clk_gate_ops.disable(hw);
628 }
629
630 static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
631                 unsigned long parent_rate)
632 {
633         struct clk_gate *gate = to_clk_gate(hw);
634         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
635         unsigned long n;
636
637         n = (readl(base + pll->offset) >> 6) & 0x1ff;
638
639         return parent_rate * n;
640 }
641
642 static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
643                 unsigned long *prate)
644 {
645         struct clk_gate *gate = to_clk_gate(hw);
646         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
647         unsigned long n;
648
649         n = rate / *prate;
650
651         if (n < pll->n_start)
652                 n = pll->n_start;
653         else if (n > 432)
654                 n = 432;
655
656         return *prate * n;
657 }
658
659 static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
660                                 unsigned long parent_rate)
661 {
662         struct clk_gate *gate = to_clk_gate(hw);
663         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
664
665         unsigned long n;
666         unsigned long val;
667         int pll_state;
668
669         pll_state = stm32f4_pll_is_enabled(hw);
670
671         if (pll_state)
672                 stm32f4_pll_disable(hw);
673
674         n = rate  / parent_rate;
675
676         val = readl(base + pll->offset) & ~(0x1ff << 6);
677
678         writel(val | ((n & 0x1ff) <<  6), base + pll->offset);
679
680         if (pll_state)
681                 stm32f4_pll_enable(hw);
682
683         return 0;
684 }
685
686 static const struct clk_ops stm32f4_pll_gate_ops = {
687         .enable         = stm32f4_pll_enable,
688         .disable        = stm32f4_pll_disable,
689         .is_enabled     = stm32f4_pll_is_enabled,
690         .recalc_rate    = stm32f4_pll_recalc,
691         .round_rate     = stm32f4_pll_round_rate,
692         .set_rate       = stm32f4_pll_set_rate,
693 };
694
695 struct stm32f4_pll_div {
696         struct clk_divider div;
697         struct clk_hw *hw_pll;
698 };
699
700 #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
701
702 static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
703                 unsigned long parent_rate)
704 {
705         return clk_divider_ops.recalc_rate(hw, parent_rate);
706 }
707
708 static int stm32f4_pll_div_determine_rate(struct clk_hw *hw,
709                                           struct clk_rate_request *req)
710 {
711         return clk_divider_ops.determine_rate(hw, req);
712 }
713
714 static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
715                                 unsigned long parent_rate)
716 {
717         int pll_state, ret;
718
719         struct clk_divider *div = to_clk_divider(hw);
720         struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
721
722         pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
723
724         if (pll_state)
725                 stm32f4_pll_disable(pll_div->hw_pll);
726
727         ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
728
729         if (pll_state)
730                 stm32f4_pll_enable(pll_div->hw_pll);
731
732         return ret;
733 }
734
735 static const struct clk_ops stm32f4_pll_div_ops = {
736         .recalc_rate = stm32f4_pll_div_recalc_rate,
737         .determine_rate = stm32f4_pll_div_determine_rate,
738         .set_rate = stm32f4_pll_div_set_rate,
739 };
740
741 static struct clk_hw *clk_register_pll_div(const char *name,
742                 const char *parent_name, unsigned long flags,
743                 void __iomem *reg, u8 shift, u8 width,
744                 u8 clk_divider_flags, const struct clk_div_table *table,
745                 struct clk_hw *pll_hw, spinlock_t *lock)
746 {
747         struct stm32f4_pll_div *pll_div;
748         struct clk_hw *hw;
749         struct clk_init_data init;
750         int ret;
751
752         /* allocate the divider */
753         pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
754         if (!pll_div)
755                 return ERR_PTR(-ENOMEM);
756
757         init.name = name;
758         init.ops = &stm32f4_pll_div_ops;
759         init.flags = flags;
760         init.parent_names = (parent_name ? &parent_name : NULL);
761         init.num_parents = (parent_name ? 1 : 0);
762
763         /* struct clk_divider assignments */
764         pll_div->div.reg = reg;
765         pll_div->div.shift = shift;
766         pll_div->div.width = width;
767         pll_div->div.flags = clk_divider_flags;
768         pll_div->div.lock = lock;
769         pll_div->div.table = table;
770         pll_div->div.hw.init = &init;
771
772         pll_div->hw_pll = pll_hw;
773
774         /* register the clock */
775         hw = &pll_div->div.hw;
776         ret = clk_hw_register(NULL, hw);
777         if (ret) {
778                 kfree(pll_div);
779                 hw = ERR_PTR(ret);
780         }
781
782         return hw;
783 }
784
785 static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
786                 const struct stm32f4_pll_data *data,  spinlock_t *lock)
787 {
788         struct stm32f4_pll *pll;
789         struct clk_init_data init = { NULL };
790         void __iomem *reg;
791         struct clk_hw *pll_hw;
792         int ret;
793         int i;
794         const struct stm32f4_vco_data *vco;
795
796
797         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
798         if (!pll)
799                 return ERR_PTR(-ENOMEM);
800
801         vco = &vco_data[data->pll_num];
802
803         init.name = vco->vco_name;
804         init.ops = &stm32f4_pll_gate_ops;
805         init.flags = CLK_SET_RATE_GATE;
806         init.parent_names = &pllsrc;
807         init.num_parents = 1;
808
809         pll->gate.lock = lock;
810         pll->gate.reg = base + STM32F4_RCC_CR;
811         pll->gate.bit_idx = vco->bit_idx;
812         pll->gate.hw.init = &init;
813
814         pll->offset = vco->offset;
815         pll->n_start = data->n_start;
816         pll->bit_rdy_idx = vco->bit_rdy_idx;
817         pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
818
819         reg = base + pll->offset;
820
821         pll_hw = &pll->gate.hw;
822         ret = clk_hw_register(NULL, pll_hw);
823         if (ret) {
824                 kfree(pll);
825                 return ERR_PTR(ret);
826         }
827
828         for (i = 0; i < MAX_PLL_DIV; i++)
829                 if (data->div_name[i])
830                         clk_register_pll_div(data->div_name[i],
831                                         vco->vco_name,
832                                         0,
833                                         reg,
834                                         div_data[i].shift,
835                                         div_data[i].width,
836                                         div_data[i].flag_div,
837                                         div_data[i].div_table,
838                                         pll_hw,
839                                         lock);
840         return pll_hw;
841 }
842
843 /*
844  * Converts the primary and secondary indices (as they appear in DT) to an
845  * offset into our struct clock array.
846  */
847 static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
848 {
849         u64 table[MAX_GATE_MAP];
850
851         if (primary == 1) {
852                 if (WARN_ON(secondary >= stm32fx_end_primary_clk))
853                         return -EINVAL;
854                 return secondary;
855         }
856
857         memcpy(table, stm32f4_gate_map, sizeof(table));
858
859         /* only bits set in table can be used as indices */
860         if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
861                     0 == (table[BIT_ULL_WORD(secondary)] &
862                           BIT_ULL_MASK(secondary))))
863                 return -EINVAL;
864
865         /* mask out bits above our current index */
866         table[BIT_ULL_WORD(secondary)] &=
867             GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
868
869         return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
870                (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
871                (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
872 }
873
874 static struct clk_hw *
875 stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
876 {
877         int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
878
879         if (i < 0)
880                 return ERR_PTR(-EINVAL);
881
882         return clks[i];
883 }
884
885 #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
886
887 static inline void disable_power_domain_write_protection(void)
888 {
889         if (pdrm)
890                 regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
891 }
892
893 static inline void enable_power_domain_write_protection(void)
894 {
895         if (pdrm)
896                 regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
897 }
898
899 static inline void sofware_reset_backup_domain(void)
900 {
901         unsigned long val;
902
903         val = readl(base + STM32F4_RCC_BDCR);
904         writel(val | BIT(16), base + STM32F4_RCC_BDCR);
905         writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
906 }
907
908 struct stm32_rgate {
909         struct  clk_gate gate;
910         u8      bit_rdy_idx;
911 };
912
913 #define RGATE_TIMEOUT 50000
914
915 static int rgclk_enable(struct clk_hw *hw)
916 {
917         struct clk_gate *gate = to_clk_gate(hw);
918         struct stm32_rgate *rgate = to_rgclk(gate);
919         int bit_status;
920         unsigned int timeout = RGATE_TIMEOUT;
921
922         if (clk_gate_ops.is_enabled(hw))
923                 return 0;
924
925         disable_power_domain_write_protection();
926
927         clk_gate_ops.enable(hw);
928
929         do {
930                 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
931                 if (bit_status)
932                         udelay(100);
933
934         } while (bit_status && --timeout);
935
936         enable_power_domain_write_protection();
937
938         return bit_status;
939 }
940
941 static void rgclk_disable(struct clk_hw *hw)
942 {
943         clk_gate_ops.disable(hw);
944 }
945
946 static int rgclk_is_enabled(struct clk_hw *hw)
947 {
948         return clk_gate_ops.is_enabled(hw);
949 }
950
951 static const struct clk_ops rgclk_ops = {
952         .enable = rgclk_enable,
953         .disable = rgclk_disable,
954         .is_enabled = rgclk_is_enabled,
955 };
956
957 static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
958                 const char *parent_name, unsigned long flags,
959                 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
960                 u8 clk_gate_flags, spinlock_t *lock)
961 {
962         struct stm32_rgate *rgate;
963         struct clk_init_data init = { NULL };
964         struct clk_hw *hw;
965         int ret;
966
967         rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
968         if (!rgate)
969                 return ERR_PTR(-ENOMEM);
970
971         init.name = name;
972         init.ops = &rgclk_ops;
973         init.flags = flags;
974         init.parent_names = &parent_name;
975         init.num_parents = 1;
976
977         rgate->bit_rdy_idx = bit_rdy_idx;
978
979         rgate->gate.lock = lock;
980         rgate->gate.reg = reg;
981         rgate->gate.bit_idx = bit_idx;
982         rgate->gate.hw.init = &init;
983
984         hw = &rgate->gate.hw;
985         ret = clk_hw_register(dev, hw);
986         if (ret) {
987                 kfree(rgate);
988                 hw = ERR_PTR(ret);
989         }
990
991         return hw;
992 }
993
994 static int cclk_gate_enable(struct clk_hw *hw)
995 {
996         int ret;
997
998         disable_power_domain_write_protection();
999
1000         ret = clk_gate_ops.enable(hw);
1001
1002         enable_power_domain_write_protection();
1003
1004         return ret;
1005 }
1006
1007 static void cclk_gate_disable(struct clk_hw *hw)
1008 {
1009         disable_power_domain_write_protection();
1010
1011         clk_gate_ops.disable(hw);
1012
1013         enable_power_domain_write_protection();
1014 }
1015
1016 static int cclk_gate_is_enabled(struct clk_hw *hw)
1017 {
1018         return clk_gate_ops.is_enabled(hw);
1019 }
1020
1021 static const struct clk_ops cclk_gate_ops = {
1022         .enable         = cclk_gate_enable,
1023         .disable        = cclk_gate_disable,
1024         .is_enabled     = cclk_gate_is_enabled,
1025 };
1026
1027 static u8 cclk_mux_get_parent(struct clk_hw *hw)
1028 {
1029         return clk_mux_ops.get_parent(hw);
1030 }
1031
1032 static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
1033 {
1034         int ret;
1035
1036         disable_power_domain_write_protection();
1037
1038         sofware_reset_backup_domain();
1039
1040         ret = clk_mux_ops.set_parent(hw, index);
1041
1042         enable_power_domain_write_protection();
1043
1044         return ret;
1045 }
1046
1047 static const struct clk_ops cclk_mux_ops = {
1048         .get_parent = cclk_mux_get_parent,
1049         .set_parent = cclk_mux_set_parent,
1050 };
1051
1052 static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
1053                 const char * const *parent_names, int num_parents,
1054                 void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
1055                 spinlock_t *lock)
1056 {
1057         struct clk_hw *hw;
1058         struct clk_gate *gate;
1059         struct clk_mux *mux;
1060
1061         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1062         if (!gate) {
1063                 hw = ERR_PTR(-EINVAL);
1064                 goto fail;
1065         }
1066
1067         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1068         if (!mux) {
1069                 kfree(gate);
1070                 hw = ERR_PTR(-EINVAL);
1071                 goto fail;
1072         }
1073
1074         gate->reg = reg;
1075         gate->bit_idx = bit_idx;
1076         gate->flags = 0;
1077         gate->lock = lock;
1078
1079         mux->reg = reg;
1080         mux->shift = shift;
1081         mux->mask = 3;
1082         mux->flags = 0;
1083
1084         hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
1085                         &mux->hw, &cclk_mux_ops,
1086                         NULL, NULL,
1087                         &gate->hw, &cclk_gate_ops,
1088                         flags);
1089
1090         if (IS_ERR(hw)) {
1091                 kfree(gate);
1092                 kfree(mux);
1093         }
1094
1095 fail:
1096         return hw;
1097 }
1098
1099 static const char *sys_parents[] __initdata =   { "hsi", NULL, "pll" };
1100
1101 static const struct clk_div_table ahb_div_table[] = {
1102         { 0x0,   1 }, { 0x1,   1 }, { 0x2,   1 }, { 0x3,   1 },
1103         { 0x4,   1 }, { 0x5,   1 }, { 0x6,   1 }, { 0x7,   1 },
1104         { 0x8,   2 }, { 0x9,   4 }, { 0xa,   8 }, { 0xb,  16 },
1105         { 0xc,  64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
1106         { 0 },
1107 };
1108
1109 static const struct clk_div_table apb_div_table[] = {
1110         { 0,  1 }, { 0,  1 }, { 0,  1 }, { 0,  1 },
1111         { 4,  2 }, { 5,  4 }, { 6,  8 }, { 7, 16 },
1112         { 0 },
1113 };
1114
1115 static const char *rtc_parents[4] = {
1116         "no-clock", "lse", "lsi", "hse-rtc"
1117 };
1118
1119 static const char *pll_src = "pll-src";
1120
1121 static const char *pllsrc_parent[2] = { "hsi", NULL };
1122
1123 static const char *dsi_parent[2] = { NULL, "pll-r" };
1124
1125 static const char *lcd_parent[1] = { "pllsai-r-div" };
1126
1127 static const char *i2s_parents[2] = { "plli2s-r", NULL };
1128
1129 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1130         "no-clock" };
1131
1132 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1133
1134 static const char *sdmux_parents[2] = { "pll48", "sys" };
1135
1136 static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
1137
1138 static const char *spdif_parent[1] = { "plli2s-p" };
1139
1140 static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
1141
1142 static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
1143 static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
1144
1145 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1146
1147 static const char * const dfsdm1_src[] = { "apb2_div", "sys" };
1148 static const char * const adsfdm1_parent[] = { "sai1_clk", "sai2_clk" };
1149
1150 struct stm32_aux_clk {
1151         int idx;
1152         const char *name;
1153         const char * const *parent_names;
1154         int num_parents;
1155         int offset_mux;
1156         u8 shift;
1157         u8 mask;
1158         int offset_gate;
1159         u8 bit_idx;
1160         unsigned long flags;
1161 };
1162
1163 struct stm32f4_clk_data {
1164         const struct stm32f4_gate_data *gates_data;
1165         const u64 *gates_map;
1166         int gates_num;
1167         const struct stm32f4_pll_data *pll_data;
1168         const struct stm32_aux_clk *aux_clk;
1169         int aux_clk_num;
1170         int end_primary;
1171 };
1172
1173 static const struct stm32_aux_clk stm32f429_aux_clk[] = {
1174         {
1175                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1176                 NO_MUX, 0, 0,
1177                 STM32F4_RCC_APB2ENR, 26,
1178                 CLK_SET_RATE_PARENT
1179         },
1180         {
1181                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1182                 STM32F4_RCC_CFGR, 23, 1,
1183                 NO_GATE, 0,
1184                 CLK_SET_RATE_PARENT
1185         },
1186         {
1187                 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1188                 STM32F4_RCC_DCKCFGR, 20, 3,
1189                 STM32F4_RCC_APB2ENR, 22,
1190                 CLK_SET_RATE_PARENT
1191         },
1192         {
1193                 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1194                 STM32F4_RCC_DCKCFGR, 22, 3,
1195                 STM32F4_RCC_APB2ENR, 22,
1196                 CLK_SET_RATE_PARENT
1197         },
1198 };
1199
1200 static const struct stm32_aux_clk stm32f469_aux_clk[] = {
1201         {
1202                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1203                 NO_MUX, 0, 0,
1204                 STM32F4_RCC_APB2ENR, 26,
1205                 CLK_SET_RATE_PARENT
1206         },
1207         {
1208                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1209                 STM32F4_RCC_CFGR, 23, 1,
1210                 NO_GATE, 0,
1211                 CLK_SET_RATE_PARENT
1212         },
1213         {
1214                 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1215                 STM32F4_RCC_DCKCFGR, 20, 3,
1216                 STM32F4_RCC_APB2ENR, 22,
1217                 CLK_SET_RATE_PARENT
1218         },
1219         {
1220                 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1221                 STM32F4_RCC_DCKCFGR, 22, 3,
1222                 STM32F4_RCC_APB2ENR, 22,
1223                 CLK_SET_RATE_PARENT
1224         },
1225         {
1226                 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1227                 STM32F4_RCC_DCKCFGR, 27, 1,
1228                 NO_GATE, 0,
1229                 0
1230         },
1231         {
1232                 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1233                 STM32F4_RCC_DCKCFGR, 28, 1,
1234                 NO_GATE, 0,
1235                 0
1236         },
1237         {
1238                 CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
1239                 STM32F4_RCC_DCKCFGR, 29, 1,
1240                 STM32F4_RCC_APB2ENR, 27,
1241                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
1242         },
1243 };
1244
1245 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
1246         {
1247                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1248                 NO_MUX, 0, 0,
1249                 STM32F4_RCC_APB2ENR, 26,
1250                 CLK_SET_RATE_PARENT
1251         },
1252         {
1253                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1254                 STM32F4_RCC_CFGR, 23, 1,
1255                 NO_GATE, 0,
1256                 CLK_SET_RATE_PARENT
1257         },
1258         {
1259                 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1260                 STM32F4_RCC_DCKCFGR, 20, 3,
1261                 STM32F4_RCC_APB2ENR, 22,
1262                 CLK_SET_RATE_PARENT
1263         },
1264         {
1265                 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1266                 STM32F4_RCC_DCKCFGR, 22, 3,
1267                 STM32F4_RCC_APB2ENR, 23,
1268                 CLK_SET_RATE_PARENT
1269         },
1270         {
1271                 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1272                 STM32F7_RCC_DCKCFGR2, 27, 1,
1273                 NO_GATE, 0,
1274                 0
1275         },
1276         {
1277                 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1278                 STM32F7_RCC_DCKCFGR2, 28, 1,
1279                 NO_GATE, 0,
1280                 0
1281         },
1282         {
1283                 CLK_HDMI_CEC, "hdmi-cec",
1284                 hdmi_parents, ARRAY_SIZE(hdmi_parents),
1285                 STM32F7_RCC_DCKCFGR2, 26, 1,
1286                 NO_GATE, 0,
1287                 0
1288         },
1289         {
1290                 CLK_SPDIF, "spdif-rx",
1291                 spdif_parent, ARRAY_SIZE(spdif_parent),
1292                 STM32F7_RCC_DCKCFGR2, 22, 3,
1293                 STM32F4_RCC_APB2ENR, 23,
1294                 CLK_SET_RATE_PARENT
1295         },
1296         {
1297                 CLK_USART1, "usart1",
1298                 uart_parents1, ARRAY_SIZE(uart_parents1),
1299                 STM32F7_RCC_DCKCFGR2, 0, 3,
1300                 STM32F4_RCC_APB2ENR, 4,
1301                 CLK_SET_RATE_PARENT,
1302         },
1303         {
1304                 CLK_USART2, "usart2",
1305                 uart_parents2, ARRAY_SIZE(uart_parents1),
1306                 STM32F7_RCC_DCKCFGR2, 2, 3,
1307                 STM32F4_RCC_APB1ENR, 17,
1308                 CLK_SET_RATE_PARENT,
1309         },
1310         {
1311                 CLK_USART3, "usart3",
1312                 uart_parents2, ARRAY_SIZE(uart_parents1),
1313                 STM32F7_RCC_DCKCFGR2, 4, 3,
1314                 STM32F4_RCC_APB1ENR, 18,
1315                 CLK_SET_RATE_PARENT,
1316         },
1317         {
1318                 CLK_UART4, "uart4",
1319                 uart_parents2, ARRAY_SIZE(uart_parents1),
1320                 STM32F7_RCC_DCKCFGR2, 6, 3,
1321                 STM32F4_RCC_APB1ENR, 19,
1322                 CLK_SET_RATE_PARENT,
1323         },
1324         {
1325                 CLK_UART5, "uart5",
1326                 uart_parents2, ARRAY_SIZE(uart_parents1),
1327                 STM32F7_RCC_DCKCFGR2, 8, 3,
1328                 STM32F4_RCC_APB1ENR, 20,
1329                 CLK_SET_RATE_PARENT,
1330         },
1331         {
1332                 CLK_USART6, "usart6",
1333                 uart_parents1, ARRAY_SIZE(uart_parents1),
1334                 STM32F7_RCC_DCKCFGR2, 10, 3,
1335                 STM32F4_RCC_APB2ENR, 5,
1336                 CLK_SET_RATE_PARENT,
1337         },
1338
1339         {
1340                 CLK_UART7, "uart7",
1341                 uart_parents2, ARRAY_SIZE(uart_parents1),
1342                 STM32F7_RCC_DCKCFGR2, 12, 3,
1343                 STM32F4_RCC_APB1ENR, 30,
1344                 CLK_SET_RATE_PARENT,
1345         },
1346         {
1347                 CLK_UART8, "uart8",
1348                 uart_parents2, ARRAY_SIZE(uart_parents1),
1349                 STM32F7_RCC_DCKCFGR2, 14, 3,
1350                 STM32F4_RCC_APB1ENR, 31,
1351                 CLK_SET_RATE_PARENT,
1352         },
1353         {
1354                 CLK_I2C1, "i2c1",
1355                 i2c_parents, ARRAY_SIZE(i2c_parents),
1356                 STM32F7_RCC_DCKCFGR2, 16, 3,
1357                 STM32F4_RCC_APB1ENR, 21,
1358                 CLK_SET_RATE_PARENT,
1359         },
1360         {
1361                 CLK_I2C2, "i2c2",
1362                 i2c_parents, ARRAY_SIZE(i2c_parents),
1363                 STM32F7_RCC_DCKCFGR2, 18, 3,
1364                 STM32F4_RCC_APB1ENR, 22,
1365                 CLK_SET_RATE_PARENT,
1366         },
1367         {
1368                 CLK_I2C3, "i2c3",
1369                 i2c_parents, ARRAY_SIZE(i2c_parents),
1370                 STM32F7_RCC_DCKCFGR2, 20, 3,
1371                 STM32F4_RCC_APB1ENR, 23,
1372                 CLK_SET_RATE_PARENT,
1373         },
1374         {
1375                 CLK_I2C4, "i2c4",
1376                 i2c_parents, ARRAY_SIZE(i2c_parents),
1377                 STM32F7_RCC_DCKCFGR2, 22, 3,
1378                 STM32F4_RCC_APB1ENR, 24,
1379                 CLK_SET_RATE_PARENT,
1380         },
1381
1382         {
1383                 CLK_LPTIMER, "lptim1",
1384                 lptim_parent, ARRAY_SIZE(lptim_parent),
1385                 STM32F7_RCC_DCKCFGR2, 24, 3,
1386                 STM32F4_RCC_APB1ENR, 9,
1387                 CLK_SET_RATE_PARENT
1388         },
1389 };
1390
1391 static const struct stm32_aux_clk stm32f769_aux_clk[] = {
1392         {
1393                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1394                 NO_MUX, 0, 0,
1395                 STM32F4_RCC_APB2ENR, 26,
1396                 CLK_SET_RATE_PARENT
1397         },
1398         {
1399                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1400                 STM32F4_RCC_CFGR, 23, 1,
1401                 NO_GATE, 0,
1402                 CLK_SET_RATE_PARENT
1403         },
1404         {
1405                 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1406                 STM32F4_RCC_DCKCFGR, 20, 3,
1407                 STM32F4_RCC_APB2ENR, 22,
1408                 CLK_SET_RATE_PARENT
1409         },
1410         {
1411                 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1412                 STM32F4_RCC_DCKCFGR, 22, 3,
1413                 STM32F4_RCC_APB2ENR, 23,
1414                 CLK_SET_RATE_PARENT
1415         },
1416         {
1417                 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1418                 STM32F7_RCC_DCKCFGR2, 27, 1,
1419                 NO_GATE, 0,
1420                 0
1421         },
1422         {
1423                 NO_IDX, "sdmux1", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1424                 STM32F7_RCC_DCKCFGR2, 28, 1,
1425                 NO_GATE, 0,
1426                 0
1427         },
1428         {
1429                 NO_IDX, "sdmux2", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1430                 STM32F7_RCC_DCKCFGR2, 29, 1,
1431                 NO_GATE, 0,
1432                 0
1433         },
1434         {
1435                 CLK_HDMI_CEC, "hdmi-cec",
1436                 hdmi_parents, ARRAY_SIZE(hdmi_parents),
1437                 STM32F7_RCC_DCKCFGR2, 26, 1,
1438                 NO_GATE, 0,
1439                 0
1440         },
1441         {
1442                 CLK_SPDIF, "spdif-rx",
1443                 spdif_parent, ARRAY_SIZE(spdif_parent),
1444                 STM32F7_RCC_DCKCFGR2, 22, 3,
1445                 STM32F4_RCC_APB2ENR, 23,
1446                 CLK_SET_RATE_PARENT
1447         },
1448         {
1449                 CLK_USART1, "usart1",
1450                 uart_parents1, ARRAY_SIZE(uart_parents1),
1451                 STM32F7_RCC_DCKCFGR2, 0, 3,
1452                 STM32F4_RCC_APB2ENR, 4,
1453                 CLK_SET_RATE_PARENT,
1454         },
1455         {
1456                 CLK_USART2, "usart2",
1457                 uart_parents2, ARRAY_SIZE(uart_parents1),
1458                 STM32F7_RCC_DCKCFGR2, 2, 3,
1459                 STM32F4_RCC_APB1ENR, 17,
1460                 CLK_SET_RATE_PARENT,
1461         },
1462         {
1463                 CLK_USART3, "usart3",
1464                 uart_parents2, ARRAY_SIZE(uart_parents1),
1465                 STM32F7_RCC_DCKCFGR2, 4, 3,
1466                 STM32F4_RCC_APB1ENR, 18,
1467                 CLK_SET_RATE_PARENT,
1468         },
1469         {
1470                 CLK_UART4, "uart4",
1471                 uart_parents2, ARRAY_SIZE(uart_parents1),
1472                 STM32F7_RCC_DCKCFGR2, 6, 3,
1473                 STM32F4_RCC_APB1ENR, 19,
1474                 CLK_SET_RATE_PARENT,
1475         },
1476         {
1477                 CLK_UART5, "uart5",
1478                 uart_parents2, ARRAY_SIZE(uart_parents1),
1479                 STM32F7_RCC_DCKCFGR2, 8, 3,
1480                 STM32F4_RCC_APB1ENR, 20,
1481                 CLK_SET_RATE_PARENT,
1482         },
1483         {
1484                 CLK_USART6, "usart6",
1485                 uart_parents1, ARRAY_SIZE(uart_parents1),
1486                 STM32F7_RCC_DCKCFGR2, 10, 3,
1487                 STM32F4_RCC_APB2ENR, 5,
1488                 CLK_SET_RATE_PARENT,
1489         },
1490         {
1491                 CLK_UART7, "uart7",
1492                 uart_parents2, ARRAY_SIZE(uart_parents1),
1493                 STM32F7_RCC_DCKCFGR2, 12, 3,
1494                 STM32F4_RCC_APB1ENR, 30,
1495                 CLK_SET_RATE_PARENT,
1496         },
1497         {
1498                 CLK_UART8, "uart8",
1499                 uart_parents2, ARRAY_SIZE(uart_parents1),
1500                 STM32F7_RCC_DCKCFGR2, 14, 3,
1501                 STM32F4_RCC_APB1ENR, 31,
1502                 CLK_SET_RATE_PARENT,
1503         },
1504         {
1505                 CLK_I2C1, "i2c1",
1506                 i2c_parents, ARRAY_SIZE(i2c_parents),
1507                 STM32F7_RCC_DCKCFGR2, 16, 3,
1508                 STM32F4_RCC_APB1ENR, 21,
1509                 CLK_SET_RATE_PARENT,
1510         },
1511         {
1512                 CLK_I2C2, "i2c2",
1513                 i2c_parents, ARRAY_SIZE(i2c_parents),
1514                 STM32F7_RCC_DCKCFGR2, 18, 3,
1515                 STM32F4_RCC_APB1ENR, 22,
1516                 CLK_SET_RATE_PARENT,
1517         },
1518         {
1519                 CLK_I2C3, "i2c3",
1520                 i2c_parents, ARRAY_SIZE(i2c_parents),
1521                 STM32F7_RCC_DCKCFGR2, 20, 3,
1522                 STM32F4_RCC_APB1ENR, 23,
1523                 CLK_SET_RATE_PARENT,
1524         },
1525         {
1526                 CLK_I2C4, "i2c4",
1527                 i2c_parents, ARRAY_SIZE(i2c_parents),
1528                 STM32F7_RCC_DCKCFGR2, 22, 3,
1529                 STM32F4_RCC_APB1ENR, 24,
1530                 CLK_SET_RATE_PARENT,
1531         },
1532         {
1533                 CLK_LPTIMER, "lptim1",
1534                 lptim_parent, ARRAY_SIZE(lptim_parent),
1535                 STM32F7_RCC_DCKCFGR2, 24, 3,
1536                 STM32F4_RCC_APB1ENR, 9,
1537                 CLK_SET_RATE_PARENT
1538         },
1539         {
1540                 CLK_F769_DSI, "dsi",
1541                 dsi_parent, ARRAY_SIZE(dsi_parent),
1542                 STM32F7_RCC_DCKCFGR2, 0, 1,
1543                 STM32F4_RCC_APB2ENR, 27,
1544                 CLK_SET_RATE_PARENT
1545         },
1546         {
1547                 CLK_DFSDM1, "dfsdm1",
1548                 dfsdm1_src, ARRAY_SIZE(dfsdm1_src),
1549                 STM32F4_RCC_DCKCFGR, 25, 1,
1550                 STM32F4_RCC_APB2ENR, 29,
1551                 CLK_SET_RATE_PARENT
1552         },
1553         {
1554                 CLK_ADFSDM1, "adfsdm1",
1555                 adsfdm1_parent, ARRAY_SIZE(adsfdm1_parent),
1556                 STM32F4_RCC_DCKCFGR, 26, 1,
1557                 STM32F4_RCC_APB2ENR, 29,
1558                 CLK_SET_RATE_PARENT
1559         },
1560 };
1561
1562 static const struct stm32f4_clk_data stm32f429_clk_data = {
1563         .end_primary    = END_PRIMARY_CLK,
1564         .gates_data     = stm32f429_gates,
1565         .gates_map      = stm32f42xx_gate_map,
1566         .gates_num      = ARRAY_SIZE(stm32f429_gates),
1567         .pll_data       = stm32f429_pll,
1568         .aux_clk        = stm32f429_aux_clk,
1569         .aux_clk_num    = ARRAY_SIZE(stm32f429_aux_clk),
1570 };
1571
1572 static const struct stm32f4_clk_data stm32f469_clk_data = {
1573         .end_primary    = END_PRIMARY_CLK,
1574         .gates_data     = stm32f469_gates,
1575         .gates_map      = stm32f46xx_gate_map,
1576         .gates_num      = ARRAY_SIZE(stm32f469_gates),
1577         .pll_data       = stm32f469_pll,
1578         .aux_clk        = stm32f469_aux_clk,
1579         .aux_clk_num    = ARRAY_SIZE(stm32f469_aux_clk),
1580 };
1581
1582 static const struct stm32f4_clk_data stm32f746_clk_data = {
1583         .end_primary    = END_PRIMARY_CLK_F7,
1584         .gates_data     = stm32f746_gates,
1585         .gates_map      = stm32f746_gate_map,
1586         .gates_num      = ARRAY_SIZE(stm32f746_gates),
1587         .pll_data       = stm32f469_pll,
1588         .aux_clk        = stm32f746_aux_clk,
1589         .aux_clk_num    = ARRAY_SIZE(stm32f746_aux_clk),
1590 };
1591
1592 static const struct stm32f4_clk_data stm32f769_clk_data = {
1593         .end_primary    = END_PRIMARY_CLK_F7,
1594         .gates_data     = stm32f769_gates,
1595         .gates_map      = stm32f769_gate_map,
1596         .gates_num      = ARRAY_SIZE(stm32f769_gates),
1597         .pll_data       = stm32f469_pll,
1598         .aux_clk        = stm32f769_aux_clk,
1599         .aux_clk_num    = ARRAY_SIZE(stm32f769_aux_clk),
1600 };
1601
1602 static const struct of_device_id stm32f4_of_match[] = {
1603         {
1604                 .compatible = "st,stm32f42xx-rcc",
1605                 .data = &stm32f429_clk_data
1606         },
1607         {
1608                 .compatible = "st,stm32f469-rcc",
1609                 .data = &stm32f469_clk_data
1610         },
1611         {
1612                 .compatible = "st,stm32f746-rcc",
1613                 .data = &stm32f746_clk_data
1614         },
1615         {
1616                 .compatible = "st,stm32f769-rcc",
1617                 .data = &stm32f769_clk_data
1618         },
1619         {}
1620 };
1621
1622 static struct clk_hw *stm32_register_aux_clk(const char *name,
1623                 const char * const *parent_names, int num_parents,
1624                 int offset_mux, u8 shift, u8 mask,
1625                 int offset_gate, u8 bit_idx,
1626                 unsigned long flags, spinlock_t *lock)
1627 {
1628         struct clk_hw *hw;
1629         struct clk_gate *gate = NULL;
1630         struct clk_mux *mux = NULL;
1631         struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
1632         const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
1633
1634         if (offset_gate != NO_GATE) {
1635                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1636                 if (!gate) {
1637                         hw = ERR_PTR(-EINVAL);
1638                         goto fail;
1639                 }
1640
1641                 gate->reg = base + offset_gate;
1642                 gate->bit_idx = bit_idx;
1643                 gate->flags = 0;
1644                 gate->lock = lock;
1645                 gate_hw = &gate->hw;
1646                 gate_ops = &clk_gate_ops;
1647         }
1648
1649         if (offset_mux != NO_MUX) {
1650                 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1651                 if (!mux) {
1652                         hw = ERR_PTR(-EINVAL);
1653                         goto fail;
1654                 }
1655
1656                 mux->reg = base + offset_mux;
1657                 mux->shift = shift;
1658                 mux->mask = mask;
1659                 mux->flags = 0;
1660                 mux_hw = &mux->hw;
1661                 mux_ops = &clk_mux_ops;
1662         }
1663
1664         if (mux_hw == NULL && gate_hw == NULL) {
1665                 hw = ERR_PTR(-EINVAL);
1666                 goto fail;
1667         }
1668
1669         hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
1670                         mux_hw, mux_ops,
1671                         NULL, NULL,
1672                         gate_hw, gate_ops,
1673                         flags);
1674
1675 fail:
1676         if (IS_ERR(hw)) {
1677                 kfree(gate);
1678                 kfree(mux);
1679         }
1680
1681         return hw;
1682 }
1683
1684 static void __init stm32f4_rcc_init(struct device_node *np)
1685 {
1686         const char *hse_clk, *i2s_in_clk;
1687         int n;
1688         const struct of_device_id *match;
1689         const struct stm32f4_clk_data *data;
1690         unsigned long pllm;
1691         struct clk_hw *pll_src_hw;
1692
1693         base = of_iomap(np, 0);
1694         if (!base) {
1695                 pr_err("%pOFn: unable to map resource\n", np);
1696                 return;
1697         }
1698
1699         pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1700         if (IS_ERR(pdrm)) {
1701                 pdrm = NULL;
1702                 pr_warn("%s: Unable to get syscfg\n", __func__);
1703         }
1704
1705         match = of_match_node(stm32f4_of_match, np);
1706         if (WARN_ON(!match))
1707                 return;
1708
1709         data = match->data;
1710
1711         stm32fx_end_primary_clk = data->end_primary;
1712
1713         clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
1714                         sizeof(*clks), GFP_KERNEL);
1715         if (!clks)
1716                 goto fail;
1717
1718         stm32f4_gate_map = data->gates_map;
1719
1720         hse_clk = of_clk_get_parent_name(np, 0);
1721         dsi_parent[0] = hse_clk;
1722         pllsrc_parent[1] = hse_clk;
1723
1724         i2s_in_clk = of_clk_get_parent_name(np, 1);
1725
1726         i2s_parents[1] = i2s_in_clk;
1727         sai_parents[2] = i2s_in_clk;
1728
1729         if (of_device_is_compatible(np, "st,stm32f769-rcc")) {
1730                 clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
1731                                      base + STM32F4_RCC_APB2ENR, 29,
1732                                      CLK_IGNORE_UNUSED, &stm32f4_clk_lock);
1733                 dsi_parent[0] = pll_src;
1734                 sai_parents[3] = pll_src;
1735         }
1736
1737         clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
1738                         NULL, 0, 16000000, 160000);
1739
1740         pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent,
1741                                          ARRAY_SIZE(pllsrc_parent), 0,
1742                                          base + STM32F4_RCC_PLLCFGR, 22, 1, 0,
1743                                          &stm32f4_clk_lock);
1744
1745         pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f;
1746
1747         clk_hw_register_fixed_factor(NULL, "vco_in", pll_src,
1748                                      0, 1, pllm);
1749
1750         stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
1751                         &stm32f4_clk_lock);
1752
1753         clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
1754                         &data->pll_data[1], &stm32f4_clk_lock);
1755
1756         clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
1757                         &data->pll_data[2], &stm32f4_clk_lock);
1758
1759         for (n = 0; n < MAX_POST_DIV; n++) {
1760                 const struct stm32f4_pll_post_div_data *post_div;
1761                 struct clk_hw *hw;
1762
1763                 post_div = &post_div_data[n];
1764
1765                 hw = clk_register_pll_div(post_div->name,
1766                                 post_div->parent,
1767                                 post_div->flag,
1768                                 base + post_div->offset,
1769                                 post_div->shift,
1770                                 post_div->width,
1771                                 post_div->flag_div,
1772                                 post_div->div_table,
1773                                 clks[post_div->pll_idx],
1774                                 &stm32f4_clk_lock);
1775
1776                 if (post_div->idx != NO_IDX)
1777                         clks[post_div->idx] = hw;
1778         }
1779
1780         sys_parents[1] = hse_clk;
1781
1782         clks[CLK_SYSCLK] = clk_hw_register_mux_table(
1783             NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
1784             base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1785
1786         clk_register_divider_table(NULL, "ahb_div", "sys",
1787                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1788                                    4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
1789
1790         clk_register_divider_table(NULL, "apb1_div", "ahb_div",
1791                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1792                                    10, 3, 0, apb_div_table, &stm32f4_clk_lock);
1793         clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
1794                              CLK_SET_RATE_PARENT, 12);
1795
1796         clk_register_divider_table(NULL, "apb2_div", "ahb_div",
1797                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1798                                    13, 3, 0, apb_div_table, &stm32f4_clk_lock);
1799         clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
1800                              CLK_SET_RATE_PARENT, 15);
1801
1802         clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
1803                                                   0, 1, 8);
1804         clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
1805                                                0, 1, 1);
1806
1807         for (n = 0; n < data->gates_num; n++) {
1808                 const struct stm32f4_gate_data *gd;
1809                 unsigned int secondary;
1810                 int idx;
1811
1812                 gd = &data->gates_data[n];
1813                 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
1814                         gd->bit_idx;
1815                 idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
1816
1817                 if (idx < 0)
1818                         goto fail;
1819
1820                 clks[idx] = clk_hw_register_gate(
1821                     NULL, gd->name, gd->parent_name, gd->flags,
1822                     base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1823
1824                 if (IS_ERR(clks[idx])) {
1825                         pr_err("%pOF: Unable to register leaf clock %s\n",
1826                                np, gd->name);
1827                         goto fail;
1828                 }
1829         }
1830
1831         clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1832                         base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
1833
1834         if (IS_ERR(clks[CLK_LSI])) {
1835                 pr_err("Unable to register lsi clock\n");
1836                 goto fail;
1837         }
1838
1839         clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1840                         base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
1841
1842         if (IS_ERR(clks[CLK_LSE])) {
1843                 pr_err("Unable to register lse clock\n");
1844                 goto fail;
1845         }
1846
1847         clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
1848                         0, base + STM32F4_RCC_CFGR, 16, 5, 0,
1849                         &stm32f4_clk_lock);
1850
1851         if (IS_ERR(clks[CLK_HSE_RTC])) {
1852                 pr_err("Unable to register hse-rtc clock\n");
1853                 goto fail;
1854         }
1855
1856         clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
1857                         base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
1858
1859         if (IS_ERR(clks[CLK_RTC])) {
1860                 pr_err("Unable to register rtc clock\n");
1861                 goto fail;
1862         }
1863
1864         for (n = 0; n < data->aux_clk_num; n++) {
1865                 const struct stm32_aux_clk *aux_clk;
1866                 struct clk_hw *hw;
1867
1868                 aux_clk = &data->aux_clk[n];
1869
1870                 hw = stm32_register_aux_clk(aux_clk->name,
1871                                 aux_clk->parent_names, aux_clk->num_parents,
1872                                 aux_clk->offset_mux, aux_clk->shift,
1873                                 aux_clk->mask, aux_clk->offset_gate,
1874                                 aux_clk->bit_idx, aux_clk->flags,
1875                                 &stm32f4_clk_lock);
1876
1877                 if (IS_ERR(hw)) {
1878                         pr_warn("Unable to register %s clk\n", aux_clk->name);
1879                         continue;
1880                 }
1881
1882                 if (aux_clk->idx != NO_IDX)
1883                         clks[aux_clk->idx] = hw;
1884         }
1885
1886         if (of_device_is_compatible(np, "st,stm32f746-rcc")) {
1887
1888                 clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
1889                                 1, 488);
1890
1891                 clks[CLK_PLL_SRC] = pll_src_hw;
1892         }
1893
1894         of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
1895
1896         return;
1897 fail:
1898         kfree(clks);
1899         iounmap(base);
1900 }
1901 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1902 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
1903 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
1904 CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init);