drivers/clk/clk-lmk04832.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
   4  * Pin compatible with the LMK0482x family
   5  *
   6  * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf
   7  *
   8  * Copyright (c) 2020, Xiphos Systems Corp.
   9  *
  10  */
  11
  12 #include <linux/bitfield.h>
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/device.h>
  17 #include <linux/gcd.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/module.h>
  20 #include <linux/uaccess.h>
  21 #include <linux/regmap.h>
  22 #include <linux/spi/spi.h>
  23
  24 /* 0x000 - 0x00d System Functions */
  25 #define LMK04832_REG_RST3W              0x000
  26 #define LMK04832_BIT_RESET                      BIT(7)
  27 #define LMK04832_BIT_SPI_3WIRE_DIS              BIT(4)
  28 #define LMK04832_REG_POWERDOWN          0x002
  29 #define LMK04832_REG_ID_DEV_TYPE        0x003
  30 #define LMK04832_REG_ID_PROD_MSB        0x004
  31 #define LMK04832_REG_ID_PROD_LSB        0x005
  32 #define LMK04832_REG_ID_MASKREV         0x006
  33 #define LMK04832_REG_ID_VNDR_MSB        0x00c
  34 #define LMK04832_REG_ID_VNDR_LSB        0x00d
  35
  36 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
  37 #define LMK04832_REG_CLKOUT_CTRL0(ch)   (0x100 + (ch >> 1) * 8)
  38 #define LMK04832_BIT_DCLK_DIV_LSB               GENMASK(7, 0)
  39 #define LMK04832_REG_CLKOUT_CTRL1(ch)   (0x101 + (ch >> 1) * 8)
  40 #define LMK04832_BIT_DCLKX_Y_DDLY_LSB           GENMASK(7, 0)
  41 #define LMK04832_REG_CLKOUT_CTRL2(ch)   (0x102 + (ch >> 1) * 8)
  42 #define LMK04832_BIT_CLKOUTX_Y_PD               BIT(7)
  43 #define LMK04832_BIT_DCLKX_Y_DDLY_PD            BIT(4)
  44 #define LMK04832_BIT_DCLKX_Y_DDLY_MSB           GENMASK(3, 2)
  45 #define LMK04832_BIT_DCLK_DIV_MSB               GENMASK(1, 0)
  46 #define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8)
  47 #define LMK04832_BIT_CLKOUT_SRC_MUX             BIT(5)
  48 #define LMK04832_REG_CLKOUT_CTRL3(ch)   (0x103 + (ch >> 1) * 8)
  49 #define LMK04832_BIT_DCLKX_Y_PD                 BIT(4)
  50 #define LMK04832_BIT_DCLKX_Y_DCC                BIT(2)
  51 #define LMK04832_BIT_DCLKX_Y_HS                 BIT(0)
  52 #define LMK04832_REG_CLKOUT_CTRL4(ch)   (0x104 + (ch >> 1) * 8)
  53 #define LMK04832_BIT_SCLK_PD                    BIT(4)
  54 #define LMK04832_BIT_SCLKX_Y_DIS_MODE           GENMASK(3, 2)
  55 #define LMK04832_REG_SCLKX_Y_ADLY(ch)   (0x105 + (ch >> 1) * 8)
  56 #define LMK04832_REG_SCLKX_Y_DDLY(ch)   (0x106 + (ch >> 1) * 8)
  57 #define LMK04832_BIT_SCLKX_Y_DDLY               GENMASK(3, 0)
  58 #define LMK04832_REG_CLKOUT_FMT(ch)     (0x107 + (ch >> 1) * 8)
  59 #define LMK04832_BIT_CLKOUT_FMT(ch)             (ch % 2 ? 0xf0 : 0x0f)
  60 #define LMK04832_VAL_CLKOUT_FMT_POWERDOWN               0x00
  61 #define LMK04832_VAL_CLKOUT_FMT_LVDS                    0x01
  62 #define LMK04832_VAL_CLKOUT_FMT_HSDS6                   0x02
  63 #define LMK04832_VAL_CLKOUT_FMT_HSDS8                   0x03
  64 #define LMK04832_VAL_CLKOUT_FMT_LVPECL1600              0x04
  65 #define LMK04832_VAL_CLKOUT_FMT_LVPECL2000              0x05
  66 #define LMK04832_VAL_CLKOUT_FMT_LCPECL                  0x06
  67 #define LMK04832_VAL_CLKOUT_FMT_CML16                   0x07
  68 #define LMK04832_VAL_CLKOUT_FMT_CML24                   0x08
  69 #define LMK04832_VAL_CLKOUT_FMT_CML32                   0x09
  70 #define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV            0x0a
  71 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF            0x0b
  72 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV            0x0c
  73 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR            0x0d
  74 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV            0x0e
  75 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR            0x0f
  76
  77 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
  78 #define LMK04832_REG_VCO_OSCOUT         0x138
  79 #define LMK04832_BIT_VCO_MUX                    GENMASK(6, 5)
  80 #define LMK04832_VAL_VCO_MUX_VCO0                       0x00
  81 #define LMK04832_VAL_VCO_MUX_VCO1                       0x01
  82 #define LMK04832_VAL_VCO_MUX_EXT                        0x02
  83 #define LMK04832_REG_SYSREF_OUT         0x139
  84 #define LMK04832_BIT_SYSREF_REQ_EN              BIT(6)
  85 #define LMK04832_BIT_SYSREF_MUX                 GENMASK(1, 0)
  86 #define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC             0x00
  87 #define LMK04832_VAL_SYSREF_MUX_RECLK                   0x01
  88 #define LMK04832_VAL_SYSREF_MUX_PULSER                  0x02
  89 #define LMK04832_VAL_SYSREF_MUX_CONTINUOUS              0x03
  90 #define LMK04832_REG_SYSREF_DIV_MSB     0x13a
  91 #define LMK04832_BIT_SYSREF_DIV_MSB             GENMASK(4, 0)
  92 #define LMK04832_REG_SYSREF_DIV_LSB     0x13b
  93 #define LMK04832_REG_SYSREF_DDLY_MSB    0x13c
  94 #define LMK04832_BIT_SYSREF_DDLY_MSB            GENMASK(4, 0)
  95 #define LMK04832_REG_SYSREF_DDLY_LSB    0x13d
  96 #define LMK04832_REG_SYSREF_PULSE_CNT   0x13e
  97 #define LMK04832_REG_FB_CTRL            0x13f
  98 #define LMK04832_BIT_PLL2_RCLK_MUX              BIT(7)
  99 #define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN                0x00
 100 #define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN                0x01
 101 #define LMK04832_BIT_PLL2_NCLK_MUX              BIT(5)
 102 #define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P               0x00
 103 #define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX               0x01
 104 #define LMK04832_BIT_FB_MUX_EN                  BIT(0)
 105 #define LMK04832_REG_MAIN_PD            0x140
 106 #define LMK04832_BIT_PLL1_PD                    BIT(7)
 107 #define LMK04832_BIT_VCO_LDO_PD                 BIT(6)
 108 #define LMK04832_BIT_VCO_PD                     BIT(5)
 109 #define LMK04832_BIT_OSCIN_PD                   BIT(4)
 110 #define LMK04832_BIT_SYSREF_GBL_PD              BIT(3)
 111 #define LMK04832_BIT_SYSREF_PD                  BIT(2)
 112 #define LMK04832_BIT_SYSREF_DDLY_PD             BIT(1)
 113 #define LMK04832_BIT_SYSREF_PLSR_PD             BIT(0)
 114 #define LMK04832_REG_SYNC               0x143
 115 #define LMK04832_BIT_SYNC_CLR                   BIT(7)
 116 #define LMK04832_BIT_SYNC_1SHOT_EN              BIT(6)
 117 #define LMK04832_BIT_SYNC_POL                   BIT(5)
 118 #define LMK04832_BIT_SYNC_EN                    BIT(4)
 119 #define LMK04832_BIT_SYNC_MODE                  GENMASK(1, 0)
 120 #define LMK04832_VAL_SYNC_MODE_OFF                      0x00
 121 #define LMK04832_VAL_SYNC_MODE_ON                       0x01
 122 #define LMK04832_VAL_SYNC_MODE_PULSER_PIN               0x02
 123 #define LMK04832_VAL_SYNC_MODE_PULSER_SPI               0x03
 124 #define LMK04832_REG_SYNC_DIS           0x144
 125
 126 /* 0x146 - 0x14a CLKin Control */
 127 #define LMK04832_REG_CLKIN_SEL0         0x148
 128 #define LMK04832_REG_CLKIN_SEL1         0x149
 129 #define LMK04832_REG_CLKIN_RST          0x14a
 130 #define LMK04832_BIT_SDIO_RDBK_TYPE             BIT(6)
 131 #define LMK04832_BIT_CLKIN_SEL_MUX              GENMASK(5, 3)
 132 #define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK             0x06
 133 #define LMK04832_BIT_CLKIN_SEL_TYPE             GENMASK(2, 0)
 134 #define LMK04832_VAL_CLKIN_SEL_TYPE_OUT                 0x03
 135
 136 /* 0x14b - 0x152 Holdover */
 137
 138 /* 0x153 - 0x15f PLL1 Configuration */
 139
 140 /* 0x160 - 0x16e PLL2 Configuration */
 141 #define LMK04832_REG_PLL2_R_MSB         0x160
 142 #define LMK04832_BIT_PLL2_R_MSB                 GENMASK(3, 0)
 143 #define LMK04832_REG_PLL2_R_LSB         0x161
 144 #define LMK04832_REG_PLL2_MISC          0x162
 145 #define LMK04832_BIT_PLL2_MISC_P                GENMASK(7, 5)
 146 #define LMK04832_BIT_PLL2_MISC_REF_2X_EN        BIT(0)
 147 #define LMK04832_REG_PLL2_N_CAL_0       0x163
 148 #define LMK04832_BIT_PLL2_N_CAL_0               GENMASK(1, 0)
 149 #define LMK04832_REG_PLL2_N_CAL_1       0x164
 150 #define LMK04832_REG_PLL2_N_CAL_2       0x165
 151 #define LMK04832_REG_PLL2_N_0           0x166
 152 #define LMK04832_BIT_PLL2_N_0                   GENMASK(1, 0)
 153 #define LMK04832_REG_PLL2_N_1           0x167
 154 #define LMK04832_REG_PLL2_N_2           0x168
 155 #define LMK04832_REG_PLL2_DLD_CNT_MSB   0x16a
 156 #define LMK04832_REG_PLL2_DLD_CNT_LSB   0x16b
 157 #define LMK04832_REG_PLL2_LD            0x16e
 158 #define LMK04832_BIT_PLL2_LD_MUX                GENMASK(7, 3)
 159 #define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD               0x02
 160 #define LMK04832_BIT_PLL2_LD_TYPE               GENMASK(2, 0)
 161 #define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP                0x03
 162
 163 /* 0x16F - 0x555 Misc Registers */
 164 #define LMK04832_REG_PLL2_PD            0x173
 165 #define LMK04832_BIT_PLL2_PRE_PD                BIT(6)
 166 #define LMK04832_BIT_PLL2_PD                    BIT(5)
 167 #define LMK04832_REG_PLL1R_RST          0x177
 168 #define LMK04832_REG_CLR_PLL_LOST       0x182
 169 #define LMK04832_REG_RB_PLL_LD          0x183
 170 #define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184
 171 #define LMK04832_REG_RB_DAC_VAL_LSB     0x185
 172 #define LMK04832_REG_RB_HOLDOVER        0x188
 173 #define LMK04832_REG_SPI_LOCK           0x555
 174
 175 enum lmk04832_device_types {
 176         LMK04832,
 177 };
 178
 179 /**
 180  * lmk04832_device_info - Holds static device information that is specific to
 181  *                        the chip revision
 182  *
 183  * pid:          Product Identifier
 184  * maskrev:      IC version identifier
 185  * num_channels: Number of available output channels (clkout count)
 186  * vco0_range:   {min, max} of the VCO0 operating range (in MHz)
 187  * vco1_range:   {min, max} of the VCO1 operating range (in MHz)
 188  */
 189 struct lmk04832_device_info {
 190         u16 pid;
 191         u8 maskrev;
 192         size_t num_channels;
 193         unsigned int vco0_range[2];
 194         unsigned int vco1_range[2];
 195 };
 196
 197 static const struct lmk04832_device_info lmk04832_device_info[] = {
 198         [LMK04832] = {
 199                 .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */
 200                 .maskrev = 0x70,
 201                 .num_channels = 14,
 202                 .vco0_range = { 2440, 2580 },
 203                 .vco1_range = { 2945, 3255 },
 204         },
 205 };
 206
 207 enum lmk04832_rdbk_type {
 208         RDBK_CLKIN_SEL0,
 209         RDBK_CLKIN_SEL1,
 210         RDBK_RESET,
 211 };
 212
 213 struct lmk_dclk {
 214         struct lmk04832 *lmk;
 215         struct clk_hw hw;
 216         u8 id;
 217 };
 218
 219 struct lmk_clkout {
 220         struct lmk04832 *lmk;
 221         struct clk_hw hw;
 222         bool sysref;
 223         u32 format;
 224         u8 id;
 225 };
 226
 227 /**
 228  * struct lmk04832 - The LMK04832 device structure
 229  *
 230  * @dev: reference to a struct device, linked to the spi_device
 231  * @regmap: struct regmap instance use to access the chip
 232  * @sync_mode: operational mode for SYNC signal
 233  * @sysref_mux: select SYSREF source
 234  * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
 235  *                    mode.
 236  * @sysref_ddly: SYSREF digital delay value
 237  * @oscin: PLL2 input clock
 238  * @vco: reference to the internal VCO clock
 239  * @sclk: reference to the internal sysref clock (SCLK)
 240  * @vco_rate: user provided VCO rate
 241  * @reset_gpio: reference to the reset GPIO
 242  * @dclk: list of internal device clock references.
 243  *        Each pair of clkout clocks share a single device clock (DCLKX_Y)
 244  * @clkout: list of output clock references
 245  * @clk_data: holds clkout related data like clk_hw* and number of clocks
 246  */
 247 struct lmk04832 {
 248         struct device *dev;
 249         struct regmap *regmap;
 250
 251         unsigned int sync_mode;
 252         unsigned int sysref_mux;
 253         unsigned int sysref_pulse_cnt;
 254         unsigned int sysref_ddly;
 255
 256         struct clk *oscin;
 257         struct clk_hw vco;
 258         struct clk_hw sclk;
 259         unsigned int vco_rate;
 260
 261         struct gpio_desc *reset_gpio;
 262
 263         struct lmk_dclk *dclk;
 264         struct lmk_clkout *clkout;
 265         struct clk_hw_onecell_data *clk_data;
 266 };
 267
 268 static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg)
 269 {
 270         switch (reg) {
 271         case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV:
 272                 fallthrough;
 273         case LMK04832_REG_ID_VNDR_MSB:
 274                 fallthrough;
 275         case LMK04832_REG_ID_VNDR_LSB:
 276                 fallthrough;
 277         case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
 278                 fallthrough;
 279         case LMK04832_REG_PLL2_LD:
 280                 fallthrough;
 281         case LMK04832_REG_PLL2_PD:
 282                 fallthrough;
 283         case LMK04832_REG_PLL1R_RST:
 284                 fallthrough;
 285         case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
 286                 fallthrough;
 287         case LMK04832_REG_RB_HOLDOVER:
 288                 fallthrough;
 289         case LMK04832_REG_SPI_LOCK:
 290                 return true;
 291         default:
 292                 return false;
 293         };
 294 };
 295
 296 static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
 297 {
 298         switch (reg) {
 299         case LMK04832_REG_RST3W:
 300                 fallthrough;
 301         case LMK04832_REG_POWERDOWN:
 302                 return true;
 303         case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV:
 304                 fallthrough;
 305         case LMK04832_REG_ID_VNDR_MSB:
 306                 fallthrough;
 307         case LMK04832_REG_ID_VNDR_LSB:
 308                 return false;
 309         case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
 310                 fallthrough;
 311         case LMK04832_REG_PLL2_LD:
 312                 fallthrough;
 313         case LMK04832_REG_PLL2_PD:
 314                 fallthrough;
 315         case LMK04832_REG_PLL1R_RST:
 316                 fallthrough;
 317         case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
 318                 fallthrough;
 319         case LMK04832_REG_RB_HOLDOVER:
 320                 fallthrough;
 321         case LMK04832_REG_SPI_LOCK:
 322                 return true;
 323         default:
 324                 return false;
 325         };
 326 };
 327
 328 static const struct regmap_config regmap_config = {
 329         .name = "lmk04832",
 330         .reg_bits = 16,
 331         .val_bits = 8,
 332         .use_single_read = 1,
 333         .use_single_write = 1,
 334         .read_flag_mask = 0x80,
 335         .write_flag_mask = 0x00,
 336         .readable_reg = lmk04832_regmap_rd_regs,
 337         .writeable_reg = lmk04832_regmap_wr_regs,
 338         .cache_type = REGCACHE_NONE,
 339         .max_register = LMK04832_REG_SPI_LOCK,
 340 };
 341
 342 static int lmk04832_vco_is_enabled(struct clk_hw *hw)
 343 {
 344         struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 345         unsigned int tmp;
 346         int ret;
 347
 348         ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
 349         if (ret)
 350                 return ret;
 351
 352         return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) |
 353                  FIELD_GET(LMK04832_BIT_VCO_PD, tmp) |
 354                  FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp));
 355 }
 356
 357 static int lmk04832_vco_prepare(struct clk_hw *hw)
 358 {
 359         struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 360         int ret;
 361
 362         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
 363                                  LMK04832_BIT_PLL2_PRE_PD |
 364                                  LMK04832_BIT_PLL2_PD,
 365                                  0x00);
 366         if (ret)
 367                 return ret;
 368
 369         return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 370                                   LMK04832_BIT_VCO_LDO_PD |
 371                                   LMK04832_BIT_VCO_PD |
 372                                   LMK04832_BIT_OSCIN_PD, 0x00);
 373 }
 374
 375 static void lmk04832_vco_unprepare(struct clk_hw *hw)
 376 {
 377         struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 378
 379         regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
 380                            LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD,
 381                            0xff);
 382
 383         /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */
 384         regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 385                            LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff);
 386 }
 387
 388 static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
 389                                               unsigned long prate)
 390 {
 391         struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 392         unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
 393         unsigned int pll2_n, p, pll2_r;
 394         unsigned int pll2_misc;
 395         unsigned long vco_rate;
 396         u8 tmp[3];
 397         int ret;
 398
 399         ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc);
 400         if (ret)
 401                 return ret;
 402
 403         p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc);
 404
 405         ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3);
 406         if (ret)
 407                 return ret;
 408
 409         pll2_n = FIELD_PREP(0x030000, tmp[0]) |
 410                  FIELD_PREP(0x00ff00, tmp[1]) |
 411                  FIELD_PREP(0x0000ff, tmp[2]);
 412
 413         ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2);
 414         if (ret)
 415                 return ret;
 416
 417         pll2_r = FIELD_PREP(0x0f00, tmp[0]) |
 418                  FIELD_PREP(0x00ff, tmp[1]);
 419
 420         vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN,
 421                                        pll2_misc)) * pll2_n * pll2_p[p] / pll2_r;
 422
 423         return vco_rate;
 424 };
 425
 426 /**
 427  * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
 428  *
 429  * @lmk:   Reference to the lmk device
 430  * @rate:  Desired output rate for the VCO
 431  *
 432  * The LMK04832 has 2 internal VCO, each with independent operating ranges.
 433  * Use the device_info structure to determine which VCO to use based on rate.
 434  *
 435  * Returns VCO_MUX value or negative errno.
 436  */
 437 static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
 438 {
 439         struct spi_device *spi = to_spi_device(lmk->dev);
 440         const struct lmk04832_device_info *info;
 441         unsigned long mhz = rate / 1000000;
 442
 443         info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
 444
 445         if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1])
 446                 return LMK04832_VAL_VCO_MUX_VCO0;
 447
 448         if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1])
 449                 return LMK04832_VAL_VCO_MUX_VCO1;
 450
 451         dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate);
 452         return -ERANGE;
 453 }
 454
 455 /**
 456  * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
 457  *
 458  * @prate: parent rate to the PLL2, usually OSCin
 459  * @rate:  Desired output rate for the VCO
 460  * @n:     reference to PLL2_N
 461  * @p:     reference to PLL2_P
 462  * @r:     reference to PLL2_R
 463  *
 464  * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is
 465  * recommended in the datasheet because a higher phase detector frequencies
 466  * makes the design of wider loop bandwidth filters possible.
 467  *
 468  * the VCO rate can be calculated using the following expression:
 469  *
 470  *      VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
 471  *
 472  * Returns vco rate or negative errno.
 473  */
 474 static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate,
 475                                       unsigned int *n, unsigned int *p,
 476                                       unsigned int *r)
 477 {
 478         unsigned int pll2_n, pll2_p, pll2_r;
 479         unsigned long num, div;
 480
 481         /* Set PLL2_P to a fixed value to simplify optimizations */
 482         pll2_p = 2;
 483
 484         div = gcd(rate, prate);
 485
 486         num = DIV_ROUND_CLOSEST(rate, div);
 487         pll2_r = DIV_ROUND_CLOSEST(prate, div);
 488
 489         if (num > 4) {
 490                 pll2_n = num >> 2;
 491         } else {
 492                 pll2_r = pll2_r << 2;
 493                 pll2_n = num;
 494         }
 495
 496         if (pll2_n < 1 || pll2_n > 0x03ffff)
 497                 return -EINVAL;
 498         if (pll2_r < 1 || pll2_r > 0xfff)
 499                 return -EINVAL;
 500
 501         *n = pll2_n;
 502         *p = pll2_p;
 503         *r = pll2_r;
 504
 505         return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r);
 506 }
 507
 508 static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
 509                                     unsigned long *prate)
 510 {
 511         struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 512         unsigned int n, p, r;
 513         long vco_rate;
 514         int ret;
 515
 516         ret = lmk04832_check_vco_ranges(lmk, rate);
 517         if (ret < 0)
 518                 return ret;
 519
 520         vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
 521         if (vco_rate < 0) {
 522                 dev_err(lmk->dev, "PLL2 parameters out of range\n");
 523                 return vco_rate;
 524         }
 525
 526         if (rate != vco_rate)
 527                 return -EINVAL;
 528
 529         return vco_rate;
 530 };
 531
 532 static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 533                                  unsigned long prate)
 534 {
 535         struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
 536         unsigned int n, p, r;
 537         long vco_rate;
 538         int vco_mux;
 539         int ret;
 540
 541         vco_mux = lmk04832_check_vco_ranges(lmk, rate);
 542         if (vco_mux < 0)
 543                 return vco_mux;
 544
 545         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
 546                                  LMK04832_BIT_VCO_MUX,
 547                                  FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux));
 548         if (ret)
 549                 return ret;
 550
 551         vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
 552         if (vco_rate < 0) {
 553                 dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
 554                 return vco_rate;
 555         }
 556
 557         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB,
 558                                  LMK04832_BIT_PLL2_R_MSB,
 559                                  FIELD_GET(0x000700, r));
 560         if (ret)
 561                 return ret;
 562
 563         ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB,
 564                            FIELD_GET(0x0000ff, r));
 565         if (ret)
 566                 return ret;
 567
 568         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
 569                                  LMK04832_BIT_PLL2_MISC_P,
 570                                  FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p));
 571         if (ret)
 572                 return ret;
 573
 574         /*
 575          * PLL2_N registers must be programmed after other PLL2 dividers are
 576          * programmed to ensure proper VCO frequency calibration
 577          */
 578         ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
 579                            FIELD_GET(0x030000, n));
 580         if (ret)
 581                 return ret;
 582         ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1,
 583                            FIELD_GET(0x00ff00, n));
 584         if (ret)
 585                 return ret;
 586
 587         return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2,
 588                             FIELD_GET(0x0000ff, n));
 589 };
 590
 591 static const struct clk_ops lmk04832_vco_ops = {
 592         .is_enabled = lmk04832_vco_is_enabled,
 593         .prepare = lmk04832_vco_prepare,
 594         .unprepare = lmk04832_vco_unprepare,
 595         .recalc_rate = lmk04832_vco_recalc_rate,
 596         .round_rate = lmk04832_vco_round_rate,
 597         .set_rate = lmk04832_vco_set_rate,
 598 };
 599
 600 /*
 601  * lmk04832_register_vco - Initialize the internal VCO and clock distribution
 602  *                         path in PLL2 single loop mode.
 603  */
 604 static int lmk04832_register_vco(struct lmk04832 *lmk)
 605 {
 606         const char *parent_names[1];
 607         struct clk_init_data init;
 608         int ret;
 609
 610         init.name = "lmk-vco";
 611         parent_names[0] = __clk_get_name(lmk->oscin);
 612         init.parent_names = parent_names;
 613
 614         init.ops = &lmk04832_vco_ops;
 615         init.num_parents = 1;
 616
 617         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
 618                                  LMK04832_BIT_VCO_MUX,
 619                                  FIELD_PREP(LMK04832_BIT_VCO_MUX,
 620                                             LMK04832_VAL_VCO_MUX_VCO1));
 621         if (ret)
 622                 return ret;
 623
 624         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL,
 625                                  LMK04832_BIT_PLL2_RCLK_MUX |
 626                                  LMK04832_BIT_PLL2_NCLK_MUX,
 627                                  FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX,
 628                                             LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)|
 629                                  FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX,
 630                                             LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P));
 631         if (ret)
 632                 return ret;
 633
 634         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
 635                                  LMK04832_BIT_PLL2_MISC_REF_2X_EN,
 636                                  LMK04832_BIT_PLL2_MISC_REF_2X_EN);
 637         if (ret)
 638                 return ret;
 639
 640         ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD,
 641                            FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX,
 642                                       LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) |
 643                            FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE,
 644                                       LMK04832_VAL_PLL2_LD_TYPE_OUT_PP));
 645         if (ret)
 646                 return ret;
 647
 648         lmk->vco.init = &init;
 649         return devm_clk_hw_register(lmk->dev, &lmk->vco);
 650 }
 651
 652 static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
 653 {
 654         int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
 655         unsigned int sclkx_y_ddly = 10;
 656         unsigned int dclkx_y_ddly;
 657         unsigned int dclkx_y_div;
 658         unsigned int sysref_ddly;
 659         unsigned int dclkx_y_hs;
 660         unsigned int lsb, msb;
 661         int ret;
 662
 663         ret = regmap_update_bits(lmk->regmap,
 664                                  LMK04832_REG_CLKOUT_CTRL2(id),
 665                                  LMK04832_BIT_DCLKX_Y_DDLY_PD,
 666                                  FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0));
 667         if (ret)
 668                 return ret;
 669
 670         ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb);
 671         if (ret)
 672                 return ret;
 673
 674         ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb);
 675         if (ret)
 676                 return ret;
 677
 678         sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb;
 679
 680         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb);
 681         if (ret)
 682                 return ret;
 683
 684         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb);
 685         if (ret)
 686                 return ret;
 687
 688         dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
 689
 690         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb);
 691         if (ret)
 692                 return ret;
 693
 694         dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb);
 695
 696         dclkx_y_ddly = sysref_ddly + 1 -
 697                 dclk_div_adj[dclkx_y_div < 6 ?  dclkx_y_div : 7] -
 698                 dclkx_y_hs + sclkx_y_ddly;
 699
 700         if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) {
 701                 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n",
 702                         dclkx_y_ddly);
 703                 return -EINVAL;
 704         }
 705
 706         ret = regmap_write(lmk->regmap,
 707                            LMK04832_REG_SCLKX_Y_DDLY(id),
 708                            FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly));
 709         if (ret)
 710                 return ret;
 711
 712         ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id),
 713                                 FIELD_GET(0x00ff, dclkx_y_ddly));
 714         if (ret)
 715                 return ret;
 716
 717         dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, "
 718                 "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n",
 719                 id, sysref_ddly, dclkx_y_ddly,
 720                 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7],
 721                 dclkx_y_hs, sclkx_y_ddly);
 722
 723         return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id),
 724                                   LMK04832_BIT_DCLKX_Y_DDLY_MSB,
 725                                   FIELD_GET(0x0300, dclkx_y_ddly));
 726 }
 727
 728 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
 729  *                       and dclk
 730  *
 731  * @lmk: Reference to the lmk device
 732  *
 733  * The synchronization sequence:
 734  * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
 735  *   (8.3.3.1 How to enable SYSREF)
 736  * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
 737  *
 738  * Returns 0 or negative errno.
 739  */
 740 static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk)
 741 {
 742         int ret;
 743         int i;
 744
 745         /* 1. (optional) mute all sysref_outputs during synchronization */
 746         /* 2. Enable and write device clock digital delay to applicable clocks */
 747         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 748                                  LMK04832_BIT_SYSREF_DDLY_PD,
 749                                  FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0));
 750         if (ret)
 751                 return ret;
 752
 753         for (i = 0; i < lmk->clk_data->num; i += 2) {
 754                 ret = lmk04832_clkout_set_ddly(lmk, i);
 755                 if (ret)
 756                         return ret;
 757         }
 758
 759         /*
 760          * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC,
 761          *    and clear SYSREF_REQ_EN (see 6.)
 762          */
 763         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
 764                                  LMK04832_BIT_SYSREF_REQ_EN |
 765                                  LMK04832_BIT_SYSREF_MUX,
 766                                  FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) |
 767                                  FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
 768                                             LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC));
 769         if (ret)
 770                 return ret;
 771
 772         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 773                                  LMK04832_BIT_SYNC_MODE,
 774                                  FIELD_PREP(LMK04832_BIT_SYNC_MODE,
 775                                             LMK04832_VAL_SYNC_MODE_ON));
 776         if (ret)
 777                 return ret;
 778
 779         /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */
 780         ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
 781         if (ret)
 782                 return ret;
 783
 784         /*
 785          * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock
 786          *    distribution path cycles (VCO cycles), then back to 0. In
 787          *    PLL2-only use case, this will be complete in less than one SPI
 788          *    transaction. If SYSREF local digital delay is not used, this step
 789          *    can be skipped.
 790          */
 791         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 792                                  LMK04832_BIT_SYNC_CLR,
 793                                  FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01));
 794         if (ret)
 795                 return ret;
 796
 797         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 798                                  LMK04832_BIT_SYNC_CLR,
 799                                  FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
 800         if (ret)
 801                 return ret;
 802
 803         /*
 804          * 6. Toggle SYNC_POL state between inverted and not inverted.
 805          *    If you use an external signal on the SYNC pin instead of toggling
 806          *    SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX
 807          *    does not shift into continuous SYSREF mode.
 808          */
 809         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 810                            LMK04832_BIT_SYNC_POL,
 811                            FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01));
 812         if (ret)
 813                 return ret;
 814
 815         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 816                            LMK04832_BIT_SYNC_POL,
 817                            FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
 818         if (ret)
 819                 return ret;
 820
 821         /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */
 822         ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
 823         if (ret)
 824                 return ret;
 825
 826         /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */
 827         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
 828                                  LMK04832_BIT_SYSREF_MUX,
 829                                  FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
 830                                             lmk->sysref_mux));
 831         if (ret)
 832                 return ret;
 833
 834         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
 835                                  LMK04832_BIT_SYNC_MODE,
 836                                  FIELD_PREP(LMK04832_BIT_SYNC_MODE,
 837                                             lmk->sync_mode));
 838         if (ret)
 839                 return ret;
 840
 841         /*
 842          * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs
 843          *    during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state,
 844          *    or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional
 845          *    option.
 846          */
 847
 848         /*
 849          * 10. (optional) To reduce power consumption, after the synchronization
 850          *     event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the
 851          *     digital delay counters (which are only used immediately after the
 852          *     SYNC pulse to delay the output by some number of VCO counts).
 853          */
 854
 855         return ret;
 856 }
 857
 858 static int lmk04832_sclk_is_enabled(struct clk_hw *hw)
 859 {
 860         struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 861         unsigned int tmp;
 862         int ret;
 863
 864         ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
 865         if (ret)
 866                 return ret;
 867
 868         return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp);
 869 }
 870
 871 static int lmk04832_sclk_prepare(struct clk_hw *hw)
 872 {
 873         struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 874
 875         return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 876                                   LMK04832_BIT_SYSREF_PD, 0x00);
 877 }
 878
 879 static void lmk04832_sclk_unprepare(struct clk_hw *hw)
 880 {
 881         struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 882
 883         regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
 884                            LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD);
 885 }
 886
 887 static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw,
 888                                                unsigned long prate)
 889 {
 890         struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 891         unsigned int sysref_div;
 892         u8 tmp[2];
 893         int ret;
 894
 895         ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2);
 896         if (ret)
 897                 return ret;
 898
 899         sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 |
 900                 tmp[1];
 901
 902         return DIV_ROUND_CLOSEST(prate, sysref_div);
 903 }
 904
 905 static long lmk04832_sclk_round_rate(struct clk_hw *hw, unsigned long rate,
 906                                      unsigned long *prate)
 907 {
 908         struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 909         unsigned long sclk_rate;
 910         unsigned int sysref_div;
 911
 912         sysref_div = DIV_ROUND_CLOSEST(*prate, rate);
 913         sclk_rate = DIV_ROUND_CLOSEST(*prate, sysref_div);
 914
 915         if (sysref_div < 0x07 || sysref_div > 0x1fff) {
 916                 dev_err(lmk->dev, "SYSREF divider out of range\n");
 917                 return -EINVAL;
 918         }
 919
 920         if (rate != sclk_rate)
 921                 return -EINVAL;
 922
 923         return sclk_rate;
 924 }
 925
 926 static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate,
 927                                   unsigned long prate)
 928 {
 929         struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
 930         unsigned int sysref_div;
 931         int ret;
 932
 933         sysref_div = DIV_ROUND_CLOSEST(prate, rate);
 934
 935         if (sysref_div < 0x07 || sysref_div > 0x1fff) {
 936                 dev_err(lmk->dev, "SYSREF divider out of range\n");
 937                 return -EINVAL;
 938         }
 939
 940         ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB,
 941                            FIELD_GET(0x1f00, sysref_div));
 942         if (ret)
 943                 return ret;
 944
 945         ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
 946                             FIELD_GET(0x00ff, sysref_div));
 947         if (ret)
 948                 return ret;
 949
 950         ret = lmk04832_sclk_sync_sequence(lmk);
 951         if (ret)
 952                 dev_err(lmk->dev, "SYNC sequence failed\n");
 953
 954         return ret;
 955 }
 956
 957 static const struct clk_ops lmk04832_sclk_ops = {
 958         .is_enabled = lmk04832_sclk_is_enabled,
 959         .prepare = lmk04832_sclk_prepare,
 960         .unprepare = lmk04832_sclk_unprepare,
 961         .recalc_rate = lmk04832_sclk_recalc_rate,
 962         .round_rate = lmk04832_sclk_round_rate,
 963         .set_rate = lmk04832_sclk_set_rate,
 964 };
 965
 966 static int lmk04832_register_sclk(struct lmk04832 *lmk)
 967 {
 968         const char *parent_names[1];
 969         struct clk_init_data init;
 970         int ret;
 971
 972         init.name = "lmk-sclk";
 973         parent_names[0] = clk_hw_get_name(&lmk->vco);
 974         init.parent_names = parent_names;
 975
 976         init.ops = &lmk04832_sclk_ops;
 977         init.flags = CLK_SET_RATE_PARENT;
 978         init.num_parents = 1;
 979
 980         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
 981                                  LMK04832_BIT_SYSREF_MUX,
 982                                  FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
 983                                             lmk->sysref_mux));
 984         if (ret)
 985                 return ret;
 986
 987         ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB,
 988                            FIELD_GET(0x00ff, lmk->sysref_ddly));
 989         if (ret)
 990                 return ret;
 991
 992         ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB,
 993                            FIELD_GET(0x1f00, lmk->sysref_ddly));
 994         if (ret)
 995                 return ret;
 996
 997         ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT,
 998                            ilog2(lmk->sysref_pulse_cnt));
 999         if (ret)
1000                 return ret;
1001
1002         ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
1003                                  LMK04832_BIT_SYSREF_DDLY_PD |
1004                                  LMK04832_BIT_SYSREF_PLSR_PD,
1005                                  FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) |
1006                                  FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0));
1007         if (ret)
1008                 return ret;
1009
1010         ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC,
1011                            FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) |
1012                            FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) |
1013                            FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode));
1014         if (ret)
1015                 return ret;
1016
1017         ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
1018         if (ret)
1019                 return ret;
1020
1021         lmk->sclk.init = &init;
1022         return devm_clk_hw_register(lmk->dev, &lmk->sclk);
1023 }
1024
1025 static int lmk04832_dclk_is_enabled(struct clk_hw *hw)
1026 {
1027         struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1028         struct lmk04832 *lmk = dclk->lmk;
1029         unsigned int tmp;
1030         int ret;
1031
1032         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1033                           &tmp);
1034         if (ret)
1035                 return ret;
1036
1037         return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp);
1038 }
1039
1040 static int lmk04832_dclk_prepare(struct clk_hw *hw)
1041 {
1042         struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1043         struct lmk04832 *lmk = dclk->lmk;
1044
1045         return regmap_update_bits(lmk->regmap,
1046                                   LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1047                                   LMK04832_BIT_DCLKX_Y_PD, 0x00);
1048 }
1049
1050 static void lmk04832_dclk_unprepare(struct clk_hw *hw)
1051 {
1052         struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1053         struct lmk04832 *lmk = dclk->lmk;
1054
1055         regmap_update_bits(lmk->regmap,
1056                            LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1057                            LMK04832_BIT_DCLKX_Y_PD, 0xff);
1058 }
1059
1060 static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw,
1061                                                unsigned long prate)
1062 {
1063         struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1064         struct lmk04832 *lmk = dclk->lmk;
1065         unsigned int dclk_div;
1066         unsigned int lsb, msb;
1067         unsigned long rate;
1068         int ret;
1069
1070         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1071                           &lsb);
1072         if (ret)
1073                 return ret;
1074
1075         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1076                           &msb);
1077         if (ret)
1078                 return ret;
1079
1080         dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
1081         rate = DIV_ROUND_CLOSEST(prate, dclk_div);
1082
1083         return rate;
1084 };
1085
1086 static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
1087                                      unsigned long *prate)
1088 {
1089         struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1090         struct lmk04832 *lmk = dclk->lmk;
1091         unsigned long dclk_rate;
1092         unsigned int dclk_div;
1093
1094         dclk_div = DIV_ROUND_CLOSEST(*prate, rate);
1095         dclk_rate = DIV_ROUND_CLOSEST(*prate, dclk_div);
1096
1097         if (dclk_div < 1 || dclk_div > 0x3ff) {
1098                 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1099                 return -EINVAL;
1100         }
1101
1102         if (rate != dclk_rate)
1103                 return -EINVAL;
1104
1105         return dclk_rate;
1106 };
1107
1108 static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
1109                                   unsigned long prate)
1110 {
1111         struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1112         struct lmk04832 *lmk = dclk->lmk;
1113         unsigned int dclk_div;
1114         int ret;
1115
1116         dclk_div = DIV_ROUND_CLOSEST(prate, rate);
1117
1118         if (dclk_div > 0x3ff) {
1119                 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1120                 return -EINVAL;
1121         }
1122
1123         /* Enable Duty Cycle Correction */
1124         if (dclk_div == 1) {
1125                 ret = regmap_update_bits(lmk->regmap,
1126                                          LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1127                                          LMK04832_BIT_DCLKX_Y_DCC,
1128                                          FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1));
1129                 if (ret)
1130                         return ret;
1131         }
1132
1133         /*
1134          * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC
1135          * procedure requires to first program Divide-by-4 and then back to
1136          * Divide-by-2 or Divide-by-3 before doing SYNC.
1137          */
1138         if (dclk_div == 2 || dclk_div == 3) {
1139                 ret = regmap_update_bits(lmk->regmap,
1140                                          LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1141                                          LMK04832_BIT_DCLK_DIV_MSB, 0x00);
1142                 if (ret)
1143                         return ret;
1144
1145                 ret = regmap_write(lmk->regmap,
1146                                    LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04);
1147                 if (ret)
1148                         return ret;
1149         }
1150
1151         ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1152                            FIELD_GET(0x0ff, dclk_div));
1153         if (ret)
1154                 return ret;
1155
1156         ret = regmap_update_bits(lmk->regmap,
1157                                   LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1158                                   LMK04832_BIT_DCLK_DIV_MSB,
1159                                   FIELD_GET(0x300, dclk_div));
1160         if (ret)
1161                 return ret;
1162
1163         ret = lmk04832_sclk_sync_sequence(lmk);
1164         if (ret)
1165                 dev_err(lmk->dev, "SYNC sequence failed\n");
1166
1167         return ret;
1168 };
1169
1170 static const struct clk_ops lmk04832_dclk_ops = {
1171         .is_enabled = lmk04832_dclk_is_enabled,
1172         .prepare = lmk04832_dclk_prepare,
1173         .unprepare = lmk04832_dclk_unprepare,
1174         .recalc_rate = lmk04832_dclk_recalc_rate,
1175         .round_rate = lmk04832_dclk_round_rate,
1176         .set_rate = lmk04832_dclk_set_rate,
1177 };
1178
1179 static int lmk04832_clkout_is_enabled(struct clk_hw *hw)
1180 {
1181         struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1182         struct lmk04832 *lmk = clkout->lmk;
1183         unsigned int clkoutx_y_pd;
1184         unsigned int sclkx_y_pd;
1185         unsigned int tmp;
1186         u32 enabled;
1187         int ret;
1188         u8 fmt;
1189
1190         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1191                           &clkoutx_y_pd);
1192         if (ret)
1193                 return ret;
1194
1195         enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd);
1196
1197         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1198                           &tmp);
1199         if (ret)
1200                 return ret;
1201
1202         if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1203                 ret = regmap_read(lmk->regmap,
1204                                   LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1205                                   &sclkx_y_pd);
1206                 if (ret)
1207                         return ret;
1208
1209                 enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd);
1210         }
1211
1212         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1213                           &tmp);
1214         if (ret)
1215                 return ret;
1216
1217         if (clkout->id % 2)
1218                 fmt = FIELD_GET(0xf0, tmp);
1219         else
1220                 fmt = FIELD_GET(0x0f, tmp);
1221
1222         return enabled && !fmt;
1223 }
1224
1225 static int lmk04832_clkout_prepare(struct clk_hw *hw)
1226 {
1227         struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1228         struct lmk04832 *lmk = clkout->lmk;
1229         unsigned int tmp;
1230         int ret;
1231
1232         if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN)
1233                 dev_err(lmk->dev, "prepared %s but format is powerdown\n",
1234                         clk_hw_get_name(hw));
1235
1236         ret = regmap_update_bits(lmk->regmap,
1237                                  LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1238                                  LMK04832_BIT_CLKOUTX_Y_PD, 0x00);
1239         if (ret)
1240                 return ret;
1241
1242         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1243                           &tmp);
1244         if (ret)
1245                 return ret;
1246
1247         if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1248                 ret = regmap_update_bits(lmk->regmap,
1249                                          LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1250                                          LMK04832_BIT_SCLK_PD, 0x00);
1251                 if (ret)
1252                         return ret;
1253         }
1254
1255         return regmap_update_bits(lmk->regmap,
1256                                   LMK04832_REG_CLKOUT_FMT(clkout->id),
1257                                   LMK04832_BIT_CLKOUT_FMT(clkout->id),
1258                                   clkout->format << 4 * (clkout->id % 2));
1259 }
1260
1261 static void lmk04832_clkout_unprepare(struct clk_hw *hw)
1262 {
1263         struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1264         struct lmk04832 *lmk = clkout->lmk;
1265
1266         regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1267                            LMK04832_BIT_CLKOUT_FMT(clkout->id),
1268                            0x00);
1269 }
1270
1271 static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index)
1272 {
1273         struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1274         struct lmk04832 *lmk = clkout->lmk;
1275
1276         return regmap_update_bits(lmk->regmap,
1277                                   LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1278                                   LMK04832_BIT_CLKOUT_SRC_MUX,
1279                                   FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1280                                              index));
1281 }
1282
1283 static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw)
1284 {
1285         struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1286         struct lmk04832 *lmk = clkout->lmk;
1287         unsigned int tmp;
1288         int ret;
1289
1290         ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1291                           &tmp);
1292         if (ret)
1293                 return ret;
1294
1295         return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp);
1296 }
1297
1298 static const struct clk_ops lmk04832_clkout_ops = {
1299         .is_enabled = lmk04832_clkout_is_enabled,
1300         .prepare = lmk04832_clkout_prepare,
1301         .unprepare = lmk04832_clkout_unprepare,
1302         .set_parent = lmk04832_clkout_set_parent,
1303         .get_parent = lmk04832_clkout_get_parent,
1304 };
1305
1306 static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
1307 {
1308         char name[] = "lmk-clkoutXX";
1309         char dclk_name[] = "lmk-dclkXX_YY";
1310         const char *parent_names[2];
1311         struct clk_init_data init;
1312         int dclk_num = num / 2;
1313         int ret;
1314
1315         if (num % 2 == 0) {
1316                 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
1317                 init.name = dclk_name;
1318                 parent_names[0] = clk_hw_get_name(&lmk->vco);
1319                 init.ops = &lmk04832_dclk_ops;
1320                 init.flags = CLK_SET_RATE_PARENT;
1321                 init.num_parents = 1;
1322
1323                 lmk->dclk[dclk_num].id = num;
1324                 lmk->dclk[dclk_num].lmk = lmk;
1325                 lmk->dclk[dclk_num].hw.init = &init;
1326
1327                 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw);
1328                 if (ret)
1329                         return ret;
1330         } else {
1331                 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num);
1332         }
1333
1334         if (of_property_read_string_index(lmk->dev->of_node,
1335                                           "clock-output-names",
1336                                           num, &init.name)) {
1337                 sprintf(name, "lmk-clkout%02d", num);
1338                 init.name = name;
1339         }
1340
1341         parent_names[0] = dclk_name;
1342         parent_names[1] = clk_hw_get_name(&lmk->sclk);
1343         init.parent_names = parent_names;
1344         init.ops = &lmk04832_clkout_ops;
1345         init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
1346         init.num_parents = ARRAY_SIZE(parent_names);
1347
1348         lmk->clkout[num].id = num;
1349         lmk->clkout[num].lmk = lmk;
1350         lmk->clkout[num].hw.init = &init;
1351         lmk->clk_data->hws[num] = &lmk->clkout[num].hw;
1352
1353         /* Set initial parent */
1354         regmap_update_bits(lmk->regmap,
1355                            LMK04832_REG_CLKOUT_SRC_MUX(num),
1356                            LMK04832_BIT_CLKOUT_SRC_MUX,
1357                            FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1358                                       lmk->clkout[num].sysref));
1359
1360         return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw);
1361 }
1362
1363 static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
1364 {
1365         int reg;
1366         int ret;
1367
1368         dev_info(lmk->dev, "setting up 4-wire mode\n");
1369         ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
1370                            LMK04832_BIT_SPI_3WIRE_DIS);
1371         if (ret)
1372                 return ret;
1373
1374         switch (rdbk_pin) {
1375         case RDBK_CLKIN_SEL0:
1376                 reg = LMK04832_REG_CLKIN_SEL0;
1377                 break;
1378         case RDBK_CLKIN_SEL1:
1379                 reg = LMK04832_REG_CLKIN_SEL1;
1380                 break;
1381         case RDBK_RESET:
1382                 reg = LMK04832_REG_CLKIN_RST;
1383                 break;
1384         default:
1385                 return -EINVAL;
1386         }
1387
1388         return regmap_write(lmk->regmap, reg,
1389                             FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
1390                                        LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
1391                             FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
1392                                        LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
1393 }
1394
1395 static int lmk04832_probe(struct spi_device *spi)
1396 {
1397         const struct lmk04832_device_info *info;
1398         int rdbk_pin = RDBK_CLKIN_SEL1;
1399         struct device_node *child;
1400         struct lmk04832 *lmk;
1401         u8 tmp[3];
1402         int ret;
1403         int i;
1404
1405         info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
1406
1407         lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL);
1408         if (!lmk)
1409                 return -ENOMEM;
1410
1411         lmk->dev = &spi->dev;
1412
1413         lmk->oscin = devm_clk_get(lmk->dev, "oscin");
1414         if (IS_ERR(lmk->oscin)) {
1415                 dev_err(lmk->dev, "failed to get oscin clock\n");
1416                 return PTR_ERR(lmk->oscin);
1417         }
1418
1419         ret = clk_prepare_enable(lmk->oscin);
1420         if (ret)
1421                 return ret;
1422
1423         lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
1424                                                   GPIOD_OUT_LOW);
1425
1426         lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
1427                                  sizeof(struct lmk_dclk), GFP_KERNEL);
1428         if (!lmk->dclk) {
1429                 ret = -ENOMEM;
1430                 goto err_disable_oscin;
1431         }
1432
1433         lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
1434                                    sizeof(*lmk->clkout), GFP_KERNEL);
1435         if (!lmk->clkout) {
1436                 ret = -ENOMEM;
1437                 goto err_disable_oscin;
1438         }
1439
1440         lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
1441                                                            info->num_channels),
1442                                      GFP_KERNEL);
1443         if (!lmk->clk_data) {
1444                 ret = -ENOMEM;
1445                 goto err_disable_oscin;
1446         }
1447
1448         device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
1449
1450         lmk->sysref_ddly = 8;
1451         device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);
1452
1453         lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS;
1454         device_property_read_u32(lmk->dev, "ti,sysref-mux",
1455                                  &lmk->sysref_mux);
1456
1457         lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF;
1458         device_property_read_u32(lmk->dev, "ti,sync-mode",
1459                                  &lmk->sync_mode);
1460
1461         lmk->sysref_pulse_cnt = 4;
1462         device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
1463                                  &lmk->sysref_pulse_cnt);
1464
1465         for_each_child_of_node(lmk->dev->of_node, child) {
1466                 int reg;
1467
1468                 ret = of_property_read_u32(child, "reg", &reg);
1469                 if (ret) {
1470                         dev_err(lmk->dev, "missing reg property in child: %s\n",
1471                                 child->full_name);
1472                         of_node_put(child);
1473                         goto err_disable_oscin;
1474                 }
1475
1476                 of_property_read_u32(child, "ti,clkout-fmt",
1477                                      &lmk->clkout[reg].format);
1478
1479                 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0
1480                     && reg != 8 && reg != 10)
1481                         dev_err(lmk->dev, "invalid format for clkout%02d\n",
1482                                 reg);
1483
1484                 lmk->clkout[reg].sysref =
1485                         of_property_read_bool(child, "ti,clkout-sysref");
1486         }
1487
1488         lmk->regmap = devm_regmap_init_spi(spi, &regmap_config);
1489         if (IS_ERR(lmk->regmap)) {
1490                 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n",
1491
1492                         __func__, PTR_ERR(lmk->regmap));
1493                 ret = PTR_ERR(lmk->regmap);
1494                 goto err_disable_oscin;
1495         }
1496
1497         regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET);
1498
1499         if (!(spi->mode & SPI_3WIRE)) {
1500                 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk",
1501                                          &rdbk_pin);
1502                 ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin);
1503                 if (ret)
1504                         goto err_disable_oscin;
1505         }
1506
1507         regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3);
1508         if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) {
1509                 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n",
1510                         tmp[0] << 8 | tmp[1], tmp[2]);
1511                 ret = -EINVAL;
1512                 goto err_disable_oscin;
1513         }
1514
1515         ret = lmk04832_register_vco(lmk);
1516         if (ret) {
1517                 dev_err(lmk->dev, "failed to init device clock path\n");
1518                 goto err_disable_oscin;
1519         }
1520
1521         if (lmk->vco_rate) {
1522                 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate);
1523                 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
1524                 if (ret) {
1525                         dev_err(lmk->dev, "failed to set VCO rate\n");
1526                         goto err_disable_vco;
1527                 }
1528         }
1529
1530         ret = lmk04832_register_sclk(lmk);
1531         if (ret) {
1532                 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
1533                 goto err_disable_vco;
1534         }
1535
1536         for (i = 0; i < info->num_channels; i++) {
1537                 ret = lmk04832_register_clkout(lmk, i);
1538                 if (ret) {
1539                         dev_err(lmk->dev, "failed to register clk %d\n", i);
1540                         goto err_disable_vco;
1541                 }
1542         }
1543
1544         lmk->clk_data->num = info->num_channels;
1545         ret = of_clk_add_hw_provider(lmk->dev->of_node, of_clk_hw_onecell_get,
1546                                      lmk->clk_data);
1547         if (ret) {
1548                 dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
1549                 goto err_disable_vco;
1550         }
1551
1552         spi_set_drvdata(spi, lmk);
1553
1554         return 0;
1555
1556 err_disable_vco:
1557         clk_disable_unprepare(lmk->vco.clk);
1558
1559 err_disable_oscin:
1560         clk_disable_unprepare(lmk->oscin);
1561
1562         return ret;
1563 }
1564
1565 static int lmk04832_remove(struct spi_device *spi)
1566 {
1567         struct lmk04832 *lmk = spi_get_drvdata(spi);
1568
1569         clk_disable_unprepare(lmk->oscin);
1570         of_clk_del_provider(spi->dev.of_node);
1571
1572         return 0;
1573 }
1574 static const struct spi_device_id lmk04832_id[] = {
1575         { "lmk04832", LMK04832 },
1576         {}
1577 };
1578 MODULE_DEVICE_TABLE(spi, lmk04832_id);
1579
1580 static const struct of_device_id lmk04832_of_id[] = {
1581         { .compatible = "ti,lmk04832" },
1582         {}
1583 };
1584 MODULE_DEVICE_TABLE(of, lmk04832_of_id);
1585
1586 static struct spi_driver lmk04832_driver = {
1587         .driver = {
1588                 .name   = "lmk04832",
1589                 .of_match_table = lmk04832_of_id,
1590         },
1591         .probe          = lmk04832_probe,
1592         .remove         = lmk04832_remove,
1593         .id_table       = lmk04832_id,
1594 };
1595 module_spi_driver(lmk04832_driver);
1596
1597 MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>");
1598 MODULE_DESCRIPTION("Texas Instruments LMK04832");
1599 MODULE_LICENSE("GPL v2");