drivers/clk/clk-ast2600.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 // Copyright IBM Corp
   3 // Copyright ASPEED Technology
   4
   5 #define pr_fmt(fmt) "clk-ast2600: " fmt
   6
   7 #include <linux/mfd/syscon.h>
   8 #include <linux/of_address.h>
   9 #include <linux/of_device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/regmap.h>
  12 #include <linux/slab.h>
  13
  14 #include <dt-bindings/clock/ast2600-clock.h>
  15
  16 #include "clk-aspeed.h"
  17
  18 #define ASPEED_G6_NUM_CLKS              71
  19
  20 #define ASPEED_G6_SILICON_REV           0x014
  21 #define CHIP_REVISION_ID                        GENMASK(23, 16)
  22
  23 #define ASPEED_G6_RESET_CTRL            0x040
  24 #define ASPEED_G6_RESET_CTRL2           0x050
  25
  26 #define ASPEED_G6_CLK_STOP_CTRL         0x080
  27 #define ASPEED_G6_CLK_STOP_CTRL2        0x090
  28
  29 #define ASPEED_G6_MISC_CTRL             0x0C0
  30 #define  UART_DIV13_EN                  BIT(12)
  31
  32 #define ASPEED_G6_CLK_SELECTION1        0x300
  33 #define ASPEED_G6_CLK_SELECTION2        0x304
  34 #define ASPEED_G6_CLK_SELECTION4        0x310
  35
  36 #define ASPEED_HPLL_PARAM               0x200
  37 #define ASPEED_APLL_PARAM               0x210
  38 #define ASPEED_MPLL_PARAM               0x220
  39 #define ASPEED_EPLL_PARAM               0x240
  40 #define ASPEED_DPLL_PARAM               0x260
  41
  42 #define ASPEED_G6_STRAP1                0x500
  43
  44 #define ASPEED_MAC12_CLK_DLY            0x340
  45 #define ASPEED_MAC34_CLK_DLY            0x350
  46
  47 /* Globally visible clocks */
  48 static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
  49
  50 /* Keeps track of all clocks */
  51 static struct clk_hw_onecell_data *aspeed_g6_clk_data;
  52
  53 static void __iomem *scu_g6_base;
  54
  55 /*
  56  * Clocks marked with CLK_IS_CRITICAL:
  57  *
  58  *  ref0 and ref1 are essential for the SoC to operate
  59  *  mpll is required if SDRAM is used
  60  */
  61 static const struct aspeed_gate_data aspeed_g6_gates[] = {
  62         /*                                  clk rst  name               parent   flags */
  63         [ASPEED_CLK_GATE_MCLK]          = {  0, -1, "mclk-gate",        "mpll",  CLK_IS_CRITICAL }, /* SDRAM */
  64         [ASPEED_CLK_GATE_ECLK]          = {  1,  6, "eclk-gate",        "eclk",  0 },   /* Video Engine */
  65         [ASPEED_CLK_GATE_GCLK]          = {  2,  7, "gclk-gate",        NULL,    0 },   /* 2D engine */
  66         /* vclk parent - dclk/d1clk/hclk/mclk */
  67         [ASPEED_CLK_GATE_VCLK]          = {  3, -1, "vclk-gate",        NULL,    0 },   /* Video Capture */
  68         [ASPEED_CLK_GATE_BCLK]          = {  4,  8, "bclk-gate",        "bclk",  0 }, /* PCIe/PCI */
  69         /* From dpll */
  70         [ASPEED_CLK_GATE_DCLK]          = {  5, -1, "dclk-gate",        NULL,    CLK_IS_CRITICAL }, /* DAC */
  71         [ASPEED_CLK_GATE_REF0CLK]       = {  6, -1, "ref0clk-gate",     "clkin", CLK_IS_CRITICAL },
  72         [ASPEED_CLK_GATE_USBPORT2CLK]   = {  7,  3, "usb-port2-gate",   NULL,    0 },   /* USB2.0 Host port 2 */
  73         /* Reserved 8 */
  74         [ASPEED_CLK_GATE_USBUHCICLK]    = {  9, 15, "usb-uhci-gate",    NULL,    0 },   /* USB1.1 (requires port 2 enabled) */
  75         /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
  76         [ASPEED_CLK_GATE_D1CLK]         = { 10, 13, "d1clk-gate",       "d1clk", 0 },   /* GFX CRT */
  77         /* Reserved 11/12 */
  78         [ASPEED_CLK_GATE_YCLK]          = { 13,  4, "yclk-gate",        NULL,    0 },   /* HAC */
  79         [ASPEED_CLK_GATE_USBPORT1CLK]   = { 14, 14, "usb-port1-gate",   NULL,    0 },   /* USB2 hub/USB2 host port 1/USB1.1 dev */
  80         [ASPEED_CLK_GATE_UART5CLK]      = { 15, -1, "uart5clk-gate",    "uart",  0 },   /* UART5 */
  81         /* Reserved 16/19 */
  82         [ASPEED_CLK_GATE_MAC1CLK]       = { 20, 11, "mac1clk-gate",     "mac12", 0 },   /* MAC1 */
  83         [ASPEED_CLK_GATE_MAC2CLK]       = { 21, 12, "mac2clk-gate",     "mac12", 0 },   /* MAC2 */
  84         /* Reserved 22/23 */
  85         [ASPEED_CLK_GATE_RSACLK]        = { 24,  4, "rsaclk-gate",      NULL,    0 },   /* HAC */
  86         [ASPEED_CLK_GATE_RVASCLK]       = { 25,  9, "rvasclk-gate",     NULL,    0 },   /* RVAS */
  87         /* Reserved 26 */
  88         [ASPEED_CLK_GATE_EMMCCLK]       = { 27, 16, "emmcclk-gate",     NULL,    0 },   /* For card clk */
  89         /* Reserved 28/29/30 */
  90         [ASPEED_CLK_GATE_LCLK]          = { 32, 32, "lclk-gate",        NULL,    0 }, /* LPC */
  91         [ASPEED_CLK_GATE_ESPICLK]       = { 33, -1, "espiclk-gate",     NULL,    0 }, /* eSPI */
  92         [ASPEED_CLK_GATE_REF1CLK]       = { 34, -1, "ref1clk-gate",     "clkin", CLK_IS_CRITICAL },
  93         /* Reserved 35 */
  94         [ASPEED_CLK_GATE_SDCLK]         = { 36, 56, "sdclk-gate",       NULL,    0 },   /* SDIO/SD */
  95         [ASPEED_CLK_GATE_LHCCLK]        = { 37, -1, "lhclk-gate",       "lhclk", 0 },   /* LPC master/LPC+ */
  96         /* Reserved 38 RSA: no longer used */
  97         /* Reserved 39 */
  98         [ASPEED_CLK_GATE_I3C0CLK]       = { 40,  40, "i3c0clk-gate",    NULL,    0 },   /* I3C0 */
  99         [ASPEED_CLK_GATE_I3C1CLK]       = { 41,  41, "i3c1clk-gate",    NULL,    0 },   /* I3C1 */
 100         [ASPEED_CLK_GATE_I3C2CLK]       = { 42,  42, "i3c2clk-gate",    NULL,    0 },   /* I3C2 */
 101         [ASPEED_CLK_GATE_I3C3CLK]       = { 43,  43, "i3c3clk-gate",    NULL,    0 },   /* I3C3 */
 102         [ASPEED_CLK_GATE_I3C4CLK]       = { 44,  44, "i3c4clk-gate",    NULL,    0 },   /* I3C4 */
 103         [ASPEED_CLK_GATE_I3C5CLK]       = { 45,  45, "i3c5clk-gate",    NULL,    0 },   /* I3C5 */
 104         [ASPEED_CLK_GATE_I3C6CLK]       = { 46,  46, "i3c6clk-gate",    NULL,    0 },   /* I3C6 */
 105         [ASPEED_CLK_GATE_I3C7CLK]       = { 47,  47, "i3c7clk-gate",    NULL,    0 },   /* I3C7 */
 106         [ASPEED_CLK_GATE_UART1CLK]      = { 48,  -1, "uart1clk-gate",   "uart",  0 },   /* UART1 */
 107         [ASPEED_CLK_GATE_UART2CLK]      = { 49,  -1, "uart2clk-gate",   "uart",  0 },   /* UART2 */
 108         [ASPEED_CLK_GATE_UART3CLK]      = { 50,  -1, "uart3clk-gate",   "uart",  0 },   /* UART3 */
 109         [ASPEED_CLK_GATE_UART4CLK]      = { 51,  -1, "uart4clk-gate",   "uart",  0 },   /* UART4 */
 110         [ASPEED_CLK_GATE_MAC3CLK]       = { 52,  52, "mac3clk-gate",    "mac34", 0 },   /* MAC3 */
 111         [ASPEED_CLK_GATE_MAC4CLK]       = { 53,  53, "mac4clk-gate",    "mac34", 0 },   /* MAC4 */
 112         [ASPEED_CLK_GATE_UART6CLK]      = { 54,  -1, "uart6clk-gate",   "uartx", 0 },   /* UART6 */
 113         [ASPEED_CLK_GATE_UART7CLK]      = { 55,  -1, "uart7clk-gate",   "uartx", 0 },   /* UART7 */
 114         [ASPEED_CLK_GATE_UART8CLK]      = { 56,  -1, "uart8clk-gate",   "uartx", 0 },   /* UART8 */
 115         [ASPEED_CLK_GATE_UART9CLK]      = { 57,  -1, "uart9clk-gate",   "uartx", 0 },   /* UART9 */
 116         [ASPEED_CLK_GATE_UART10CLK]     = { 58,  -1, "uart10clk-gate",  "uartx", 0 },   /* UART10 */
 117         [ASPEED_CLK_GATE_UART11CLK]     = { 59,  -1, "uart11clk-gate",  "uartx", 0 },   /* UART11 */
 118         [ASPEED_CLK_GATE_UART12CLK]     = { 60,  -1, "uart12clk-gate",  "uartx", 0 },   /* UART12 */
 119         [ASPEED_CLK_GATE_UART13CLK]     = { 61,  -1, "uart13clk-gate",  "uartx", 0 },   /* UART13 */
 120         [ASPEED_CLK_GATE_FSICLK]        = { 62,  59, "fsiclk-gate",     NULL,    0 },   /* FSI */
 121 };
 122
 123 static const struct clk_div_table ast2600_eclk_div_table[] = {
 124         { 0x0, 2 },
 125         { 0x1, 2 },
 126         { 0x2, 3 },
 127         { 0x3, 4 },
 128         { 0x4, 5 },
 129         { 0x5, 6 },
 130         { 0x6, 7 },
 131         { 0x7, 8 },
 132         { 0 }
 133 };
 134
 135 static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
 136         { 0x0, 2 },
 137         { 0x1, 4 },
 138         { 0x2, 6 },
 139         { 0x3, 8 },
 140         { 0x4, 10 },
 141         { 0x5, 12 },
 142         { 0x6, 14 },
 143         { 0x7, 16 },
 144         { 0 }
 145 };
 146
 147 static const struct clk_div_table ast2600_mac_div_table[] = {
 148         { 0x0, 4 },
 149         { 0x1, 4 },
 150         { 0x2, 6 },
 151         { 0x3, 8 },
 152         { 0x4, 10 },
 153         { 0x5, 12 },
 154         { 0x6, 14 },
 155         { 0x7, 16 },
 156         { 0 }
 157 };
 158
 159 static const struct clk_div_table ast2600_div_table[] = {
 160         { 0x0, 4 },
 161         { 0x1, 8 },
 162         { 0x2, 12 },
 163         { 0x3, 16 },
 164         { 0x4, 20 },
 165         { 0x5, 24 },
 166         { 0x6, 28 },
 167         { 0x7, 32 },
 168         { 0 }
 169 };
 170
 171 /* For hpll/dpll/epll/mpll */
 172 static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
 173 {
 174         unsigned int mult, div;
 175
 176         if (val & BIT(24)) {
 177                 /* Pass through mode */
 178                 mult = div = 1;
 179         } else {
 180                 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
 181                 u32 m = val  & 0x1fff;
 182                 u32 n = (val >> 13) & 0x3f;
 183                 u32 p = (val >> 19) & 0xf;
 184                 mult = (m + 1) / (n + 1);
 185                 div = (p + 1);
 186         }
 187         return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
 188                         mult, div);
 189 };
 190
 191 static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
 192 {
 193         unsigned int mult, div;
 194         u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);
 195
 196         if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {
 197                 if (val & BIT(24)) {
 198                         /* Pass through mode */
 199                         mult = div = 1;
 200                 } else {
 201                         /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */
 202                         u32 m = val & 0x1fff;
 203                         u32 n = (val >> 13) & 0x3f;
 204                         u32 p = (val >> 19) & 0xf;
 205
 206                         mult = (m + 1);
 207                         div = (n + 1) * (p + 1);
 208                 }
 209         } else {
 210                 if (val & BIT(20)) {
 211                         /* Pass through mode */
 212                         mult = div = 1;
 213                 } else {
 214                         /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
 215                         u32 m = (val >> 5) & 0x3f;
 216                         u32 od = (val >> 4) & 0x1;
 217                         u32 n = val & 0xf;
 218
 219                         mult = (2 - od) * (m + 2);
 220                         div = n + 1;
 221                 }
 222         }
 223         return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
 224                         mult, div);
 225 };
 226
 227 static u32 get_bit(u8 idx)
 228 {
 229         return BIT(idx % 32);
 230 }
 231
 232 static u32 get_reset_reg(struct aspeed_clk_gate *gate)
 233 {
 234         if (gate->reset_idx < 32)
 235                 return ASPEED_G6_RESET_CTRL;
 236
 237         return ASPEED_G6_RESET_CTRL2;
 238 }
 239
 240 static u32 get_clock_reg(struct aspeed_clk_gate *gate)
 241 {
 242         if (gate->clock_idx < 32)
 243                 return ASPEED_G6_CLK_STOP_CTRL;
 244
 245         return ASPEED_G6_CLK_STOP_CTRL2;
 246 }
 247
 248 static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
 249 {
 250         struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
 251         u32 clk = get_bit(gate->clock_idx);
 252         u32 rst = get_bit(gate->reset_idx);
 253         u32 reg;
 254         u32 enval;
 255
 256         /*
 257          * If the IP is in reset, treat the clock as not enabled,
 258          * this happens with some clocks such as the USB one when
 259          * coming from cold reset. Without this, aspeed_clk_enable()
 260          * will fail to lift the reset.
 261          */
 262         if (gate->reset_idx >= 0) {
 263                 regmap_read(gate->map, get_reset_reg(gate), &reg);
 264
 265                 if (reg & rst)
 266                         return 0;
 267         }
 268
 269         regmap_read(gate->map, get_clock_reg(gate), &reg);
 270
 271         enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
 272
 273         return ((reg & clk) == enval) ? 1 : 0;
 274 }
 275
 276 static int aspeed_g6_clk_enable(struct clk_hw *hw)
 277 {
 278         struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
 279         unsigned long flags;
 280         u32 clk = get_bit(gate->clock_idx);
 281         u32 rst = get_bit(gate->reset_idx);
 282
 283         spin_lock_irqsave(gate->lock, flags);
 284
 285         if (aspeed_g6_clk_is_enabled(hw)) {
 286                 spin_unlock_irqrestore(gate->lock, flags);
 287                 return 0;
 288         }
 289
 290         if (gate->reset_idx >= 0) {
 291                 /* Put IP in reset */
 292                 regmap_write(gate->map, get_reset_reg(gate), rst);
 293                 /* Delay 100us */
 294                 udelay(100);
 295         }
 296
 297         /* Enable clock */
 298         if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
 299                 /* Clock is clear to enable, so use set to clear register */
 300                 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
 301         } else {
 302                 /* Clock is set to enable, so use write to set register */
 303                 regmap_write(gate->map, get_clock_reg(gate), clk);
 304         }
 305
 306         if (gate->reset_idx >= 0) {
 307                 /* A delay of 10ms is specified by the ASPEED docs */
 308                 mdelay(10);
 309                 /* Take IP out of reset */
 310                 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
 311         }
 312
 313         spin_unlock_irqrestore(gate->lock, flags);
 314
 315         return 0;
 316 }
 317
 318 static void aspeed_g6_clk_disable(struct clk_hw *hw)
 319 {
 320         struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
 321         unsigned long flags;
 322         u32 clk = get_bit(gate->clock_idx);
 323
 324         spin_lock_irqsave(gate->lock, flags);
 325
 326         if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
 327                 regmap_write(gate->map, get_clock_reg(gate), clk);
 328         } else {
 329                 /* Use set to clear register */
 330                 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
 331         }
 332
 333         spin_unlock_irqrestore(gate->lock, flags);
 334 }
 335
 336 static const struct clk_ops aspeed_g6_clk_gate_ops = {
 337         .enable = aspeed_g6_clk_enable,
 338         .disable = aspeed_g6_clk_disable,
 339         .is_enabled = aspeed_g6_clk_is_enabled,
 340 };
 341
 342 static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
 343                                     unsigned long id)
 344 {
 345         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
 346         u32 rst = get_bit(id);
 347         u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
 348
 349         /* Use set to clear register */
 350         return regmap_write(ar->map, reg + 0x04, rst);
 351 }
 352
 353 static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
 354                                   unsigned long id)
 355 {
 356         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
 357         u32 rst = get_bit(id);
 358         u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
 359
 360         return regmap_write(ar->map, reg, rst);
 361 }
 362
 363 static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
 364                                   unsigned long id)
 365 {
 366         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
 367         int ret;
 368         u32 val;
 369         u32 rst = get_bit(id);
 370         u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
 371
 372         ret = regmap_read(ar->map, reg, &val);
 373         if (ret)
 374                 return ret;
 375
 376         return !!(val & rst);
 377 }
 378
 379 static const struct reset_control_ops aspeed_g6_reset_ops = {
 380         .assert = aspeed_g6_reset_assert,
 381         .deassert = aspeed_g6_reset_deassert,
 382         .status = aspeed_g6_reset_status,
 383 };
 384
 385 static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
 386                 const char *name, const char *parent_name, unsigned long flags,
 387                 struct regmap *map, u8 clock_idx, u8 reset_idx,
 388                 u8 clk_gate_flags, spinlock_t *lock)
 389 {
 390         struct aspeed_clk_gate *gate;
 391         struct clk_init_data init;
 392         struct clk_hw *hw;
 393         int ret;
 394
 395         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 396         if (!gate)
 397                 return ERR_PTR(-ENOMEM);
 398
 399         init.name = name;
 400         init.ops = &aspeed_g6_clk_gate_ops;
 401         init.flags = flags;
 402         init.parent_names = parent_name ? &parent_name : NULL;
 403         init.num_parents = parent_name ? 1 : 0;
 404
 405         gate->map = map;
 406         gate->clock_idx = clock_idx;
 407         gate->reset_idx = reset_idx;
 408         gate->flags = clk_gate_flags;
 409         gate->lock = lock;
 410         gate->hw.init = &init;
 411
 412         hw = &gate->hw;
 413         ret = clk_hw_register(dev, hw);
 414         if (ret) {
 415                 kfree(gate);
 416                 hw = ERR_PTR(ret);
 417         }
 418
 419         return hw;
 420 }
 421
 422 static const char *const emmc_extclk_parent_names[] = {
 423         "emmc_extclk_hpll_in",
 424         "mpll",
 425 };
 426
 427 static const char * const vclk_parent_names[] = {
 428         "dpll",
 429         "d1pll",
 430         "hclk",
 431         "mclk",
 432 };
 433
 434 static const char * const d1clk_parent_names[] = {
 435         "dpll",
 436         "epll",
 437         "usb-phy-40m",
 438         "gpioc6_clkin",
 439         "dp_phy_pll",
 440 };
 441
 442 static int aspeed_g6_clk_probe(struct platform_device *pdev)
 443 {
 444         struct device *dev = &pdev->dev;
 445         struct aspeed_reset *ar;
 446         struct regmap *map;
 447         struct clk_hw *hw;
 448         u32 val, rate;
 449         int i, ret;
 450
 451         map = syscon_node_to_regmap(dev->of_node);
 452         if (IS_ERR(map)) {
 453                 dev_err(dev, "no syscon regmap\n");
 454                 return PTR_ERR(map);
 455         }
 456
 457         ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
 458         if (!ar)
 459                 return -ENOMEM;
 460
 461         ar->map = map;
 462
 463         ar->rcdev.owner = THIS_MODULE;
 464         ar->rcdev.nr_resets = 64;
 465         ar->rcdev.ops = &aspeed_g6_reset_ops;
 466         ar->rcdev.of_node = dev->of_node;
 467
 468         ret = devm_reset_controller_register(dev, &ar->rcdev);
 469         if (ret) {
 470                 dev_err(dev, "could not register reset controller\n");
 471                 return ret;
 472         }
 473
 474         /* UART clock div13 setting */
 475         regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
 476         if (val & UART_DIV13_EN)
 477                 rate = 24000000 / 13;
 478         else
 479                 rate = 24000000;
 480         hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
 481         if (IS_ERR(hw))
 482                 return PTR_ERR(hw);
 483         aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
 484
 485         /* UART6~13 clock div13 setting */
 486         regmap_read(map, 0x80, &val);
 487         if (val & BIT(31))
 488                 rate = 24000000 / 13;
 489         else
 490                 rate = 24000000;
 491         hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
 492         if (IS_ERR(hw))
 493                 return PTR_ERR(hw);
 494         aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
 495
 496         /* EMMC ext clock */
 497         hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
 498                                           0, 1, 2);
 499         if (IS_ERR(hw))
 500                 return PTR_ERR(hw);
 501
 502         hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
 503                                  emmc_extclk_parent_names,
 504                                  ARRAY_SIZE(emmc_extclk_parent_names), 0,
 505                                  scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
 506                                  0, &aspeed_g6_clk_lock);
 507         if (IS_ERR(hw))
 508                 return PTR_ERR(hw);
 509
 510         hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
 511                                   0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
 512                                   15, 0, &aspeed_g6_clk_lock);
 513         if (IS_ERR(hw))
 514                 return PTR_ERR(hw);
 515
 516         hw = clk_hw_register_divider_table(dev, "emmc_extclk",
 517                                            "emmc_extclk_gate", 0,
 518                                            scu_g6_base +
 519                                                 ASPEED_G6_CLK_SELECTION1, 12,
 520                                            3, 0, ast2600_emmc_extclk_div_table,
 521                                            &aspeed_g6_clk_lock);
 522         if (IS_ERR(hw))
 523                 return PTR_ERR(hw);
 524         aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
 525
 526         /* SD/SDIO clock divider and gate */
 527         hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
 528                         scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
 529                         &aspeed_g6_clk_lock);
 530         if (IS_ERR(hw))
 531                 return PTR_ERR(hw);
 532         hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
 533                         0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
 534                         ast2600_div_table,
 535                         &aspeed_g6_clk_lock);
 536         if (IS_ERR(hw))
 537                 return PTR_ERR(hw);
 538         aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
 539
 540         /* MAC1/2 RMII 50MHz RCLK */
 541         hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
 542         if (IS_ERR(hw))
 543                 return PTR_ERR(hw);
 544
 545         /* MAC1/2 AHB bus clock divider */
 546         hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
 547                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
 548                         ast2600_mac_div_table,
 549                         &aspeed_g6_clk_lock);
 550         if (IS_ERR(hw))
 551                 return PTR_ERR(hw);
 552         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
 553
 554         /* RMII1 50MHz (RCLK) output enable */
 555         hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
 556                         scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
 557                         &aspeed_g6_clk_lock);
 558         if (IS_ERR(hw))
 559                 return PTR_ERR(hw);
 560         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
 561
 562         /* RMII2 50MHz (RCLK) output enable */
 563         hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
 564                         scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
 565                         &aspeed_g6_clk_lock);
 566         if (IS_ERR(hw))
 567                 return PTR_ERR(hw);
 568         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
 569
 570         /* MAC1/2 RMII 50MHz RCLK */
 571         hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
 572         if (IS_ERR(hw))
 573                 return PTR_ERR(hw);
 574
 575         /* MAC3/4 AHB bus clock divider */
 576         hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
 577                         scu_g6_base + 0x310, 24, 3, 0,
 578                         ast2600_mac_div_table,
 579                         &aspeed_g6_clk_lock);
 580         if (IS_ERR(hw))
 581                 return PTR_ERR(hw);
 582         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
 583
 584         /* RMII3 50MHz (RCLK) output enable */
 585         hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
 586                         scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
 587                         &aspeed_g6_clk_lock);
 588         if (IS_ERR(hw))
 589                 return PTR_ERR(hw);
 590         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
 591
 592         /* RMII4 50MHz (RCLK) output enable */
 593         hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
 594                         scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
 595                         &aspeed_g6_clk_lock);
 596         if (IS_ERR(hw))
 597                 return PTR_ERR(hw);
 598         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;
 599
 600         /* LPC Host (LHCLK) clock divider */
 601         hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
 602                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
 603                         ast2600_div_table,
 604                         &aspeed_g6_clk_lock);
 605         if (IS_ERR(hw))
 606                 return PTR_ERR(hw);
 607         aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
 608
 609         /* gfx d1clk : use dp clk */
 610         regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
 611         /* SoC Display clock selection */
 612         hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
 613                         ARRAY_SIZE(d1clk_parent_names), 0,
 614                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
 615                         &aspeed_g6_clk_lock);
 616         if (IS_ERR(hw))
 617                 return PTR_ERR(hw);
 618         aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
 619
 620         /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
 621         regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
 622
 623         /* P-Bus (BCLK) clock divider */
 624         hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
 625                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
 626                         ast2600_div_table,
 627                         &aspeed_g6_clk_lock);
 628         if (IS_ERR(hw))
 629                 return PTR_ERR(hw);
 630         aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
 631
 632         /* Video Capture clock selection */
 633         hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
 634                         ARRAY_SIZE(vclk_parent_names), 0,
 635                         scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
 636                         &aspeed_g6_clk_lock);
 637         if (IS_ERR(hw))
 638                 return PTR_ERR(hw);
 639         aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
 640
 641         /* Video Engine clock divider */
 642         hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
 643                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
 644                         ast2600_eclk_div_table,
 645                         &aspeed_g6_clk_lock);
 646         if (IS_ERR(hw))
 647                 return PTR_ERR(hw);
 648         aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
 649
 650         for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
 651                 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
 652                 u32 gate_flags;
 653
 654                 /*
 655                  * Special case: the USB port 1 clock (bit 14) is always
 656                  * working the opposite way from the other ones.
 657                  */
 658                 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
 659                 hw = aspeed_g6_clk_hw_register_gate(dev,
 660                                 gd->name,
 661                                 gd->parent_name,
 662                                 gd->flags,
 663                                 map,
 664                                 gd->clock_idx,
 665                                 gd->reset_idx,
 666                                 gate_flags,
 667                                 &aspeed_g6_clk_lock);
 668                 if (IS_ERR(hw))
 669                         return PTR_ERR(hw);
 670                 aspeed_g6_clk_data->hws[i] = hw;
 671         }
 672
 673         return 0;
 674 };
 675
 676 static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
 677         { .compatible = "aspeed,ast2600-scu" },
 678         { }
 679 };
 680
 681 static struct platform_driver aspeed_g6_clk_driver = {
 682         .probe  = aspeed_g6_clk_probe,
 683         .driver = {
 684                 .name = "ast2600-clk",
 685                 .of_match_table = aspeed_g6_clk_dt_ids,
 686                 .suppress_bind_attrs = true,
 687         },
 688 };
 689 builtin_platform_driver(aspeed_g6_clk_driver);
 690
 691 static const u32 ast2600_a0_axi_ahb_div_table[] = {
 692         2, 2, 3, 5,
 693 };
 694
 695 static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {
 696         3, 2, 3, 4,
 697 };
 698
 699 static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {
 700         3, 4, 6, 8,
 701 };
 702
 703 static const u32 ast2600_a1_axi_ahb200_tbl[] = {
 704         3, 4, 3, 4, 2, 2, 2, 2,
 705 };
 706
 707 static void __init aspeed_g6_cc(struct regmap *map)
 708 {
 709         struct clk_hw *hw;
 710         u32 val, div, divbits, chip_id, axi_div, ahb_div;
 711
 712         clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
 713
 714         /*
 715          * High-speed PLL clock derived from the crystal. This the CPU clock,
 716          * and we assume that it is enabled
 717          */
 718         regmap_read(map, ASPEED_HPLL_PARAM, &val);
 719         aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
 720
 721         regmap_read(map, ASPEED_MPLL_PARAM, &val);
 722         aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
 723
 724         regmap_read(map, ASPEED_DPLL_PARAM, &val);
 725         aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
 726
 727         regmap_read(map, ASPEED_EPLL_PARAM, &val);
 728         aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
 729
 730         regmap_read(map, ASPEED_APLL_PARAM, &val);
 731         aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
 732
 733         /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
 734         regmap_read(map, ASPEED_G6_STRAP1, &val);
 735         if (val & BIT(16))
 736                 axi_div = 1;
 737         else
 738                 axi_div = 2;
 739
 740         divbits = (val >> 11) & 0x3;
 741         regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
 742         if (chip_id & BIT(16)) {
 743                 if (!divbits) {
 744                         ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
 745                         if (val & BIT(16))
 746                                 ahb_div *= 2;
 747                 } else {
 748                         if (val & BIT(16))
 749                                 ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
 750                         else
 751                                 ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
 752                 }
 753         } else {
 754                 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
 755         }
 756
 757         hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
 758         aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
 759
 760         regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
 761         val = (val >> 23) & 0x7;
 762         div = 4 * (val + 1);
 763         hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
 764         aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
 765
 766         regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
 767         val = (val >> 9) & 0x7;
 768         div = 2 * (val + 1);
 769         hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
 770         aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
 771
 772         /* USB 2.0 port1 phy 40MHz clock */
 773         hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
 774         aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
 775 };
 776
 777 static void __init aspeed_g6_cc_init(struct device_node *np)
 778 {
 779         struct regmap *map;
 780         int ret;
 781         int i;
 782
 783         scu_g6_base = of_iomap(np, 0);
 784         if (!scu_g6_base)
 785                 return;
 786
 787         aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
 788                                       ASPEED_G6_NUM_CLKS), GFP_KERNEL);
 789         if (!aspeed_g6_clk_data)
 790                 return;
 791
 792         /*
 793          * This way all clocks fetched before the platform device probes,
 794          * except those we assign here for early use, will be deferred.
 795          */
 796         for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
 797                 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
 798
 799         /*
 800          * We check that the regmap works on this very first access,
 801          * but as this is an MMIO-backed regmap, subsequent regmap
 802          * access is not going to fail and we skip error checks from
 803          * this point.
 804          */
 805         map = syscon_node_to_regmap(np);
 806         if (IS_ERR(map)) {
 807                 pr_err("no syscon regmap\n");
 808                 return;
 809         }
 810
 811         aspeed_g6_cc(map);
 812         aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
 813         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
 814         if (ret)
 815                 pr_err("failed to add DT provider: %d\n", ret);
 816 };
 817 CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);