drivers/clk/clk-ast2600.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 // Copyright IBM Corp
   3 // Copyright ASPEED Technology
   4
   5 #define pr_fmt(fmt) "clk-ast2600: " fmt
   6
   7 #include <linux/mfd/syscon.h>
   8 #include <linux/of_address.h>
   9 #include <linux/of_device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/regmap.h>
  12 #include <linux/slab.h>
  13
  14 #include <dt-bindings/clock/ast2600-clock.h>
  15
  16 #include "clk-aspeed.h"
  17
  18 #define ASPEED_G6_NUM_CLKS              71
  19
  20 #define ASPEED_G6_SILICON_REV           0x004
  21
  22 #define ASPEED_G6_RESET_CTRL            0x040
  23 #define ASPEED_G6_RESET_CTRL2           0x050
  24
  25 #define ASPEED_G6_CLK_STOP_CTRL         0x080
  26 #define ASPEED_G6_CLK_STOP_CTRL2        0x090
  27
  28 #define ASPEED_G6_MISC_CTRL             0x0C0
  29 #define  UART_DIV13_EN                  BIT(12)
  30
  31 #define ASPEED_G6_CLK_SELECTION1        0x300
  32 #define ASPEED_G6_CLK_SELECTION2        0x304
  33 #define ASPEED_G6_CLK_SELECTION4        0x310
  34
  35 #define ASPEED_HPLL_PARAM               0x200
  36 #define ASPEED_APLL_PARAM               0x210
  37 #define ASPEED_MPLL_PARAM               0x220
  38 #define ASPEED_EPLL_PARAM               0x240
  39 #define ASPEED_DPLL_PARAM               0x260
  40
  41 #define ASPEED_G6_STRAP1                0x500
  42
  43 #define ASPEED_MAC12_CLK_DLY            0x340
  44 #define ASPEED_MAC34_CLK_DLY            0x350
  45
  46 /* Globally visible clocks */
  47 static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
  48
  49 /* Keeps track of all clocks */
  50 static struct clk_hw_onecell_data *aspeed_g6_clk_data;
  51
  52 static void __iomem *scu_g6_base;
  53
  54 /*
  55  * Clocks marked with CLK_IS_CRITICAL:
  56  *
  57  *  ref0 and ref1 are essential for the SoC to operate
  58  *  mpll is required if SDRAM is used
  59  */
  60 static const struct aspeed_gate_data aspeed_g6_gates[] = {
  61         /*                                  clk rst  name               parent   flags */
  62         [ASPEED_CLK_GATE_MCLK]          = {  0, -1, "mclk-gate",        "mpll",  CLK_IS_CRITICAL }, /* SDRAM */
  63         [ASPEED_CLK_GATE_ECLK]          = {  1, -1, "eclk-gate",        "eclk",  0 },   /* Video Engine */
  64         [ASPEED_CLK_GATE_GCLK]          = {  2,  7, "gclk-gate",        NULL,    0 },   /* 2D engine */
  65         /* vclk parent - dclk/d1clk/hclk/mclk */
  66         [ASPEED_CLK_GATE_VCLK]          = {  3,  6, "vclk-gate",        NULL,    0 },   /* Video Capture */
  67         [ASPEED_CLK_GATE_BCLK]          = {  4,  8, "bclk-gate",        "bclk",  0 }, /* PCIe/PCI */
  68         /* From dpll */
  69         [ASPEED_CLK_GATE_DCLK]          = {  5, -1, "dclk-gate",        NULL,    CLK_IS_CRITICAL }, /* DAC */
  70         [ASPEED_CLK_GATE_REF0CLK]       = {  6, -1, "ref0clk-gate",     "clkin", CLK_IS_CRITICAL },
  71         [ASPEED_CLK_GATE_USBPORT2CLK]   = {  7,  3, "usb-port2-gate",   NULL,    0 },   /* USB2.0 Host port 2 */
  72         /* Reserved 8 */
  73         [ASPEED_CLK_GATE_USBUHCICLK]    = {  9, 15, "usb-uhci-gate",    NULL,    0 },   /* USB1.1 (requires port 2 enabled) */
  74         /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
  75         [ASPEED_CLK_GATE_D1CLK]         = { 10, 13, "d1clk-gate",       "d1clk", 0 },   /* GFX CRT */
  76         /* Reserved 11/12 */
  77         [ASPEED_CLK_GATE_YCLK]          = { 13,  4, "yclk-gate",        NULL,    0 },   /* HAC */
  78         [ASPEED_CLK_GATE_USBPORT1CLK]   = { 14, 14, "usb-port1-gate",   NULL,    0 },   /* USB2 hub/USB2 host port 1/USB1.1 dev */
  79         [ASPEED_CLK_GATE_UART5CLK]      = { 15, -1, "uart5clk-gate",    "uart",  0 },   /* UART5 */
  80         /* Reserved 16/19 */
  81         [ASPEED_CLK_GATE_MAC1CLK]       = { 20, 11, "mac1clk-gate",     "mac12", 0 },   /* MAC1 */
  82         [ASPEED_CLK_GATE_MAC2CLK]       = { 21, 12, "mac2clk-gate",     "mac12", 0 },   /* MAC2 */
  83         /* Reserved 22/23 */
  84         [ASPEED_CLK_GATE_RSACLK]        = { 24,  4, "rsaclk-gate",      NULL,    0 },   /* HAC */
  85         [ASPEED_CLK_GATE_RVASCLK]       = { 25,  9, "rvasclk-gate",     NULL,    0 },   /* RVAS */
  86         /* Reserved 26 */
  87         [ASPEED_CLK_GATE_EMMCCLK]       = { 27, 16, "emmcclk-gate",     NULL,    0 },   /* For card clk */
  88         /* Reserved 28/29/30 */
  89         [ASPEED_CLK_GATE_LCLK]          = { 32, 32, "lclk-gate",        NULL,    0 }, /* LPC */
  90         [ASPEED_CLK_GATE_ESPICLK]       = { 33, -1, "espiclk-gate",     NULL,    0 }, /* eSPI */
  91         [ASPEED_CLK_GATE_REF1CLK]       = { 34, -1, "ref1clk-gate",     "clkin", CLK_IS_CRITICAL },
  92         /* Reserved 35 */
  93         [ASPEED_CLK_GATE_SDCLK]         = { 36, 56, "sdclk-gate",       NULL,    0 },   /* SDIO/SD */
  94         [ASPEED_CLK_GATE_LHCCLK]        = { 37, -1, "lhclk-gate",       "lhclk", 0 },   /* LPC master/LPC+ */
  95         /* Reserved 38 RSA: no longer used */
  96         /* Reserved 39 */
  97         [ASPEED_CLK_GATE_I3C0CLK]       = { 40,  40, "i3c0clk-gate",    NULL,    0 },   /* I3C0 */
  98         [ASPEED_CLK_GATE_I3C1CLK]       = { 41,  41, "i3c1clk-gate",    NULL,    0 },   /* I3C1 */
  99         [ASPEED_CLK_GATE_I3C2CLK]       = { 42,  42, "i3c2clk-gate",    NULL,    0 },   /* I3C2 */
 100         [ASPEED_CLK_GATE_I3C3CLK]       = { 43,  43, "i3c3clk-gate",    NULL,    0 },   /* I3C3 */
 101         [ASPEED_CLK_GATE_I3C4CLK]       = { 44,  44, "i3c4clk-gate",    NULL,    0 },   /* I3C4 */
 102         [ASPEED_CLK_GATE_I3C5CLK]       = { 45,  45, "i3c5clk-gate",    NULL,    0 },   /* I3C5 */
 103         [ASPEED_CLK_GATE_I3C6CLK]       = { 46,  46, "i3c6clk-gate",    NULL,    0 },   /* I3C6 */
 104         [ASPEED_CLK_GATE_I3C7CLK]       = { 47,  47, "i3c7clk-gate",    NULL,    0 },   /* I3C7 */
 105         [ASPEED_CLK_GATE_UART1CLK]      = { 48,  -1, "uart1clk-gate",   "uart",  0 },   /* UART1 */
 106         [ASPEED_CLK_GATE_UART2CLK]      = { 49,  -1, "uart2clk-gate",   "uart",  0 },   /* UART2 */
 107         [ASPEED_CLK_GATE_UART3CLK]      = { 50,  -1, "uart3clk-gate",   "uart",  0 },   /* UART3 */
 108         [ASPEED_CLK_GATE_UART4CLK]      = { 51,  -1, "uart4clk-gate",   "uart",  0 },   /* UART4 */
 109         [ASPEED_CLK_GATE_MAC3CLK]       = { 52,  52, "mac3clk-gate",    "mac34", 0 },   /* MAC3 */
 110         [ASPEED_CLK_GATE_MAC4CLK]       = { 53,  53, "mac4clk-gate",    "mac34", 0 },   /* MAC4 */
 111         [ASPEED_CLK_GATE_UART6CLK]      = { 54,  -1, "uart6clk-gate",   "uartx", 0 },   /* UART6 */
 112         [ASPEED_CLK_GATE_UART7CLK]      = { 55,  -1, "uart7clk-gate",   "uartx", 0 },   /* UART7 */
 113         [ASPEED_CLK_GATE_UART8CLK]      = { 56,  -1, "uart8clk-gate",   "uartx", 0 },   /* UART8 */
 114         [ASPEED_CLK_GATE_UART9CLK]      = { 57,  -1, "uart9clk-gate",   "uartx", 0 },   /* UART9 */
 115         [ASPEED_CLK_GATE_UART10CLK]     = { 58,  -1, "uart10clk-gate",  "uartx", 0 },   /* UART10 */
 116         [ASPEED_CLK_GATE_UART11CLK]     = { 59,  -1, "uart11clk-gate",  "uartx", 0 },   /* UART11 */
 117         [ASPEED_CLK_GATE_UART12CLK]     = { 60,  -1, "uart12clk-gate",  "uartx", 0 },   /* UART12 */
 118         [ASPEED_CLK_GATE_UART13CLK]     = { 61,  -1, "uart13clk-gate",  "uartx", 0 },   /* UART13 */
 119         [ASPEED_CLK_GATE_FSICLK]        = { 62,  59, "fsiclk-gate",     NULL,    0 },   /* FSI */
 120 };
 121
 122 static const struct clk_div_table ast2600_eclk_div_table[] = {
 123         { 0x0, 2 },
 124         { 0x1, 2 },
 125         { 0x2, 3 },
 126         { 0x3, 4 },
 127         { 0x4, 5 },
 128         { 0x5, 6 },
 129         { 0x6, 7 },
 130         { 0x7, 8 },
 131         { 0 }
 132 };
 133
 134 static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
 135         { 0x0, 2 },
 136         { 0x1, 4 },
 137         { 0x2, 6 },
 138         { 0x3, 8 },
 139         { 0x4, 10 },
 140         { 0x5, 12 },
 141         { 0x6, 14 },
 142         { 0x7, 16 },
 143         { 0 }
 144 };
 145
 146 static const struct clk_div_table ast2600_mac_div_table[] = {
 147         { 0x0, 4 },
 148         { 0x1, 4 },
 149         { 0x2, 6 },
 150         { 0x3, 8 },
 151         { 0x4, 10 },
 152         { 0x5, 12 },
 153         { 0x6, 14 },
 154         { 0x7, 16 },
 155         { 0 }
 156 };
 157
 158 static const struct clk_div_table ast2600_div_table[] = {
 159         { 0x0, 4 },
 160         { 0x1, 8 },
 161         { 0x2, 12 },
 162         { 0x3, 16 },
 163         { 0x4, 20 },
 164         { 0x5, 24 },
 165         { 0x6, 28 },
 166         { 0x7, 32 },
 167         { 0 }
 168 };
 169
 170 /* For hpll/dpll/epll/mpll */
 171 static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
 172 {
 173         unsigned int mult, div;
 174
 175         if (val & BIT(24)) {
 176                 /* Pass through mode */
 177                 mult = div = 1;
 178         } else {
 179                 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
 180                 u32 m = val  & 0x1fff;
 181                 u32 n = (val >> 13) & 0x3f;
 182                 u32 p = (val >> 19) & 0xf;
 183                 mult = (m + 1) / (n + 1);
 184                 div = (p + 1);
 185         }
 186         return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
 187                         mult, div);
 188 };
 189
 190 static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
 191 {
 192         unsigned int mult, div;
 193
 194         if (val & BIT(20)) {
 195                 /* Pass through mode */
 196                 mult = div = 1;
 197         } else {
 198                 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
 199                 u32 m = (val >> 5) & 0x3f;
 200                 u32 od = (val >> 4) & 0x1;
 201                 u32 n = val & 0xf;
 202
 203                 mult = (2 - od) * (m + 2);
 204                 div = n + 1;
 205         }
 206         return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
 207                         mult, div);
 208 };
 209
 210 static u32 get_bit(u8 idx)
 211 {
 212         return BIT(idx % 32);
 213 }
 214
 215 static u32 get_reset_reg(struct aspeed_clk_gate *gate)
 216 {
 217         if (gate->reset_idx < 32)
 218                 return ASPEED_G6_RESET_CTRL;
 219
 220         return ASPEED_G6_RESET_CTRL2;
 221 }
 222
 223 static u32 get_clock_reg(struct aspeed_clk_gate *gate)
 224 {
 225         if (gate->clock_idx < 32)
 226                 return ASPEED_G6_CLK_STOP_CTRL;
 227
 228         return ASPEED_G6_CLK_STOP_CTRL2;
 229 }
 230
 231 static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
 232 {
 233         struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
 234         u32 clk = get_bit(gate->clock_idx);
 235         u32 rst = get_bit(gate->reset_idx);
 236         u32 reg;
 237         u32 enval;
 238
 239         /*
 240          * If the IP is in reset, treat the clock as not enabled,
 241          * this happens with some clocks such as the USB one when
 242          * coming from cold reset. Without this, aspeed_clk_enable()
 243          * will fail to lift the reset.
 244          */
 245         if (gate->reset_idx >= 0) {
 246                 regmap_read(gate->map, get_reset_reg(gate), &reg);
 247
 248                 if (reg & rst)
 249                         return 0;
 250         }
 251
 252         regmap_read(gate->map, get_clock_reg(gate), &reg);
 253
 254         enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
 255
 256         return ((reg & clk) == enval) ? 1 : 0;
 257 }
 258
 259 static int aspeed_g6_clk_enable(struct clk_hw *hw)
 260 {
 261         struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
 262         unsigned long flags;
 263         u32 clk = get_bit(gate->clock_idx);
 264         u32 rst = get_bit(gate->reset_idx);
 265
 266         spin_lock_irqsave(gate->lock, flags);
 267
 268         if (aspeed_g6_clk_is_enabled(hw)) {
 269                 spin_unlock_irqrestore(gate->lock, flags);
 270                 return 0;
 271         }
 272
 273         if (gate->reset_idx >= 0) {
 274                 /* Put IP in reset */
 275                 regmap_write(gate->map, get_reset_reg(gate), rst);
 276                 /* Delay 100us */
 277                 udelay(100);
 278         }
 279
 280         /* Enable clock */
 281         if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
 282                 /* Clock is clear to enable, so use set to clear register */
 283                 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
 284         } else {
 285                 /* Clock is set to enable, so use write to set register */
 286                 regmap_write(gate->map, get_clock_reg(gate), clk);
 287         }
 288
 289         if (gate->reset_idx >= 0) {
 290                 /* A delay of 10ms is specified by the ASPEED docs */
 291                 mdelay(10);
 292                 /* Take IP out of reset */
 293                 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
 294         }
 295
 296         spin_unlock_irqrestore(gate->lock, flags);
 297
 298         return 0;
 299 }
 300
 301 static void aspeed_g6_clk_disable(struct clk_hw *hw)
 302 {
 303         struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
 304         unsigned long flags;
 305         u32 clk = get_bit(gate->clock_idx);
 306
 307         spin_lock_irqsave(gate->lock, flags);
 308
 309         if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
 310                 regmap_write(gate->map, get_clock_reg(gate), clk);
 311         } else {
 312                 /* Use set to clear register */
 313                 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
 314         }
 315
 316         spin_unlock_irqrestore(gate->lock, flags);
 317 }
 318
 319 static const struct clk_ops aspeed_g6_clk_gate_ops = {
 320         .enable = aspeed_g6_clk_enable,
 321         .disable = aspeed_g6_clk_disable,
 322         .is_enabled = aspeed_g6_clk_is_enabled,
 323 };
 324
 325 static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
 326                                     unsigned long id)
 327 {
 328         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
 329         u32 rst = get_bit(id);
 330         u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
 331
 332         /* Use set to clear register */
 333         return regmap_write(ar->map, reg + 0x04, rst);
 334 }
 335
 336 static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
 337                                   unsigned long id)
 338 {
 339         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
 340         u32 rst = get_bit(id);
 341         u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
 342
 343         return regmap_write(ar->map, reg, rst);
 344 }
 345
 346 static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
 347                                   unsigned long id)
 348 {
 349         struct aspeed_reset *ar = to_aspeed_reset(rcdev);
 350         int ret;
 351         u32 val;
 352         u32 rst = get_bit(id);
 353         u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
 354
 355         ret = regmap_read(ar->map, reg, &val);
 356         if (ret)
 357                 return ret;
 358
 359         return !!(val & rst);
 360 }
 361
 362 static const struct reset_control_ops aspeed_g6_reset_ops = {
 363         .assert = aspeed_g6_reset_assert,
 364         .deassert = aspeed_g6_reset_deassert,
 365         .status = aspeed_g6_reset_status,
 366 };
 367
 368 static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
 369                 const char *name, const char *parent_name, unsigned long flags,
 370                 struct regmap *map, u8 clock_idx, u8 reset_idx,
 371                 u8 clk_gate_flags, spinlock_t *lock)
 372 {
 373         struct aspeed_clk_gate *gate;
 374         struct clk_init_data init;
 375         struct clk_hw *hw;
 376         int ret;
 377
 378         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 379         if (!gate)
 380                 return ERR_PTR(-ENOMEM);
 381
 382         init.name = name;
 383         init.ops = &aspeed_g6_clk_gate_ops;
 384         init.flags = flags;
 385         init.parent_names = parent_name ? &parent_name : NULL;
 386         init.num_parents = parent_name ? 1 : 0;
 387
 388         gate->map = map;
 389         gate->clock_idx = clock_idx;
 390         gate->reset_idx = reset_idx;
 391         gate->flags = clk_gate_flags;
 392         gate->lock = lock;
 393         gate->hw.init = &init;
 394
 395         hw = &gate->hw;
 396         ret = clk_hw_register(dev, hw);
 397         if (ret) {
 398                 kfree(gate);
 399                 hw = ERR_PTR(ret);
 400         }
 401
 402         return hw;
 403 }
 404
 405 static const char *const emmc_extclk_parent_names[] = {
 406         "emmc_extclk_hpll_in",
 407         "mpll",
 408 };
 409
 410 static const char * const vclk_parent_names[] = {
 411         "dpll",
 412         "d1pll",
 413         "hclk",
 414         "mclk",
 415 };
 416
 417 static const char * const d1clk_parent_names[] = {
 418         "dpll",
 419         "epll",
 420         "usb-phy-40m",
 421         "gpioc6_clkin",
 422         "dp_phy_pll",
 423 };
 424
 425 static int aspeed_g6_clk_probe(struct platform_device *pdev)
 426 {
 427         struct device *dev = &pdev->dev;
 428         struct aspeed_reset *ar;
 429         struct regmap *map;
 430         struct clk_hw *hw;
 431         u32 val, rate;
 432         int i, ret;
 433
 434         map = syscon_node_to_regmap(dev->of_node);
 435         if (IS_ERR(map)) {
 436                 dev_err(dev, "no syscon regmap\n");
 437                 return PTR_ERR(map);
 438         }
 439
 440         ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
 441         if (!ar)
 442                 return -ENOMEM;
 443
 444         ar->map = map;
 445
 446         ar->rcdev.owner = THIS_MODULE;
 447         ar->rcdev.nr_resets = 64;
 448         ar->rcdev.ops = &aspeed_g6_reset_ops;
 449         ar->rcdev.of_node = dev->of_node;
 450
 451         ret = devm_reset_controller_register(dev, &ar->rcdev);
 452         if (ret) {
 453                 dev_err(dev, "could not register reset controller\n");
 454                 return ret;
 455         }
 456
 457         /* UART clock div13 setting */
 458         regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
 459         if (val & UART_DIV13_EN)
 460                 rate = 24000000 / 13;
 461         else
 462                 rate = 24000000;
 463         hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
 464         if (IS_ERR(hw))
 465                 return PTR_ERR(hw);
 466         aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
 467
 468         /* UART6~13 clock div13 setting */
 469         regmap_read(map, 0x80, &val);
 470         if (val & BIT(31))
 471                 rate = 24000000 / 13;
 472         else
 473                 rate = 24000000;
 474         hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
 475         if (IS_ERR(hw))
 476                 return PTR_ERR(hw);
 477         aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
 478
 479         /* EMMC ext clock */
 480         hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
 481                                           0, 1, 2);
 482         if (IS_ERR(hw))
 483                 return PTR_ERR(hw);
 484
 485         hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
 486                                  emmc_extclk_parent_names,
 487                                  ARRAY_SIZE(emmc_extclk_parent_names), 0,
 488                                  scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
 489                                  0, &aspeed_g6_clk_lock);
 490         if (IS_ERR(hw))
 491                 return PTR_ERR(hw);
 492
 493         hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
 494                                   0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
 495                                   15, 0, &aspeed_g6_clk_lock);
 496         if (IS_ERR(hw))
 497                 return PTR_ERR(hw);
 498
 499         hw = clk_hw_register_divider_table(dev, "emmc_extclk",
 500                                            "emmc_extclk_gate", 0,
 501                                            scu_g6_base +
 502                                                 ASPEED_G6_CLK_SELECTION1, 12,
 503                                            3, 0, ast2600_emmc_extclk_div_table,
 504                                            &aspeed_g6_clk_lock);
 505         if (IS_ERR(hw))
 506                 return PTR_ERR(hw);
 507         aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
 508
 509         /* SD/SDIO clock divider and gate */
 510         hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
 511                         scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
 512                         &aspeed_g6_clk_lock);
 513         if (IS_ERR(hw))
 514                 return PTR_ERR(hw);
 515         hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
 516                         0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
 517                         ast2600_div_table,
 518                         &aspeed_g6_clk_lock);
 519         if (IS_ERR(hw))
 520                 return PTR_ERR(hw);
 521         aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
 522
 523         /* MAC1/2 RMII 50MHz RCLK */
 524         hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
 525         if (IS_ERR(hw))
 526                 return PTR_ERR(hw);
 527
 528         /* MAC1/2 AHB bus clock divider */
 529         hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
 530                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
 531                         ast2600_mac_div_table,
 532                         &aspeed_g6_clk_lock);
 533         if (IS_ERR(hw))
 534                 return PTR_ERR(hw);
 535         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
 536
 537         /* RMII1 50MHz (RCLK) output enable */
 538         hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
 539                         scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
 540                         &aspeed_g6_clk_lock);
 541         if (IS_ERR(hw))
 542                 return PTR_ERR(hw);
 543         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
 544
 545         /* RMII2 50MHz (RCLK) output enable */
 546         hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
 547                         scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
 548                         &aspeed_g6_clk_lock);
 549         if (IS_ERR(hw))
 550                 return PTR_ERR(hw);
 551         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
 552
 553         /* MAC1/2 RMII 50MHz RCLK */
 554         hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
 555         if (IS_ERR(hw))
 556                 return PTR_ERR(hw);
 557
 558         /* MAC3/4 AHB bus clock divider */
 559         hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
 560                         scu_g6_base + 0x310, 24, 3, 0,
 561                         ast2600_mac_div_table,
 562                         &aspeed_g6_clk_lock);
 563         if (IS_ERR(hw))
 564                 return PTR_ERR(hw);
 565         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
 566
 567         /* RMII3 50MHz (RCLK) output enable */
 568         hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
 569                         scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
 570                         &aspeed_g6_clk_lock);
 571         if (IS_ERR(hw))
 572                 return PTR_ERR(hw);
 573         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
 574
 575         /* RMII4 50MHz (RCLK) output enable */
 576         hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
 577                         scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
 578                         &aspeed_g6_clk_lock);
 579         if (IS_ERR(hw))
 580                 return PTR_ERR(hw);
 581         aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;
 582
 583         /* LPC Host (LHCLK) clock divider */
 584         hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
 585                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
 586                         ast2600_div_table,
 587                         &aspeed_g6_clk_lock);
 588         if (IS_ERR(hw))
 589                 return PTR_ERR(hw);
 590         aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
 591
 592         /* gfx d1clk : use dp clk */
 593         regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
 594         /* SoC Display clock selection */
 595         hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
 596                         ARRAY_SIZE(d1clk_parent_names), 0,
 597                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
 598                         &aspeed_g6_clk_lock);
 599         if (IS_ERR(hw))
 600                 return PTR_ERR(hw);
 601         aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
 602
 603         /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
 604         regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
 605
 606         /* P-Bus (BCLK) clock divider */
 607         hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
 608                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
 609                         ast2600_div_table,
 610                         &aspeed_g6_clk_lock);
 611         if (IS_ERR(hw))
 612                 return PTR_ERR(hw);
 613         aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
 614
 615         /* Video Capture clock selection */
 616         hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
 617                         ARRAY_SIZE(vclk_parent_names), 0,
 618                         scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
 619                         &aspeed_g6_clk_lock);
 620         if (IS_ERR(hw))
 621                 return PTR_ERR(hw);
 622         aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
 623
 624         /* Video Engine clock divider */
 625         hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
 626                         scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
 627                         ast2600_eclk_div_table,
 628                         &aspeed_g6_clk_lock);
 629         if (IS_ERR(hw))
 630                 return PTR_ERR(hw);
 631         aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
 632
 633         for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
 634                 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
 635                 u32 gate_flags;
 636
 637                 /*
 638                  * Special case: the USB port 1 clock (bit 14) is always
 639                  * working the opposite way from the other ones.
 640                  */
 641                 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
 642                 hw = aspeed_g6_clk_hw_register_gate(dev,
 643                                 gd->name,
 644                                 gd->parent_name,
 645                                 gd->flags,
 646                                 map,
 647                                 gd->clock_idx,
 648                                 gd->reset_idx,
 649                                 gate_flags,
 650                                 &aspeed_g6_clk_lock);
 651                 if (IS_ERR(hw))
 652                         return PTR_ERR(hw);
 653                 aspeed_g6_clk_data->hws[i] = hw;
 654         }
 655
 656         return 0;
 657 };
 658
 659 static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
 660         { .compatible = "aspeed,ast2600-scu" },
 661         { }
 662 };
 663
 664 static struct platform_driver aspeed_g6_clk_driver = {
 665         .probe  = aspeed_g6_clk_probe,
 666         .driver = {
 667                 .name = "ast2600-clk",
 668                 .of_match_table = aspeed_g6_clk_dt_ids,
 669                 .suppress_bind_attrs = true,
 670         },
 671 };
 672 builtin_platform_driver(aspeed_g6_clk_driver);
 673
 674 static const u32 ast2600_a0_axi_ahb_div_table[] = {
 675         2, 2, 3, 5,
 676 };
 677
 678 static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {
 679         3, 2, 3, 4,
 680 };
 681
 682 static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {
 683         3, 4, 6, 8,
 684 };
 685
 686 static const u32 ast2600_a1_axi_ahb200_tbl[] = {
 687         3, 4, 3, 4, 2, 2, 2, 2,
 688 };
 689
 690 static void __init aspeed_g6_cc(struct regmap *map)
 691 {
 692         struct clk_hw *hw;
 693         u32 val, div, divbits, chip_id, axi_div, ahb_div;
 694
 695         clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
 696
 697         /*
 698          * High-speed PLL clock derived from the crystal. This the CPU clock,
 699          * and we assume that it is enabled
 700          */
 701         regmap_read(map, ASPEED_HPLL_PARAM, &val);
 702         aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
 703
 704         regmap_read(map, ASPEED_MPLL_PARAM, &val);
 705         aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
 706
 707         regmap_read(map, ASPEED_DPLL_PARAM, &val);
 708         aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
 709
 710         regmap_read(map, ASPEED_EPLL_PARAM, &val);
 711         aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
 712
 713         regmap_read(map, ASPEED_APLL_PARAM, &val);
 714         aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
 715
 716         /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
 717         regmap_read(map, ASPEED_G6_STRAP1, &val);
 718         if (val & BIT(16))
 719                 axi_div = 1;
 720         else
 721                 axi_div = 2;
 722
 723         divbits = (val >> 11) & 0x3;
 724         regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
 725         if (chip_id & BIT(16)) {
 726                 if (!divbits) {
 727                         ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
 728                         if (val & BIT(16))
 729                                 ahb_div *= 2;
 730                 } else {
 731                         if (val & BIT(16))
 732                                 ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
 733                         else
 734                                 ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
 735                 }
 736         } else {
 737                 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
 738         }
 739
 740         hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
 741         aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
 742
 743         regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
 744         val = (val >> 23) & 0x7;
 745         div = 4 * (val + 1);
 746         hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
 747         aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
 748
 749         regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
 750         val = (val >> 9) & 0x7;
 751         div = 2 * (val + 1);
 752         hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
 753         aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
 754
 755         /* USB 2.0 port1 phy 40MHz clock */
 756         hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
 757         aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
 758 };
 759
 760 static void __init aspeed_g6_cc_init(struct device_node *np)
 761 {
 762         struct regmap *map;
 763         int ret;
 764         int i;
 765
 766         scu_g6_base = of_iomap(np, 0);
 767         if (!scu_g6_base)
 768                 return;
 769
 770         aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
 771                                       ASPEED_G6_NUM_CLKS), GFP_KERNEL);
 772         if (!aspeed_g6_clk_data)
 773                 return;
 774
 775         /*
 776          * This way all clocks fetched before the platform device probes,
 777          * except those we assign here for early use, will be deferred.
 778          */
 779         for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
 780                 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
 781
 782         /*
 783          * We check that the regmap works on this very first access,
 784          * but as this is an MMIO-backed regmap, subsequent regmap
 785          * access is not going to fail and we skip error checks from
 786          * this point.
 787          */
 788         map = syscon_node_to_regmap(np);
 789         if (IS_ERR(map)) {
 790                 pr_err("no syscon regmap\n");
 791                 return;
 792         }
 793
 794         aspeed_g6_cc(map);
 795         aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
 796         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
 797         if (ret)
 798                 pr_err("failed to add DT provider: %d\n", ret);
 799 };
 800 CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);