drivers/clk/at91/sama7g5.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SAMA7G5 PMC code.
   4  *
   5  * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
   8  *
   9  */
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/slab.h>
  14
  15 #include <dt-bindings/clock/at91.h>
  16
  17 #include "pmc.h"
  18
  19 #define SAMA7G5_INIT_TABLE(_table, _count)              \
  20         do {                                            \
  21                 u8 _i;                                  \
  22                 for (_i = 0; _i < (_count); _i++)       \
  23                         (_table)[_i] = _i;              \
  24         } while (0)
  25
  26 #define SAMA7G5_FILL_TABLE(_to, _from, _count)          \
  27         do {                                            \
  28                 u8 _i;                                  \
  29                 for (_i = 0; _i < (_count); _i++) {     \
  30                         (_to)[_i] = (_from)[_i];        \
  31                 }                                       \
  32         } while (0)
  33
  34 static DEFINE_SPINLOCK(pmc_pll_lock);
  35 static DEFINE_SPINLOCK(pmc_mck0_lock);
  36 static DEFINE_SPINLOCK(pmc_mckX_lock);
  37
  38 /*
  39  * PLL clocks identifiers
  40  * @PLL_ID_CPU:         CPU PLL identifier
  41  * @PLL_ID_SYS:         System PLL identifier
  42  * @PLL_ID_DDR:         DDR PLL identifier
  43  * @PLL_ID_IMG:         Image subsystem PLL identifier
  44  * @PLL_ID_BAUD:        Baud PLL identifier
  45  * @PLL_ID_AUDIO:       Audio PLL identifier
  46  * @PLL_ID_ETH:         Ethernet PLL identifier
  47  */
  48 enum pll_ids {
  49         PLL_ID_CPU,
  50         PLL_ID_SYS,
  51         PLL_ID_DDR,
  52         PLL_ID_IMG,
  53         PLL_ID_BAUD,
  54         PLL_ID_AUDIO,
  55         PLL_ID_ETH,
  56         PLL_ID_MAX,
  57 };
  58
  59 /*
  60  * PLL type identifiers
  61  * @PLL_TYPE_FRAC:      fractional PLL identifier
  62  * @PLL_TYPE_DIV:       divider PLL identifier
  63  */
  64 enum pll_type {
  65         PLL_TYPE_FRAC,
  66         PLL_TYPE_DIV,
  67 };
  68
  69 /* Layout for fractional PLLs. */
  70 static const struct clk_pll_layout pll_layout_frac = {
  71         .mul_mask       = GENMASK(31, 24),
  72         .frac_mask      = GENMASK(21, 0),
  73         .mul_shift      = 24,
  74         .frac_shift     = 0,
  75 };
  76
  77 /* Layout for DIVPMC dividers. */
  78 static const struct clk_pll_layout pll_layout_divpmc = {
  79         .div_mask       = GENMASK(7, 0),
  80         .endiv_mask     = BIT(29),
  81         .div_shift      = 0,
  82         .endiv_shift    = 29,
  83 };
  84
  85 /* Layout for DIVIO dividers. */
  86 static const struct clk_pll_layout pll_layout_divio = {
  87         .div_mask       = GENMASK(19, 12),
  88         .endiv_mask     = BIT(30),
  89         .div_shift      = 12,
  90         .endiv_shift    = 30,
  91 };
  92
  93 /*
  94  * CPU PLL output range.
  95  * Notice: The upper limit has been setup to 1000000002 due to hardware
  96  * block which cannot output exactly 1GHz.
  97  */
  98 static const struct clk_range cpu_pll_outputs[] = {
  99         { .min = 2343750, .max = 1000000002 },
 100 };
 101
 102 /* PLL output range. */
 103 static const struct clk_range pll_outputs[] = {
 104         { .min = 2343750, .max = 1200000000 },
 105 };
 106
 107 /* CPU PLL characteristics. */
 108 static const struct clk_pll_characteristics cpu_pll_characteristics = {
 109         .input = { .min = 12000000, .max = 50000000 },
 110         .num_output = ARRAY_SIZE(cpu_pll_outputs),
 111         .output = cpu_pll_outputs,
 112 };
 113
 114 /* PLL characteristics. */
 115 static const struct clk_pll_characteristics pll_characteristics = {
 116         .input = { .min = 12000000, .max = 50000000 },
 117         .num_output = ARRAY_SIZE(pll_outputs),
 118         .output = pll_outputs,
 119 };
 120
 121 /*
 122  * PLL clocks description
 123  * @n:          clock name
 124  * @p:          clock parent
 125  * @l:          clock layout
 126  * @c:          clock characteristics
 127  * @t:          clock type
 128  * @f:          clock flags
 129  * @eid:        export index in sama7g5->chws[] array
 130  */
 131 static const struct {
 132         const char *n;
 133         const char *p;
 134         const struct clk_pll_layout *l;
 135         const struct clk_pll_characteristics *c;
 136         unsigned long f;
 137         u8 t;
 138         u8 eid;
 139 } sama7g5_plls[][PLL_ID_MAX] = {
 140         [PLL_ID_CPU] = {
 141                 { .n = "cpupll_fracck",
 142                   .p = "mainck",
 143                   .l = &pll_layout_frac,
 144                   .c = &cpu_pll_characteristics,
 145                   .t = PLL_TYPE_FRAC,
 146                    /*
 147                     * This feeds cpupll_divpmcck which feeds CPU. It should
 148                     * not be disabled.
 149                     */
 150                   .f = CLK_IS_CRITICAL, },
 151
 152                 { .n = "cpupll_divpmcck",
 153                   .p = "cpupll_fracck",
 154                   .l = &pll_layout_divpmc,
 155                   .c = &cpu_pll_characteristics,
 156                   .t = PLL_TYPE_DIV,
 157                    /* This feeds CPU. It should not be disabled. */
 158                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
 159                   .eid = PMC_CPUPLL, },
 160         },
 161
 162         [PLL_ID_SYS] = {
 163                 { .n = "syspll_fracck",
 164                   .p = "mainck",
 165                   .l = &pll_layout_frac,
 166                   .c = &pll_characteristics,
 167                   .t = PLL_TYPE_FRAC,
 168                    /*
 169                     * This feeds syspll_divpmcck which may feed critical parts
 170                     * of the systems like timers. Therefore it should not be
 171                     * disabled.
 172                     */
 173                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
 174
 175                 { .n = "syspll_divpmcck",
 176                   .p = "syspll_fracck",
 177                   .l = &pll_layout_divpmc,
 178                   .c = &pll_characteristics,
 179                   .t = PLL_TYPE_DIV,
 180                    /*
 181                     * This may feed critical parts of the systems like timers.
 182                     * Therefore it should not be disabled.
 183                     */
 184                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
 185                   .eid = PMC_SYSPLL, },
 186         },
 187
 188         [PLL_ID_DDR] = {
 189                 { .n = "ddrpll_fracck",
 190                   .p = "mainck",
 191                   .l = &pll_layout_frac,
 192                   .c = &pll_characteristics,
 193                   .t = PLL_TYPE_FRAC,
 194                    /*
 195                     * This feeds ddrpll_divpmcck which feeds DDR. It should not
 196                     * be disabled.
 197                     */
 198                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
 199
 200                 { .n = "ddrpll_divpmcck",
 201                   .p = "ddrpll_fracck",
 202                   .l = &pll_layout_divpmc,
 203                   .c = &pll_characteristics,
 204                   .t = PLL_TYPE_DIV,
 205                    /* This feeds DDR. It should not be disabled. */
 206                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
 207         },
 208
 209         [PLL_ID_IMG] = {
 210                 { .n = "imgpll_fracck",
 211                   .p = "mainck",
 212                   .l = &pll_layout_frac,
 213                   .c = &pll_characteristics,
 214                   .t = PLL_TYPE_FRAC,
 215                   .f = CLK_SET_RATE_GATE, },
 216
 217                 { .n = "imgpll_divpmcck",
 218                   .p = "imgpll_fracck",
 219                   .l = &pll_layout_divpmc,
 220                   .c = &pll_characteristics,
 221                   .t = PLL_TYPE_DIV,
 222                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 223                        CLK_SET_RATE_PARENT, },
 224         },
 225
 226         [PLL_ID_BAUD] = {
 227                 { .n = "baudpll_fracck",
 228                   .p = "mainck",
 229                   .l = &pll_layout_frac,
 230                   .c = &pll_characteristics,
 231                   .t = PLL_TYPE_FRAC,
 232                   .f = CLK_SET_RATE_GATE, },
 233
 234                 { .n = "baudpll_divpmcck",
 235                   .p = "baudpll_fracck",
 236                   .l = &pll_layout_divpmc,
 237                   .c = &pll_characteristics,
 238                   .t = PLL_TYPE_DIV,
 239                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 240                        CLK_SET_RATE_PARENT, },
 241         },
 242
 243         [PLL_ID_AUDIO] = {
 244                 { .n = "audiopll_fracck",
 245                   .p = "main_xtal",
 246                   .l = &pll_layout_frac,
 247                   .c = &pll_characteristics,
 248                   .t = PLL_TYPE_FRAC,
 249                   .f = CLK_SET_RATE_GATE, },
 250
 251                 { .n = "audiopll_divpmcck",
 252                   .p = "audiopll_fracck",
 253                   .l = &pll_layout_divpmc,
 254                   .c = &pll_characteristics,
 255                   .t = PLL_TYPE_DIV,
 256                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 257                        CLK_SET_RATE_PARENT,
 258                   .eid = PMC_AUDIOPMCPLL, },
 259
 260                 { .n = "audiopll_diviock",
 261                   .p = "audiopll_fracck",
 262                   .l = &pll_layout_divio,
 263                   .c = &pll_characteristics,
 264                   .t = PLL_TYPE_DIV,
 265                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 266                        CLK_SET_RATE_PARENT,
 267                   .eid = PMC_AUDIOIOPLL, },
 268         },
 269
 270         [PLL_ID_ETH] = {
 271                 { .n = "ethpll_fracck",
 272                   .p = "main_xtal",
 273                   .l = &pll_layout_frac,
 274                   .c = &pll_characteristics,
 275                   .t = PLL_TYPE_FRAC,
 276                   .f = CLK_SET_RATE_GATE, },
 277
 278                 { .n = "ethpll_divpmcck",
 279                   .p = "ethpll_fracck",
 280                   .l = &pll_layout_divpmc,
 281                   .c = &pll_characteristics,
 282                   .t = PLL_TYPE_DIV,
 283                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 284                        CLK_SET_RATE_PARENT, },
 285         },
 286 };
 287
 288 /*
 289  * Master clock (MCK[1..4]) description
 290  * @n:                  clock name
 291  * @ep:                 extra parents names array
 292  * @ep_chg_chg_id:      index in parents array that specifies the changeable
 293  *                      parent
 294  * @ep_count:           extra parents count
 295  * @ep_mux_table:       mux table for extra parents
 296  * @id:                 clock id
 297  * @c:                  true if clock is critical and cannot be disabled
 298  */
 299 static const struct {
 300         const char *n;
 301         const char *ep[4];
 302         int ep_chg_id;
 303         u8 ep_count;
 304         u8 ep_mux_table[4];
 305         u8 id;
 306         u8 c;
 307 } sama7g5_mckx[] = {
 308         { .n = "mck1",
 309           .id = 1,
 310           .ep = { "syspll_divpmcck", },
 311           .ep_mux_table = { 5, },
 312           .ep_count = 1,
 313           .ep_chg_id = INT_MIN,
 314           .c = 1, },
 315
 316         { .n = "mck2",
 317           .id = 2,
 318           .ep = { "ddrpll_divpmcck", },
 319           .ep_mux_table = { 6, },
 320           .ep_count = 1,
 321           .ep_chg_id = INT_MIN,
 322           .c = 1, },
 323
 324         { .n = "mck3",
 325           .id = 3,
 326           .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", },
 327           .ep_mux_table = { 5, 6, 7, },
 328           .ep_count = 3,
 329           .ep_chg_id = 5, },
 330
 331         { .n = "mck4",
 332           .id = 4,
 333           .ep = { "syspll_divpmcck", },
 334           .ep_mux_table = { 5, },
 335           .ep_count = 1,
 336           .ep_chg_id = INT_MIN,
 337           .c = 1, },
 338 };
 339
 340 /*
 341  * System clock description
 342  * @n:  clock name
 343  * @p:  clock parent name
 344  * @id: clock id
 345  */
 346 static const struct {
 347         const char *n;
 348         const char *p;
 349         u8 id;
 350 } sama7g5_systemck[] = {
 351         { .n = "pck0",          .p = "prog0", .id = 8, },
 352         { .n = "pck1",          .p = "prog1", .id = 9, },
 353         { .n = "pck2",          .p = "prog2", .id = 10, },
 354         { .n = "pck3",          .p = "prog3", .id = 11, },
 355         { .n = "pck4",          .p = "prog4", .id = 12, },
 356         { .n = "pck5",          .p = "prog5", .id = 13, },
 357         { .n = "pck6",          .p = "prog6", .id = 14, },
 358         { .n = "pck7",          .p = "prog7", .id = 15, },
 359 };
 360
 361 /* Mux table for programmable clocks. */
 362 static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
 363
 364 /*
 365  * Peripheral clock description
 366  * @n:          clock name
 367  * @p:          clock parent name
 368  * @r:          clock range values
 369  * @id:         clock id
 370  * @chgp:       index in parent array of the changeable parent
 371  */
 372 static const struct {
 373         const char *n;
 374         const char *p;
 375         struct clk_range r;
 376         u8 chgp;
 377         u8 id;
 378 } sama7g5_periphck[] = {
 379         { .n = "pioA_clk",      .p = "mck0", .id = 11, },
 380         { .n = "sfr_clk",       .p = "mck1", .id = 19, },
 381         { .n = "hsmc_clk",      .p = "mck1", .id = 21, },
 382         { .n = "xdmac0_clk",    .p = "mck1", .id = 22, },
 383         { .n = "xdmac1_clk",    .p = "mck1", .id = 23, },
 384         { .n = "xdmac2_clk",    .p = "mck1", .id = 24, },
 385         { .n = "acc_clk",       .p = "mck1", .id = 25, },
 386         { .n = "aes_clk",       .p = "mck1", .id = 27, },
 387         { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, },
 388         { .n = "asrc_clk",      .p = "mck1", .id = 30, .r = { .max = 200000000, }, },
 389         { .n = "cpkcc_clk",     .p = "mck0", .id = 32, },
 390         { .n = "csi_clk",       .p = "mck3", .id = 33, .r = { .max = 266000000, }, .chgp = 1, },
 391         { .n = "csi2dc_clk",    .p = "mck3", .id = 34, .r = { .max = 266000000, }, .chgp = 1, },
 392         { .n = "eic_clk",       .p = "mck1", .id = 37, },
 393         { .n = "flex0_clk",     .p = "mck1", .id = 38, },
 394         { .n = "flex1_clk",     .p = "mck1", .id = 39, },
 395         { .n = "flex2_clk",     .p = "mck1", .id = 40, },
 396         { .n = "flex3_clk",     .p = "mck1", .id = 41, },
 397         { .n = "flex4_clk",     .p = "mck1", .id = 42, },
 398         { .n = "flex5_clk",     .p = "mck1", .id = 43, },
 399         { .n = "flex6_clk",     .p = "mck1", .id = 44, },
 400         { .n = "flex7_clk",     .p = "mck1", .id = 45, },
 401         { .n = "flex8_clk",     .p = "mck1", .id = 46, },
 402         { .n = "flex9_clk",     .p = "mck1", .id = 47, },
 403         { .n = "flex10_clk",    .p = "mck1", .id = 48, },
 404         { .n = "flex11_clk",    .p = "mck1", .id = 49, },
 405         { .n = "gmac0_clk",     .p = "mck1", .id = 51, },
 406         { .n = "gmac1_clk",     .p = "mck1", .id = 52, },
 407         { .n = "icm_clk",       .p = "mck1", .id = 55, },
 408         { .n = "isc_clk",       .p = "mck3", .id = 56, .r = { .max = 266000000, }, .chgp = 1, },
 409         { .n = "i2smcc0_clk",   .p = "mck1", .id = 57, .r = { .max = 200000000, }, },
 410         { .n = "i2smcc1_clk",   .p = "mck1", .id = 58, .r = { .max = 200000000, }, },
 411         { .n = "matrix_clk",    .p = "mck1", .id = 60, },
 412         { .n = "mcan0_clk",     .p = "mck1", .id = 61, .r = { .max = 200000000, }, },
 413         { .n = "mcan1_clk",     .p = "mck1", .id = 62, .r = { .max = 200000000, }, },
 414         { .n = "mcan2_clk",     .p = "mck1", .id = 63, .r = { .max = 200000000, }, },
 415         { .n = "mcan3_clk",     .p = "mck1", .id = 64, .r = { .max = 200000000, }, },
 416         { .n = "mcan4_clk",     .p = "mck1", .id = 65, .r = { .max = 200000000, }, },
 417         { .n = "mcan5_clk",     .p = "mck1", .id = 66, .r = { .max = 200000000, }, },
 418         { .n = "pdmc0_clk",     .p = "mck1", .id = 68, .r = { .max = 200000000, }, },
 419         { .n = "pdmc1_clk",     .p = "mck1", .id = 69, .r = { .max = 200000000, }, },
 420         { .n = "pit64b0_clk",   .p = "mck1", .id = 70, },
 421         { .n = "pit64b1_clk",   .p = "mck1", .id = 71, },
 422         { .n = "pit64b2_clk",   .p = "mck1", .id = 72, },
 423         { .n = "pit64b3_clk",   .p = "mck1", .id = 73, },
 424         { .n = "pit64b4_clk",   .p = "mck1", .id = 74, },
 425         { .n = "pit64b5_clk",   .p = "mck1", .id = 75, },
 426         { .n = "pwm_clk",       .p = "mck1", .id = 77, },
 427         { .n = "qspi0_clk",     .p = "mck1", .id = 78, },
 428         { .n = "qspi1_clk",     .p = "mck1", .id = 79, },
 429         { .n = "sdmmc0_clk",    .p = "mck1", .id = 80, },
 430         { .n = "sdmmc1_clk",    .p = "mck1", .id = 81, },
 431         { .n = "sdmmc2_clk",    .p = "mck1", .id = 82, },
 432         { .n = "sha_clk",       .p = "mck1", .id = 83, },
 433         { .n = "spdifrx_clk",   .p = "mck1", .id = 84, .r = { .max = 200000000, }, },
 434         { .n = "spdiftx_clk",   .p = "mck1", .id = 85, .r = { .max = 200000000, }, },
 435         { .n = "ssc0_clk",      .p = "mck1", .id = 86, .r = { .max = 200000000, }, },
 436         { .n = "ssc1_clk",      .p = "mck1", .id = 87, .r = { .max = 200000000, }, },
 437         { .n = "tcb0_ch0_clk",  .p = "mck1", .id = 88, .r = { .max = 200000000, }, },
 438         { .n = "tcb0_ch1_clk",  .p = "mck1", .id = 89, .r = { .max = 200000000, }, },
 439         { .n = "tcb0_ch2_clk",  .p = "mck1", .id = 90, .r = { .max = 200000000, }, },
 440         { .n = "tcb1_ch0_clk",  .p = "mck1", .id = 91, .r = { .max = 200000000, }, },
 441         { .n = "tcb1_ch1_clk",  .p = "mck1", .id = 92, .r = { .max = 200000000, }, },
 442         { .n = "tcb1_ch2_clk",  .p = "mck1", .id = 93, .r = { .max = 200000000, }, },
 443         { .n = "tcpca_clk",     .p = "mck1", .id = 94, },
 444         { .n = "tcpcb_clk",     .p = "mck1", .id = 95, },
 445         { .n = "tdes_clk",      .p = "mck1", .id = 96, },
 446         { .n = "trng_clk",      .p = "mck1", .id = 97, },
 447         { .n = "udphsa_clk",    .p = "mck1", .id = 104, },
 448         { .n = "udphsb_clk",    .p = "mck1", .id = 105, },
 449         { .n = "uhphs_clk",     .p = "mck1", .id = 106, },
 450 };
 451
 452 /*
 453  * Generic clock description
 454  * @n:                  clock name
 455  * @pp:                 PLL parents
 456  * @pp_mux_table:       PLL parents mux table
 457  * @r:                  clock output range
 458  * @pp_chg_id:          id in parent array of changeable PLL parent
 459  * @pp_count:           PLL parents count
 460  * @id:                 clock id
 461  */
 462 static const struct {
 463         const char *n;
 464         const char *pp[8];
 465         const char pp_mux_table[8];
 466         struct clk_range r;
 467         int pp_chg_id;
 468         u8 pp_count;
 469         u8 id;
 470 } sama7g5_gck[] = {
 471         { .n  = "adc_gclk",
 472           .id = 26,
 473           .r = { .max = 100000000, },
 474           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "audiopll_divpmcck", },
 475           .pp_mux_table = { 5, 7, 9, },
 476           .pp_count = 3,
 477           .pp_chg_id = INT_MIN, },
 478
 479         { .n  = "asrc_gclk",
 480           .id = 30,
 481           .r = { .max = 200000000 },
 482           .pp = { "audiopll_divpmcck", },
 483           .pp_mux_table = { 9, },
 484           .pp_count = 1,
 485           .pp_chg_id = 3, },
 486
 487         { .n  = "csi_gclk",
 488           .id = 33,
 489           .r = { .max = 27000000  },
 490           .pp = { "ddrpll_divpmcck", "imgpll_divpmcck", },
 491           .pp_mux_table = { 6, 7, },
 492           .pp_count = 2,
 493           .pp_chg_id = INT_MIN, },
 494
 495         { .n  = "flex0_gclk",
 496           .id = 38,
 497           .r = { .max = 200000000 },
 498           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 499           .pp_mux_table = { 5, 8, },
 500           .pp_count = 2,
 501           .pp_chg_id = INT_MIN, },
 502
 503         { .n  = "flex1_gclk",
 504           .id = 39,
 505           .r = { .max = 200000000 },
 506           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 507           .pp_mux_table = { 5, 8, },
 508           .pp_count = 2,
 509           .pp_chg_id = INT_MIN, },
 510
 511         { .n  = "flex2_gclk",
 512           .id = 40,
 513           .r = { .max = 200000000 },
 514           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 515           .pp_mux_table = { 5, 8, },
 516           .pp_count = 2,
 517           .pp_chg_id = INT_MIN, },
 518
 519         { .n  = "flex3_gclk",
 520           .id = 41,
 521           .r = { .max = 200000000 },
 522           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 523           .pp_mux_table = { 5, 8, },
 524           .pp_count = 2,
 525           .pp_chg_id = INT_MIN, },
 526
 527         { .n  = "flex4_gclk",
 528           .id = 42,
 529           .r = { .max = 200000000 },
 530           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 531           .pp_mux_table = { 5, 8, },
 532           .pp_count = 2,
 533           .pp_chg_id = INT_MIN, },
 534
 535         { .n  = "flex5_gclk",
 536           .id = 43,
 537           .r = { .max = 200000000 },
 538           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 539           .pp_mux_table = { 5, 8, },
 540           .pp_count = 2,
 541           .pp_chg_id = INT_MIN, },
 542
 543         { .n  = "flex6_gclk",
 544           .id = 44,
 545           .r = { .max = 200000000 },
 546           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 547           .pp_mux_table = { 5, 8, },
 548           .pp_count = 2,
 549           .pp_chg_id = INT_MIN, },
 550
 551         { .n  = "flex7_gclk",
 552           .id = 45,
 553           .r = { .max = 200000000 },
 554           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 555           .pp_mux_table = { 5, 8, },
 556           .pp_count = 2,
 557           .pp_chg_id = INT_MIN, },
 558
 559         { .n  = "flex8_gclk",
 560           .id = 46,
 561           .r = { .max = 200000000 },
 562           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 563           .pp_mux_table = { 5, 8, },
 564           .pp_count = 2,
 565           .pp_chg_id = INT_MIN, },
 566
 567         { .n  = "flex9_gclk",
 568           .id = 47,
 569           .r = { .max = 200000000 },
 570           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 571           .pp_mux_table = { 5, 8, },
 572           .pp_count = 2,
 573           .pp_chg_id = INT_MIN, },
 574
 575         { .n  = "flex10_gclk",
 576           .id = 48,
 577           .r = { .max = 200000000 },
 578           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 579           .pp_mux_table = { 5, 8, },
 580           .pp_count = 2,
 581           .pp_chg_id = INT_MIN, },
 582
 583         { .n  = "flex11_gclk",
 584           .id = 49,
 585           .r = { .max = 200000000 },
 586           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 587           .pp_mux_table = { 5, 8, },
 588           .pp_count = 2,
 589           .pp_chg_id = INT_MIN, },
 590
 591         { .n  = "gmac0_gclk",
 592           .id = 51,
 593           .r = { .max = 125000000 },
 594           .pp = { "ethpll_divpmcck", },
 595           .pp_mux_table = { 10, },
 596           .pp_count = 1,
 597           .pp_chg_id = 3, },
 598
 599         { .n  = "gmac1_gclk",
 600           .id = 52,
 601           .r = { .max = 50000000  },
 602           .pp = { "ethpll_divpmcck", },
 603           .pp_mux_table = { 10, },
 604           .pp_count = 1,
 605           .pp_chg_id = INT_MIN, },
 606
 607         { .n  = "gmac0_tsu_gclk",
 608           .id = 53,
 609           .r = { .max = 300000000 },
 610           .pp = { "audiopll_divpmcck", "ethpll_divpmcck", },
 611           .pp_mux_table = { 9, 10, },
 612           .pp_count = 2,
 613           .pp_chg_id = INT_MIN, },
 614
 615         { .n  = "gmac1_tsu_gclk",
 616           .id = 54,
 617           .r = { .max = 300000000 },
 618           .pp = { "audiopll_divpmcck", "ethpll_divpmcck", },
 619           .pp_mux_table = { 9, 10, },
 620           .pp_count = 2,
 621           .pp_chg_id = INT_MIN, },
 622
 623         { .n  = "i2smcc0_gclk",
 624           .id = 57,
 625           .r = { .max = 100000000 },
 626           .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
 627           .pp_mux_table = { 5, 9, },
 628           .pp_count = 2,
 629           .pp_chg_id = 4, },
 630
 631         { .n  = "i2smcc1_gclk",
 632           .id = 58,
 633           .r = { .max = 100000000 },
 634           .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
 635           .pp_mux_table = { 5, 9, },
 636           .pp_count = 2,
 637           .pp_chg_id = 4, },
 638
 639         { .n  = "mcan0_gclk",
 640           .id = 61,
 641           .r = { .max = 200000000 },
 642           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 643           .pp_mux_table = { 5, 8, },
 644           .pp_count = 2,
 645           .pp_chg_id = INT_MIN, },
 646
 647         { .n  = "mcan1_gclk",
 648           .id = 62,
 649           .r = { .max = 200000000 },
 650           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 651           .pp_mux_table = { 5, 8, },
 652           .pp_count = 2,
 653           .pp_chg_id = INT_MIN, },
 654
 655         { .n  = "mcan2_gclk",
 656           .id = 63,
 657           .r = { .max = 200000000 },
 658           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 659           .pp_mux_table = { 5, 8, },
 660           .pp_count = 2,
 661           .pp_chg_id = INT_MIN, },
 662
 663         { .n  = "mcan3_gclk",
 664           .id = 64,
 665           .r = { .max = 200000000 },
 666           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 667           .pp_mux_table = { 5, 8, },
 668           .pp_count = 2,
 669           .pp_chg_id = INT_MIN, },
 670
 671         { .n  = "mcan4_gclk",
 672           .id = 65,
 673           .r = { .max = 200000000 },
 674           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 675           .pp_mux_table = { 5, 8, },
 676           .pp_count = 2,
 677           .pp_chg_id = INT_MIN, },
 678
 679         { .n  = "mcan5_gclk",
 680           .id = 66,
 681           .r = { .max = 200000000 },
 682           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 683           .pp_mux_table = { 5, 8, },
 684           .pp_count = 2,
 685           .pp_chg_id = INT_MIN, },
 686
 687         { .n  = "pdmc0_gclk",
 688           .id = 68,
 689           .r = { .max = 50000000  },
 690           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 691           .pp_mux_table = { 5, 8, },
 692           .pp_count = 2,
 693           .pp_chg_id = INT_MIN, },
 694
 695         { .n  = "pdmc1_gclk",
 696           .id = 69,
 697           .r = { .max = 50000000, },
 698           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 699           .pp_mux_table = { 5, 8, },
 700           .pp_count = 2,
 701           .pp_chg_id = INT_MIN, },
 702
 703         { .n  = "pit64b0_gclk",
 704           .id = 70,
 705           .r = { .max = 200000000 },
 706           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
 707                   "audiopll_divpmcck", "ethpll_divpmcck", },
 708           .pp_mux_table = { 5, 7, 8, 9, 10, },
 709           .pp_count = 5,
 710           .pp_chg_id = INT_MIN, },
 711
 712         { .n  = "pit64b1_gclk",
 713           .id = 71,
 714           .r = { .max = 200000000 },
 715           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
 716                   "audiopll_divpmcck", "ethpll_divpmcck", },
 717           .pp_mux_table = { 5, 7, 8, 9, 10, },
 718           .pp_count = 5,
 719           .pp_chg_id = INT_MIN, },
 720
 721         { .n  = "pit64b2_gclk",
 722           .id = 72,
 723           .r = { .max = 200000000 },
 724           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
 725                   "audiopll_divpmcck", "ethpll_divpmcck", },
 726           .pp_mux_table = { 5, 7, 8, 9, 10, },
 727           .pp_count = 5,
 728           .pp_chg_id = INT_MIN, },
 729
 730         { .n  = "pit64b3_gclk",
 731           .id = 73,
 732           .r = { .max = 200000000 },
 733           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
 734                   "audiopll_divpmcck", "ethpll_divpmcck", },
 735           .pp_mux_table = { 5, 7, 8, 9, 10, },
 736           .pp_count = 5,
 737           .pp_chg_id = INT_MIN, },
 738
 739         { .n  = "pit64b4_gclk",
 740           .id = 74,
 741           .r = { .max = 200000000 },
 742           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
 743                   "audiopll_divpmcck", "ethpll_divpmcck", },
 744           .pp_mux_table = { 5, 7, 8, 9, 10, },
 745           .pp_count = 5,
 746           .pp_chg_id = INT_MIN, },
 747
 748         { .n  = "pit64b5_gclk",
 749           .id = 75,
 750           .r = { .max = 200000000 },
 751           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
 752                   "audiopll_divpmcck", "ethpll_divpmcck", },
 753           .pp_mux_table = { 5, 7, 8, 9, 10, },
 754           .pp_count = 5,
 755           .pp_chg_id = INT_MIN, },
 756
 757         { .n  = "qspi0_gclk",
 758           .id = 78,
 759           .r = { .max = 200000000 },
 760           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 761           .pp_mux_table = { 5, 8, },
 762           .pp_count = 2,
 763           .pp_chg_id = INT_MIN, },
 764
 765         { .n  = "qspi1_gclk",
 766           .id = 79,
 767           .r = { .max = 200000000 },
 768           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 769           .pp_mux_table = { 5, 8, },
 770           .pp_count = 2,
 771           .pp_chg_id = INT_MIN, },
 772
 773         { .n  = "sdmmc0_gclk",
 774           .id = 80,
 775           .r = { .max = 208000000 },
 776           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 777           .pp_mux_table = { 5, 8, },
 778           .pp_count = 2,
 779           .pp_chg_id = 4, },
 780
 781         { .n  = "sdmmc1_gclk",
 782           .id = 81,
 783           .r = { .max = 208000000 },
 784           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 785           .pp_mux_table = { 5, 8, },
 786           .pp_count = 2,
 787           .pp_chg_id = 4, },
 788
 789         { .n  = "sdmmc2_gclk",
 790           .id = 82,
 791           .r = { .max = 208000000 },
 792           .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 793           .pp_mux_table = { 5, 8, },
 794           .pp_count = 2,
 795           .pp_chg_id = 4, },
 796
 797         { .n  = "spdifrx_gclk",
 798           .id = 84,
 799           .r = { .max = 150000000 },
 800           .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
 801           .pp_mux_table = { 5, 9, },
 802           .pp_count = 2,
 803           .pp_chg_id = 4, },
 804
 805         { .n = "spdiftx_gclk",
 806           .id = 85,
 807           .r = { .max = 25000000  },
 808           .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
 809           .pp_mux_table = { 5, 9, },
 810           .pp_count = 2,
 811           .pp_chg_id = 4, },
 812
 813         { .n  = "tcb0_ch0_gclk",
 814           .id = 88,
 815           .r = { .max = 200000000 },
 816           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
 817                   "audiopll_divpmcck", "ethpll_divpmcck", },
 818           .pp_mux_table = { 5, 7, 8, 9, 10, },
 819           .pp_count = 5,
 820           .pp_chg_id = INT_MIN, },
 821
 822         { .n  = "tcb1_ch0_gclk",
 823           .id = 91,
 824           .r = { .max = 200000000 },
 825           .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
 826                   "audiopll_divpmcck", "ethpll_divpmcck", },
 827           .pp_mux_table = { 5, 7, 8, 9, 10, },
 828           .pp_count = 5,
 829           .pp_chg_id = INT_MIN, },
 830
 831         { .n  = "tcpca_gclk",
 832           .id = 94,
 833           .r = { .max = 32768, },
 834           .pp_chg_id = INT_MIN, },
 835
 836         { .n  = "tcpcb_gclk",
 837           .id = 95,
 838           .r = { .max = 32768, },
 839           .pp_chg_id = INT_MIN, },
 840 };
 841
 842 /* MCK0 characteristics. */
 843 static const struct clk_master_characteristics mck0_characteristics = {
 844         .output = { .min = 50000000, .max = 200000000 },
 845         .divisors = { 1, 2, 4, 3, 5 },
 846         .have_div3_pres = 1,
 847 };
 848
 849 /* MCK0 layout. */
 850 static const struct clk_master_layout mck0_layout = {
 851         .mask = 0x773,
 852         .pres_shift = 4,
 853         .offset = 0x28,
 854 };
 855
 856 /* Programmable clock layout. */
 857 static const struct clk_programmable_layout programmable_layout = {
 858         .pres_mask = 0xff,
 859         .pres_shift = 8,
 860         .css_mask = 0x1f,
 861         .have_slck_mck = 0,
 862         .is_pres_direct = 1,
 863 };
 864
 865 /* Peripheral clock layout. */
 866 static const struct clk_pcr_layout sama7g5_pcr_layout = {
 867         .offset = 0x88,
 868         .cmd = BIT(31),
 869         .gckcss_mask = GENMASK(12, 8),
 870         .pid_mask = GENMASK(6, 0),
 871 };
 872
 873 static void __init sama7g5_pmc_setup(struct device_node *np)
 874 {
 875         const char *td_slck_name, *md_slck_name, *mainxtal_name;
 876         struct pmc_data *sama7g5_pmc;
 877         const char *parent_names[10];
 878         void **alloc_mem = NULL;
 879         int alloc_mem_size = 0;
 880         struct regmap *regmap;
 881         struct clk_hw *hw;
 882         bool bypass;
 883         int i, j;
 884
 885         i = of_property_match_string(np, "clock-names", "td_slck");
 886         if (i < 0)
 887                 return;
 888
 889         td_slck_name = of_clk_get_parent_name(np, i);
 890
 891         i = of_property_match_string(np, "clock-names", "md_slck");
 892         if (i < 0)
 893                 return;
 894
 895         md_slck_name = of_clk_get_parent_name(np, i);
 896
 897         i = of_property_match_string(np, "clock-names", "main_xtal");
 898         if (i < 0)
 899                 return;
 900
 901         mainxtal_name = of_clk_get_parent_name(np, i);
 902
 903         regmap = device_node_to_regmap(np);
 904         if (IS_ERR(regmap))
 905                 return;
 906
 907         sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
 908                                         nck(sama7g5_systemck),
 909                                         nck(sama7g5_periphck),
 910                                         nck(sama7g5_gck), 8);
 911         if (!sama7g5_pmc)
 912                 return;
 913
 914         alloc_mem = kmalloc(sizeof(void *) *
 915                             (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)),
 916                             GFP_KERNEL);
 917         if (!alloc_mem)
 918                 goto err_free;
 919
 920         hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
 921                                            50000000);
 922         if (IS_ERR(hw))
 923                 goto err_free;
 924
 925         bypass = of_property_read_bool(np, "atmel,osc-bypass");
 926
 927         hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
 928                                         bypass);
 929         if (IS_ERR(hw))
 930                 goto err_free;
 931
 932         parent_names[0] = "main_rc_osc";
 933         parent_names[1] = "main_osc";
 934         hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
 935         if (IS_ERR(hw))
 936                 goto err_free;
 937
 938         sama7g5_pmc->chws[PMC_MAIN] = hw;
 939
 940         for (i = 0; i < PLL_ID_MAX; i++) {
 941                 for (j = 0; j < 3; j++) {
 942                         struct clk_hw *parent_hw;
 943
 944                         if (!sama7g5_plls[i][j].n)
 945                                 continue;
 946
 947                         switch (sama7g5_plls[i][j].t) {
 948                         case PLL_TYPE_FRAC:
 949                                 if (!strcmp(sama7g5_plls[i][j].p, "mainck"))
 950                                         parent_hw = sama7g5_pmc->chws[PMC_MAIN];
 951                                 else
 952                                         parent_hw = __clk_get_hw(of_clk_get_by_name(np,
 953                                                 sama7g5_plls[i][j].p));
 954
 955                                 hw = sam9x60_clk_register_frac_pll(regmap,
 956                                         &pmc_pll_lock, sama7g5_plls[i][j].n,
 957                                         sama7g5_plls[i][j].p, parent_hw, i,
 958                                         sama7g5_plls[i][j].c,
 959                                         sama7g5_plls[i][j].l,
 960                                         sama7g5_plls[i][j].f);
 961                                 break;
 962
 963                         case PLL_TYPE_DIV:
 964                                 hw = sam9x60_clk_register_div_pll(regmap,
 965                                         &pmc_pll_lock, sama7g5_plls[i][j].n,
 966                                         sama7g5_plls[i][j].p, i,
 967                                         sama7g5_plls[i][j].c,
 968                                         sama7g5_plls[i][j].l,
 969                                         sama7g5_plls[i][j].f);
 970                                 break;
 971
 972                         default:
 973                                 continue;
 974                         }
 975
 976                         if (IS_ERR(hw))
 977                                 goto err_free;
 978
 979                         if (sama7g5_plls[i][j].eid)
 980                                 sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw;
 981                 }
 982         }
 983
 984         parent_names[0] = "cpupll_divpmcck";
 985         hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
 986                                            &mck0_layout, &mck0_characteristics,
 987                                            &pmc_mck0_lock,
 988                                            CLK_SET_RATE_PARENT, 0);
 989         if (IS_ERR(hw))
 990                 goto err_free;
 991
 992         sama7g5_pmc->chws[PMC_CPU] = hw;
 993
 994         hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
 995                                           &mck0_layout, &mck0_characteristics,
 996                                           &pmc_mck0_lock, 0);
 997         if (IS_ERR(hw))
 998                 goto err_free;
 999
1000         sama7g5_pmc->chws[PMC_MCK] = hw;
1001
1002         parent_names[0] = md_slck_name;
1003         parent_names[1] = td_slck_name;
1004         parent_names[2] = "mainck";
1005         for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
1006                 u8 num_parents = 3 + sama7g5_mckx[i].ep_count;
1007                 u32 *mux_table;
1008
1009                 mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
1010                                           GFP_KERNEL);
1011                 if (!mux_table)
1012                         goto err_free;
1013
1014                 SAMA7G5_INIT_TABLE(mux_table, 3);
1015                 SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
1016                                    sama7g5_mckx[i].ep_count);
1017                 SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep,
1018                                    sama7g5_mckx[i].ep_count);
1019
1020                 hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
1021                                    num_parents, parent_names, mux_table,
1022                                    &pmc_mckX_lock, sama7g5_mckx[i].id,
1023                                    sama7g5_mckx[i].c,
1024                                    sama7g5_mckx[i].ep_chg_id);
1025                 if (IS_ERR(hw))
1026                         goto err_free;
1027
1028                 alloc_mem[alloc_mem_size++] = mux_table;
1029         }
1030
1031         hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", "main_xtal");
1032         if (IS_ERR(hw))
1033                 goto err_free;
1034
1035         sama7g5_pmc->chws[PMC_UTMI] = hw;
1036
1037         parent_names[0] = md_slck_name;
1038         parent_names[1] = td_slck_name;
1039         parent_names[2] = "mainck";
1040         parent_names[3] = "syspll_divpmcck";
1041         parent_names[4] = "ddrpll_divpmcck";
1042         parent_names[5] = "imgpll_divpmcck";
1043         parent_names[6] = "baudpll_divpmcck";
1044         parent_names[7] = "audiopll_divpmcck";
1045         parent_names[8] = "ethpll_divpmcck";
1046         for (i = 0; i < 8; i++) {
1047                 char name[6];
1048
1049                 snprintf(name, sizeof(name), "prog%d", i);
1050
1051                 hw = at91_clk_register_programmable(regmap, name, parent_names,
1052                                                     9, i,
1053                                                     &programmable_layout,
1054                                                     sama7g5_prog_mux_table);
1055                 if (IS_ERR(hw))
1056                         goto err_free;
1057
1058                 sama7g5_pmc->pchws[i] = hw;
1059         }
1060
1061         for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) {
1062                 hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n,
1063                                               sama7g5_systemck[i].p,
1064                                               sama7g5_systemck[i].id);
1065                 if (IS_ERR(hw))
1066                         goto err_free;
1067
1068                 sama7g5_pmc->shws[sama7g5_systemck[i].id] = hw;
1069         }
1070
1071         for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) {
1072                 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
1073                                                 &sama7g5_pcr_layout,
1074                                                 sama7g5_periphck[i].n,
1075                                                 sama7g5_periphck[i].p,
1076                                                 sama7g5_periphck[i].id,
1077                                                 &sama7g5_periphck[i].r,
1078                                                 sama7g5_periphck[i].chgp ? 0 :
1079                                                 INT_MIN);
1080                 if (IS_ERR(hw))
1081                         goto err_free;
1082
1083                 sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw;
1084         }
1085
1086         parent_names[0] = md_slck_name;
1087         parent_names[1] = td_slck_name;
1088         parent_names[2] = "mainck";
1089         for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
1090                 u8 num_parents = 3 + sama7g5_gck[i].pp_count;
1091                 u32 *mux_table;
1092
1093                 mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
1094                                           GFP_KERNEL);
1095                 if (!mux_table)
1096                         goto err_free;
1097
1098                 SAMA7G5_INIT_TABLE(mux_table, 3);
1099                 SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
1100                                    sama7g5_gck[i].pp_count);
1101                 SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp,
1102                                    sama7g5_gck[i].pp_count);
1103
1104                 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
1105                                                  &sama7g5_pcr_layout,
1106                                                  sama7g5_gck[i].n,
1107                                                  parent_names, mux_table,
1108                                                  num_parents,
1109                                                  sama7g5_gck[i].id,
1110                                                  &sama7g5_gck[i].r,
1111                                                  sama7g5_gck[i].pp_chg_id);
1112                 if (IS_ERR(hw))
1113                         goto err_free;
1114
1115                 sama7g5_pmc->ghws[sama7g5_gck[i].id] = hw;
1116                 alloc_mem[alloc_mem_size++] = mux_table;
1117         }
1118
1119         of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc);
1120
1121         return;
1122
1123 err_free:
1124         if (alloc_mem) {
1125                 for (i = 0; i < alloc_mem_size; i++)
1126                         kfree(alloc_mem[i]);
1127                 kfree(alloc_mem);
1128         }
1129
1130         kfree(sama7g5_pmc);
1131 }
1132
1133 /* Some clks are used for a clocksource */
1134 CLK_OF_DECLARE(sama7g5_pmc, "microchip,sama7g5-pmc", sama7g5_pmc_setup);