1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 #include <linux/clkdev.h>
9 #include <linux/cpu_pm.h>
10 #include <linux/delay.h>
11 #include <linux/list.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
17 #include <linux/of_address.h>
18 #include <linux/of_platform.h>
19 #include <linux/slab.h>
20 #include <linux/sys_soc.h>
21 #include <linux/timekeeping.h>
22 #include <linux/iopoll.h>
24 #include <linux/platform_data/ti-sysc.h>
26 #include <dt-bindings/bus/ti-sysc.h>
28 #define DIS_ISP BIT(2)
29 #define DIS_IVA BIT(1)
30 #define DIS_SGX BIT(0)
32 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
34 #define MAX_MODULE_SOFTRESET_WAIT 10000
53 struct list_head node;
58 struct list_head node;
61 struct sysc_soc_info {
62 unsigned long general_purpose:1;
64 struct mutex list_lock; /* disabled and restored modules list lock */
65 struct list_head disabled_modules;
66 struct list_head restored_modules;
67 struct notifier_block nb;
84 static struct sysc_soc_info *sysc_soc;
85 static const char * const reg_names[] = { "rev", "sysc", "syss", };
86 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
87 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
88 "opt5", "opt6", "opt7",
91 #define SYSC_IDLEMODE_MASK 3
92 #define SYSC_CLOCKACTIVITY_MASK 3
95 * struct sysc - TI sysc interconnect target module registers and capabilities
96 * @dev: struct device pointer
97 * @module_pa: physical address of the interconnect target module
98 * @module_size: size of the interconnect target module
99 * @module_va: virtual address of the interconnect target module
100 * @offsets: register offsets from module base
101 * @mdata: ti-sysc to hwmod translation data for a module
102 * @clocks: clocks used by the interconnect target module
103 * @clock_roles: clock role names for the found clocks
104 * @nr_clocks: number of clocks used by the interconnect target module
105 * @rsts: resets used by the interconnect target module
106 * @legacy_mode: configured for legacy mode if set
107 * @cap: interconnect target module capabilities
108 * @cfg: interconnect target module configuration
109 * @cookie: data used by legacy platform callbacks
110 * @name: name if available
111 * @revision: interconnect target module revision
112 * @reserved: target module is reserved and already in use
113 * @enabled: sysc runtime enabled status
114 * @needs_resume: runtime resume needed on resume from suspend
115 * @child_needs_resume: runtime resume needed for child on resume from suspend
116 * @disable_on_idle: status flag used for disabling modules with resets
117 * @idle_work: work structure used to perform delayed idle on a module
118 * @pre_reset_quirk: module specific pre-reset quirk
119 * @post_reset_quirk: module specific post-reset quirk
120 * @reset_done_quirk: module specific reset done quirk
121 * @module_enable_quirk: module specific enable quirk
122 * @module_disable_quirk: module specific disable quirk
123 * @module_unlock_quirk: module specific sysconfig unlock quirk
124 * @module_lock_quirk: module specific sysconfig lock quirk
130 void __iomem *module_va;
131 int offsets[SYSC_MAX_REGS];
132 struct ti_sysc_module_data *mdata;
134 const char **clock_roles;
136 struct reset_control *rsts;
137 const char *legacy_mode;
138 const struct sysc_capabilities *cap;
139 struct sysc_config cfg;
140 struct ti_sysc_cookie cookie;
144 unsigned int reserved:1;
145 unsigned int enabled:1;
146 unsigned int needs_resume:1;
147 unsigned int child_needs_resume:1;
148 struct delayed_work idle_work;
149 void (*pre_reset_quirk)(struct sysc *sysc);
150 void (*post_reset_quirk)(struct sysc *sysc);
151 void (*reset_done_quirk)(struct sysc *sysc);
152 void (*module_enable_quirk)(struct sysc *sysc);
153 void (*module_disable_quirk)(struct sysc *sysc);
154 void (*module_unlock_quirk)(struct sysc *sysc);
155 void (*module_lock_quirk)(struct sysc *sysc);
158 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
161 static void sysc_write(struct sysc *ddata, int offset, u32 value)
163 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
164 writew_relaxed(value & 0xffff, ddata->module_va + offset);
166 /* Only i2c revision has LO and HI register with stride of 4 */
167 if (ddata->offsets[SYSC_REVISION] >= 0 &&
168 offset == ddata->offsets[SYSC_REVISION]) {
169 u16 hi = value >> 16;
171 writew_relaxed(hi, ddata->module_va + offset + 4);
177 writel_relaxed(value, ddata->module_va + offset);
180 static u32 sysc_read(struct sysc *ddata, int offset)
182 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
185 val = readw_relaxed(ddata->module_va + offset);
187 /* Only i2c revision has LO and HI register with stride of 4 */
188 if (ddata->offsets[SYSC_REVISION] >= 0 &&
189 offset == ddata->offsets[SYSC_REVISION]) {
190 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
198 return readl_relaxed(ddata->module_va + offset);
201 static bool sysc_opt_clks_needed(struct sysc *ddata)
203 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
206 static u32 sysc_read_revision(struct sysc *ddata)
208 int offset = ddata->offsets[SYSC_REVISION];
213 return sysc_read(ddata, offset);
216 static u32 sysc_read_sysconfig(struct sysc *ddata)
218 int offset = ddata->offsets[SYSC_SYSCONFIG];
223 return sysc_read(ddata, offset);
226 static u32 sysc_read_sysstatus(struct sysc *ddata)
228 int offset = ddata->offsets[SYSC_SYSSTATUS];
233 return sysc_read(ddata, offset);
236 static int sysc_poll_reset_sysstatus(struct sysc *ddata)
239 u32 syss_done, rstval;
241 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
244 syss_done = ddata->cfg.syss_mask;
246 if (likely(!timekeeping_suspended)) {
247 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
248 rstval, (rstval & ddata->cfg.syss_mask) ==
249 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
251 retries = MAX_MODULE_SOFTRESET_WAIT;
253 rstval = sysc_read_sysstatus(ddata);
254 if ((rstval & ddata->cfg.syss_mask) == syss_done)
256 udelay(2); /* Account for udelay flakeyness */
264 static int sysc_poll_reset_sysconfig(struct sysc *ddata)
267 u32 sysc_mask, rstval;
269 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
271 if (likely(!timekeeping_suspended)) {
272 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
273 rstval, !(rstval & sysc_mask),
274 100, MAX_MODULE_SOFTRESET_WAIT);
276 retries = MAX_MODULE_SOFTRESET_WAIT;
278 rstval = sysc_read_sysconfig(ddata);
279 if (!(rstval & sysc_mask))
281 udelay(2); /* Account for udelay flakeyness */
289 /* Poll on reset status */
290 static int sysc_wait_softreset(struct sysc *ddata)
292 int syss_offset, error = 0;
294 if (ddata->cap->regbits->srst_shift < 0)
297 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
299 if (syss_offset >= 0)
300 error = sysc_poll_reset_sysstatus(ddata);
301 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
302 error = sysc_poll_reset_sysconfig(ddata);
307 static int sysc_add_named_clock_from_child(struct sysc *ddata,
309 const char *optfck_name)
311 struct device_node *np = ddata->dev->of_node;
312 struct device_node *child;
313 struct clk_lookup *cl;
322 /* Does the clock alias already exist? */
323 clock = of_clk_get_by_name(np, n);
324 if (!IS_ERR(clock)) {
330 child = of_get_next_available_child(np, NULL);
334 clock = devm_get_clk_from_child(ddata->dev, child, name);
336 return PTR_ERR(clock);
339 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
340 * limit for clk_get(). If cl ever needs to be freed, it should be done
341 * with clkdev_drop().
343 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
348 cl->dev_id = dev_name(ddata->dev);
357 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
359 const char *optfck_name;
362 if (ddata->nr_clocks < SYSC_OPTFCK0)
363 index = SYSC_OPTFCK0;
365 index = ddata->nr_clocks;
370 optfck_name = clock_names[index];
372 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
376 ddata->clock_roles[index] = optfck_name;
382 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
384 int error, i, index = -ENODEV;
386 if (!strncmp(clock_names[SYSC_FCK], name, 3))
388 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
392 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
393 if (!ddata->clocks[i]) {
401 dev_err(ddata->dev, "clock %s not added\n", name);
405 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
406 if (IS_ERR(ddata->clocks[index])) {
407 dev_err(ddata->dev, "clock get error for %s: %li\n",
408 name, PTR_ERR(ddata->clocks[index]));
410 return PTR_ERR(ddata->clocks[index]);
413 error = clk_prepare(ddata->clocks[index]);
415 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
424 static int sysc_get_clocks(struct sysc *ddata)
426 struct device_node *np = ddata->dev->of_node;
427 struct property *prop;
429 int nr_fck = 0, nr_ick = 0, i, error = 0;
431 ddata->clock_roles = devm_kcalloc(ddata->dev,
433 sizeof(*ddata->clock_roles),
435 if (!ddata->clock_roles)
438 of_property_for_each_string(np, "clock-names", prop, name) {
439 if (!strncmp(clock_names[SYSC_FCK], name, 3))
441 if (!strncmp(clock_names[SYSC_ICK], name, 3))
443 ddata->clock_roles[ddata->nr_clocks] = name;
447 if (ddata->nr_clocks < 1)
450 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
451 error = sysc_init_ext_opt_clock(ddata, NULL);
456 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
457 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
462 if (nr_fck > 1 || nr_ick > 1) {
463 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
468 /* Always add a slot for main clocks fck and ick even if unused */
474 ddata->clocks = devm_kcalloc(ddata->dev,
475 ddata->nr_clocks, sizeof(*ddata->clocks),
480 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
481 const char *name = ddata->clock_roles[i];
486 error = sysc_get_one_clock(ddata, name);
494 static int sysc_enable_main_clocks(struct sysc *ddata)
502 for (i = 0; i < SYSC_OPTFCK0; i++) {
503 clock = ddata->clocks[i];
505 /* Main clocks may not have ick */
506 if (IS_ERR_OR_NULL(clock))
509 error = clk_enable(clock);
517 for (i--; i >= 0; i--) {
518 clock = ddata->clocks[i];
520 /* Main clocks may not have ick */
521 if (IS_ERR_OR_NULL(clock))
530 static void sysc_disable_main_clocks(struct sysc *ddata)
538 for (i = 0; i < SYSC_OPTFCK0; i++) {
539 clock = ddata->clocks[i];
540 if (IS_ERR_OR_NULL(clock))
547 static int sysc_enable_opt_clocks(struct sysc *ddata)
552 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
555 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
556 clock = ddata->clocks[i];
558 /* Assume no holes for opt clocks */
559 if (IS_ERR_OR_NULL(clock))
562 error = clk_enable(clock);
570 for (i--; i >= 0; i--) {
571 clock = ddata->clocks[i];
572 if (IS_ERR_OR_NULL(clock))
581 static void sysc_disable_opt_clocks(struct sysc *ddata)
586 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
589 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
590 clock = ddata->clocks[i];
592 /* Assume no holes for opt clocks */
593 if (IS_ERR_OR_NULL(clock))
600 static void sysc_clkdm_deny_idle(struct sysc *ddata)
602 struct ti_sysc_platform_data *pdata;
604 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
607 pdata = dev_get_platdata(ddata->dev);
608 if (pdata && pdata->clkdm_deny_idle)
609 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
612 static void sysc_clkdm_allow_idle(struct sysc *ddata)
614 struct ti_sysc_platform_data *pdata;
616 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
619 pdata = dev_get_platdata(ddata->dev);
620 if (pdata && pdata->clkdm_allow_idle)
621 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
625 * sysc_init_resets - init rstctrl reset line if configured
626 * @ddata: device driver data
628 * See sysc_rstctrl_reset_deassert().
630 static int sysc_init_resets(struct sysc *ddata)
633 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
635 return PTR_ERR_OR_ZERO(ddata->rsts);
639 * sysc_parse_and_check_child_range - parses module IO region from ranges
640 * @ddata: device driver data
642 * In general we only need rev, syss, and sysc registers and not the whole
643 * module range. But we do want the offsets for these registers from the
644 * module base. This allows us to check them against the legacy hwmod
645 * platform data. Let's also check the ranges are configured properly.
647 static int sysc_parse_and_check_child_range(struct sysc *ddata)
649 struct device_node *np = ddata->dev->of_node;
650 const __be32 *ranges;
651 u32 nr_addr, nr_size;
654 ranges = of_get_property(np, "ranges", &len);
656 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
661 len /= sizeof(*ranges);
664 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
669 error = of_property_read_u32(np, "#address-cells", &nr_addr);
673 error = of_property_read_u32(np, "#size-cells", &nr_size);
677 if (nr_addr != 1 || nr_size != 1) {
678 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
684 ddata->module_pa = of_translate_address(np, ranges++);
685 ddata->module_size = be32_to_cpup(ranges);
690 /* Interconnect instances to probe before l4_per instances */
691 static struct resource early_bus_ranges[] = {
693 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
694 /* omap4/5 and dra7 l4_cfg */
695 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
697 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
698 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
699 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
702 static atomic_t sysc_defer = ATOMIC_INIT(10);
705 * sysc_defer_non_critical - defer non_critical interconnect probing
706 * @ddata: device driver data
708 * We want to probe l4_cfg and l4_wkup interconnect instances before any
709 * l4_per instances as l4_per instances depend on resources on l4_cfg and
710 * l4_wkup interconnects.
712 static int sysc_defer_non_critical(struct sysc *ddata)
714 struct resource *res;
717 if (!atomic_read(&sysc_defer))
720 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
721 res = &early_bus_ranges[i];
722 if (ddata->module_pa >= res->start &&
723 ddata->module_pa <= res->end) {
724 atomic_set(&sysc_defer, 0);
730 atomic_dec_if_positive(&sysc_defer);
732 return -EPROBE_DEFER;
735 static struct device_node *stdout_path;
737 static void sysc_init_stdout_path(struct sysc *ddata)
739 struct device_node *np = NULL;
742 if (IS_ERR(stdout_path))
748 np = of_find_node_by_path("/chosen");
752 uart = of_get_property(np, "stdout-path", NULL);
756 np = of_find_node_by_path(uart);
765 stdout_path = ERR_PTR(-ENODEV);
768 static void sysc_check_quirk_stdout(struct sysc *ddata,
769 struct device_node *np)
771 sysc_init_stdout_path(ddata);
772 if (np != stdout_path)
775 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
776 SYSC_QUIRK_NO_RESET_ON_INIT;
780 * sysc_check_one_child - check child configuration
781 * @ddata: device driver data
782 * @np: child device node
784 * Let's avoid messy situations where we have new interconnect target
785 * node but children have "ti,hwmods". These belong to the interconnect
786 * target node and are managed by this driver.
788 static void sysc_check_one_child(struct sysc *ddata,
789 struct device_node *np)
793 name = of_get_property(np, "ti,hwmods", NULL);
794 if (name && !of_device_is_compatible(np, "ti,sysc"))
795 dev_warn(ddata->dev, "really a child ti,hwmods property?");
797 sysc_check_quirk_stdout(ddata, np);
798 sysc_parse_dts_quirks(ddata, np, true);
801 static void sysc_check_children(struct sysc *ddata)
803 struct device_node *child;
805 for_each_child_of_node(ddata->dev->of_node, child)
806 sysc_check_one_child(ddata, child);
810 * So far only I2C uses 16-bit read access with clockactivity with revision
811 * in two registers with stride of 4. We can detect this based on the rev
812 * register size to configure things far enough to be able to properly read
813 * the revision register.
815 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
817 if (resource_size(res) == 8)
818 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
822 * sysc_parse_one - parses the interconnect target module registers
823 * @ddata: device driver data
824 * @reg: register to parse
826 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
828 struct resource *res;
835 name = reg_names[reg];
841 res = platform_get_resource_byname(to_platform_device(ddata->dev),
842 IORESOURCE_MEM, name);
844 ddata->offsets[reg] = -ENODEV;
849 ddata->offsets[reg] = res->start - ddata->module_pa;
850 if (reg == SYSC_REVISION)
851 sysc_check_quirk_16bit(ddata, res);
856 static int sysc_parse_registers(struct sysc *ddata)
860 for (i = 0; i < SYSC_MAX_REGS; i++) {
861 error = sysc_parse_one(ddata, i);
870 * sysc_check_registers - check for misconfigured register overlaps
871 * @ddata: device driver data
873 static int sysc_check_registers(struct sysc *ddata)
875 int i, j, nr_regs = 0, nr_matches = 0;
877 for (i = 0; i < SYSC_MAX_REGS; i++) {
878 if (ddata->offsets[i] < 0)
881 if (ddata->offsets[i] > (ddata->module_size - 4)) {
882 dev_err(ddata->dev, "register outside module range");
887 for (j = 0; j < SYSC_MAX_REGS; j++) {
888 if (ddata->offsets[j] < 0)
891 if (ddata->offsets[i] == ddata->offsets[j])
897 if (nr_matches > nr_regs) {
898 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
899 nr_regs, nr_matches);
908 * sysc_ioremap - ioremap register space for the interconnect target module
909 * @ddata: device driver data
911 * Note that the interconnect target module registers can be anywhere
912 * within the interconnect target module range. For example, SGX has
913 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
914 * has them at offset 0x1200 in the CPSW_WR child. Usually the
915 * the interconnect target module registers are at the beginning of
916 * the module range though.
918 static int sysc_ioremap(struct sysc *ddata)
922 if (ddata->offsets[SYSC_REVISION] < 0 &&
923 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
924 ddata->offsets[SYSC_SYSSTATUS] < 0) {
925 size = ddata->module_size;
927 size = max3(ddata->offsets[SYSC_REVISION],
928 ddata->offsets[SYSC_SYSCONFIG],
929 ddata->offsets[SYSC_SYSSTATUS]);
934 if ((size + sizeof(u32)) > ddata->module_size)
935 size = ddata->module_size;
938 ddata->module_va = devm_ioremap(ddata->dev,
941 if (!ddata->module_va)
948 * sysc_map_and_check_registers - ioremap and check device registers
949 * @ddata: device driver data
951 static int sysc_map_and_check_registers(struct sysc *ddata)
953 struct device_node *np = ddata->dev->of_node;
956 error = sysc_parse_and_check_child_range(ddata);
960 error = sysc_defer_non_critical(ddata);
964 sysc_check_children(ddata);
966 if (!of_get_property(np, "reg", NULL))
969 error = sysc_parse_registers(ddata);
973 error = sysc_ioremap(ddata);
977 error = sysc_check_registers(ddata);
985 * sysc_show_rev - read and show interconnect target module revision
986 * @bufp: buffer to print the information to
987 * @ddata: device driver data
989 static int sysc_show_rev(char *bufp, struct sysc *ddata)
993 if (ddata->offsets[SYSC_REVISION] < 0)
994 return sprintf(bufp, ":NA");
996 len = sprintf(bufp, ":%08x", ddata->revision);
1001 static int sysc_show_reg(struct sysc *ddata,
1002 char *bufp, enum sysc_registers reg)
1004 if (ddata->offsets[reg] < 0)
1005 return sprintf(bufp, ":NA");
1007 return sprintf(bufp, ":%x", ddata->offsets[reg]);
1010 static int sysc_show_name(char *bufp, struct sysc *ddata)
1015 return sprintf(bufp, ":%s", ddata->name);
1019 * sysc_show_registers - show information about interconnect target module
1020 * @ddata: device driver data
1022 static void sysc_show_registers(struct sysc *ddata)
1028 for (i = 0; i < SYSC_MAX_REGS; i++)
1029 bufp += sysc_show_reg(ddata, bufp, i);
1031 bufp += sysc_show_rev(bufp, ddata);
1032 bufp += sysc_show_name(bufp, ddata);
1034 dev_dbg(ddata->dev, "%llx:%x%s\n",
1035 ddata->module_pa, ddata->module_size,
1040 * sysc_write_sysconfig - handle sysconfig quirks for register write
1041 * @ddata: device driver data
1042 * @value: register value
1044 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
1046 if (ddata->module_unlock_quirk)
1047 ddata->module_unlock_quirk(ddata);
1049 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1051 if (ddata->module_lock_quirk)
1052 ddata->module_lock_quirk(ddata);
1055 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1056 #define SYSC_CLOCACT_ICK 2
1058 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1059 static int sysc_enable_module(struct device *dev)
1062 const struct sysc_regbits *regbits;
1063 u32 reg, idlemodes, best_mode;
1066 ddata = dev_get_drvdata(dev);
1069 * Some modules like DSS reset automatically on idle. Enable optional
1070 * reset clocks and wait for OCP softreset to complete.
1072 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1073 error = sysc_enable_opt_clocks(ddata);
1076 "Optional clocks failed for enable: %i\n",
1082 * Some modules like i2c and hdq1w have unusable reset status unless
1083 * the module reset quirk is enabled. Skip status check on enable.
1085 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1086 error = sysc_wait_softreset(ddata);
1088 dev_warn(ddata->dev, "OCP softreset timed out\n");
1090 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1091 sysc_disable_opt_clocks(ddata);
1094 * Some subsystem private interconnects, like DSS top level module,
1095 * need only the automatic OCP softreset handling with no sysconfig
1096 * register bits to configure.
1098 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1101 regbits = ddata->cap->regbits;
1102 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1105 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1106 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1107 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1109 if (regbits->clkact_shift >= 0 &&
1110 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1111 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1113 /* Set SIDLE mode */
1114 idlemodes = ddata->cfg.sidlemodes;
1115 if (!idlemodes || regbits->sidle_shift < 0)
1118 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1119 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1120 best_mode = SYSC_IDLE_NO;
1122 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1123 if (best_mode > SYSC_IDLE_MASK) {
1124 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1129 if (regbits->enwkup_shift >= 0 &&
1130 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1131 reg |= BIT(regbits->enwkup_shift);
1134 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1135 reg |= best_mode << regbits->sidle_shift;
1136 sysc_write_sysconfig(ddata, reg);
1139 /* Set MIDLE mode */
1140 idlemodes = ddata->cfg.midlemodes;
1141 if (!idlemodes || regbits->midle_shift < 0)
1144 best_mode = fls(ddata->cfg.midlemodes) - 1;
1145 if (best_mode > SYSC_IDLE_MASK) {
1146 dev_err(dev, "%s: invalid midlemode\n", __func__);
1151 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1152 best_mode = SYSC_IDLE_NO;
1154 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1155 reg |= best_mode << regbits->midle_shift;
1156 sysc_write_sysconfig(ddata, reg);
1159 /* Autoidle bit must enabled separately if available */
1160 if (regbits->autoidle_shift >= 0 &&
1161 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1162 reg |= 1 << regbits->autoidle_shift;
1163 sysc_write_sysconfig(ddata, reg);
1169 /* Save context and flush posted write */
1170 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1172 if (ddata->module_enable_quirk)
1173 ddata->module_enable_quirk(ddata);
1178 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1180 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1181 *best_mode = SYSC_IDLE_SMART_WKUP;
1182 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1183 *best_mode = SYSC_IDLE_SMART;
1184 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1185 *best_mode = SYSC_IDLE_FORCE;
1192 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1193 static int sysc_disable_module(struct device *dev)
1196 const struct sysc_regbits *regbits;
1197 u32 reg, idlemodes, best_mode;
1200 ddata = dev_get_drvdata(dev);
1201 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1204 if (ddata->module_disable_quirk)
1205 ddata->module_disable_quirk(ddata);
1207 regbits = ddata->cap->regbits;
1208 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1210 /* Set MIDLE mode */
1211 idlemodes = ddata->cfg.midlemodes;
1212 if (!idlemodes || regbits->midle_shift < 0)
1215 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1217 dev_err(dev, "%s: invalid midlemode\n", __func__);
1221 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1222 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1223 best_mode = SYSC_IDLE_FORCE;
1225 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1226 reg |= best_mode << regbits->midle_shift;
1227 sysc_write_sysconfig(ddata, reg);
1230 /* Set SIDLE mode */
1231 idlemodes = ddata->cfg.sidlemodes;
1232 if (!idlemodes || regbits->sidle_shift < 0) {
1237 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1238 best_mode = SYSC_IDLE_FORCE;
1240 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1242 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1248 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1249 reg |= best_mode << regbits->sidle_shift;
1250 if (regbits->autoidle_shift >= 0 &&
1251 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1252 reg |= 1 << regbits->autoidle_shift;
1253 sysc_write_sysconfig(ddata, reg);
1258 /* Save context and flush posted write */
1259 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1264 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1267 struct ti_sysc_platform_data *pdata;
1270 pdata = dev_get_platdata(ddata->dev);
1274 if (!pdata->idle_module)
1277 error = pdata->idle_module(dev, &ddata->cookie);
1279 dev_err(dev, "%s: could not idle: %i\n",
1282 reset_control_assert(ddata->rsts);
1287 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1290 struct ti_sysc_platform_data *pdata;
1293 pdata = dev_get_platdata(ddata->dev);
1297 if (!pdata->enable_module)
1300 error = pdata->enable_module(dev, &ddata->cookie);
1302 dev_err(dev, "%s: could not enable: %i\n",
1305 reset_control_deassert(ddata->rsts);
1310 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1315 ddata = dev_get_drvdata(dev);
1317 if (!ddata->enabled)
1320 sysc_clkdm_deny_idle(ddata);
1322 if (ddata->legacy_mode) {
1323 error = sysc_runtime_suspend_legacy(dev, ddata);
1325 goto err_allow_idle;
1327 error = sysc_disable_module(dev);
1329 goto err_allow_idle;
1332 sysc_disable_main_clocks(ddata);
1334 if (sysc_opt_clks_needed(ddata))
1335 sysc_disable_opt_clocks(ddata);
1337 ddata->enabled = false;
1340 sysc_clkdm_allow_idle(ddata);
1342 reset_control_assert(ddata->rsts);
1347 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1352 ddata = dev_get_drvdata(dev);
1358 sysc_clkdm_deny_idle(ddata);
1360 if (sysc_opt_clks_needed(ddata)) {
1361 error = sysc_enable_opt_clocks(ddata);
1363 goto err_allow_idle;
1366 error = sysc_enable_main_clocks(ddata);
1368 goto err_opt_clocks;
1370 reset_control_deassert(ddata->rsts);
1372 if (ddata->legacy_mode) {
1373 error = sysc_runtime_resume_legacy(dev, ddata);
1375 goto err_main_clocks;
1377 error = sysc_enable_module(dev);
1379 goto err_main_clocks;
1382 ddata->enabled = true;
1384 sysc_clkdm_allow_idle(ddata);
1389 sysc_disable_main_clocks(ddata);
1391 if (sysc_opt_clks_needed(ddata))
1392 sysc_disable_opt_clocks(ddata);
1394 sysc_clkdm_allow_idle(ddata);
1400 * Checks if device context was lost. Assumes the sysconfig register value
1401 * after lost context is different from the configured value. Only works for
1404 * Eventually we may want to also add support to using the context lost
1405 * registers that some SoCs have.
1407 static int sysc_check_context(struct sysc *ddata)
1411 if (!ddata->enabled)
1414 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1415 if (reg == ddata->sysconfig)
1421 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1423 struct device *dev = ddata->dev;
1426 if (ddata->enabled) {
1427 /* Nothing to do if enabled and context not lost */
1428 error = sysc_check_context(ddata);
1432 /* Disable target module if it is enabled */
1433 error = sysc_runtime_suspend(dev);
1435 dev_warn(dev, "reinit suspend failed: %i\n", error);
1438 /* Enable target module */
1439 error = sysc_runtime_resume(dev);
1441 dev_warn(dev, "reinit resume failed: %i\n", error);
1446 /* Disable target module if no leave_enabled was set */
1447 error = sysc_runtime_suspend(dev);
1449 dev_warn(dev, "reinit suspend failed: %i\n", error);
1454 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1458 ddata = dev_get_drvdata(dev);
1460 if (ddata->cfg.quirks &
1461 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1464 if (!ddata->enabled)
1467 ddata->needs_resume = 1;
1469 return sysc_runtime_suspend(dev);
1472 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1477 ddata = dev_get_drvdata(dev);
1479 if (ddata->cfg.quirks &
1480 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1483 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1484 error = sysc_reinit_module(ddata, ddata->needs_resume);
1486 dev_warn(dev, "noirq_resume failed: %i\n", error);
1487 } else if (ddata->needs_resume) {
1488 error = sysc_runtime_resume(dev);
1490 dev_warn(dev, "noirq_resume failed: %i\n", error);
1493 ddata->needs_resume = 0;
1498 static const struct dev_pm_ops sysc_pm_ops = {
1499 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1500 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1501 sysc_runtime_resume,
1505 /* Module revision register based quirks */
1506 struct sysc_revision_quirk {
1517 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1518 optrev_val, optrevmask, optquirkmask) \
1520 .name = (optname), \
1521 .base = (optbase), \
1522 .rev_offset = (optrev), \
1523 .sysc_offset = (optsysc), \
1524 .syss_offset = (optsyss), \
1525 .revision = (optrev_val), \
1526 .revision_mask = (optrevmask), \
1527 .quirks = (optquirkmask), \
1530 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1531 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1532 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1533 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1534 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1535 SYSC_QUIRK_LEGACY_IDLE),
1536 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1537 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1538 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1539 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1540 /* Uarts on omap4 and later */
1541 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1542 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1543 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1544 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1546 /* Quirks that need to be set based on the module address */
1547 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1548 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1549 SYSC_QUIRK_SWSUP_SIDLE),
1551 /* Quirks that need to be set based on detected module */
1552 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1553 SYSC_MODULE_QUIRK_AESS),
1554 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1555 SYSC_QUIRK_CLKDM_NOAUTO),
1556 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1557 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1558 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1559 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1560 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1561 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1562 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1563 SYSC_QUIRK_CLKDM_NOAUTO),
1564 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1565 SYSC_QUIRK_CLKDM_NOAUTO),
1566 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1567 SYSC_QUIRK_GPMC_DEBUG),
1568 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1569 SYSC_QUIRK_OPT_CLKS_NEEDED),
1570 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1571 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1572 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1573 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1574 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1575 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1576 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1577 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1578 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1579 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1580 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1581 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1582 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1583 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1584 SYSC_MODULE_QUIRK_SGX),
1585 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1586 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1587 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff,
1588 SYSC_QUIRK_SWSUP_SIDLE),
1589 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1590 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1591 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1592 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1593 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1594 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1595 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1596 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1597 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1598 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1599 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1600 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1601 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1602 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1603 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1604 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1605 SYSC_QUIRK_REINIT_ON_RESUME),
1606 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1607 SYSC_MODULE_QUIRK_WDT),
1608 /* PRUSS on am3, am4 and am5 */
1609 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1610 SYSC_MODULE_QUIRK_PRUSS),
1611 /* Watchdog on am3 and am4 */
1612 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1613 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1616 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1617 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1618 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1619 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1620 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1622 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1623 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1624 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1625 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1626 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1627 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1628 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1629 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1630 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1631 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1632 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1633 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1634 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1635 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1636 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1637 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
1638 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1639 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1640 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1641 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1642 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1643 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1644 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1645 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1646 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1647 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1648 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1649 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1650 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1651 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1652 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1653 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1654 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1655 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1656 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1657 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1658 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1659 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1660 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1661 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1662 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1663 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1664 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1665 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1666 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1667 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1668 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1669 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1670 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1671 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1672 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0),
1673 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0),
1674 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1675 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1676 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1677 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1678 /* Some timers on omap4 and later */
1679 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1680 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1681 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1682 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1683 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1684 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1685 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1686 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1687 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1688 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1693 * Early quirks based on module base and register offsets only that are
1694 * needed before the module revision can be read
1696 static void sysc_init_early_quirks(struct sysc *ddata)
1698 const struct sysc_revision_quirk *q;
1701 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1702 q = &sysc_revision_quirks[i];
1707 if (q->base != ddata->module_pa)
1710 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1713 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1716 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1719 ddata->name = q->name;
1720 ddata->cfg.quirks |= q->quirks;
1724 /* Quirks that also consider the revision register value */
1725 static void sysc_init_revision_quirks(struct sysc *ddata)
1727 const struct sysc_revision_quirk *q;
1730 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1731 q = &sysc_revision_quirks[i];
1733 if (q->base && q->base != ddata->module_pa)
1736 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1739 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1742 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1745 if (q->revision == ddata->revision ||
1746 (q->revision & q->revision_mask) ==
1747 (ddata->revision & q->revision_mask)) {
1748 ddata->name = q->name;
1749 ddata->cfg.quirks |= q->quirks;
1755 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1756 * enabled DSS interrupts. Eventually we may be able to do this on
1757 * dispc init rather than top-level DSS init.
1759 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1762 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1763 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1765 bool framedonetv_irq = true;
1766 u32 val, irq_mask = 0;
1768 switch (sysc_soc->soc) {
1769 case SOC_2420 ... SOC_3630:
1771 framedonetv_irq = false;
1773 case SOC_4430 ... SOC_4470:
1782 framedonetv_irq = false;
1789 /* Remap the whole module range to be able to reset dispc outputs */
1790 devm_iounmap(ddata->dev, ddata->module_va);
1791 ddata->module_va = devm_ioremap(ddata->dev,
1793 ddata->module_size);
1794 if (!ddata->module_va)
1798 val = sysc_read(ddata, dispc_offset + 0x40);
1799 lcd_en = val & lcd_en_mask;
1800 digit_en = val & digit_en_mask;
1802 irq_mask |= BIT(0); /* FRAMEDONE */
1804 if (framedonetv_irq)
1805 irq_mask |= BIT(24); /* FRAMEDONETV */
1807 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1809 if (disable & (lcd_en | digit_en))
1810 sysc_write(ddata, dispc_offset + 0x40,
1811 val & ~(lcd_en_mask | digit_en_mask));
1813 if (manager_count <= 2)
1816 /* DISPC_CONTROL2 */
1817 val = sysc_read(ddata, dispc_offset + 0x238);
1818 lcd2_en = val & lcd_en_mask;
1820 irq_mask |= BIT(22); /* FRAMEDONE2 */
1821 if (disable && lcd2_en)
1822 sysc_write(ddata, dispc_offset + 0x238,
1823 val & ~lcd_en_mask);
1825 if (manager_count <= 3)
1828 /* DISPC_CONTROL3 */
1829 val = sysc_read(ddata, dispc_offset + 0x848);
1830 lcd3_en = val & lcd_en_mask;
1832 irq_mask |= BIT(30); /* FRAMEDONE3 */
1833 if (disable && lcd3_en)
1834 sysc_write(ddata, dispc_offset + 0x848,
1835 val & ~lcd_en_mask);
1840 /* DSS needs child outputs disabled and SDI registers cleared for reset */
1841 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1843 const int dispc_offset = 0x1000;
1847 /* Get enabled outputs */
1848 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1852 /* Clear IRQSTATUS */
1853 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1855 /* Disable outputs */
1856 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1858 /* Poll IRQSTATUS */
1859 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1860 val, val != irq_mask, 100, 50);
1862 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1863 __func__, val, irq_mask);
1865 if (sysc_soc->soc == SOC_3430) {
1866 /* Clear DSS_SDI_CONTROL */
1867 sysc_write(ddata, 0x44, 0);
1869 /* Clear DSS_PLL_CONTROL */
1870 sysc_write(ddata, 0x48, 0);
1873 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1874 sysc_write(ddata, 0x40, 0);
1877 /* 1-wire needs module's internal clocks enabled for reset */
1878 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1880 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1883 val = sysc_read(ddata, offset);
1885 sysc_write(ddata, offset, val);
1888 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1889 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1891 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1893 sysc_write(ddata, offset, 1);
1896 /* I2C needs to be disabled for reset */
1897 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1902 /* I2C_CON, omap2/3 is different from omap4 and later */
1903 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1909 val = sysc_read(ddata, offset);
1914 sysc_write(ddata, offset, val);
1917 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1919 sysc_clk_quirk_i2c(ddata, false);
1922 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1924 sysc_clk_quirk_i2c(ddata, true);
1927 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1928 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1930 u32 val, kick0_val = 0, kick1_val = 0;
1931 unsigned long flags;
1935 kick0_val = 0x83e70b13;
1936 kick1_val = 0x95a4f1e0;
1939 local_irq_save(flags);
1940 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1941 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1942 !(val & BIT(0)), 100, 50);
1944 dev_warn(ddata->dev, "rtc busy timeout\n");
1945 /* Now we have ~15 microseconds to read/write various registers */
1946 sysc_write(ddata, 0x6c, kick0_val);
1947 sysc_write(ddata, 0x70, kick1_val);
1948 local_irq_restore(flags);
1951 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1953 sysc_quirk_rtc(ddata, false);
1956 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1958 sysc_quirk_rtc(ddata, true);
1961 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1962 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1964 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1965 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1967 sysc_write(ddata, offset, val);
1970 /* Watchdog timer needs a disable sequence after reset */
1971 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1973 int wps, spr, error;
1979 sysc_write(ddata, spr, 0xaaaa);
1980 error = readl_poll_timeout(ddata->module_va + wps, val,
1982 MAX_MODULE_SOFTRESET_WAIT);
1984 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1986 sysc_write(ddata, spr, 0x5555);
1987 error = readl_poll_timeout(ddata->module_va + wps, val,
1989 MAX_MODULE_SOFTRESET_WAIT);
1991 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1994 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
1995 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1999 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
2000 reg |= SYSC_PRUSS_STANDBY_INIT;
2001 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
2004 static void sysc_init_module_quirks(struct sysc *ddata)
2006 if (ddata->legacy_mode || !ddata->name)
2009 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
2010 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
2015 #ifdef CONFIG_OMAP_GPMC_DEBUG
2016 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
2017 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
2023 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
2024 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
2025 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
2030 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
2031 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
2033 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
2034 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
2036 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
2037 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
2038 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
2043 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
2044 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
2046 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
2047 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
2048 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
2051 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
2052 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
2055 static int sysc_clockdomain_init(struct sysc *ddata)
2057 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2058 struct clk *fck = NULL, *ick = NULL;
2061 if (!pdata || !pdata->init_clockdomain)
2064 switch (ddata->nr_clocks) {
2066 ick = ddata->clocks[SYSC_ICK];
2069 fck = ddata->clocks[SYSC_FCK];
2075 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
2076 if (!error || error == -ENODEV)
2083 * Note that pdata->init_module() typically does a reset first. After
2084 * pdata->init_module() is done, PM runtime can be used for the interconnect
2087 static int sysc_legacy_init(struct sysc *ddata)
2089 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2092 if (!pdata || !pdata->init_module)
2095 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2096 if (error == -EEXIST)
2103 * Note that the caller must ensure the interconnect target module is enabled
2104 * before calling reset. Otherwise reset will not complete.
2106 static int sysc_reset(struct sysc *ddata)
2108 int sysc_offset, sysc_val, error;
2111 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2113 if (ddata->legacy_mode ||
2114 ddata->cap->regbits->srst_shift < 0 ||
2115 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2118 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2120 if (ddata->pre_reset_quirk)
2121 ddata->pre_reset_quirk(ddata);
2123 if (sysc_offset >= 0) {
2124 sysc_val = sysc_read_sysconfig(ddata);
2125 sysc_val |= sysc_mask;
2126 sysc_write(ddata, sysc_offset, sysc_val);
2129 if (ddata->cfg.srst_udelay)
2130 usleep_range(ddata->cfg.srst_udelay,
2131 ddata->cfg.srst_udelay * 2);
2133 if (ddata->post_reset_quirk)
2134 ddata->post_reset_quirk(ddata);
2136 error = sysc_wait_softreset(ddata);
2138 dev_warn(ddata->dev, "OCP softreset timed out\n");
2140 if (ddata->reset_done_quirk)
2141 ddata->reset_done_quirk(ddata);
2147 * At this point the module is configured enough to read the revision but
2148 * module may not be completely configured yet to use PM runtime. Enable
2149 * all clocks directly during init to configure the quirks needed for PM
2150 * runtime based on the revision register.
2152 static int sysc_init_module(struct sysc *ddata)
2154 bool rstctrl_deasserted = false;
2157 error = sysc_clockdomain_init(ddata);
2161 sysc_clkdm_deny_idle(ddata);
2164 * Always enable clocks. The bootloader may or may not have enabled
2165 * the related clocks.
2167 error = sysc_enable_opt_clocks(ddata);
2171 error = sysc_enable_main_clocks(ddata);
2173 goto err_opt_clocks;
2175 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2176 error = reset_control_deassert(ddata->rsts);
2178 goto err_main_clocks;
2179 rstctrl_deasserted = true;
2182 ddata->revision = sysc_read_revision(ddata);
2183 sysc_init_revision_quirks(ddata);
2184 sysc_init_module_quirks(ddata);
2186 if (ddata->legacy_mode) {
2187 error = sysc_legacy_init(ddata);
2189 goto err_main_clocks;
2192 if (!ddata->legacy_mode) {
2193 error = sysc_enable_module(ddata->dev);
2195 goto err_main_clocks;
2198 error = sysc_reset(ddata);
2200 dev_err(ddata->dev, "Reset failed with %d\n", error);
2202 if (error && !ddata->legacy_mode)
2203 sysc_disable_module(ddata->dev);
2207 sysc_disable_main_clocks(ddata);
2209 /* No re-enable of clockdomain autoidle to prevent module autoidle */
2211 sysc_disable_opt_clocks(ddata);
2212 sysc_clkdm_allow_idle(ddata);
2215 if (error && rstctrl_deasserted &&
2216 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2217 reset_control_assert(ddata->rsts);
2222 static int sysc_init_sysc_mask(struct sysc *ddata)
2224 struct device_node *np = ddata->dev->of_node;
2228 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2232 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2237 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2240 struct device_node *np = ddata->dev->of_node;
2241 struct property *prop;
2245 of_property_for_each_u32(np, name, prop, p, val) {
2246 if (val >= SYSC_NR_IDLEMODES) {
2247 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2250 *idlemodes |= (1 << val);
2256 static int sysc_init_idlemodes(struct sysc *ddata)
2260 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2265 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2274 * Only some devices on omap4 and later have SYSCONFIG reset done
2275 * bit. We can detect this if there is no SYSSTATUS at all, or the
2276 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2277 * have multiple bits for the child devices like OHCI and EHCI.
2278 * Depends on SYSC being parsed first.
2280 static int sysc_init_syss_mask(struct sysc *ddata)
2282 struct device_node *np = ddata->dev->of_node;
2286 error = of_property_read_u32(np, "ti,syss-mask", &val);
2288 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2289 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2290 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2291 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2296 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2297 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2299 ddata->cfg.syss_mask = val;
2305 * Many child device drivers need to have fck and opt clocks available
2306 * to get the clock rate for device internal configuration etc.
2308 static int sysc_child_add_named_clock(struct sysc *ddata,
2309 struct device *child,
2313 struct clk_lookup *l;
2319 clk = clk_get(child, name);
2325 clk = clk_get(ddata->dev, name);
2329 l = clkdev_create(clk, name, dev_name(child));
2338 static int sysc_child_add_clocks(struct sysc *ddata,
2339 struct device *child)
2343 for (i = 0; i < ddata->nr_clocks; i++) {
2344 error = sysc_child_add_named_clock(ddata,
2346 ddata->clock_roles[i]);
2347 if (error && error != -EEXIST) {
2348 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2349 ddata->clock_roles[i], error);
2358 static struct device_type sysc_device_type = {
2361 static struct sysc *sysc_child_to_parent(struct device *dev)
2363 struct device *parent = dev->parent;
2365 if (!parent || parent->type != &sysc_device_type)
2368 return dev_get_drvdata(parent);
2371 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2376 ddata = sysc_child_to_parent(dev);
2378 error = pm_generic_runtime_suspend(dev);
2382 if (!ddata->enabled)
2385 return sysc_runtime_suspend(ddata->dev);
2388 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2393 ddata = sysc_child_to_parent(dev);
2395 if (!ddata->enabled) {
2396 error = sysc_runtime_resume(ddata->dev);
2399 "%s error: %i\n", __func__, error);
2402 return pm_generic_runtime_resume(dev);
2405 #ifdef CONFIG_PM_SLEEP
2406 static int sysc_child_suspend_noirq(struct device *dev)
2411 ddata = sysc_child_to_parent(dev);
2413 dev_dbg(ddata->dev, "%s %s\n", __func__,
2414 ddata->name ? ddata->name : "");
2416 error = pm_generic_suspend_noirq(dev);
2418 dev_err(dev, "%s error at %i: %i\n",
2419 __func__, __LINE__, error);
2424 if (!pm_runtime_status_suspended(dev)) {
2425 error = pm_generic_runtime_suspend(dev);
2427 dev_dbg(dev, "%s busy at %i: %i\n",
2428 __func__, __LINE__, error);
2433 error = sysc_runtime_suspend(ddata->dev);
2435 dev_err(dev, "%s error at %i: %i\n",
2436 __func__, __LINE__, error);
2441 ddata->child_needs_resume = true;
2447 static int sysc_child_resume_noirq(struct device *dev)
2452 ddata = sysc_child_to_parent(dev);
2454 dev_dbg(ddata->dev, "%s %s\n", __func__,
2455 ddata->name ? ddata->name : "");
2457 if (ddata->child_needs_resume) {
2458 ddata->child_needs_resume = false;
2460 error = sysc_runtime_resume(ddata->dev);
2463 "%s runtime resume error: %i\n",
2466 error = pm_generic_runtime_resume(dev);
2469 "%s generic runtime resume: %i\n",
2473 return pm_generic_resume_noirq(dev);
2477 static struct dev_pm_domain sysc_child_pm_domain = {
2479 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2480 sysc_child_runtime_resume,
2482 USE_PLATFORM_PM_SLEEP_OPS
2483 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2484 sysc_child_resume_noirq)
2488 /* Caller needs to take list_lock if ever used outside of cpu_pm */
2489 static void sysc_reinit_modules(struct sysc_soc_info *soc)
2491 struct sysc_module *module;
2492 struct list_head *pos;
2496 list_for_each(pos, &sysc_soc->restored_modules) {
2497 module = list_entry(pos, struct sysc_module, node);
2498 ddata = module->ddata;
2499 error = sysc_reinit_module(ddata, ddata->enabled);
2504 * sysc_context_notifier - optionally reset and restore module after idle
2505 * @nb: notifier block
2509 * Some interconnect target modules need to be restored, or reset and restored
2510 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
2511 * OTG and GPMC target modules even if the modules are unused.
2513 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
2516 struct sysc_soc_info *soc;
2518 soc = container_of(nb, struct sysc_soc_info, nb);
2521 case CPU_CLUSTER_PM_ENTER:
2523 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2525 case CPU_CLUSTER_PM_EXIT:
2526 sysc_reinit_modules(soc);
2534 * sysc_add_restored - optionally add reset and restore quirk hanlling
2535 * @ddata: device data
2537 static void sysc_add_restored(struct sysc *ddata)
2539 struct sysc_module *restored_module;
2541 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
2542 if (!restored_module)
2545 restored_module->ddata = ddata;
2547 mutex_lock(&sysc_soc->list_lock);
2549 list_add(&restored_module->node, &sysc_soc->restored_modules);
2551 if (sysc_soc->nb.notifier_call)
2554 sysc_soc->nb.notifier_call = sysc_context_notifier;
2555 cpu_pm_register_notifier(&sysc_soc->nb);
2558 mutex_unlock(&sysc_soc->list_lock);
2562 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2563 * @ddata: device driver data
2564 * @child: child device driver
2566 * Allow idle for child devices as done with _od_runtime_suspend().
2567 * Otherwise many child devices will not idle because of the permanent
2568 * parent usecount set in pm_runtime_irq_safe().
2570 * Note that the long term solution is to just modify the child device
2571 * drivers to not set pm_runtime_irq_safe() and then this can be just
2574 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2576 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2577 dev_pm_domain_set(child, &sysc_child_pm_domain);
2580 static int sysc_notifier_call(struct notifier_block *nb,
2581 unsigned long event, void *device)
2583 struct device *dev = device;
2587 ddata = sysc_child_to_parent(dev);
2592 case BUS_NOTIFY_ADD_DEVICE:
2593 error = sysc_child_add_clocks(ddata, dev);
2596 sysc_legacy_idle_quirk(ddata, dev);
2605 static struct notifier_block sysc_nb = {
2606 .notifier_call = sysc_notifier_call,
2609 /* Device tree configured quirks */
2610 struct sysc_dts_quirk {
2615 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2616 { .name = "ti,no-idle-on-init",
2617 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2618 { .name = "ti,no-reset-on-init",
2619 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2620 { .name = "ti,no-idle",
2621 .mask = SYSC_QUIRK_NO_IDLE, },
2624 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2627 const struct property *prop;
2630 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2631 const char *name = sysc_dts_quirks[i].name;
2633 prop = of_get_property(np, name, &len);
2637 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2639 dev_warn(ddata->dev,
2640 "dts flag should be at module level for %s\n",
2646 static int sysc_init_dts_quirks(struct sysc *ddata)
2648 struct device_node *np = ddata->dev->of_node;
2652 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2654 sysc_parse_dts_quirks(ddata, np, false);
2655 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2658 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2662 ddata->cfg.srst_udelay = (u8)val;
2668 static void sysc_unprepare(struct sysc *ddata)
2675 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2676 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2677 clk_unprepare(ddata->clocks[i]);
2682 * Common sysc register bits found on omap2, also known as type1
2684 static const struct sysc_regbits sysc_regbits_omap2 = {
2685 .dmadisable_shift = -ENODEV,
2692 .autoidle_shift = 0,
2695 static const struct sysc_capabilities sysc_omap2 = {
2696 .type = TI_SYSC_OMAP2,
2697 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2698 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2699 SYSC_OMAP2_AUTOIDLE,
2700 .regbits = &sysc_regbits_omap2,
2703 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2704 static const struct sysc_capabilities sysc_omap2_timer = {
2705 .type = TI_SYSC_OMAP2_TIMER,
2706 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2707 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2708 SYSC_OMAP2_AUTOIDLE,
2709 .regbits = &sysc_regbits_omap2,
2710 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2714 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2715 * with different sidle position
2717 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2718 .dmadisable_shift = -ENODEV,
2719 .midle_shift = -ENODEV,
2721 .clkact_shift = -ENODEV,
2722 .enwkup_shift = -ENODEV,
2724 .autoidle_shift = 0,
2725 .emufree_shift = -ENODEV,
2728 static const struct sysc_capabilities sysc_omap3_sham = {
2729 .type = TI_SYSC_OMAP3_SHAM,
2730 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2731 .regbits = &sysc_regbits_omap3_sham,
2735 * AES register bits found on omap3 and later, a variant of
2736 * sysc_regbits_omap2 with different sidle position
2738 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2739 .dmadisable_shift = -ENODEV,
2740 .midle_shift = -ENODEV,
2742 .clkact_shift = -ENODEV,
2743 .enwkup_shift = -ENODEV,
2745 .autoidle_shift = 0,
2746 .emufree_shift = -ENODEV,
2749 static const struct sysc_capabilities sysc_omap3_aes = {
2750 .type = TI_SYSC_OMAP3_AES,
2751 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2752 .regbits = &sysc_regbits_omap3_aes,
2756 * Common sysc register bits found on omap4, also known as type2
2758 static const struct sysc_regbits sysc_regbits_omap4 = {
2759 .dmadisable_shift = 16,
2762 .clkact_shift = -ENODEV,
2763 .enwkup_shift = -ENODEV,
2766 .autoidle_shift = -ENODEV,
2769 static const struct sysc_capabilities sysc_omap4 = {
2770 .type = TI_SYSC_OMAP4,
2771 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2772 SYSC_OMAP4_SOFTRESET,
2773 .regbits = &sysc_regbits_omap4,
2776 static const struct sysc_capabilities sysc_omap4_timer = {
2777 .type = TI_SYSC_OMAP4_TIMER,
2778 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2779 SYSC_OMAP4_SOFTRESET,
2780 .regbits = &sysc_regbits_omap4,
2784 * Common sysc register bits found on omap4, also known as type3
2786 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2787 .dmadisable_shift = -ENODEV,
2790 .clkact_shift = -ENODEV,
2791 .enwkup_shift = -ENODEV,
2792 .srst_shift = -ENODEV,
2793 .emufree_shift = -ENODEV,
2794 .autoidle_shift = -ENODEV,
2797 static const struct sysc_capabilities sysc_omap4_simple = {
2798 .type = TI_SYSC_OMAP4_SIMPLE,
2799 .regbits = &sysc_regbits_omap4_simple,
2803 * SmartReflex sysc found on omap34xx
2805 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2806 .dmadisable_shift = -ENODEV,
2807 .midle_shift = -ENODEV,
2808 .sidle_shift = -ENODEV,
2810 .enwkup_shift = -ENODEV,
2811 .srst_shift = -ENODEV,
2812 .emufree_shift = -ENODEV,
2813 .autoidle_shift = -ENODEV,
2816 static const struct sysc_capabilities sysc_34xx_sr = {
2817 .type = TI_SYSC_OMAP34XX_SR,
2818 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2819 .regbits = &sysc_regbits_omap34xx_sr,
2820 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2821 SYSC_QUIRK_LEGACY_IDLE,
2825 * SmartReflex sysc found on omap36xx and later
2827 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2828 .dmadisable_shift = -ENODEV,
2829 .midle_shift = -ENODEV,
2831 .clkact_shift = -ENODEV,
2833 .srst_shift = -ENODEV,
2834 .emufree_shift = -ENODEV,
2835 .autoidle_shift = -ENODEV,
2838 static const struct sysc_capabilities sysc_36xx_sr = {
2839 .type = TI_SYSC_OMAP36XX_SR,
2840 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2841 .regbits = &sysc_regbits_omap36xx_sr,
2842 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2845 static const struct sysc_capabilities sysc_omap4_sr = {
2846 .type = TI_SYSC_OMAP4_SR,
2847 .regbits = &sysc_regbits_omap36xx_sr,
2848 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2852 * McASP register bits found on omap4 and later
2854 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2855 .dmadisable_shift = -ENODEV,
2856 .midle_shift = -ENODEV,
2858 .clkact_shift = -ENODEV,
2859 .enwkup_shift = -ENODEV,
2860 .srst_shift = -ENODEV,
2861 .emufree_shift = -ENODEV,
2862 .autoidle_shift = -ENODEV,
2865 static const struct sysc_capabilities sysc_omap4_mcasp = {
2866 .type = TI_SYSC_OMAP4_MCASP,
2867 .regbits = &sysc_regbits_omap4_mcasp,
2868 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2872 * McASP found on dra7 and later
2874 static const struct sysc_capabilities sysc_dra7_mcasp = {
2875 .type = TI_SYSC_OMAP4_SIMPLE,
2876 .regbits = &sysc_regbits_omap4_simple,
2877 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2881 * FS USB host found on omap4 and later
2883 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2884 .dmadisable_shift = -ENODEV,
2885 .midle_shift = -ENODEV,
2887 .clkact_shift = -ENODEV,
2889 .srst_shift = -ENODEV,
2890 .emufree_shift = -ENODEV,
2891 .autoidle_shift = -ENODEV,
2894 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2895 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2896 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2897 .regbits = &sysc_regbits_omap4_usb_host_fs,
2900 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2901 .dmadisable_shift = -ENODEV,
2902 .midle_shift = -ENODEV,
2903 .sidle_shift = -ENODEV,
2904 .clkact_shift = -ENODEV,
2907 .emufree_shift = -ENODEV,
2908 .autoidle_shift = -ENODEV,
2911 static const struct sysc_capabilities sysc_dra7_mcan = {
2912 .type = TI_SYSC_DRA7_MCAN,
2913 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2914 .regbits = &sysc_regbits_dra7_mcan,
2915 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2919 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2921 static const struct sysc_capabilities sysc_pruss = {
2922 .type = TI_SYSC_PRUSS,
2923 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2924 .regbits = &sysc_regbits_omap4_simple,
2925 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2928 static int sysc_init_pdata(struct sysc *ddata)
2930 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2931 struct ti_sysc_module_data *mdata;
2936 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2940 if (ddata->legacy_mode) {
2941 mdata->name = ddata->legacy_mode;
2942 mdata->module_pa = ddata->module_pa;
2943 mdata->module_size = ddata->module_size;
2944 mdata->offsets = ddata->offsets;
2945 mdata->nr_offsets = SYSC_MAX_REGS;
2946 mdata->cap = ddata->cap;
2947 mdata->cfg = &ddata->cfg;
2950 ddata->mdata = mdata;
2955 static int sysc_init_match(struct sysc *ddata)
2957 const struct sysc_capabilities *cap;
2959 cap = of_device_get_match_data(ddata->dev);
2965 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2970 static void ti_sysc_idle(struct work_struct *work)
2974 ddata = container_of(work, struct sysc, idle_work.work);
2977 * One time decrement of clock usage counts if left on from init.
2978 * Note that we disable opt clocks unconditionally in this case
2979 * as they are enabled unconditionally during init without
2980 * considering sysc_opt_clks_needed() at that point.
2982 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2983 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2984 sysc_disable_main_clocks(ddata);
2985 sysc_disable_opt_clocks(ddata);
2986 sysc_clkdm_allow_idle(ddata);
2989 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2990 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2994 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2995 * and SYSC_QUIRK_NO_RESET_ON_INIT
2997 if (pm_runtime_active(ddata->dev))
2998 pm_runtime_put_sync(ddata->dev);
3002 * SoC model and features detection. Only needed for SoCs that need
3003 * special handling for quirks, no need to list others.
3005 static const struct soc_device_attribute sysc_soc_match[] = {
3006 SOC_FLAG("OMAP242*", SOC_2420),
3007 SOC_FLAG("OMAP243*", SOC_2430),
3008 SOC_FLAG("OMAP3[45]*", SOC_3430),
3009 SOC_FLAG("OMAP3[67]*", SOC_3630),
3010 SOC_FLAG("OMAP443*", SOC_4430),
3011 SOC_FLAG("OMAP446*", SOC_4460),
3012 SOC_FLAG("OMAP447*", SOC_4470),
3013 SOC_FLAG("OMAP54*", SOC_5430),
3014 SOC_FLAG("AM433", SOC_AM3),
3015 SOC_FLAG("AM43*", SOC_AM4),
3016 SOC_FLAG("DRA7*", SOC_DRA7),
3022 * List of SoCs variants with disabled features. By default we assume all
3023 * devices in the device tree are available so no need to list those SoCs.
3025 static const struct soc_device_attribute sysc_soc_feat_match[] = {
3026 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
3027 SOC_FLAG("AM3505", DIS_SGX),
3028 SOC_FLAG("OMAP3525", DIS_SGX),
3029 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
3030 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
3032 /* OMAP3630/DM3730 variants with some accelerators disabled */
3033 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
3034 SOC_FLAG("DM3725", DIS_SGX),
3035 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
3036 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
3037 SOC_FLAG("OMAP3621", DIS_ISP),
3042 static int sysc_add_disabled(unsigned long base)
3044 struct sysc_address *disabled_module;
3046 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
3047 if (!disabled_module)
3050 disabled_module->base = base;
3052 mutex_lock(&sysc_soc->list_lock);
3053 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
3054 mutex_unlock(&sysc_soc->list_lock);
3060 * One time init to detect the booted SoC, disable unavailable features
3061 * and initialize list for optional cpu_pm notifier.
3063 * Note that we initialize static data shared across all ti-sysc instances
3064 * so ddata is only used for SoC type. This can be called from module_init
3065 * once we no longer need to rely on platform data.
3067 static int sysc_init_static_data(struct sysc *ddata)
3069 const struct soc_device_attribute *match;
3070 struct ti_sysc_platform_data *pdata;
3071 unsigned long features = 0;
3072 struct device_node *np;
3077 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
3081 mutex_init(&sysc_soc->list_lock);
3082 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
3083 INIT_LIST_HEAD(&sysc_soc->restored_modules);
3084 sysc_soc->general_purpose = true;
3086 pdata = dev_get_platdata(ddata->dev);
3087 if (pdata && pdata->soc_type_gp)
3088 sysc_soc->general_purpose = pdata->soc_type_gp();
3090 match = soc_device_match(sysc_soc_match);
3091 if (match && match->data)
3092 sysc_soc->soc = (int)match->data;
3095 * Check and warn about possible old incomplete dtb. We now want to see
3096 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
3098 switch (sysc_soc->soc) {
3101 case SOC_4430 ... SOC_4470:
3104 np = of_find_node_by_path("/ocp");
3105 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
3106 "ti-sysc: Incomplete old dtb, please update\n");
3112 /* Ignore devices that are not available on HS and EMU SoCs */
3113 if (!sysc_soc->general_purpose) {
3114 switch (sysc_soc->soc) {
3115 case SOC_3430 ... SOC_3630:
3116 sysc_add_disabled(0x48304000); /* timer12 */
3119 sysc_add_disabled(0x48310000); /* rng */
3125 match = soc_device_match(sysc_soc_feat_match);
3130 features = (unsigned long)match->data;
3133 * Add disabled devices to the list based on the module base.
3134 * Note that this must be done before we attempt to access the
3135 * device and have module revision checks working.
3137 if (features & DIS_ISP)
3138 sysc_add_disabled(0x480bd400);
3139 if (features & DIS_IVA)
3140 sysc_add_disabled(0x5d000000);
3141 if (features & DIS_SGX)
3142 sysc_add_disabled(0x50000000);
3147 static void sysc_cleanup_static_data(void)
3149 struct sysc_module *restored_module;
3150 struct sysc_address *disabled_module;
3151 struct list_head *pos, *tmp;
3156 if (sysc_soc->nb.notifier_call)
3157 cpu_pm_unregister_notifier(&sysc_soc->nb);
3159 mutex_lock(&sysc_soc->list_lock);
3160 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
3161 restored_module = list_entry(pos, struct sysc_module, node);
3163 kfree(restored_module);
3165 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
3166 disabled_module = list_entry(pos, struct sysc_address, node);
3168 kfree(disabled_module);
3170 mutex_unlock(&sysc_soc->list_lock);
3173 static int sysc_check_disabled_devices(struct sysc *ddata)
3175 struct sysc_address *disabled_module;
3176 struct list_head *pos;
3179 mutex_lock(&sysc_soc->list_lock);
3180 list_for_each(pos, &sysc_soc->disabled_modules) {
3181 disabled_module = list_entry(pos, struct sysc_address, node);
3182 if (ddata->module_pa == disabled_module->base) {
3183 dev_dbg(ddata->dev, "module disabled for this SoC\n");
3188 mutex_unlock(&sysc_soc->list_lock);
3194 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
3195 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3196 * are needed, we could also look at the timer register configuration.
3198 static int sysc_check_active_timer(struct sysc *ddata)
3200 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3201 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3204 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3205 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3211 static const struct of_device_id sysc_match_table[] = {
3212 { .compatible = "simple-bus", },
3216 static int sysc_probe(struct platform_device *pdev)
3218 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3222 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3226 ddata->offsets[SYSC_REVISION] = -ENODEV;
3227 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3228 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
3229 ddata->dev = &pdev->dev;
3230 platform_set_drvdata(pdev, ddata);
3232 error = sysc_init_static_data(ddata);
3236 error = sysc_init_match(ddata);
3240 error = sysc_init_dts_quirks(ddata);
3244 error = sysc_map_and_check_registers(ddata);
3248 error = sysc_init_sysc_mask(ddata);
3252 error = sysc_init_idlemodes(ddata);
3256 error = sysc_init_syss_mask(ddata);
3260 error = sysc_init_pdata(ddata);
3264 sysc_init_early_quirks(ddata);
3266 error = sysc_check_disabled_devices(ddata);
3270 error = sysc_check_active_timer(ddata);
3271 if (error == -ENXIO)
3272 ddata->reserved = true;
3276 error = sysc_get_clocks(ddata);
3280 error = sysc_init_resets(ddata);
3284 error = sysc_init_module(ddata);
3288 pm_runtime_enable(ddata->dev);
3289 error = pm_runtime_resume_and_get(ddata->dev);
3291 pm_runtime_disable(ddata->dev);
3295 /* Balance use counts as PM runtime should have enabled these all */
3296 if (!(ddata->cfg.quirks &
3297 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3298 sysc_disable_main_clocks(ddata);
3299 sysc_disable_opt_clocks(ddata);
3300 sysc_clkdm_allow_idle(ddata);
3303 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3304 reset_control_assert(ddata->rsts);
3306 sysc_show_registers(ddata);
3308 ddata->dev->type = &sysc_device_type;
3310 if (!ddata->reserved) {
3311 error = of_platform_populate(ddata->dev->of_node,
3313 pdata ? pdata->auxdata : NULL,
3319 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3321 /* At least earlycon won't survive without deferred idle */
3322 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3323 SYSC_QUIRK_NO_IDLE_ON_INIT |
3324 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3325 schedule_delayed_work(&ddata->idle_work, 3000);
3327 pm_runtime_put(&pdev->dev);
3330 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
3331 sysc_add_restored(ddata);
3336 pm_runtime_put_sync(&pdev->dev);
3337 pm_runtime_disable(&pdev->dev);
3339 sysc_unprepare(ddata);
3344 static int sysc_remove(struct platform_device *pdev)
3346 struct sysc *ddata = platform_get_drvdata(pdev);
3349 cancel_delayed_work_sync(&ddata->idle_work);
3351 error = pm_runtime_resume_and_get(ddata->dev);
3353 pm_runtime_disable(ddata->dev);
3357 of_platform_depopulate(&pdev->dev);
3359 pm_runtime_put_sync(&pdev->dev);
3360 pm_runtime_disable(&pdev->dev);
3362 if (!reset_control_status(ddata->rsts))
3363 reset_control_assert(ddata->rsts);
3366 sysc_unprepare(ddata);
3371 static const struct of_device_id sysc_match[] = {
3372 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3373 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3374 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3375 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3376 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3377 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3378 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3379 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3380 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3381 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3382 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3383 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3384 { .compatible = "ti,sysc-usb-host-fs",
3385 .data = &sysc_omap4_usb_host_fs, },
3386 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3387 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3390 MODULE_DEVICE_TABLE(of, sysc_match);
3392 static struct platform_driver sysc_driver = {
3393 .probe = sysc_probe,
3394 .remove = sysc_remove,
3397 .of_match_table = sysc_match,
3402 static int __init sysc_init(void)
3404 bus_register_notifier(&platform_bus_type, &sysc_nb);
3406 return platform_driver_register(&sysc_driver);
3408 module_init(sysc_init);
3410 static void __exit sysc_exit(void)
3412 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3413 platform_driver_unregister(&sysc_driver);
3414 sysc_cleanup_static_data();
3416 module_exit(sysc_exit);
3418 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3419 MODULE_LICENSE("GPL v2");