1 /******************************************************************************
2 Device driver for Interphase ATM PCI adapter cards
3 Author: Peter Wang <pwang@iphase.com>
4 Interphase Corporation <www.iphase.com>
6 iphase.h: This is the header file for iphase.c.
7 *******************************************************************************
9 This software may be used and distributed according to the terms
10 of the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on this skeleton fall under the GPL and must retain
12 the authorship (implicit copyright) notice.
14 This program is distributed in the hope that it will be useful, but
15 WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 General Public License for more details.
19 Modified from an incomplete driver for Interphase 5575 1KVC 1M card which
20 was originally written by Monalisa Agrawal at UNH. Now this driver
21 supports a variety of varients of Interphase ATM PCI (i)Chip adapter
22 card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM)
23 in terms of PHY type, the size of control memory and the size of
24 packet memory. The following are the change log and history:
26 Bugfix the Mona's UBR driver.
27 Modify the basic memory allocation and dma logic.
28 Port the driver to the latest kernel from 2.0.46.
29 Complete the ABR logic of the driver, and added the ABR work-
30 around for the hardware anormalies.
32 Add the flow control logic to the driver to allow rate-limit VC.
33 Add 4K VC support to the board with 512K control memory.
34 Add the support of all the variants of the Interphase ATM PCI
35 (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
36 (25M UTP25) and x531 (DS3 and E3).
39 Support and updates available at: ftp://ftp.iphase.com/pub/atm
41 *******************************************************************************/
47 /************************ IADBG DEFINE *********************************/
48 /* IADebugFlag Bit Map */
49 #define IF_IADBG_INIT_ADAPTER 0x00000001 // init adapter info
50 #define IF_IADBG_TX 0x00000002 // debug TX
51 #define IF_IADBG_RX 0x00000004 // debug RX
52 #define IF_IADBG_QUERY_INFO 0x00000008 // debug Request call
53 #define IF_IADBG_SHUTDOWN 0x00000010 // debug shutdown event
54 #define IF_IADBG_INTR 0x00000020 // debug interrupt DPC
55 #define IF_IADBG_TXPKT 0x00000040 // debug TX PKT
56 #define IF_IADBG_RXPKT 0x00000080 // debug RX PKT
57 #define IF_IADBG_ERR 0x00000100 // debug system error
58 #define IF_IADBG_EVENT 0x00000200 // debug event
59 #define IF_IADBG_DIS_INTR 0x00001000 // debug disable interrupt
60 #define IF_IADBG_EN_INTR 0x00002000 // debug enable interrupt
61 #define IF_IADBG_LOUD 0x00004000 // debugging info
62 #define IF_IADBG_VERY_LOUD 0x00008000 // excessive debugging info
63 #define IF_IADBG_CBR 0x00100000 //
64 #define IF_IADBG_UBR 0x00200000 //
65 #define IF_IADBG_ABR 0x00400000 //
66 #define IF_IADBG_DESC 0x01000000 //
67 #define IF_IADBG_SUNI_STAT 0x02000000 // suni statistics
68 #define IF_IADBG_RESET 0x04000000
70 #define IF_IADBG(f) if (IADebugFlag & (f))
72 #ifdef CONFIG_ATM_IA_DEBUG /* Debug build */
74 #define IF_LOUD(A) IF_IADBG(IF_IADBG_LOUD) { A }
75 #define IF_ERR(A) IF_IADBG(IF_IADBG_ERR) { A }
76 #define IF_VERY_LOUD(A) IF_IADBG( IF_IADBG_VERY_LOUD ) { A }
78 #define IF_INIT_ADAPTER(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
79 #define IF_INIT(A) IF_IADBG( IF_IADBG_INIT_ADAPTER ) { A }
80 #define IF_SUNI_STAT(A) IF_IADBG( IF_IADBG_SUNI_STAT ) { A }
81 #define IF_QUERY_INFO(A) IF_IADBG( IF_IADBG_QUERY_INFO ) { A }
82 #define IF_COPY_OVER(A) IF_IADBG( IF_IADBG_COPY_OVER ) { A }
84 #define IF_INTR(A) IF_IADBG( IF_IADBG_INTR ) { A }
85 #define IF_DIS_INTR(A) IF_IADBG( IF_IADBG_DIS_INTR ) { A }
86 #define IF_EN_INTR(A) IF_IADBG( IF_IADBG_EN_INTR ) { A }
88 #define IF_TX(A) IF_IADBG( IF_IADBG_TX ) { A }
89 #define IF_RX(A) IF_IADBG( IF_IADBG_RX ) { A }
90 #define IF_TXPKT(A) IF_IADBG( IF_IADBG_TXPKT ) { A }
91 #define IF_RXPKT(A) IF_IADBG( IF_IADBG_RXPKT ) { A }
93 #define IF_SHUTDOWN(A) IF_IADBG(IF_IADBG_SHUTDOWN) { A }
94 #define IF_CBR(A) IF_IADBG( IF_IADBG_CBR ) { A }
95 #define IF_UBR(A) IF_IADBG( IF_IADBG_UBR ) { A }
96 #define IF_ABR(A) IF_IADBG( IF_IADBG_ABR ) { A }
97 #define IF_EVENT(A) IF_IADBG( IF_IADBG_EVENT) { A }
99 #else /* free build */
101 #define IF_VERY_LOUD(A)
102 #define IF_INIT_ADAPTER(A)
104 #define IF_SUNI_STAT(A)
105 #define IF_PVC_CHKPKT(A)
106 #define IF_QUERY_INFO(A)
107 #define IF_COPY_OVER(A)
110 #define IF_DIS_INTR(A)
111 #define IF_EN_INTR(A)
114 #define IF_TXDEBUG(A)
120 #define IF_SHUTDOWN(A)
125 #endif /* CONFIG_ATM_IA_DEBUG */
127 #define ATM_DESC(skb) (skb->protocol)
128 #define IA_SKB_STATE(skb) (skb->protocol)
133 #define IA_CMD 0x7749
141 } IA_CMDBUF, *PIA_CMDBUF;
147 #define MEMDUMP_SEGREG 0x2
148 #define MEMDUMP_DEV 0x1
149 #define MEMDUMP_REASSREG 0x3
150 #define MEMDUMP_FFL 0x4
152 #define WAKE_DBG_WAIT 0x6
154 /************************ IADBG DEFINE END ***************************/
156 #define Boolean(x) ((x) ? 1 : 0)
157 #define NR_VCI 1024 /* number of VCIs */
158 #define NR_VCI_LD 10 /* log2(NR_VCI) */
159 #define NR_VCI_4K 4096 /* number of VCIs */
160 #define NR_VCI_4K_LD 12 /* log2(NR_VCI) */
161 #define MEM_VALID 0xfffffff0 /* mask base address with this */
163 #ifndef PCI_VENDOR_ID_IPHASE
164 #define PCI_VENDOR_ID_IPHASE 0x107e
166 #ifndef PCI_DEVICE_ID_IPHASE_5575
167 #define PCI_DEVICE_ID_IPHASE_5575 0x0008
169 #define DEV_LABEL "ia"
177 #define NRMCODE 5 /* 0 - 7 */
178 #define TRMCODE 3 /* 0 - 7 */
180 #define ATDFCODE 2 /* 0 - 15 */
182 /*---------------------- Packet/Cell Memory ------------------------*/
183 #define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */
184 #define DFL_TX_BUF_SZ 10240 /* 10 K buffers */
185 #define DFL_TX_BUFFERS 50 /* number of packet buffers for Tx
186 - descriptor 0 unused */
187 #define REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */
188 #define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */
189 #define DFL_RX_BUF_SZ 10240 /* 10k buffers */
190 #define DFL_RX_BUFFERS 50 /* number of packet buffers for Rx
191 - descriptor 0 unused */
200 struct cpcs_trailer_desc
202 struct cpcs_trailer *cpcs;
214 struct sk_buff_head txing_skb;
226 u_int req_rm_cell_data1;
227 u_int req_rm_cell_data2;
228 u_int add_rm_cell_data1;
229 u_int add_rm_cell_data2;
232 /* 32 byte entries */
242 u_short rm_timestamp_hi;
243 u_short rm_timestamp_lo:8,
245 u_short remainder; /* ABR and UBR fields - last 10 bits*/
246 u_short next_vc_sched;
247 u_short present_desc; /* all classes */
248 u_short last_cell_slot; /* ABR and UBR */
256 status:8; /* all classes */
258 #define CRC_APPEND 0x40 /* for status field - CRC-32 append */
259 #define ABR_STATE 0x02
270 u_short out_of_rate_link; /* reserved for UBR and CBR */
274 #define DLE_ENTRIES 256
275 #define DMA_INT_ENABLE 0x0002 /* use for both Tx and Rx */
276 #define TX_DLE_PSI 0x0001
277 #define DLE_TOTAL_SIZE (sizeof(struct dle)*DLE_ENTRIES)
279 /* Descriptor List Entries (DLE) */
299 int desc; /* Descriptor number */
300 struct free_desc_q *next;
304 unsigned short desc_mode;
305 unsigned short vc_index;
306 unsigned short res1; /* reserved field */
307 unsigned short bytes;
308 unsigned short buf_start_hi;
309 unsigned short buf_start_lo;
310 unsigned short res2[10]; /* reserved field */
315 unsigned short desc_mode;
316 unsigned short vc_index;
318 unsigned short bytes;
319 unsigned short buf_start_hi;
320 unsigned short buf_start_lo;
321 unsigned short dma_start_hi;
322 unsigned short dma_start_lo;
323 unsigned short crc_upper;
324 unsigned short crc_lower;
325 unsigned short res:8, timeout:8;
326 unsigned short res2[5]; /* reserved field */
329 /*--------SAR stuff ---------------------*/
331 #define EPROM_SIZE 0x40000 /* says 64K in the docs ??? */
335 /*------------ PCI Memory Space Map, 128K SAR memory ----------------*/
336 #define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000
337 #define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */
338 #define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000
339 #define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000
340 #define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000
341 #define IPHASE5575_FRONT_END_REG_BASE IPHASE5575_DMA_CONTROL_REG_BASE
342 #define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000
343 #define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000
345 /*------------ Bus interface control registers -----------------*/
346 #define IPHASE5575_BUS_CONTROL_REG 0x00
347 #define IPHASE5575_BUS_STATUS_REG 0x01 /* actual offset 0x04 */
348 #define IPHASE5575_MAC1 0x02
349 #define IPHASE5575_REV 0x03
350 #define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/
351 #define IPHASE5575_EXT_RESET 0x04
352 #define IPHASE5575_INT_RESET 0x05 /* addr 1c ?? reg 0x06 */
353 #define IPHASE5575_PCI_ADDR_PAGE 0x07 /* reg 0x08, 0x09 ?? */
354 #define IPHASE5575_EEPROM_ACCESS 0x0a /* actual offset 0x28 */
355 #define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b
356 #define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c
357 #define IPHASE5575_CELL_FIFO_READ_PTR 0x0d
358 #define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e
359 #define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f /* actual offset 0x3c */
361 /* Bus Interface Control Register bits */
362 #define CTRL_FE_RST 0x80000000
363 #define CTRL_LED 0x40000000
364 #define CTRL_25MBPHY 0x10000000
365 #define CTRL_ENCMBMEM 0x08000000
366 #define CTRL_ENOFFSEG 0x01000000
367 #define CTRL_ERRMASK 0x00400000
368 #define CTRL_DLETMASK 0x00100000
369 #define CTRL_DLERMASK 0x00080000
370 #define CTRL_FEMASK 0x00040000
371 #define CTRL_SEGMASK 0x00020000
372 #define CTRL_REASSMASK 0x00010000
373 #define CTRL_CSPREEMPT 0x00002000
374 #define CTRL_B128 0x00000200
375 #define CTRL_B64 0x00000100
376 #define CTRL_B48 0x00000080
377 #define CTRL_B32 0x00000040
378 #define CTRL_B16 0x00000020
379 #define CTRL_B8 0x00000010
381 /* Bus Interface Status Register bits */
382 #define STAT_CMEMSIZ 0xc0000000
383 #define STAT_ADPARCK 0x20000000
384 #define STAT_RESVD 0x1fffff80
385 #define STAT_ERRINT 0x00000040
386 #define STAT_MARKINT 0x00000020
387 #define STAT_DLETINT 0x00000010
388 #define STAT_DLERINT 0x00000008
389 #define STAT_FEINT 0x00000004
390 #define STAT_SEGINT 0x00000002
391 #define STAT_REASSINT 0x00000001
394 /*--------------- Segmentation control registers -----------------*/
395 /* The segmentation registers are 16 bits access and the addresses
396 are defined as such so the addresses are the actual "offsets" */
397 #define IDLEHEADHI 0x00
398 #define IDLEHEADLO 0x01
400 /* Values for MAXRATE register for 155Mbps and 25.6 Mbps operation */
401 #define RATE155 0x64b1 // 16 bits float format
402 #define MAX_ATM_155 352768 // Cells/second p.118
403 #define RATE25 0x5f9d
406 #define STPARMS_1K 0x008c
407 #define STPARMS_2K 0x0049
408 #define STPARMS_4K 0x0026
409 #define COMP_EN 0x4000
410 #define CBR_EN 0x2000
411 #define ABR_EN 0x0800
412 #define UBR_EN 0x0400
414 #define ABRUBR_ARB 0x04
416 /*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/
417 #define RM_TYPE_4_0 0x0100
419 #define SEG_COMMAND_REG 0x17
420 /* Values for the command register */
421 #define RESET_SEG 0x0055
422 #define RESET_SEG_STATE 0x00aa
423 #define RESET_TX_CELL_CTR 0x00cc
425 #define CBR_PTR_BASE 0x20
426 #define ABR_SBPTR_BASE 0x22
427 #define UBR_SBPTR_BASE 0x23
428 #define ABRWQ_BASE 0x26
429 #define UBRWQ_BASE 0x27
430 #define VCT_BASE 0x28
431 #define VCTE_BASE 0x29
432 #define CBR_TAB_BEG 0x2c
433 #define CBR_TAB_END 0x2d
434 #define PRQ_ST_ADR 0x30
435 #define PRQ_ED_ADR 0x31
436 #define PRQ_RD_PTR 0x32
437 #define PRQ_WR_PTR 0x33
438 #define TCQ_ST_ADR 0x34
439 #define TCQ_ED_ADR 0x35
440 #define TCQ_RD_PTR 0x36
441 #define TCQ_WR_PTR 0x37
442 #define SEG_QUEUE_BASE 0x40
443 #define SEG_DESC_BASE 0x41
444 #define MODE_REG_0 0x45
445 #define T_ONLINE 0x0002 /* (i)chipSAR is online */
447 #define MODE_REG_1 0x46
448 #define MODE_REG_1_VAL 0x0400 /*for propoer device operation*/
450 #define SEG_INTR_STATUS_REG 0x47
451 #define SEG_MASK_REG 0x48
452 #define TRANSMIT_DONE 0x0200
453 #define TCQ_NOT_EMPTY 0x1000 /* this can be used for both the interrupt
454 status registers as well as the mask register */
456 #define CELL_CTR_HIGH_AUTO 0x49
457 #define CELL_CTR_HIGH_NOAUTO 0xc9
458 #define CELL_CTR_LO_AUTO 0x4a
459 #define CELL_CTR_LO_NOAUTO 0xca
461 /* Diagnostic registers */
462 #define NEXTDESC 0x59
464 #define PSLOTCNT 0x5d
468 #define ABRWQ_WRPTR 0x6f
469 #define ABRWQ_RDPTR 0x70
470 #define UBRWQ_WRPTR 0x71
471 #define UBRWQ_RDPTR 0x72
473 #define ABR_SBVC 0x75
474 #define UBR_SBVC 0x76
475 #define ABRNEXTLINK 0x78
476 #define UBRNEXTLINK 0x79
479 /*----------------- Reassembly control registers ---------------------*/
480 /* The reassembly registers are 16 bits access and the addresses
481 are defined as such so the addresses are the actual "offsets" */
482 #define MODE_REG 0x00
483 #define R_ONLINE 0x0002 /* (i)chip is online */
484 #define IGN_RAW_FL 0x0004
486 #define PROTOCOL_ID 0x01
487 #define REASS_MASK_REG 0x02
488 #define REASS_INTR_STATUS_REG 0x03
489 /* Interrupt Status register bits */
490 #define RX_PKT_CTR_OF 0x8000
491 #define RX_ERR_CTR_OF 0x4000
492 #define RX_CELL_CTR_OF 0x1000
493 #define RX_FREEQ_EMPT 0x0200
494 #define RX_EXCPQ_FL 0x0080
495 #define RX_RAWQ_FL 0x0010
496 #define RX_EXCP_RCVD 0x0008
497 #define RX_PKT_RCVD 0x0004
498 #define RX_RAW_RCVD 0x0001
500 #define DRP_PKT_CNTR 0x04
501 #define ERR_CNTR 0x05
502 #define RAW_BASE_ADR 0x08
503 #define CELL_CTR0 0x0c
504 #define CELL_CTR1 0x0d
505 #define REASS_COMMAND_REG 0x0f
506 /* Values for command register */
507 #define RESET_REASS 0x0055
508 #define RESET_REASS_STATE 0x00aa
509 #define RESET_DRP_PKT_CNTR 0x00f1
510 #define RESET_ERR_CNTR 0x00f2
511 #define RESET_CELL_CNTR 0x00f8
512 #define RESET_REASS_ALL_REGS 0x00ff
514 #define REASS_DESC_BASE 0x10
515 #define VC_LKUP_BASE 0x11
516 #define REASS_TABLE_BASE 0x12
517 #define REASS_QUEUE_BASE 0x13
518 #define PKT_TM_CNT 0x16
519 #define TMOUT_RANGE 0x17
520 #define INTRVL_CNTR 0x18
521 #define TMOUT_INDX 0x19
522 #define VP_LKUP_BASE 0x1c
523 #define VP_FILTER 0x1d
524 #define ABR_LKUP_BASE 0x1e
525 #define FREEQ_ST_ADR 0x24
526 #define FREEQ_ED_ADR 0x25
527 #define FREEQ_RD_PTR 0x26
528 #define FREEQ_WR_PTR 0x27
529 #define PCQ_ST_ADR 0x28
530 #define PCQ_ED_ADR 0x29
531 #define PCQ_RD_PTR 0x2a
532 #define PCQ_WR_PTR 0x2b
533 #define EXCP_Q_ST_ADR 0x2c
534 #define EXCP_Q_ED_ADR 0x2d
535 #define EXCP_Q_RD_PTR 0x2e
536 #define EXCP_Q_WR_PTR 0x2f
537 #define CC_FIFO_ST_ADR 0x34
538 #define CC_FIFO_ED_ADR 0x35
539 #define CC_FIFO_RD_PTR 0x36
540 #define CC_FIFO_WR_PTR 0x37
541 #define STATE_REG 0x38
542 #define BUF_SIZE 0x42
543 #define XTRA_RM_OFFSET 0x44
544 #define DRP_PKT_CNTR_NC 0x84
545 #define ERR_CNTR_NC 0x85
546 #define CELL_CNTR0_NC 0x8c
547 #define CELL_CNTR1_NC 0x8d
549 /* State Register bits */
550 #define EXCPQ_EMPTY 0x0040
551 #define PCQ_EMPTY 0x0010
552 #define FREEQ_EMPTY 0x0004
555 /*----------------- Front End registers/ DMA control --------------*/
556 /* There is a lot of documentation error regarding these offsets ???
557 eg:- 2 offsets given 800, a00 for rx counter
558 similarly many others
559 Remember again that the offsets are to be 4*register number, so
560 correct the #defines here
562 #define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */
563 #define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */
564 #define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */
565 #define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */
567 /*--------------------------- RAM ---------------------------*/
568 /* These memory maps are actually offsets from the segmentation and reassembly RAM base addresses */
570 /* Segmentation Control Memory map */
571 #define TX_DESC_BASE 0x0000 /* Buffer Decriptor Table */
572 #define TX_COMP_Q 0x1000 /* Transmit Complete Queue */
573 #define PKT_RDY_Q 0x1400 /* Packet Ready Queue */
574 #define CBR_SCHED_TABLE 0x1800 /* CBR Table */
575 #define UBR_SCHED_TABLE 0x3000 /* UBR Table */
576 #define UBR_WAIT_Q 0x4000 /* UBR Wait Queue */
577 #define ABR_SCHED_TABLE 0x5000 /* ABR Table */
578 #define ABR_WAIT_Q 0x5800 /* ABR Wait Queue */
579 #define EXT_VC_TABLE 0x6000 /* Extended VC Table */
580 #define MAIN_VC_TABLE 0x8000 /* Main VC Table */
581 #define SCHEDSZ 1024 /* ABR and UBR Scheduling Table size */
582 #define TX_DESC_TABLE_SZ 128 /* Number of entries in the Transmit
583 Buffer Descriptor Table */
585 /* These are used as table offsets in Descriptor Table address generation */
586 #define DESC_MODE 0x0
589 #define PKT_START_HI 0x4
590 #define PKT_START_LO 0x5
592 /* Descriptor Mode Word Bits */
593 #define EOM_EN 0x0800
595 #define APP_CRC32 0x0400
596 #define CMPL_INT 0x1000
598 #define TABLE_ADDRESS(db, dn, to) \
599 (((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1)
601 /* Reassembly Control Memory Map */
602 #define RX_DESC_BASE 0x0000 /* Buffer Descriptor Table */
603 #define VP_TABLE 0x5c00 /* VP Table */
604 #define EXCEPTION_Q 0x5e00 /* Exception Queue */
605 #define FREE_BUF_DESC_Q 0x6000 /* Free Buffer Descriptor Queue */
606 #define PKT_COMP_Q 0x6800 /* Packet Complete Queue */
607 #define REASS_TABLE 0x7000 /* Reassembly Table */
608 #define RX_VC_TABLE 0x7800 /* VC Table */
609 #define ABR_VC_TABLE 0x8000 /* ABR VC Table */
610 #define RX_DESC_TABLE_SZ 736 /* Number of entries in the Receive
611 Buffer Descriptor Table */
612 #define VP_TABLE_SZ 256 /* Number of entries in VPTable */
613 #define RX_VC_TABLE_SZ 1024 /* Number of entries in VC Table */
614 #define REASS_TABLE_SZ 1024 /* Number of entries in Reassembly Table */
615 /* Buffer Descriptor Table */
616 #define RX_ACT 0x8000
617 #define RX_VPVC 0x4000
618 #define RX_CNG 0x0040
619 #define RX_CER 0x0008
620 #define RX_PTE 0x0004
621 #define RX_OFL 0x0002
622 #define NUM_RX_EXCP 32
624 /* Reassembly Table */
625 #define NO_AAL5_PKT 0x0000
626 #define AAL5_PKT_REASSEMBLED 0x4000
627 #define AAL5_PKT_TERMINATED 0x8000
628 #define RAW_PKT 0xc000
629 #define REASS_ABR 0x2000
631 /*-------------------- Base Registers --------------------*/
632 #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE
633 #define RAM_BASE IPHASE5575_FRAG_CONTROL_RAM_BASE
634 #define PHY_BASE IPHASE5575_FRONT_END_REG_BASE
635 #define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE
636 #define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE
638 typedef volatile u_int ffreg_t;
639 typedef u_int rreg_t;
641 typedef struct _ffredn_t {
642 ffreg_t idlehead_high; /* Idle cell header (high) */
643 ffreg_t idlehead_low; /* Idle cell header (low) */
644 ffreg_t maxrate; /* Maximum rate */
645 ffreg_t stparms; /* Traffic Management Parameters */
646 ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
647 ffreg_t rm_type; /* */
648 u_int filler5[0x17 - 0x06];
649 ffreg_t cmd_reg; /* Command register */
650 u_int filler18[0x20 - 0x18];
651 ffreg_t cbr_base; /* CBR Pointer Base */
652 ffreg_t vbr_base; /* VBR Pointer Base */
653 ffreg_t abr_base; /* ABR Pointer Base */
654 ffreg_t ubr_base; /* UBR Pointer Base */
656 ffreg_t vbrwq_base; /* VBR Wait Queue Base */
657 ffreg_t abrwq_base; /* ABR Wait Queue Base */
658 ffreg_t ubrwq_base; /* UBR Wait Queue Base */
659 ffreg_t vct_base; /* Main VC Table Base */
660 ffreg_t vcte_base; /* Extended Main VC Table Base */
661 u_int filler2a[0x2C - 0x2A];
662 ffreg_t cbr_tab_beg; /* CBR Table Begin */
663 ffreg_t cbr_tab_end; /* CBR Table End */
664 ffreg_t cbr_pointer; /* CBR Pointer */
665 u_int filler2f[0x30 - 0x2F];
666 ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */
667 ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */
668 ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
669 ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
670 ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
671 ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
672 ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
673 ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
674 u_int filler38[0x40 - 0x38];
675 ffreg_t queue_base; /* Base address for PRQ and TCQ */
676 ffreg_t desc_base; /* Base address of descriptor table */
677 u_int filler42[0x45 - 0x42];
678 ffreg_t mode_reg_0; /* Mode register 0 */
679 ffreg_t mode_reg_1; /* Mode register 1 */
680 ffreg_t intr_status_reg;/* Interrupt Status register */
681 ffreg_t mask_reg; /* Mask Register */
682 ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */
683 ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */
684 ffreg_t state_reg; /* Status register */
685 u_int filler4c[0x58 - 0x4c];
686 ffreg_t curr_desc_num; /* Contains the current descriptor num */
687 ffreg_t next_desc; /* Next descriptor */
688 ffreg_t next_vc; /* Next VC */
689 u_int filler5b[0x5d - 0x5b];
690 ffreg_t present_slot_cnt;/* Present slot count */
691 u_int filler5e[0x6a - 0x5e];
692 ffreg_t new_desc_num; /* New descriptor number */
693 ffreg_t new_vc; /* New VC */
694 ffreg_t sched_tbl_ptr; /* Schedule table pointer */
695 ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */
696 ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */
697 ffreg_t abrwq_wptr; /* ABR wait queue write pointer */
698 ffreg_t abrwq_rptr; /* ABR wait queue read pointer */
699 ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */
700 ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */
701 ffreg_t cbr_vc; /* CBR VC */
702 ffreg_t vbr_sb_vc; /* VBR SB VC */
703 ffreg_t abr_sb_vc; /* ABR SB VC */
704 ffreg_t ubr_sb_vc; /* UBR SB VC */
705 ffreg_t vbr_next_link; /* VBR next link */
706 ffreg_t abr_next_link; /* ABR next link */
707 ffreg_t ubr_next_link; /* UBR next link */
708 u_int filler7a[0x7c-0x7a];
709 ffreg_t out_rate_head; /* Out of rate head */
710 u_int filler7d[0xca-0x7d]; /* pad out to full address space */
711 ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
712 ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
713 u_int fillercc[0x100-0xcc]; /* pad out to full address space */
716 typedef struct _rfredn_t {
717 rreg_t mode_reg_0; /* Mode register 0 */
718 rreg_t protocol_id; /* Protocol ID */
719 rreg_t mask_reg; /* Mask Register */
720 rreg_t intr_status_reg;/* Interrupt status register */
721 rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */
722 rreg_t err_cntr; /* Error Counter (cleared on read) */
723 u_int filler6[0x08 - 0x06];
724 rreg_t raw_base_adr; /* Base addr for raw cell Q */
725 u_int filler2[0x0c - 0x09];
726 rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
727 rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */
728 u_int filler3[0x0f - 0x0e];
729 rreg_t cmd_reg; /* Command register */
730 rreg_t desc_base; /* Base address for description table */
731 rreg_t vc_lkup_base; /* Base address for VC lookup table */
732 rreg_t reass_base; /* Base address for reassembler table */
733 rreg_t queue_base; /* Base address for Communication queue */
734 u_int filler14[0x16 - 0x14];
735 rreg_t pkt_tm_cnt; /* Packet Timeout and count register */
736 rreg_t tmout_range; /* Range of reassembley IDs for timeout */
737 rreg_t intrvl_cntr; /* Packet aging interval counter */
738 rreg_t tmout_indx; /* index of pkt being tested for aging */
739 u_int filler1a[0x1c - 0x1a];
740 rreg_t vp_lkup_base; /* Base address for VP lookup table */
741 rreg_t vp_filter; /* VP filter register */
742 rreg_t abr_lkup_base; /* Base address of ABR VC Table */
743 u_int filler1f[0x24 - 0x1f];
744 rreg_t fdq_st_adr; /* Free desc queue start address */
745 rreg_t fdq_ed_adr; /* Free desc queue end address */
746 rreg_t fdq_rd_ptr; /* Free desc queue read pointer */
747 rreg_t fdq_wr_ptr; /* Free desc queue write pointer */
748 rreg_t pcq_st_adr; /* Packet Complete queue start address */
749 rreg_t pcq_ed_adr; /* Packet Complete queue end address */
750 rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */
751 rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */
752 rreg_t excp_st_adr; /* Exception queue start address */
753 rreg_t excp_ed_adr; /* Exception queue end address */
754 rreg_t excp_rd_ptr; /* Exception queue read pointer */
755 rreg_t excp_wr_ptr; /* Exception queue write pointer */
756 u_int filler30[0x34 - 0x30];
757 rreg_t raw_st_adr; /* Raw Cell start address */
758 rreg_t raw_ed_adr; /* Raw Cell end address */
759 rreg_t raw_rd_ptr; /* Raw Cell read pointer */
760 rreg_t raw_wr_ptr; /* Raw Cell write pointer */
761 rreg_t state_reg; /* State Register */
762 u_int filler39[0x42 - 0x39];
763 rreg_t buf_size; /* Buffer size */
765 rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */
766 u_int filler45[0x84 - 0x45];
767 rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */
768 rreg_t err_cntr_nc; /* Error Counter, Not clear on read */
769 u_int filler86[0x8c - 0x86];
770 rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */
771 rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */
772 u_int filler8e[0x100-0x8e]; /* pad out to full address space */
777 ffredn_t ffredn; /* F FRED */
778 rfredn_t rfredn; /* R FRED */
782 u_short f_vc_type; /* VC type */
783 u_short f_nrm; /* Nrm */
784 u_short f_nrmexp; /* Nrm Exp */
785 u_short reserved6; /* */
786 u_short f_crm; /* Crm */
787 u_short reserved10; /* Reserved */
788 u_short reserved12; /* Reserved */
789 u_short reserved14; /* Reserved */
790 u_short last_cell_slot; /* last_cell_slot_count */
791 u_short f_pcr; /* Peak Cell Rate */
792 u_short fraction; /* fraction */
793 u_short f_icr; /* Initial Cell Rate */
795 u_short f_mcr; /* Minimum Cell Rate */
796 u_short f_acr; /* Allowed Cell Rate */
797 u_short f_status; /* */
801 u_short r_status_rdf; /* status + RDF */
802 u_short r_air; /* AIR */
803 u_short reserved4[14]; /* Reserved */
808 typedef struct srv_cls_param {
809 u32 class_type; /* CBR/VBR/ABR/UBR; use the enum above */
810 u32 pcr; /* Peak Cell Rate (24-bit) */
812 u32 scr; /* sustainable cell rate */
813 u32 max_burst_size; /* ?? cell rate or data rate */
815 /* ABR only UNI 4.0 Parameters */
816 u32 mcr; /* Min Cell Rate (24-bit) */
817 u32 icr; /* Initial Cell Rate (24-bit) */
818 u32 tbe; /* Transient Buffer Exposure (24-bit) */
819 u32 frtt; /* Fixed Round Trip Time (24-bit) */
821 #if 0 /* Additional Parameters of TM 4.0 */
822 bits 31 30 29 28 27-25 24-22 21-19 18-9
823 -----------------------------------------------------------------------------
824 | NRM present | TRM prsnt | CDF prsnt | ADTF prsnt | NRM | TRM | CDF | ADTF |
825 -----------------------------------------------------------------------------
828 u8 nrm; /* Max # of Cells for each forward RM
830 u8 trm; /* Time between forward RM cells (3-bit) */
831 u16 adtf; /* ACR Decrease Time Factor (10-bit) */
832 u8 cdf; /* Cutoff Decrease Factor (3-bit) */
833 u8 rif; /* Rate Increment Factor (4-bit) */
834 u8 rdf; /* Rate Decrease Factor (4-bit) */
835 u8 reserved; /* 8 bits to keep structure word aligned */
854 #define VC_ACTIVE 0x01
860 u32 fdq_st; /* Free desc queue start address */
861 u32 fdq_ed; /* Free desc queue end address */
862 u32 fdq_rd; /* Free desc queue read pointer */
863 u32 fdq_wr; /* Free desc queue write pointer */
864 u32 pcq_st; /* Packet Complete queue start address */
865 u32 pcq_ed; /* Packet Complete queue end address */
866 u32 pcq_rd; /* Packet Complete queue read pointer */
867 u32 pcq_wr; /* Packet Complete queue write pointer */
871 u32 prq_st; /* Packet Ready Queue Start Address */
872 u32 prq_ed; /* Packet Ready Queue End Address */
873 u32 prq_wr; /* Packet Ready Queue write pointer */
874 u32 tcq_st; /* Transmit Complete Queue Start Address*/
875 u32 tcq_ed; /* Transmit Complete Queue End Address */
876 u32 tcq_rd; /* Transmit Complete Queue read pointer */
881 struct ia_vcc *iavcc;
882 struct sk_buff *txskb;
885 typedef struct ia_rtn_q {
886 struct desc_tbl_t data;
887 struct ia_rtn_q *next, *tail;
890 #define SUNI_LOSV 0x04
892 SUNI_MASTER_RESET = 0x000, /* SUNI Master Reset and Identity */
893 SUNI_MASTER_CONFIG = 0x004, /* SUNI Master Configuration */
894 SUNI_MASTER_INTR_STAT = 0x008, /* SUNI Master Interrupt Status */
895 SUNI_RESERVED1 = 0x00c, /* Reserved */
896 SUNI_MASTER_CLK_MONITOR = 0x010, /* SUNI Master Clock Monitor */
897 SUNI_MASTER_CONTROL = 0x014, /* SUNI Master Clock Monitor */
899 SUNI_RSOP_CONTROL = 0x040, /* RSOP Control/Interrupt Enable */
900 SUNI_RSOP_STATUS = 0x044, /* RSOP Status/Interrupt States */
901 SUNI_RSOP_SECTION_BIP8L = 0x048, /* RSOP Section BIP-8 LSB */
902 SUNI_RSOP_SECTION_BIP8M = 0x04c, /* RSOP Section BIP-8 MSB */
904 SUNI_TSOP_CONTROL = 0x050, /* TSOP Control */
905 SUNI_TSOP_DIAG = 0x054, /* TSOP Disgnostics */
907 SUNI_RLOP_CS = 0x060, /* RLOP Control/Status */
908 SUNI_RLOP_INTR = 0x064, /* RLOP Interrupt Enable/Status */
909 SUNI_RLOP_LINE_BIP24L = 0x068, /* RLOP Line BIP-24 LSB */
910 SUNI_RLOP_LINE_BIP24 = 0x06c, /* RLOP Line BIP-24 */
911 SUNI_RLOP_LINE_BIP24M = 0x070, /* RLOP Line BIP-24 MSB */
912 SUNI_RLOP_LINE_FEBEL = 0x074, /* RLOP Line FEBE LSB */
913 SUNI_RLOP_LINE_FEBE = 0x078, /* RLOP Line FEBE */
914 SUNI_RLOP_LINE_FEBEM = 0x07c, /* RLOP Line FEBE MSB */
916 SUNI_TLOP_CONTROL = 0x080, /* TLOP Control */
917 SUNI_TLOP_DISG = 0x084, /* TLOP Disgnostics */
919 SUNI_RPOP_CS = 0x0c0, /* RPOP Status/Control */
920 SUNI_RPOP_INTR = 0x0c4, /* RPOP Interrupt/Status */
921 SUNI_RPOP_RESERVED = 0x0c8, /* RPOP Reserved */
922 SUNI_RPOP_INTR_ENA = 0x0cc, /* RPOP Interrupt Enable */
924 SUNI_RPOP_PATH_SIG = 0x0dc, /* RPOP Path Signal Label */
925 SUNI_RPOP_BIP8L = 0x0e0, /* RPOP Path BIP-8 LSB */
926 SUNI_RPOP_BIP8M = 0x0e4, /* RPOP Path BIP-8 MSB */
927 SUNI_RPOP_FEBEL = 0x0e8, /* RPOP Path FEBE LSB */
928 SUNI_RPOP_FEBEM = 0x0ec, /* RPOP Path FEBE MSB */
930 SUNI_TPOP_CNTRL_DAIG = 0x100, /* TPOP Control/Disgnostics */
931 SUNI_TPOP_POINTER_CTRL = 0x104, /* TPOP Pointer Control */
932 SUNI_TPOP_SOURCER_CTRL = 0x108, /* TPOP Source Control */
934 SUNI_TPOP_ARB_PRTL = 0x114, /* TPOP Arbitrary Pointer LSB */
935 SUNI_TPOP_ARB_PRTM = 0x118, /* TPOP Arbitrary Pointer MSB */
936 SUNI_TPOP_RESERVED2 = 0x11c, /* TPOP Reserved */
937 SUNI_TPOP_PATH_SIG = 0x120, /* TPOP Path Signal Lable */
938 SUNI_TPOP_PATH_STATUS = 0x124, /* TPOP Path Status */
940 SUNI_RACP_CS = 0x140, /* RACP Control/Status */
941 SUNI_RACP_INTR = 0x144, /* RACP Interrupt Enable/Status */
942 SUNI_RACP_HDR_PATTERN = 0x148, /* RACP Match Header Pattern */
943 SUNI_RACP_HDR_MASK = 0x14c, /* RACP Match Header Mask */
944 SUNI_RACP_CORR_HCS = 0x150, /* RACP Correctable HCS Error Count */
945 SUNI_RACP_UNCORR_HCS = 0x154, /* RACP Uncorrectable HCS Err Count */
947 SUNI_TACP_CONTROL = 0x180, /* TACP Control */
948 SUNI_TACP_IDLE_HDR_PAT = 0x184, /* TACP Idle Cell Header Pattern */
949 SUNI_TACP_IDLE_PAY_PAY = 0x188, /* TACP Idle Cell Payld Octet Patrn */
952 /* FIXME: unused but name conflicts.
953 * SUNI_MASTER_TEST = 0x200, SUNI Master Test */
954 SUNI_RESERVED_TEST = 0x204 /* SUNI Reserved for Test */
957 typedef struct _SUNI_STATS_
959 u32 valid; // 1 = oc3 PHY card
960 u32 carrier_detect; // GPIN input
961 // RSOP: receive section overhead processor
962 u16 rsop_oof_state; // 1 = out of frame
963 u16 rsop_lof_state; // 1 = loss of frame
964 u16 rsop_los_state; // 1 = loss of signal
965 u32 rsop_los_count; // loss of signal count
966 u32 rsop_bse_count; // section BIP-8 error count
967 // RLOP: receive line overhead processor
968 u16 rlop_ferf_state; // 1 = far end receive failure
969 u16 rlop_lais_state; // 1 = line AIS
970 u32 rlop_lbe_count; // BIP-24 count
971 u32 rlop_febe_count; // FEBE count;
972 // RPOP: receive path overhead processor
973 u16 rpop_lop_state; // 1 = LOP
974 u16 rpop_pais_state; // 1 = path AIS
975 u16 rpop_pyel_state; // 1 = path yellow alert
976 u32 rpop_bip_count; // path BIP-8 error count
977 u32 rpop_febe_count; // path FEBE error count
978 u16 rpop_psig; // path signal label value
979 // RACP: receive ATM cell processor
980 u16 racp_hp_state; // hunt/presync state
981 u32 racp_fu_count; // FIFO underrun count
982 u32 racp_fo_count; // FIFO overrun count
983 u32 racp_chcs_count; // correctable HCS error count
984 u32 racp_uchcs_count; // uncorrectable HCS error count
987 typedef struct iadev_priv {
988 /*-----base pointers into (i)chipSAR+ address space */
989 u32 __iomem *phy; /* Base pointer into phy (SUNI). */
990 u32 __iomem *dma; /* Base pointer into DMA control registers. */
991 u32 __iomem *reg; /* Base pointer to SAR registers. */
992 u32 __iomem *seg_reg; /* base pointer to segmentation engine
993 internal registers */
994 u32 __iomem *reass_reg; /* base pointer to reassemble engine
995 internal registers */
996 u32 __iomem *ram; /* base pointer to SAR RAM */
997 void __iomem *seg_ram;
998 void __iomem *reass_ram;
999 struct dle_q tx_dle_q;
1000 struct free_desc_q *tx_free_desc_qhead;
1001 struct sk_buff_head tx_dma_q, tx_backlog;
1003 IARTN_Q tx_return_q;
1005 wait_queue_head_t close_wait;
1006 wait_queue_head_t timeout_wait;
1007 struct cpcs_trailer_desc *tx_buf;
1008 u16 num_tx_desc, tx_buf_sz, rate_limit;
1009 u32 tx_cell_cnt, tx_pkt_cnt;
1010 void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;
1011 struct dle_q rx_dle_q;
1012 struct free_desc_q *rx_free_desc_qhead;
1013 struct sk_buff_head rx_dma_q;
1015 struct atm_vcc **rx_open; /* list of all open VCs */
1016 u16 num_rx_desc, rx_buf_sz, rxing;
1017 u32 rx_pkt_ram, rx_tmp_cnt;
1018 unsigned long rx_tmp_jif;
1019 void __iomem *RX_DESC_BASE_ADDR;
1020 u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
1021 struct atm_dev *next_board; /* other iphase devices */
1022 struct pci_dev *pci;
1024 unsigned int real_base; /* real and virtual base address */
1026 unsigned int pci_map_size; /*pci map size of board */
1029 unsigned char dev_fn;
1031 u_short num_vc, memSize, memType;
1032 struct ia_ffL_t ffL;
1033 struct ia_rfL_t rfL;
1035 // IA_SUNI_STATS suni_stats;
1036 unsigned char carrier_detect;
1038 // transmit DMA & Receive
1039 unsigned int tx_dma_cnt; // number of elements on dma queue
1040 unsigned int rx_dma_cnt; // number of elements on rx dma queue
1041 unsigned int NumEnabledCBR; // number of CBR VCI's enabled. CBR
1042 // receive MARK for Cell FIFO
1043 unsigned int rx_mark_cnt; // number of elements on mark queue
1044 unsigned int CbrTotEntries; // Total CBR Entries in Scheduling Table.
1045 unsigned int CbrRemEntries; // Remaining CBR Entries in Scheduling Table.
1046 unsigned int CbrEntryPt; // CBR Sched Table Entry Point.
1047 unsigned int Granularity; // CBR Granularity given Table Size.
1049 unsigned int sum_mcr, sum_cbr, LineRate;
1051 struct desc_tbl_t *desc_tbl;
1052 u_short host_tcq_wr;
1053 struct testTable_t **testTable;
1054 dma_addr_t tx_dle_dma;
1055 dma_addr_t rx_dle_dma;
1059 #define INPH_IA_DEV(d) ((IADEV *) (d)->dev_data)
1060 #define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
1062 /******************* IDT77105 25MB/s PHY DEFINE *****************************/
1064 MB25_MASTER_CTRL = 0x00, /* Master control */
1065 MB25_INTR_STATUS = 0x04, /* Interrupt status */
1066 MB25_DIAG_CONTROL = 0x08, /* Diagnostic control */
1067 MB25_LED_HEC = 0x0c, /* LED driver and HEC status/control */
1068 MB25_LOW_BYTE_COUNTER = 0x10,
1069 MB25_HIGH_BYTE_COUNTER = 0x14
1075 #define MB25_MC_UPLO 0x80 /* UPLO */
1076 #define MB25_MC_DREC 0x40 /* Discard receive cell errors */
1077 #define MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */
1078 #define MB25_MC_TDPC 0x10 /* Transmit data parity check */
1079 #define MB25_MC_DRIC 0x08 /* Discard receive idle cells */
1080 #define MB25_MC_HALTTX 0x04 /* Halt Tx */
1081 #define MB25_MC_UMS 0x02 /* UTOPIA mode select */
1082 #define MB25_MC_ENABLED 0x01 /* Enable interrupt */
1087 #define MB25_IS_GSB 0x40 /* GOOD Symbol Bit */
1088 #define MB25_IS_HECECR 0x20 /* HEC error cell received */
1089 #define MB25_IS_SCR 0x10 /* "Short Cell" Received */
1090 #define MB25_IS_TPE 0x08 /* Trnamsit Parity Error */
1091 #define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */
1092 #define MB25_IS_RCSE 0x02 /* Received Cell Symbol Error */
1093 #define MB25_IS_RFIFOO 0x01 /* Received FIFO Overrun */
1096 * Diagnostic Control
1098 #define MB25_DC_FTXCD 0x80 /* Force TxClav deassert */
1099 #define MB25_DC_RXCOS 0x40 /* RxClav operation select */
1100 #define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */
1101 #define MB25_DC_RLFLUSH 0x10 /* Clear receive FIFO */
1102 #define MB25_DC_IXPE 0x08 /* Insert xmit payload error */
1103 #define MB25_DC_IXHECE 0x04 /* Insert Xmit HEC Error */
1104 #define MB25_DC_LB_MASK 0x03 /* Loopback control mask */
1106 #define MB25_DC_LL 0x03 /* Line Loopback */
1107 #define MB25_DC_PL 0x02 /* PHY Loopback */
1108 #define MB25_DC_NM 0x00
1110 #define FE_MASK 0x00F0
1111 #define FE_MULTI_MODE 0x0000
1112 #define FE_SINGLE_MODE 0x0010
1113 #define FE_UTP_OPTION 0x0020
1114 #define FE_25MBIT_PHY 0x0040
1115 #define FE_DS3_PHY 0x0080 /* DS3 */
1116 #define FE_E3_PHY 0x0090 /* E3 */
1118 /*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
1120 SUNI_CONFIG = 0x000, /* SUNI Configuration */
1121 SUNI_INTR_ENBL = 0x004, /* SUNI Interrupt Enable */
1122 SUNI_INTR_STAT = 0x008, /* SUNI Interrupt Status */
1123 SUNI_CONTROL = 0x00c, /* SUNI Control */
1124 SUNI_ID_RESET = 0x010, /* SUNI Reset and Identity */
1125 SUNI_DATA_LINK_CTRL = 0x014,
1126 SUNI_RBOC_CONF_INTR_ENBL = 0x018,
1127 SUNI_RBOC_STAT = 0x01c,
1128 SUNI_DS3_FRM_CFG = 0x020,
1129 SUNI_DS3_FRM_INTR_ENBL = 0x024,
1130 SUNI_DS3_FRM_INTR_STAT = 0x028,
1131 SUNI_DS3_FRM_STAT = 0x02c,
1132 SUNI_RFDL_CFG = 0x030,
1133 SUNI_RFDL_ENBL_STAT = 0x034,
1134 SUNI_RFDL_STAT = 0x038,
1135 SUNI_RFDL_DATA = 0x03c,
1136 SUNI_PMON_CHNG = 0x040,
1137 SUNI_PMON_INTR_ENBL_STAT = 0x044,
1138 /* SUNI_RESERVED1 (0x13 - 0x11) */
1139 SUNI_PMON_LCV_EVT_CNT_LSB = 0x050,
1140 SUNI_PMON_LCV_EVT_CNT_MSB = 0x054,
1141 SUNI_PMON_FBE_EVT_CNT_LSB = 0x058,
1142 SUNI_PMON_FBE_EVT_CNT_MSB = 0x05c,
1143 SUNI_PMON_SEZ_DET_CNT_LSB = 0x060,
1144 SUNI_PMON_SEZ_DET_CNT_MSB = 0x064,
1145 SUNI_PMON_PE_EVT_CNT_LSB = 0x068,
1146 SUNI_PMON_PE_EVT_CNT_MSB = 0x06c,
1147 SUNI_PMON_PPE_EVT_CNT_LSB = 0x070,
1148 SUNI_PMON_PPE_EVT_CNT_MSB = 0x074,
1149 SUNI_PMON_FEBE_EVT_CNT_LSB = 0x078,
1150 SUNI_PMON_FEBE_EVT_CNT_MSB = 0x07c,
1151 SUNI_DS3_TRAN_CFG = 0x080,
1152 SUNI_DS3_TRAN_DIAG = 0x084,
1153 /* SUNI_RESERVED2 (0x23 - 0x21) */
1154 SUNI_XFDL_CFG = 0x090,
1155 SUNI_XFDL_INTR_ST = 0x094,
1156 SUNI_XFDL_XMIT_DATA = 0x098,
1157 SUNI_XBOC_CODE = 0x09c,
1158 SUNI_SPLR_CFG = 0x0a0,
1159 SUNI_SPLR_INTR_EN = 0x0a4,
1160 SUNI_SPLR_INTR_ST = 0x0a8,
1161 SUNI_SPLR_STATUS = 0x0ac,
1162 SUNI_SPLT_CFG = 0x0b0,
1163 SUNI_SPLT_CNTL = 0x0b4,
1164 SUNI_SPLT_DIAG_G1 = 0x0b8,
1165 SUNI_SPLT_F1 = 0x0bc,
1166 SUNI_CPPM_LOC_METERS = 0x0c0,
1167 SUNI_CPPM_CHG_OF_CPPM_PERF_METR = 0x0c4,
1168 SUNI_CPPM_B1_ERR_CNT_LSB = 0x0c8,
1169 SUNI_CPPM_B1_ERR_CNT_MSB = 0x0cc,
1170 SUNI_CPPM_FRAMING_ERR_CNT_LSB = 0x0d0,
1171 SUNI_CPPM_FRAMING_ERR_CNT_MSB = 0x0d4,
1172 SUNI_CPPM_FEBE_CNT_LSB = 0x0d8,
1173 SUNI_CPPM_FEBE_CNT_MSB = 0x0dc,
1174 SUNI_CPPM_HCS_ERR_CNT_LSB = 0x0e0,
1175 SUNI_CPPM_HCS_ERR_CNT_MSB = 0x0e4,
1176 SUNI_CPPM_IDLE_UN_CELL_CNT_LSB = 0x0e8,
1177 SUNI_CPPM_IDLE_UN_CELL_CNT_MSB = 0x0ec,
1178 SUNI_CPPM_RCV_CELL_CNT_LSB = 0x0f0,
1179 SUNI_CPPM_RCV_CELL_CNT_MSB = 0x0f4,
1180 SUNI_CPPM_XMIT_CELL_CNT_LSB = 0x0f8,
1181 SUNI_CPPM_XMIT_CELL_CNT_MSB = 0x0fc,
1182 SUNI_RXCP_CTRL = 0x100,
1183 SUNI_RXCP_FCTRL = 0x104,
1184 SUNI_RXCP_INTR_EN_STS = 0x108,
1185 SUNI_RXCP_IDLE_PAT_H1 = 0x10c,
1186 SUNI_RXCP_IDLE_PAT_H2 = 0x110,
1187 SUNI_RXCP_IDLE_PAT_H3 = 0x114,
1188 SUNI_RXCP_IDLE_PAT_H4 = 0x118,
1189 SUNI_RXCP_IDLE_MASK_H1 = 0x11c,
1190 SUNI_RXCP_IDLE_MASK_H2 = 0x120,
1191 SUNI_RXCP_IDLE_MASK_H3 = 0x124,
1192 SUNI_RXCP_IDLE_MASK_H4 = 0x128,
1193 SUNI_RXCP_CELL_PAT_H1 = 0x12c,
1194 SUNI_RXCP_CELL_PAT_H2 = 0x130,
1195 SUNI_RXCP_CELL_PAT_H3 = 0x134,
1196 SUNI_RXCP_CELL_PAT_H4 = 0x138,
1197 SUNI_RXCP_CELL_MASK_H1 = 0x13c,
1198 SUNI_RXCP_CELL_MASK_H2 = 0x140,
1199 SUNI_RXCP_CELL_MASK_H3 = 0x144,
1200 SUNI_RXCP_CELL_MASK_H4 = 0x148,
1201 SUNI_RXCP_HCS_CS = 0x14c,
1202 SUNI_RXCP_LCD_CNT_THRESHOLD = 0x150,
1203 /* SUNI_RESERVED3 (0x57 - 0x54) */
1204 SUNI_TXCP_CTRL = 0x160,
1205 SUNI_TXCP_INTR_EN_STS = 0x164,
1206 SUNI_TXCP_IDLE_PAT_H1 = 0x168,
1207 SUNI_TXCP_IDLE_PAT_H2 = 0x16c,
1208 SUNI_TXCP_IDLE_PAT_H3 = 0x170,
1209 SUNI_TXCP_IDLE_PAT_H4 = 0x174,
1210 SUNI_TXCP_IDLE_PAT_H5 = 0x178,
1211 SUNI_TXCP_IDLE_PAYLOAD = 0x17c,
1212 SUNI_E3_FRM_FRAM_OPTIONS = 0x180,
1213 SUNI_E3_FRM_MAINT_OPTIONS = 0x184,
1214 SUNI_E3_FRM_FRAM_INTR_ENBL = 0x188,
1215 SUNI_E3_FRM_FRAM_INTR_IND_STAT = 0x18c,
1216 SUNI_E3_FRM_MAINT_INTR_ENBL = 0x190,
1217 SUNI_E3_FRM_MAINT_INTR_IND = 0x194,
1218 SUNI_E3_FRM_MAINT_STAT = 0x198,
1219 SUNI_RESERVED4 = 0x19c,
1220 SUNI_E3_TRAN_FRAM_OPTIONS = 0x1a0,
1221 SUNI_E3_TRAN_STAT_DIAG_OPTIONS = 0x1a4,
1222 SUNI_E3_TRAN_BIP_8_ERR_MASK = 0x1a8,
1223 SUNI_E3_TRAN_MAINT_ADAPT_OPTS = 0x1ac,
1224 SUNI_TTB_CTRL = 0x1b0,
1225 SUNI_TTB_TRAIL_TRACE_ID_STAT = 0x1b4,
1226 SUNI_TTB_IND_ADDR = 0x1b8,
1227 SUNI_TTB_IND_DATA = 0x1bc,
1228 SUNI_TTB_EXP_PAYLOAD_TYPE = 0x1c0,
1229 SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT = 0x1c4,
1230 /* SUNI_PAD5 (0x7f - 0x71) */
1231 SUNI_MASTER_TEST = 0x200,
1232 /* SUNI_PAD6 (0xff - 0x80) */
1235 #define SUNI_PM7345_T suni_pm7345_t
1236 #define SUNI_PM7345 0x20 /* Suni chip type */
1237 #define SUNI_PM5346 0x30 /* Suni chip type */
1239 * SUNI_PM7345 Configuration
1241 #define SUNI_PM7345_CLB 0x01 /* Cell loopback */
1242 #define SUNI_PM7345_PLB 0x02 /* Payload loopback */
1243 #define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */
1244 #define SUNI_PM7345_LLB 0x80 /* Line loopback */
1245 #define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */
1246 #define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */
1247 #define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */
1248 #define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */
1250 * DS3 FRMR Interrupt Enable
1252 #define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */
1253 #define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */
1254 #define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */
1255 #define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/
1256 #define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */
1257 #define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/
1258 #define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */
1259 #define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */
1264 #define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */
1265 #define SUNI_DS3_REDV 0x40 /* DS3 RED state */
1266 #define SUNI_DS3_CBITV 0x20 /* Application ID channel state */
1267 #define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/
1268 #define SUNI_DS3_IDLV 0x08 /* Idle signal state */
1269 #define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/
1270 #define SUNI_DS3_OOFV 0x02 /* Out of frame state */
1271 #define SUNI_DS3_LOSV 0x01 /* Loss of signal state */
1274 * E3 FRMR Interrupt/Status
1276 #define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */
1277 #define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */
1278 #define SUNI_E3_LCVI 0x10 /* Line code violation intr */
1279 #define SUNI_E3_COFAI 0x08 /* Change of frame align intr */
1280 #define SUNI_E3_OOFI 0x04 /* Out of frame intr status */
1281 #define SUNI_E3_LOS 0x02 /* Loss of signal state */
1282 #define SUNI_E3_OOF 0x01 /* Out of frame state */
1285 * E3 FRMR Maintenance Status
1287 #define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/
1288 #define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */
1289 #define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/
1292 * RXCP Control/Status
1294 #define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */
1295 #define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */
1296 #define SUNI_DS3_HCSADD 0x20 /* Add coset poly */
1297 #define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/
1298 #define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */
1299 #define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */
1300 #define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */
1301 #define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */
1304 * RXCP Interrupt Enable/Status
1306 #define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */
1307 #define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */
1308 #define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */
1309 #define SUNI_DS3_OOCDI 0x10 /* SYNC state */
1310 #define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */
1311 #define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */
1312 #define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */
1313 #define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */
1315 ///////////////////SUNI_PM7345 PHY DEFINE END /////////////////////////////
1317 /* ia_eeprom define*/
1318 #define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/
1319 #define MEM_SIZE_128K 0x0000 /* board has 128k buffer */
1320 #define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */
1321 #define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */
1322 /* 0x3 to 0xF are reserved for future */
1324 #define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */
1325 #define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */
1326 #define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */
1327 #define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */
1329 #define NOVRAM_SIZE 64
1334 * Switches and defines for header files.
1336 * The following defines are used to turn on and off
1337 * various options in the header files. Primarily useful
1343 * a list of the commands that can be sent to the NOVRAM
1346 #define EXTEND 0x100
1347 #define IAWRITE 0x140
1348 #define IAREAD 0x180
1357 * these bits duplicate the hw_flip.h register settings
1358 * note: how the data in / out bits are defined in the flipper specification
1365 /***********************
1367 * This define ands the value and the current config register and puts
1368 * the result in the config register
1370 ***********************/
1372 #define CFG_AND(val) { \
1374 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1376 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1379 /***********************
1381 * This define ors the value and the current config register and puts
1382 * the result in the config register
1384 ***********************/
1386 #define CFG_OR(val) { \
1388 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1390 writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1393 /***********************
1395 * Send a command to the NOVRAM, the command is in cmd.
1397 * clear CE and SK. Then assert CE.
1398 * Clock each of the command bits out in the correct order with SK
1399 * exit with CE still asserted
1401 ***********************/
1403 #define NVRAM_CMD(cmd) { \
1406 CFG_AND(~(NVCE|NVSK)); \
1408 for (i=0; i<CMD_LEN; i++) { \
1409 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1414 /***********************
1416 * clear the CE, this must be used after each command is complete
1418 ***********************/
1420 #define NVRAM_CLR_CE {CFG_AND(~NVCE)}
1422 /***********************
1424 * clock the data bit in bitval out to the NOVRAM. The bitval must be
1425 * a 1 or 0, or the clockout operation is undefined
1427 ***********************/
1429 #define NVRAM_CLKOUT(bitval) { \
1431 CFG_OR((bitval) ? NVDI : 0); \
1436 /***********************
1438 * clock the data bit in and return a 1 or 0, depending on the value
1439 * that was received from the NOVRAM
1441 ***********************/
1443 #define NVRAM_CLKIN(value) { \
1447 _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \
1448 value = (_t & NVDO) ? 1 : 0; \
1452 #endif /* IPHASE_H */
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