1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef ARCH_X86_KVM_X86_H
3 #define ARCH_X86_KVM_X86_H
5 #include <linux/kvm_host.h>
7 #include <asm/pvclock.h>
8 #include "kvm_cache_regs.h"
9 #include "kvm_emulate.h"
11 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
13 bool failed = (consistency_check); \
15 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \
19 #define KVM_DEFAULT_PLE_GAP 128
20 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
21 #define KVM_DEFAULT_PLE_WINDOW_GROW 2
22 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0
23 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX
24 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX
25 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000
27 static inline unsigned int __grow_ple_window(unsigned int val,
28 unsigned int base, unsigned int modifier, unsigned int max)
40 return min(ret, (u64)max);
43 static inline unsigned int __shrink_ple_window(unsigned int val,
44 unsigned int base, unsigned int modifier, unsigned int min)
57 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL
59 int kvm_check_nested_events(struct kvm_vcpu *vcpu);
61 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu)
63 vcpu->arch.exception.pending = false;
64 vcpu->arch.exception.injected = false;
67 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector,
70 vcpu->arch.interrupt.injected = true;
71 vcpu->arch.interrupt.soft = soft;
72 vcpu->arch.interrupt.nr = vector;
75 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu)
77 vcpu->arch.interrupt.injected = false;
80 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu)
82 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected ||
83 vcpu->arch.nmi_injected;
86 static inline bool kvm_exception_is_soft(unsigned int nr)
88 return (nr == BP_VECTOR) || (nr == OF_VECTOR);
91 static inline bool is_protmode(struct kvm_vcpu *vcpu)
93 return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
96 static inline int is_long_mode(struct kvm_vcpu *vcpu)
99 return vcpu->arch.efer & EFER_LMA;
105 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu)
109 if (!is_long_mode(vcpu))
111 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
115 static inline bool is_la57_mode(struct kvm_vcpu *vcpu)
118 return (vcpu->arch.efer & EFER_LMA) &&
119 kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
125 static inline bool x86_exception_has_error_code(unsigned int vector)
127 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) |
128 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) |
129 BIT(PF_VECTOR) | BIT(AC_VECTOR);
131 return (1U << vector) & exception_has_error_code;
134 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu)
136 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
139 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
141 ++vcpu->stat.tlb_flush;
142 static_call(kvm_x86_tlb_flush_current)(vcpu);
145 static inline int is_pae(struct kvm_vcpu *vcpu)
147 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
150 static inline int is_pse(struct kvm_vcpu *vcpu)
152 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
155 static inline int is_paging(struct kvm_vcpu *vcpu)
157 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG));
160 static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
162 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
165 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
167 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
170 static inline u64 get_canonical(u64 la, u8 vaddr_bits)
172 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
175 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
177 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
180 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
181 gva_t gva, gfn_t gfn, unsigned access)
183 u64 gen = kvm_memslots(vcpu->kvm)->generation;
185 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
189 * If this is a shadow nested page table, the "GVA" is
192 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
193 vcpu->arch.mmio_access = access;
194 vcpu->arch.mmio_gfn = gfn;
195 vcpu->arch.mmio_gen = gen;
198 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu)
200 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation;
204 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we
205 * clear all mmio cache info.
207 #define MMIO_GVA_ANY (~(gva_t)0)
209 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva)
211 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK))
214 vcpu->arch.mmio_gva = 0;
217 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva)
219 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva &&
220 vcpu->arch.mmio_gva == (gva & PAGE_MASK))
226 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa)
228 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn &&
229 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT)
235 static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, int reg)
237 unsigned long val = kvm_register_read(vcpu, reg);
239 return is_64_bit_mode(vcpu) ? val : (u32)val;
242 static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
243 int reg, unsigned long val)
245 if (!is_64_bit_mode(vcpu))
247 return kvm_register_write(vcpu, reg, val);
250 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk)
252 return !(kvm->arch.disabled_quirks & quirk);
255 static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
257 return is_smm(vcpu) || static_call(kvm_x86_apic_init_signal_blocked)(vcpu);
260 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs);
261 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
263 u64 get_kvmclock_ns(struct kvm *kvm);
265 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
266 gva_t addr, void *val, unsigned int bytes,
267 struct x86_exception *exception);
269 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu,
270 gva_t addr, void *val, unsigned int bytes,
271 struct x86_exception *exception);
273 int handle_ud(struct kvm_vcpu *vcpu);
275 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
277 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
278 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
279 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
280 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
281 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata);
282 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
284 bool kvm_vector_hashing_enabled(void);
285 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
286 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
287 void *insn, int insn_len);
288 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
289 int emulation_type, void *insn, int insn_len);
290 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
292 extern u64 host_xcr0;
293 extern u64 supported_xcr0;
295 extern u64 supported_xss;
297 static inline bool kvm_mpx_supported(void)
299 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
300 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
303 extern unsigned int min_timer_period_us;
305 extern bool enable_vmware_backdoor;
307 extern int pi_inject_timer;
309 extern struct static_key kvm_no_apic_vcpu;
311 extern bool report_ignored_msrs;
313 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
315 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
316 vcpu->arch.virtual_tsc_shift);
319 /* Same "calling convention" as do_div:
320 * - divide (n << 32) by base
324 #define do_shl32_div32(n, base) \
327 asm("divl %2" : "=a" (__quot), "=d" (__rem) \
328 : "rm" (base), "0" (0), "1" ((u32) n)); \
333 static inline bool kvm_mwait_in_guest(struct kvm *kvm)
335 return kvm->arch.mwait_in_guest;
338 static inline bool kvm_hlt_in_guest(struct kvm *kvm)
340 return kvm->arch.hlt_in_guest;
343 static inline bool kvm_pause_in_guest(struct kvm *kvm)
345 return kvm->arch.pause_in_guest;
348 static inline bool kvm_cstate_in_guest(struct kvm *kvm)
350 return kvm->arch.cstate_in_guest;
353 DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
355 static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
357 __this_cpu_write(current_vcpu, vcpu);
360 static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu)
362 __this_cpu_write(current_vcpu, NULL);
366 static inline bool kvm_pat_valid(u64 data)
368 if (data & 0xF8F8F8F8F8F8F8F8ull)
370 /* 0, 1, 4, 5, 6, 7 are valid values. */
371 return (data | ((data & 0x0202020202020202ull) << 1)) == data;
374 static inline bool kvm_dr7_valid(u64 data)
376 /* Bits [63:32] are reserved */
377 return !(data >> 32);
379 static inline bool kvm_dr6_valid(u64 data)
381 /* Bits [63:32] are reserved */
382 return !(data >> 32);
386 * Trigger machine check on the host. We assume all the MSRs are already set up
387 * by the CPU and that we still run on the same CPU as the MCE occurred on.
388 * We pass a fake environment to the machine check handler because we want
389 * the guest to be always treated like user space, no matter what context
390 * it used internally.
392 static inline void kvm_machine_check(void)
394 #if defined(CONFIG_X86_MCE)
395 struct pt_regs regs = {
396 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
397 .flags = X86_EFLAGS_IF,
400 do_machine_check(®s);
404 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
405 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
406 int kvm_spec_ctrl_test_value(u64 value);
407 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
408 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
409 struct x86_exception *e);
410 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
411 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
414 * Internal error codes that are used to indicate that MSR emulation encountered
415 * an error that should result in #GP in the guest, unless userspace
418 #define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */
419 #define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */
421 #define __cr4_reserved_bits(__cpu_has, __c) \
423 u64 __reserved_bits = CR4_RESERVED_BITS; \
425 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
426 __reserved_bits |= X86_CR4_OSXSAVE; \
427 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
428 __reserved_bits |= X86_CR4_SMEP; \
429 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
430 __reserved_bits |= X86_CR4_SMAP; \
431 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
432 __reserved_bits |= X86_CR4_FSGSBASE; \
433 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
434 __reserved_bits |= X86_CR4_PKE; \
435 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
436 __reserved_bits |= X86_CR4_LA57; \
437 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \
438 __reserved_bits |= X86_CR4_UMIP; \
439 if (!__cpu_has(__c, X86_FEATURE_VMX)) \
440 __reserved_bits |= X86_CR4_VMXE; \
441 if (!__cpu_has(__c, X86_FEATURE_PCID)) \
442 __reserved_bits |= X86_CR4_PCIDE; \
446 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
448 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes,
450 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
451 unsigned int port, void *data, unsigned int count,