arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "mmu.h"
  22 #include "i8254.h"
  23 #include "tss.h"
  24 #include "kvm_cache_regs.h"
  25 #include "kvm_emulate.h"
  26 #include "x86.h"
  27 #include "cpuid.h"
  28 #include "pmu.h"
  29 #include "hyperv.h"
  30 #include "lapic.h"
  31
  32 #include <linux/clocksource.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/kvm.h>
  35 #include <linux/fs.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/export.h>
  38 #include <linux/moduleparam.h>
  39 #include <linux/mman.h>
  40 #include <linux/highmem.h>
  41 #include <linux/iommu.h>
  42 #include <linux/intel-iommu.h>
  43 #include <linux/cpufreq.h>
  44 #include <linux/user-return-notifier.h>
  45 #include <linux/srcu.h>
  46 #include <linux/slab.h>
  47 #include <linux/perf_event.h>
  48 #include <linux/uaccess.h>
  49 #include <linux/hash.h>
  50 #include <linux/pci.h>
  51 #include <linux/timekeeper_internal.h>
  52 #include <linux/pvclock_gtod.h>
  53 #include <linux/kvm_irqfd.h>
  54 #include <linux/irqbypass.h>
  55 #include <linux/sched/stat.h>
  56 #include <linux/sched/isolation.h>
  57 #include <linux/mem_encrypt.h>
  58
  59 #include <trace/events/kvm.h>
  60
  61 #include <asm/debugreg.h>
  62 #include <asm/msr.h>
  63 #include <asm/desc.h>
  64 #include <asm/mce.h>
  65 #include <linux/kernel_stat.h>
  66 #include <asm/fpu/internal.h> /* Ugh! */
  67 #include <asm/pvclock.h>
  68 #include <asm/div64.h>
  69 #include <asm/irq_remapping.h>
  70 #include <asm/mshyperv.h>
  71 #include <asm/hypervisor.h>
  72 #include <asm/intel_pt.h>
  73 #include <asm/emulate_prefix.h>
  74 #include <clocksource/hyperv_timer.h>
  75
  76 #define CREATE_TRACE_POINTS
  77 #include "trace.h"
  78
  79 #define MAX_IO_MSRS 256
  80 #define KVM_MAX_MCE_BANKS 32
  81 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  82 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  83
  84 #define emul_to_vcpu(ctxt) \
  85         ((struct kvm_vcpu *)(ctxt)->vcpu)
  86
  87 /* EFER defaults:
  88  * - enable syscall per default because its emulated by KVM
  89  * - enable LME and LMA per default on 64 bit KVM
  90  */
  91 #ifdef CONFIG_X86_64
  92 static
  93 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  94 #else
  95 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  96 #endif
  97
  98 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
  99
 100 #define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
 101 #define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
 102
 103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 104                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 105
 106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 107 static void process_nmi(struct kvm_vcpu *vcpu);
 108 static void enter_smm(struct kvm_vcpu *vcpu);
 109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 110 static void store_regs(struct kvm_vcpu *vcpu);
 111 static int sync_regs(struct kvm_vcpu *vcpu);
 112
 113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
 114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 115
 116 static bool __read_mostly ignore_msrs = 0;
 117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 118
 119 static bool __read_mostly report_ignored_msrs = true;
 120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 121
 122 unsigned int min_timer_period_us = 200;
 123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 124
 125 static bool __read_mostly kvmclock_periodic_sync = true;
 126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 127
 128 bool __read_mostly kvm_has_tsc_control;
 129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 130 u32  __read_mostly kvm_max_guest_tsc_khz;
 131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 132 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 134 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 138
 139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 140 static u32 __read_mostly tsc_tolerance_ppm = 250;
 141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 142
 143 /*
 144  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 145  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 146  * advancement entirely.  Any other value is used as-is and disables adaptive
 147  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 148  */
 149 static int __read_mostly lapic_timer_advance_ns = -1;
 150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 151
 152 static bool __read_mostly vector_hashing = true;
 153 module_param(vector_hashing, bool, S_IRUGO);
 154
 155 bool __read_mostly enable_vmware_backdoor = false;
 156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 158
 159 static bool __read_mostly force_emulation_prefix = false;
 160 module_param(force_emulation_prefix, bool, S_IRUGO);
 161
 162 int __read_mostly pi_inject_timer = -1;
 163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 164
 165 #define KVM_NR_SHARED_MSRS 16
 166
 167 struct kvm_shared_msrs_global {
 168         int nr;
 169         u32 msrs[KVM_NR_SHARED_MSRS];
 170 };
 171
 172 struct kvm_shared_msrs {
 173         struct user_return_notifier urn;
 174         bool registered;
 175         struct kvm_shared_msr_values {
 176                 u64 host;
 177                 u64 curr;
 178         } values[KVM_NR_SHARED_MSRS];
 179 };
 180
 181 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 182 static struct kvm_shared_msrs __percpu *shared_msrs;
 183
 184 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
 185                                 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
 186                                 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
 187                                 | XFEATURE_MASK_PKRU)
 188
 189 u64 __read_mostly host_efer;
 190 EXPORT_SYMBOL_GPL(host_efer);
 191
 192 static u64 __read_mostly host_xss;
 193 u64 __read_mostly supported_xss;
 194 EXPORT_SYMBOL_GPL(supported_xss);
 195
 196 struct kvm_stats_debugfs_item debugfs_entries[] = {
 197         { "pf_fixed", VCPU_STAT(pf_fixed) },
 198         { "pf_guest", VCPU_STAT(pf_guest) },
 199         { "tlb_flush", VCPU_STAT(tlb_flush) },
 200         { "invlpg", VCPU_STAT(invlpg) },
 201         { "exits", VCPU_STAT(exits) },
 202         { "io_exits", VCPU_STAT(io_exits) },
 203         { "mmio_exits", VCPU_STAT(mmio_exits) },
 204         { "signal_exits", VCPU_STAT(signal_exits) },
 205         { "irq_window", VCPU_STAT(irq_window_exits) },
 206         { "nmi_window", VCPU_STAT(nmi_window_exits) },
 207         { "halt_exits", VCPU_STAT(halt_exits) },
 208         { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
 209         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
 210         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
 211         { "halt_wakeup", VCPU_STAT(halt_wakeup) },
 212         { "hypercalls", VCPU_STAT(hypercalls) },
 213         { "request_irq", VCPU_STAT(request_irq_exits) },
 214         { "irq_exits", VCPU_STAT(irq_exits) },
 215         { "host_state_reload", VCPU_STAT(host_state_reload) },
 216         { "fpu_reload", VCPU_STAT(fpu_reload) },
 217         { "insn_emulation", VCPU_STAT(insn_emulation) },
 218         { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
 219         { "irq_injections", VCPU_STAT(irq_injections) },
 220         { "nmi_injections", VCPU_STAT(nmi_injections) },
 221         { "req_event", VCPU_STAT(req_event) },
 222         { "l1d_flush", VCPU_STAT(l1d_flush) },
 223         { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
 224         { "mmu_pte_write", VM_STAT(mmu_pte_write) },
 225         { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
 226         { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
 227         { "mmu_flooded", VM_STAT(mmu_flooded) },
 228         { "mmu_recycled", VM_STAT(mmu_recycled) },
 229         { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
 230         { "mmu_unsync", VM_STAT(mmu_unsync) },
 231         { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
 232         { "largepages", VM_STAT(lpages, .mode = 0444) },
 233         { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
 234         { "max_mmu_page_hash_collisions",
 235                 VM_STAT(max_mmu_page_hash_collisions) },
 236         { NULL }
 237 };
 238
 239 u64 __read_mostly host_xcr0;
 240 u64 __read_mostly supported_xcr0;
 241 EXPORT_SYMBOL_GPL(supported_xcr0);
 242
 243 struct kmem_cache *x86_fpu_cache;
 244 EXPORT_SYMBOL_GPL(x86_fpu_cache);
 245
 246 static struct kmem_cache *x86_emulator_cache;
 247
 248 static struct kmem_cache *kvm_alloc_emulator_cache(void)
 249 {
 250         unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
 251         unsigned int size = sizeof(struct x86_emulate_ctxt);
 252
 253         return kmem_cache_create_usercopy("x86_emulator", size,
 254                                           __alignof__(struct x86_emulate_ctxt),
 255                                           SLAB_ACCOUNT, useroffset,
 256                                           size - useroffset, NULL);
 257 }
 258
 259 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 260
 261 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 262 {
 263         int i;
 264         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
 265                 vcpu->arch.apf.gfns[i] = ~0;
 266 }
 267
 268 static void kvm_on_user_return(struct user_return_notifier *urn)
 269 {
 270         unsigned slot;
 271         struct kvm_shared_msrs *locals
 272                 = container_of(urn, struct kvm_shared_msrs, urn);
 273         struct kvm_shared_msr_values *values;
 274         unsigned long flags;
 275
 276         /*
 277          * Disabling irqs at this point since the following code could be
 278          * interrupted and executed through kvm_arch_hardware_disable()
 279          */
 280         local_irq_save(flags);
 281         if (locals->registered) {
 282                 locals->registered = false;
 283                 user_return_notifier_unregister(urn);
 284         }
 285         local_irq_restore(flags);
 286         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 287                 values = &locals->values[slot];
 288                 if (values->host != values->curr) {
 289                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 290                         values->curr = values->host;
 291                 }
 292         }
 293 }
 294
 295 void kvm_define_shared_msr(unsigned slot, u32 msr)
 296 {
 297         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 298         shared_msrs_global.msrs[slot] = msr;
 299         if (slot >= shared_msrs_global.nr)
 300                 shared_msrs_global.nr = slot + 1;
 301 }
 302 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 303
 304 static void kvm_shared_msr_cpu_online(void)
 305 {
 306         unsigned int cpu = smp_processor_id();
 307         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 308         u64 value;
 309         int i;
 310
 311         for (i = 0; i < shared_msrs_global.nr; ++i) {
 312                 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
 313                 smsr->values[i].host = value;
 314                 smsr->values[i].curr = value;
 315         }
 316 }
 317
 318 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 319 {
 320         unsigned int cpu = smp_processor_id();
 321         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 322         int err;
 323
 324         value = (value & mask) | (smsr->values[slot].host & ~mask);
 325         if (value == smsr->values[slot].curr)
 326                 return 0;
 327         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 328         if (err)
 329                 return 1;
 330
 331         smsr->values[slot].curr = value;
 332         if (!smsr->registered) {
 333                 smsr->urn.on_user_return = kvm_on_user_return;
 334                 user_return_notifier_register(&smsr->urn);
 335                 smsr->registered = true;
 336         }
 337         return 0;
 338 }
 339 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 340
 341 static void drop_user_return_notifiers(void)
 342 {
 343         unsigned int cpu = smp_processor_id();
 344         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 345
 346         if (smsr->registered)
 347                 kvm_on_user_return(&smsr->urn);
 348 }
 349
 350 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 351 {
 352         return vcpu->arch.apic_base;
 353 }
 354 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 355
 356 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 357 {
 358         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 359 }
 360 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 361
 362 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 363 {
 364         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 365         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 366         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 367                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 368
 369         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 370                 return 1;
 371         if (!msr_info->host_initiated) {
 372                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 373                         return 1;
 374                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 375                         return 1;
 376         }
 377
 378         kvm_lapic_set_base(vcpu, msr_info->data);
 379         kvm_recalculate_apic_map(vcpu->kvm);
 380         return 0;
 381 }
 382 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 383
 384 asmlinkage __visible void kvm_spurious_fault(void)
 385 {
 386         /* Fault while not rebooting.  We want the trace. */
 387         BUG_ON(!kvm_rebooting);
 388 }
 389 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 390
 391 #define EXCPT_BENIGN            0
 392 #define EXCPT_CONTRIBUTORY      1
 393 #define EXCPT_PF                2
 394
 395 static int exception_class(int vector)
 396 {
 397         switch (vector) {
 398         case PF_VECTOR:
 399                 return EXCPT_PF;
 400         case DE_VECTOR:
 401         case TS_VECTOR:
 402         case NP_VECTOR:
 403         case SS_VECTOR:
 404         case GP_VECTOR:
 405                 return EXCPT_CONTRIBUTORY;
 406         default:
 407                 break;
 408         }
 409         return EXCPT_BENIGN;
 410 }
 411
 412 #define EXCPT_FAULT             0
 413 #define EXCPT_TRAP              1
 414 #define EXCPT_ABORT             2
 415 #define EXCPT_INTERRUPT         3
 416
 417 static int exception_type(int vector)
 418 {
 419         unsigned int mask;
 420
 421         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 422                 return EXCPT_INTERRUPT;
 423
 424         mask = 1 << vector;
 425
 426         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 427         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 428                 return EXCPT_TRAP;
 429
 430         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 431                 return EXCPT_ABORT;
 432
 433         /* Reserved exceptions will result in fault */
 434         return EXCPT_FAULT;
 435 }
 436
 437 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 438 {
 439         unsigned nr = vcpu->arch.exception.nr;
 440         bool has_payload = vcpu->arch.exception.has_payload;
 441         unsigned long payload = vcpu->arch.exception.payload;
 442
 443         if (!has_payload)
 444                 return;
 445
 446         switch (nr) {
 447         case DB_VECTOR:
 448                 /*
 449                  * "Certain debug exceptions may clear bit 0-3.  The
 450                  * remaining contents of the DR6 register are never
 451                  * cleared by the processor".
 452                  */
 453                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 454                 /*
 455                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 456                  */
 457                 vcpu->arch.dr6 |= DR6_RTM;
 458                 vcpu->arch.dr6 |= payload;
 459                 /*
 460                  * Bit 16 should be set in the payload whenever the #DB
 461                  * exception should clear DR6.RTM. This makes the payload
 462                  * compatible with the pending debug exceptions under VMX.
 463                  * Though not currently documented in the SDM, this also
 464                  * makes the payload compatible with the exit qualification
 465                  * for #DB exceptions under VMX.
 466                  */
 467                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 468
 469                 /*
 470                  * The #DB payload is defined as compatible with the 'pending
 471                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 472                  * defined in the 'pending debug exceptions' field (enabled
 473                  * breakpoint), it is reserved and must be zero in DR6.
 474                  */
 475                 vcpu->arch.dr6 &= ~BIT(12);
 476                 break;
 477         case PF_VECTOR:
 478                 vcpu->arch.cr2 = payload;
 479                 break;
 480         }
 481
 482         vcpu->arch.exception.has_payload = false;
 483         vcpu->arch.exception.payload = 0;
 484 }
 485 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 486
 487 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 488                 unsigned nr, bool has_error, u32 error_code,
 489                 bool has_payload, unsigned long payload, bool reinject)
 490 {
 491         u32 prev_nr;
 492         int class1, class2;
 493
 494         kvm_make_request(KVM_REQ_EVENT, vcpu);
 495
 496         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 497         queue:
 498                 if (has_error && !is_protmode(vcpu))
 499                         has_error = false;
 500                 if (reinject) {
 501                         /*
 502                          * On vmentry, vcpu->arch.exception.pending is only
 503                          * true if an event injection was blocked by
 504                          * nested_run_pending.  In that case, however,
 505                          * vcpu_enter_guest requests an immediate exit,
 506                          * and the guest shouldn't proceed far enough to
 507                          * need reinjection.
 508                          */
 509                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 510                         vcpu->arch.exception.injected = true;
 511                         if (WARN_ON_ONCE(has_payload)) {
 512                                 /*
 513                                  * A reinjected event has already
 514                                  * delivered its payload.
 515                                  */
 516                                 has_payload = false;
 517                                 payload = 0;
 518                         }
 519                 } else {
 520                         vcpu->arch.exception.pending = true;
 521                         vcpu->arch.exception.injected = false;
 522                 }
 523                 vcpu->arch.exception.has_error_code = has_error;
 524                 vcpu->arch.exception.nr = nr;
 525                 vcpu->arch.exception.error_code = error_code;
 526                 vcpu->arch.exception.has_payload = has_payload;
 527                 vcpu->arch.exception.payload = payload;
 528                 if (!is_guest_mode(vcpu))
 529                         kvm_deliver_exception_payload(vcpu);
 530                 return;
 531         }
 532
 533         /* to check exception */
 534         prev_nr = vcpu->arch.exception.nr;
 535         if (prev_nr == DF_VECTOR) {
 536                 /* triple fault -> shutdown */
 537                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 538                 return;
 539         }
 540         class1 = exception_class(prev_nr);
 541         class2 = exception_class(nr);
 542         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 543                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 544                 /*
 545                  * Generate double fault per SDM Table 5-5.  Set
 546                  * exception.pending = true so that the double fault
 547                  * can trigger a nested vmexit.
 548                  */
 549                 vcpu->arch.exception.pending = true;
 550                 vcpu->arch.exception.injected = false;
 551                 vcpu->arch.exception.has_error_code = true;
 552                 vcpu->arch.exception.nr = DF_VECTOR;
 553                 vcpu->arch.exception.error_code = 0;
 554                 vcpu->arch.exception.has_payload = false;
 555                 vcpu->arch.exception.payload = 0;
 556         } else
 557                 /* replace previous exception with a new one in a hope
 558                    that instruction re-execution will regenerate lost
 559                    exception */
 560                 goto queue;
 561 }
 562
 563 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 564 {
 565         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 566 }
 567 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 568
 569 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 570 {
 571         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 572 }
 573 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 574
 575 static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 576                                   unsigned long payload)
 577 {
 578         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 579 }
 580
 581 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 582                                     u32 error_code, unsigned long payload)
 583 {
 584         kvm_multiple_exception(vcpu, nr, true, error_code,
 585                                true, payload, false);
 586 }
 587
 588 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 589 {
 590         if (err)
 591                 kvm_inject_gp(vcpu, 0);
 592         else
 593                 return kvm_skip_emulated_instruction(vcpu);
 594
 595         return 1;
 596 }
 597 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 598
 599 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 600 {
 601         ++vcpu->stat.pf_guest;
 602         vcpu->arch.exception.nested_apf =
 603                 is_guest_mode(vcpu) && fault->async_page_fault;
 604         if (vcpu->arch.exception.nested_apf) {
 605                 vcpu->arch.apf.nested_apf_token = fault->address;
 606                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 607         } else {
 608                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 609                                         fault->address);
 610         }
 611 }
 612 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 613
 614 static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 615 {
 616         if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
 617                 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
 618         else
 619                 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
 620
 621         return fault->nested_page_fault;
 622 }
 623
 624 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 625 {
 626         atomic_inc(&vcpu->arch.nmi_queued);
 627         kvm_make_request(KVM_REQ_NMI, vcpu);
 628 }
 629 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 630
 631 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 632 {
 633         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 634 }
 635 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 636
 637 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 638 {
 639         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 640 }
 641 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 642
 643 /*
 644  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 645  * a #GP and return false.
 646  */
 647 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 648 {
 649         if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
 650                 return true;
 651         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 652         return false;
 653 }
 654 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 655
 656 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 657 {
 658         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 659                 return true;
 660
 661         kvm_queue_exception(vcpu, UD_VECTOR);
 662         return false;
 663 }
 664 EXPORT_SYMBOL_GPL(kvm_require_dr);
 665
 666 /*
 667  * This function will be used to read from the physical memory of the currently
 668  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 669  * can read from guest physical or from the guest's guest physical memory.
 670  */
 671 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 672                             gfn_t ngfn, void *data, int offset, int len,
 673                             u32 access)
 674 {
 675         struct x86_exception exception;
 676         gfn_t real_gfn;
 677         gpa_t ngpa;
 678
 679         ngpa     = gfn_to_gpa(ngfn);
 680         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 681         if (real_gfn == UNMAPPED_GVA)
 682                 return -EFAULT;
 683
 684         real_gfn = gpa_to_gfn(real_gfn);
 685
 686         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 687 }
 688 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 689
 690 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 691                                void *data, int offset, int len, u32 access)
 692 {
 693         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 694                                        data, offset, len, access);
 695 }
 696
 697 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 698 {
 699         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 700                rsvd_bits(1, 2);
 701 }
 702
 703 /*
 704  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 705  */
 706 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 707 {
 708         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 709         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 710         int i;
 711         int ret;
 712         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 713
 714         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 715                                       offset * sizeof(u64), sizeof(pdpte),
 716                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 717         if (ret < 0) {
 718                 ret = 0;
 719                 goto out;
 720         }
 721         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 722                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 723                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 724                         ret = 0;
 725                         goto out;
 726                 }
 727         }
 728         ret = 1;
 729
 730         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 731         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 732
 733 out:
 734
 735         return ret;
 736 }
 737 EXPORT_SYMBOL_GPL(load_pdptrs);
 738
 739 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 740 {
 741         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 742         int offset;
 743         gfn_t gfn;
 744         int r;
 745
 746         if (!is_pae_paging(vcpu))
 747                 return false;
 748
 749         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 750                 return true;
 751
 752         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 753         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 754         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 755                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 756         if (r < 0)
 757                 return true;
 758
 759         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 760 }
 761 EXPORT_SYMBOL_GPL(pdptrs_changed);
 762
 763 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 764 {
 765         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 766         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 767
 768         cr0 |= X86_CR0_ET;
 769
 770 #ifdef CONFIG_X86_64
 771         if (cr0 & 0xffffffff00000000UL)
 772                 return 1;
 773 #endif
 774
 775         cr0 &= ~CR0_RESERVED_BITS;
 776
 777         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 778                 return 1;
 779
 780         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 781                 return 1;
 782
 783         if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 784 #ifdef CONFIG_X86_64
 785                 if ((vcpu->arch.efer & EFER_LME)) {
 786                         int cs_db, cs_l;
 787
 788                         if (!is_pae(vcpu))
 789                                 return 1;
 790                         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 791                         if (cs_l)
 792                                 return 1;
 793                 } else
 794 #endif
 795                 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 796                                                  kvm_read_cr3(vcpu)))
 797                         return 1;
 798         }
 799
 800         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 801                 return 1;
 802
 803         kvm_x86_ops.set_cr0(vcpu, cr0);
 804
 805         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 806                 kvm_clear_async_pf_completion_queue(vcpu);
 807                 kvm_async_pf_hash_reset(vcpu);
 808         }
 809
 810         if ((cr0 ^ old_cr0) & update_bits)
 811                 kvm_mmu_reset_context(vcpu);
 812
 813         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 814             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 815             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 816                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 817
 818         return 0;
 819 }
 820 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 821
 822 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 823 {
 824         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 825 }
 826 EXPORT_SYMBOL_GPL(kvm_lmsw);
 827
 828 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 829 {
 830         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 831
 832                 if (vcpu->arch.xcr0 != host_xcr0)
 833                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 834
 835                 if (vcpu->arch.xsaves_enabled &&
 836                     vcpu->arch.ia32_xss != host_xss)
 837                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 838         }
 839 }
 840 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 841
 842 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 843 {
 844         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 845
 846                 if (vcpu->arch.xcr0 != host_xcr0)
 847                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 848
 849                 if (vcpu->arch.xsaves_enabled &&
 850                     vcpu->arch.ia32_xss != host_xss)
 851                         wrmsrl(MSR_IA32_XSS, host_xss);
 852         }
 853
 854 }
 855 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 856
 857 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 858 {
 859         u64 xcr0 = xcr;
 860         u64 old_xcr0 = vcpu->arch.xcr0;
 861         u64 valid_bits;
 862
 863         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 864         if (index != XCR_XFEATURE_ENABLED_MASK)
 865                 return 1;
 866         if (!(xcr0 & XFEATURE_MASK_FP))
 867                 return 1;
 868         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 869                 return 1;
 870
 871         /*
 872          * Do not allow the guest to set bits that we do not support
 873          * saving.  However, xcr0 bit 0 is always set, even if the
 874          * emulated CPU does not support XSAVE (see fx_init).
 875          */
 876         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 877         if (xcr0 & ~valid_bits)
 878                 return 1;
 879
 880         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 881             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 882                 return 1;
 883
 884         if (xcr0 & XFEATURE_MASK_AVX512) {
 885                 if (!(xcr0 & XFEATURE_MASK_YMM))
 886                         return 1;
 887                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 888                         return 1;
 889         }
 890         vcpu->arch.xcr0 = xcr0;
 891
 892         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 893                 kvm_update_cpuid(vcpu);
 894         return 0;
 895 }
 896
 897 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 898 {
 899         if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
 900             __kvm_set_xcr(vcpu, index, xcr)) {
 901                 kvm_inject_gp(vcpu, 0);
 902                 return 1;
 903         }
 904         return 0;
 905 }
 906 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 907
 908 #define __cr4_reserved_bits(__cpu_has, __c)             \
 909 ({                                                      \
 910         u64 __reserved_bits = CR4_RESERVED_BITS;        \
 911                                                         \
 912         if (!__cpu_has(__c, X86_FEATURE_XSAVE))         \
 913                 __reserved_bits |= X86_CR4_OSXSAVE;     \
 914         if (!__cpu_has(__c, X86_FEATURE_SMEP))          \
 915                 __reserved_bits |= X86_CR4_SMEP;        \
 916         if (!__cpu_has(__c, X86_FEATURE_SMAP))          \
 917                 __reserved_bits |= X86_CR4_SMAP;        \
 918         if (!__cpu_has(__c, X86_FEATURE_FSGSBASE))      \
 919                 __reserved_bits |= X86_CR4_FSGSBASE;    \
 920         if (!__cpu_has(__c, X86_FEATURE_PKU))           \
 921                 __reserved_bits |= X86_CR4_PKE;         \
 922         if (!__cpu_has(__c, X86_FEATURE_LA57))          \
 923                 __reserved_bits |= X86_CR4_LA57;        \
 924         if (!__cpu_has(__c, X86_FEATURE_UMIP))          \
 925                 __reserved_bits |= X86_CR4_UMIP;        \
 926         __reserved_bits;                                \
 927 })
 928
 929 static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
 930 {
 931         u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
 932
 933         if (kvm_cpu_cap_has(X86_FEATURE_LA57))
 934                 reserved_bits &= ~X86_CR4_LA57;
 935
 936         if (kvm_cpu_cap_has(X86_FEATURE_UMIP))
 937                 reserved_bits &= ~X86_CR4_UMIP;
 938
 939         return reserved_bits;
 940 }
 941
 942 static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 943 {
 944         if (cr4 & cr4_reserved_bits)
 945                 return -EINVAL;
 946
 947         if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
 948                 return -EINVAL;
 949
 950         return 0;
 951 }
 952
 953 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 954 {
 955         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 956         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 957                                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
 958
 959         if (kvm_valid_cr4(vcpu, cr4))
 960                 return 1;
 961
 962         if (is_long_mode(vcpu)) {
 963                 if (!(cr4 & X86_CR4_PAE))
 964                         return 1;
 965         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 966                    && ((cr4 ^ old_cr4) & pdptr_bits)
 967                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 968                                    kvm_read_cr3(vcpu)))
 969                 return 1;
 970
 971         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 972                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 973                         return 1;
 974
 975                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 976                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
 977                         return 1;
 978         }
 979
 980         if (kvm_x86_ops.set_cr4(vcpu, cr4))
 981                 return 1;
 982
 983         if (((cr4 ^ old_cr4) & pdptr_bits) ||
 984             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
 985                 kvm_mmu_reset_context(vcpu);
 986
 987         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
 988                 kvm_update_cpuid(vcpu);
 989
 990         return 0;
 991 }
 992 EXPORT_SYMBOL_GPL(kvm_set_cr4);
 993
 994 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 995 {
 996         bool skip_tlb_flush = false;
 997 #ifdef CONFIG_X86_64
 998         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
 999
1000         if (pcid_enabled) {
1001                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1002                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1003         }
1004 #endif
1005
1006         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1007                 if (!skip_tlb_flush) {
1008                         kvm_mmu_sync_roots(vcpu);
1009                         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1010                 }
1011                 return 0;
1012         }
1013
1014         if (is_long_mode(vcpu) &&
1015             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1016                 return 1;
1017         else if (is_pae_paging(vcpu) &&
1018                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1019                 return 1;
1020
1021         kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
1022         vcpu->arch.cr3 = cr3;
1023         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1024
1025         return 0;
1026 }
1027 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1028
1029 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1030 {
1031         if (cr8 & CR8_RESERVED_BITS)
1032                 return 1;
1033         if (lapic_in_kernel(vcpu))
1034                 kvm_lapic_set_tpr(vcpu, cr8);
1035         else
1036                 vcpu->arch.cr8 = cr8;
1037         return 0;
1038 }
1039 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1040
1041 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1042 {
1043         if (lapic_in_kernel(vcpu))
1044                 return kvm_lapic_get_cr8(vcpu);
1045         else
1046                 return vcpu->arch.cr8;
1047 }
1048 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1049
1050 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1051 {
1052         int i;
1053
1054         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1055                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1056                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1057                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1058         }
1059 }
1060
1061 static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1062 {
1063         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1064                 kvm_x86_ops.set_dr6(vcpu, vcpu->arch.dr6);
1065 }
1066
1067 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1068 {
1069         unsigned long dr7;
1070
1071         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1072                 dr7 = vcpu->arch.guest_debug_dr7;
1073         else
1074                 dr7 = vcpu->arch.dr7;
1075         kvm_x86_ops.set_dr7(vcpu, dr7);
1076         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1077         if (dr7 & DR7_BP_EN_MASK)
1078                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1079 }
1080
1081 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1082 {
1083         u64 fixed = DR6_FIXED_1;
1084
1085         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1086                 fixed |= DR6_RTM;
1087         return fixed;
1088 }
1089
1090 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1091 {
1092         size_t size = ARRAY_SIZE(vcpu->arch.db);
1093
1094         switch (dr) {
1095         case 0 ... 3:
1096                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1097                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1098                         vcpu->arch.eff_db[dr] = val;
1099                 break;
1100         case 4:
1101                 /* fall through */
1102         case 6:
1103                 if (val & 0xffffffff00000000ULL)
1104                         return -1; /* #GP */
1105                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1106                 kvm_update_dr6(vcpu);
1107                 break;
1108         case 5:
1109                 /* fall through */
1110         default: /* 7 */
1111                 if (!kvm_dr7_valid(val))
1112                         return -1; /* #GP */
1113                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1114                 kvm_update_dr7(vcpu);
1115                 break;
1116         }
1117
1118         return 0;
1119 }
1120
1121 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1122 {
1123         if (__kvm_set_dr(vcpu, dr, val)) {
1124                 kvm_inject_gp(vcpu, 0);
1125                 return 1;
1126         }
1127         return 0;
1128 }
1129 EXPORT_SYMBOL_GPL(kvm_set_dr);
1130
1131 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1132 {
1133         size_t size = ARRAY_SIZE(vcpu->arch.db);
1134
1135         switch (dr) {
1136         case 0 ... 3:
1137                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1138                 break;
1139         case 4:
1140                 /* fall through */
1141         case 6:
1142                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1143                         *val = vcpu->arch.dr6;
1144                 else
1145                         *val = kvm_x86_ops.get_dr6(vcpu);
1146                 break;
1147         case 5:
1148                 /* fall through */
1149         default: /* 7 */
1150                 *val = vcpu->arch.dr7;
1151                 break;
1152         }
1153         return 0;
1154 }
1155 EXPORT_SYMBOL_GPL(kvm_get_dr);
1156
1157 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1158 {
1159         u32 ecx = kvm_rcx_read(vcpu);
1160         u64 data;
1161         int err;
1162
1163         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1164         if (err)
1165                 return err;
1166         kvm_rax_write(vcpu, (u32)data);
1167         kvm_rdx_write(vcpu, data >> 32);
1168         return err;
1169 }
1170 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1171
1172 /*
1173  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1174  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1175  *
1176  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1177  * extract the supported MSRs from the related const lists.
1178  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1179  * capabilities of the host cpu. This capabilities test skips MSRs that are
1180  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1181  * may depend on host virtualization features rather than host cpu features.
1182  */
1183
1184 static const u32 msrs_to_save_all[] = {
1185         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1186         MSR_STAR,
1187 #ifdef CONFIG_X86_64
1188         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1189 #endif
1190         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1191         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1192         MSR_IA32_SPEC_CTRL,
1193         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1194         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1195         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1196         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1197         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1198         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1199         MSR_IA32_UMWAIT_CONTROL,
1200
1201         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1202         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1203         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1204         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1205         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1206         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1207         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1208         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1209         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1210         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1211         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1212         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1213         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1214         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1215         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1216         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1217         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1218         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1219         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1220         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1221         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1222         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1223 };
1224
1225 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1226 static unsigned num_msrs_to_save;
1227
1228 static const u32 emulated_msrs_all[] = {
1229         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1230         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1231         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1232         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1233         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1234         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1235         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1236         HV_X64_MSR_RESET,
1237         HV_X64_MSR_VP_INDEX,
1238         HV_X64_MSR_VP_RUNTIME,
1239         HV_X64_MSR_SCONTROL,
1240         HV_X64_MSR_STIMER0_CONFIG,
1241         HV_X64_MSR_VP_ASSIST_PAGE,
1242         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1243         HV_X64_MSR_TSC_EMULATION_STATUS,
1244
1245         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1246         MSR_KVM_PV_EOI_EN,
1247
1248         MSR_IA32_TSC_ADJUST,
1249         MSR_IA32_TSCDEADLINE,
1250         MSR_IA32_ARCH_CAPABILITIES,
1251         MSR_IA32_MISC_ENABLE,
1252         MSR_IA32_MCG_STATUS,
1253         MSR_IA32_MCG_CTL,
1254         MSR_IA32_MCG_EXT_CTL,
1255         MSR_IA32_SMBASE,
1256         MSR_SMI_COUNT,
1257         MSR_PLATFORM_INFO,
1258         MSR_MISC_FEATURES_ENABLES,
1259         MSR_AMD64_VIRT_SPEC_CTRL,
1260         MSR_IA32_POWER_CTL,
1261         MSR_IA32_UCODE_REV,
1262
1263         /*
1264          * The following list leaves out MSRs whose values are determined
1265          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1266          * We always support the "true" VMX control MSRs, even if the host
1267          * processor does not, so I am putting these registers here rather
1268          * than in msrs_to_save_all.
1269          */
1270         MSR_IA32_VMX_BASIC,
1271         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1272         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1273         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1274         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1275         MSR_IA32_VMX_MISC,
1276         MSR_IA32_VMX_CR0_FIXED0,
1277         MSR_IA32_VMX_CR4_FIXED0,
1278         MSR_IA32_VMX_VMCS_ENUM,
1279         MSR_IA32_VMX_PROCBASED_CTLS2,
1280         MSR_IA32_VMX_EPT_VPID_CAP,
1281         MSR_IA32_VMX_VMFUNC,
1282
1283         MSR_K7_HWCR,
1284         MSR_KVM_POLL_CONTROL,
1285 };
1286
1287 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1288 static unsigned num_emulated_msrs;
1289
1290 /*
1291  * List of msr numbers which are used to expose MSR-based features that
1292  * can be used by a hypervisor to validate requested CPU features.
1293  */
1294 static const u32 msr_based_features_all[] = {
1295         MSR_IA32_VMX_BASIC,
1296         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1297         MSR_IA32_VMX_PINBASED_CTLS,
1298         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1299         MSR_IA32_VMX_PROCBASED_CTLS,
1300         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1301         MSR_IA32_VMX_EXIT_CTLS,
1302         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1303         MSR_IA32_VMX_ENTRY_CTLS,
1304         MSR_IA32_VMX_MISC,
1305         MSR_IA32_VMX_CR0_FIXED0,
1306         MSR_IA32_VMX_CR0_FIXED1,
1307         MSR_IA32_VMX_CR4_FIXED0,
1308         MSR_IA32_VMX_CR4_FIXED1,
1309         MSR_IA32_VMX_VMCS_ENUM,
1310         MSR_IA32_VMX_PROCBASED_CTLS2,
1311         MSR_IA32_VMX_EPT_VPID_CAP,
1312         MSR_IA32_VMX_VMFUNC,
1313
1314         MSR_F10H_DECFG,
1315         MSR_IA32_UCODE_REV,
1316         MSR_IA32_ARCH_CAPABILITIES,
1317 };
1318
1319 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1320 static unsigned int num_msr_based_features;
1321
1322 static u64 kvm_get_arch_capabilities(void)
1323 {
1324         u64 data = 0;
1325
1326         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1327                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1328
1329         /*
1330          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1331          * the nested hypervisor runs with NX huge pages.  If it is not,
1332          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1333          * L1 guests, so it need not worry about its own (L2) guests.
1334          */
1335         data |= ARCH_CAP_PSCHANGE_MC_NO;
1336
1337         /*
1338          * If we're doing cache flushes (either "always" or "cond")
1339          * we will do one whenever the guest does a vmlaunch/vmresume.
1340          * If an outer hypervisor is doing the cache flush for us
1341          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1342          * capability to the guest too, and if EPT is disabled we're not
1343          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1344          * require a nested hypervisor to do a flush of its own.
1345          */
1346         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1347                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1348
1349         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1350                 data |= ARCH_CAP_RDCL_NO;
1351         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1352                 data |= ARCH_CAP_SSB_NO;
1353         if (!boot_cpu_has_bug(X86_BUG_MDS))
1354                 data |= ARCH_CAP_MDS_NO;
1355
1356         /*
1357          * On TAA affected systems:
1358          *      - nothing to do if TSX is disabled on the host.
1359          *      - we emulate TSX_CTRL if present on the host.
1360          *        This lets the guest use VERW to clear CPU buffers.
1361          */
1362         if (!boot_cpu_has(X86_FEATURE_RTM))
1363                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1364         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1365                 data |= ARCH_CAP_TAA_NO;
1366
1367         return data;
1368 }
1369
1370 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1371 {
1372         switch (msr->index) {
1373         case MSR_IA32_ARCH_CAPABILITIES:
1374                 msr->data = kvm_get_arch_capabilities();
1375                 break;
1376         case MSR_IA32_UCODE_REV:
1377                 rdmsrl_safe(msr->index, &msr->data);
1378                 break;
1379         default:
1380                 if (kvm_x86_ops.get_msr_feature(msr))
1381                         return 1;
1382         }
1383         return 0;
1384 }
1385
1386 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1387 {
1388         struct kvm_msr_entry msr;
1389         int r;
1390
1391         msr.index = index;
1392         r = kvm_get_msr_feature(&msr);
1393         if (r)
1394                 return r;
1395
1396         *data = msr.data;
1397
1398         return 0;
1399 }
1400
1401 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1402 {
1403         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1404                 return false;
1405
1406         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1407                 return false;
1408
1409         if (efer & (EFER_LME | EFER_LMA) &&
1410             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1411                 return false;
1412
1413         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1414                 return false;
1415
1416         return true;
1417
1418 }
1419 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1420 {
1421         if (efer & efer_reserved_bits)
1422                 return false;
1423
1424         return __kvm_valid_efer(vcpu, efer);
1425 }
1426 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1427
1428 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1429 {
1430         u64 old_efer = vcpu->arch.efer;
1431         u64 efer = msr_info->data;
1432
1433         if (efer & efer_reserved_bits)
1434                 return 1;
1435
1436         if (!msr_info->host_initiated) {
1437                 if (!__kvm_valid_efer(vcpu, efer))
1438                         return 1;
1439
1440                 if (is_paging(vcpu) &&
1441                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1442                         return 1;
1443         }
1444
1445         efer &= ~EFER_LMA;
1446         efer |= vcpu->arch.efer & EFER_LMA;
1447
1448         kvm_x86_ops.set_efer(vcpu, efer);
1449
1450         /* Update reserved bits */
1451         if ((efer ^ old_efer) & EFER_NX)
1452                 kvm_mmu_reset_context(vcpu);
1453
1454         return 0;
1455 }
1456
1457 void kvm_enable_efer_bits(u64 mask)
1458 {
1459        efer_reserved_bits &= ~mask;
1460 }
1461 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1462
1463 /*
1464  * Write @data into the MSR specified by @index.  Select MSR specific fault
1465  * checks are bypassed if @host_initiated is %true.
1466  * Returns 0 on success, non-0 otherwise.
1467  * Assumes vcpu_load() was already called.
1468  */
1469 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1470                          bool host_initiated)
1471 {
1472         struct msr_data msr;
1473
1474         switch (index) {
1475         case MSR_FS_BASE:
1476         case MSR_GS_BASE:
1477         case MSR_KERNEL_GS_BASE:
1478         case MSR_CSTAR:
1479         case MSR_LSTAR:
1480                 if (is_noncanonical_address(data, vcpu))
1481                         return 1;
1482                 break;
1483         case MSR_IA32_SYSENTER_EIP:
1484         case MSR_IA32_SYSENTER_ESP:
1485                 /*
1486                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1487                  * non-canonical address is written on Intel but not on
1488                  * AMD (which ignores the top 32-bits, because it does
1489                  * not implement 64-bit SYSENTER).
1490                  *
1491                  * 64-bit code should hence be able to write a non-canonical
1492                  * value on AMD.  Making the address canonical ensures that
1493                  * vmentry does not fail on Intel after writing a non-canonical
1494                  * value, and that something deterministic happens if the guest
1495                  * invokes 64-bit SYSENTER.
1496                  */
1497                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1498         }
1499
1500         msr.data = data;
1501         msr.index = index;
1502         msr.host_initiated = host_initiated;
1503
1504         return kvm_x86_ops.set_msr(vcpu, &msr);
1505 }
1506
1507 /*
1508  * Read the MSR specified by @index into @data.  Select MSR specific fault
1509  * checks are bypassed if @host_initiated is %true.
1510  * Returns 0 on success, non-0 otherwise.
1511  * Assumes vcpu_load() was already called.
1512  */
1513 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1514                   bool host_initiated)
1515 {
1516         struct msr_data msr;
1517         int ret;
1518
1519         msr.index = index;
1520         msr.host_initiated = host_initiated;
1521
1522         ret = kvm_x86_ops.get_msr(vcpu, &msr);
1523         if (!ret)
1524                 *data = msr.data;
1525         return ret;
1526 }
1527
1528 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1529 {
1530         return __kvm_get_msr(vcpu, index, data, false);
1531 }
1532 EXPORT_SYMBOL_GPL(kvm_get_msr);
1533
1534 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1535 {
1536         return __kvm_set_msr(vcpu, index, data, false);
1537 }
1538 EXPORT_SYMBOL_GPL(kvm_set_msr);
1539
1540 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1541 {
1542         u32 ecx = kvm_rcx_read(vcpu);
1543         u64 data;
1544
1545         if (kvm_get_msr(vcpu, ecx, &data)) {
1546                 trace_kvm_msr_read_ex(ecx);
1547                 kvm_inject_gp(vcpu, 0);
1548                 return 1;
1549         }
1550
1551         trace_kvm_msr_read(ecx, data);
1552
1553         kvm_rax_write(vcpu, data & -1u);
1554         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1555         return kvm_skip_emulated_instruction(vcpu);
1556 }
1557 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1558
1559 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1560 {
1561         u32 ecx = kvm_rcx_read(vcpu);
1562         u64 data = kvm_read_edx_eax(vcpu);
1563
1564         if (kvm_set_msr(vcpu, ecx, data)) {
1565                 trace_kvm_msr_write_ex(ecx, data);
1566                 kvm_inject_gp(vcpu, 0);
1567                 return 1;
1568         }
1569
1570         trace_kvm_msr_write(ecx, data);
1571         return kvm_skip_emulated_instruction(vcpu);
1572 }
1573 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1574
1575 /*
1576  * The fast path for frequent and performance sensitive wrmsr emulation,
1577  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1578  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1579  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1580  * other cases which must be called after interrupts are enabled on the host.
1581  */
1582 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1583 {
1584         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1585                 return 1;
1586
1587         if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1588                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1589                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1590                 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1591
1592                 data &= ~(1 << 12);
1593                 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1594                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1595                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1596                 trace_kvm_apic_write(APIC_ICR, (u32)data);
1597                 return 0;
1598         }
1599
1600         return 1;
1601 }
1602
1603 enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1604 {
1605         u32 msr = kvm_rcx_read(vcpu);
1606         u64 data;
1607         int ret = 0;
1608
1609         switch (msr) {
1610         case APIC_BASE_MSR + (APIC_ICR >> 4):
1611                 data = kvm_read_edx_eax(vcpu);
1612                 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1613                 break;
1614         default:
1615                 return EXIT_FASTPATH_NONE;
1616         }
1617
1618         if (!ret) {
1619                 trace_kvm_msr_write(msr, data);
1620                 return EXIT_FASTPATH_SKIP_EMUL_INS;
1621         }
1622
1623         return EXIT_FASTPATH_NONE;
1624 }
1625 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1626
1627 /*
1628  * Adapt set_msr() to msr_io()'s calling convention
1629  */
1630 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1631 {
1632         return __kvm_get_msr(vcpu, index, data, true);
1633 }
1634
1635 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1636 {
1637         return __kvm_set_msr(vcpu, index, *data, true);
1638 }
1639
1640 #ifdef CONFIG_X86_64
1641 struct pvclock_clock {
1642         int vclock_mode;
1643         u64 cycle_last;
1644         u64 mask;
1645         u32 mult;
1646         u32 shift;
1647         u64 base_cycles;
1648         u64 offset;
1649 };
1650
1651 struct pvclock_gtod_data {
1652         seqcount_t      seq;
1653
1654         struct pvclock_clock clock; /* extract of a clocksource struct */
1655         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1656
1657         ktime_t         offs_boot;
1658         u64             wall_time_sec;
1659 };
1660
1661 static struct pvclock_gtod_data pvclock_gtod_data;
1662
1663 static void update_pvclock_gtod(struct timekeeper *tk)
1664 {
1665         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1666
1667         write_seqcount_begin(&vdata->seq);
1668
1669         /* copy pvclock gtod data */
1670         vdata->clock.vclock_mode        = tk->tkr_mono.clock->vdso_clock_mode;
1671         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1672         vdata->clock.mask               = tk->tkr_mono.mask;
1673         vdata->clock.mult               = tk->tkr_mono.mult;
1674         vdata->clock.shift              = tk->tkr_mono.shift;
1675         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1676         vdata->clock.offset             = tk->tkr_mono.base;
1677
1678         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->vdso_clock_mode;
1679         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1680         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1681         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1682         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1683         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1684         vdata->raw_clock.offset         = tk->tkr_raw.base;
1685
1686         vdata->wall_time_sec            = tk->xtime_sec;
1687
1688         vdata->offs_boot                = tk->offs_boot;
1689
1690         write_seqcount_end(&vdata->seq);
1691 }
1692
1693 static s64 get_kvmclock_base_ns(void)
1694 {
1695         /* Count up from boot time, but with the frequency of the raw clock.  */
1696         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1697 }
1698 #else
1699 static s64 get_kvmclock_base_ns(void)
1700 {
1701         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1702         return ktime_get_boottime_ns();
1703 }
1704 #endif
1705
1706 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1707 {
1708         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1709         kvm_vcpu_kick(vcpu);
1710 }
1711
1712 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1713 {
1714         int version;
1715         int r;
1716         struct pvclock_wall_clock wc;
1717         u64 wall_nsec;
1718
1719         if (!wall_clock)
1720                 return;
1721
1722         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1723         if (r)
1724                 return;
1725
1726         if (version & 1)
1727                 ++version;  /* first time write, random junk */
1728
1729         ++version;
1730
1731         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1732                 return;
1733
1734         /*
1735          * The guest calculates current wall clock time by adding
1736          * system time (updated by kvm_guest_time_update below) to the
1737          * wall clock specified here.  We do the reverse here.
1738          */
1739         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1740
1741         wc.nsec = do_div(wall_nsec, 1000000000);
1742         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1743         wc.version = version;
1744
1745         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1746
1747         version++;
1748         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1749 }
1750
1751 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1752 {
1753         do_shl32_div32(dividend, divisor);
1754         return dividend;
1755 }
1756
1757 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1758                                s8 *pshift, u32 *pmultiplier)
1759 {
1760         uint64_t scaled64;
1761         int32_t  shift = 0;
1762         uint64_t tps64;
1763         uint32_t tps32;
1764
1765         tps64 = base_hz;
1766         scaled64 = scaled_hz;
1767         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1768                 tps64 >>= 1;
1769                 shift--;
1770         }
1771
1772         tps32 = (uint32_t)tps64;
1773         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1774                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1775                         scaled64 >>= 1;
1776                 else
1777                         tps32 <<= 1;
1778                 shift++;
1779         }
1780
1781         *pshift = shift;
1782         *pmultiplier = div_frac(scaled64, tps32);
1783 }
1784
1785 #ifdef CONFIG_X86_64
1786 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1787 #endif
1788
1789 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1790 static unsigned long max_tsc_khz;
1791
1792 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1793 {
1794         u64 v = (u64)khz * (1000000 + ppm);
1795         do_div(v, 1000000);
1796         return v;
1797 }
1798
1799 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1800 {
1801         u64 ratio;
1802
1803         /* Guest TSC same frequency as host TSC? */
1804         if (!scale) {
1805                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1806                 return 0;
1807         }
1808
1809         /* TSC scaling supported? */
1810         if (!kvm_has_tsc_control) {
1811                 if (user_tsc_khz > tsc_khz) {
1812                         vcpu->arch.tsc_catchup = 1;
1813                         vcpu->arch.tsc_always_catchup = 1;
1814                         return 0;
1815                 } else {
1816                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1817                         return -1;
1818                 }
1819         }
1820
1821         /* TSC scaling required  - calculate ratio */
1822         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1823                                 user_tsc_khz, tsc_khz);
1824
1825         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1826                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1827                                     user_tsc_khz);
1828                 return -1;
1829         }
1830
1831         vcpu->arch.tsc_scaling_ratio = ratio;
1832         return 0;
1833 }
1834
1835 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1836 {
1837         u32 thresh_lo, thresh_hi;
1838         int use_scaling = 0;
1839
1840         /* tsc_khz can be zero if TSC calibration fails */
1841         if (user_tsc_khz == 0) {
1842                 /* set tsc_scaling_ratio to a safe value */
1843                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1844                 return -1;
1845         }
1846
1847         /* Compute a scale to convert nanoseconds in TSC cycles */
1848         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1849                            &vcpu->arch.virtual_tsc_shift,
1850                            &vcpu->arch.virtual_tsc_mult);
1851         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1852
1853         /*
1854          * Compute the variation in TSC rate which is acceptable
1855          * within the range of tolerance and decide if the
1856          * rate being applied is within that bounds of the hardware
1857          * rate.  If so, no scaling or compensation need be done.
1858          */
1859         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1860         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1861         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1862                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1863                 use_scaling = 1;
1864         }
1865         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1866 }
1867
1868 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1869 {
1870         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1871                                       vcpu->arch.virtual_tsc_mult,
1872                                       vcpu->arch.virtual_tsc_shift);
1873         tsc += vcpu->arch.this_tsc_write;
1874         return tsc;
1875 }
1876
1877 static inline int gtod_is_based_on_tsc(int mode)
1878 {
1879         return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1880 }
1881
1882 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1883 {
1884 #ifdef CONFIG_X86_64
1885         bool vcpus_matched;
1886         struct kvm_arch *ka = &vcpu->kvm->arch;
1887         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1888
1889         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1890                          atomic_read(&vcpu->kvm->online_vcpus));
1891
1892         /*
1893          * Once the masterclock is enabled, always perform request in
1894          * order to update it.
1895          *
1896          * In order to enable masterclock, the host clocksource must be TSC
1897          * and the vcpus need to have matched TSCs.  When that happens,
1898          * perform request to enable masterclock.
1899          */
1900         if (ka->use_master_clock ||
1901             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1902                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1903
1904         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1905                             atomic_read(&vcpu->kvm->online_vcpus),
1906                             ka->use_master_clock, gtod->clock.vclock_mode);
1907 #endif
1908 }
1909
1910 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1911 {
1912         u64 curr_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
1913         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1914 }
1915
1916 /*
1917  * Multiply tsc by a fixed point number represented by ratio.
1918  *
1919  * The most significant 64-N bits (mult) of ratio represent the
1920  * integral part of the fixed point number; the remaining N bits
1921  * (frac) represent the fractional part, ie. ratio represents a fixed
1922  * point number (mult + frac * 2^(-N)).
1923  *
1924  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1925  */
1926 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1927 {
1928         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1929 }
1930
1931 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1932 {
1933         u64 _tsc = tsc;
1934         u64 ratio = vcpu->arch.tsc_scaling_ratio;
1935
1936         if (ratio != kvm_default_tsc_scaling_ratio)
1937                 _tsc = __scale_tsc(ratio, tsc);
1938
1939         return _tsc;
1940 }
1941 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1942
1943 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1944 {
1945         u64 tsc;
1946
1947         tsc = kvm_scale_tsc(vcpu, rdtsc());
1948
1949         return target_tsc - tsc;
1950 }
1951
1952 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1953 {
1954         u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
1955
1956         return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
1957 }
1958 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1959
1960 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1961 {
1962         vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
1963 }
1964
1965 static inline bool kvm_check_tsc_unstable(void)
1966 {
1967 #ifdef CONFIG_X86_64
1968         /*
1969          * TSC is marked unstable when we're running on Hyper-V,
1970          * 'TSC page' clocksource is good.
1971          */
1972         if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
1973                 return false;
1974 #endif
1975         return check_tsc_unstable();
1976 }
1977
1978 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1979 {
1980         struct kvm *kvm = vcpu->kvm;
1981         u64 offset, ns, elapsed;
1982         unsigned long flags;
1983         bool matched;
1984         bool already_matched;
1985         u64 data = msr->data;
1986         bool synchronizing = false;
1987
1988         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1989         offset = kvm_compute_tsc_offset(vcpu, data);
1990         ns = get_kvmclock_base_ns();
1991         elapsed = ns - kvm->arch.last_tsc_nsec;
1992
1993         if (vcpu->arch.virtual_tsc_khz) {
1994                 if (data == 0 && msr->host_initiated) {
1995                         /*
1996                          * detection of vcpu initialization -- need to sync
1997                          * with other vCPUs. This particularly helps to keep
1998                          * kvm_clock stable after CPU hotplug
1999                          */
2000                         synchronizing = true;
2001                 } else {
2002                         u64 tsc_exp = kvm->arch.last_tsc_write +
2003                                                 nsec_to_cycles(vcpu, elapsed);
2004                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2005                         /*
2006                          * Special case: TSC write with a small delta (1 second)
2007                          * of virtual cycle time against real time is
2008                          * interpreted as an attempt to synchronize the CPU.
2009                          */
2010                         synchronizing = data < tsc_exp + tsc_hz &&
2011                                         data + tsc_hz > tsc_exp;
2012                 }
2013         }
2014
2015         /*
2016          * For a reliable TSC, we can match TSC offsets, and for an unstable
2017          * TSC, we add elapsed time in this computation.  We could let the
2018          * compensation code attempt to catch up if we fall behind, but
2019          * it's better to try to match offsets from the beginning.
2020          */
2021         if (synchronizing &&
2022             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2023                 if (!kvm_check_tsc_unstable()) {
2024                         offset = kvm->arch.cur_tsc_offset;
2025                 } else {
2026                         u64 delta = nsec_to_cycles(vcpu, elapsed);
2027                         data += delta;
2028                         offset = kvm_compute_tsc_offset(vcpu, data);
2029                 }
2030                 matched = true;
2031                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2032         } else {
2033                 /*
2034                  * We split periods of matched TSC writes into generations.
2035                  * For each generation, we track the original measured
2036                  * nanosecond time, offset, and write, so if TSCs are in
2037                  * sync, we can match exact offset, and if not, we can match
2038                  * exact software computation in compute_guest_tsc()
2039                  *
2040                  * These values are tracked in kvm->arch.cur_xxx variables.
2041                  */
2042                 kvm->arch.cur_tsc_generation++;
2043                 kvm->arch.cur_tsc_nsec = ns;
2044                 kvm->arch.cur_tsc_write = data;
2045                 kvm->arch.cur_tsc_offset = offset;
2046                 matched = false;
2047         }
2048
2049         /*
2050          * We also track th most recent recorded KHZ, write and time to
2051          * allow the matching interval to be extended at each write.
2052          */
2053         kvm->arch.last_tsc_nsec = ns;
2054         kvm->arch.last_tsc_write = data;
2055         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2056
2057         vcpu->arch.last_guest_tsc = data;
2058
2059         /* Keep track of which generation this VCPU has synchronized to */
2060         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2061         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2062         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2063
2064         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2065                 update_ia32_tsc_adjust_msr(vcpu, offset);
2066
2067         kvm_vcpu_write_tsc_offset(vcpu, offset);
2068         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2069
2070         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2071         if (!matched) {
2072                 kvm->arch.nr_vcpus_matched_tsc = 0;
2073         } else if (!already_matched) {
2074                 kvm->arch.nr_vcpus_matched_tsc++;
2075         }
2076
2077         kvm_track_tsc_matching(vcpu);
2078         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2079 }
2080
2081 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2082
2083 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2084                                            s64 adjustment)
2085 {
2086         u64 tsc_offset = kvm_x86_ops.read_l1_tsc_offset(vcpu);
2087         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2088 }
2089
2090 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2091 {
2092         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2093                 WARN_ON(adjustment < 0);
2094         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2095         adjust_tsc_offset_guest(vcpu, adjustment);
2096 }
2097
2098 #ifdef CONFIG_X86_64
2099
2100 static u64 read_tsc(void)
2101 {
2102         u64 ret = (u64)rdtsc_ordered();
2103         u64 last = pvclock_gtod_data.clock.cycle_last;
2104
2105         if (likely(ret >= last))
2106                 return ret;
2107
2108         /*
2109          * GCC likes to generate cmov here, but this branch is extremely
2110          * predictable (it's just a function of time and the likely is
2111          * very likely) and there's a data dependence, so force GCC
2112          * to generate a branch instead.  I don't barrier() because
2113          * we don't actually need a barrier, and if this function
2114          * ever gets inlined it will generate worse code.
2115          */
2116         asm volatile ("");
2117         return last;
2118 }
2119
2120 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2121                           int *mode)
2122 {
2123         long v;
2124         u64 tsc_pg_val;
2125
2126         switch (clock->vclock_mode) {
2127         case VDSO_CLOCKMODE_HVCLOCK:
2128                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2129                                                   tsc_timestamp);
2130                 if (tsc_pg_val != U64_MAX) {
2131                         /* TSC page valid */
2132                         *mode = VDSO_CLOCKMODE_HVCLOCK;
2133                         v = (tsc_pg_val - clock->cycle_last) &
2134                                 clock->mask;
2135                 } else {
2136                         /* TSC page invalid */
2137                         *mode = VDSO_CLOCKMODE_NONE;
2138                 }
2139                 break;
2140         case VDSO_CLOCKMODE_TSC:
2141                 *mode = VDSO_CLOCKMODE_TSC;
2142                 *tsc_timestamp = read_tsc();
2143                 v = (*tsc_timestamp - clock->cycle_last) &
2144                         clock->mask;
2145                 break;
2146         default:
2147                 *mode = VDSO_CLOCKMODE_NONE;
2148         }
2149
2150         if (*mode == VDSO_CLOCKMODE_NONE)
2151                 *tsc_timestamp = v = 0;
2152
2153         return v * clock->mult;
2154 }
2155
2156 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2157 {
2158         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2159         unsigned long seq;
2160         int mode;
2161         u64 ns;
2162
2163         do {
2164                 seq = read_seqcount_begin(&gtod->seq);
2165                 ns = gtod->raw_clock.base_cycles;
2166                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2167                 ns >>= gtod->raw_clock.shift;
2168                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2169         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2170         *t = ns;
2171
2172         return mode;
2173 }
2174
2175 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2176 {
2177         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2178         unsigned long seq;
2179         int mode;
2180         u64 ns;
2181
2182         do {
2183                 seq = read_seqcount_begin(&gtod->seq);
2184                 ts->tv_sec = gtod->wall_time_sec;
2185                 ns = gtod->clock.base_cycles;
2186                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2187                 ns >>= gtod->clock.shift;
2188         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2189
2190         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2191         ts->tv_nsec = ns;
2192
2193         return mode;
2194 }
2195
2196 /* returns true if host is using TSC based clocksource */
2197 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2198 {
2199         /* checked again under seqlock below */
2200         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2201                 return false;
2202
2203         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2204                                                       tsc_timestamp));
2205 }
2206
2207 /* returns true if host is using TSC based clocksource */
2208 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2209                                            u64 *tsc_timestamp)
2210 {
2211         /* checked again under seqlock below */
2212         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2213                 return false;
2214
2215         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2216 }
2217 #endif
2218
2219 /*
2220  *
2221  * Assuming a stable TSC across physical CPUS, and a stable TSC
2222  * across virtual CPUs, the following condition is possible.
2223  * Each numbered line represents an event visible to both
2224  * CPUs at the next numbered event.
2225  *
2226  * "timespecX" represents host monotonic time. "tscX" represents
2227  * RDTSC value.
2228  *
2229  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2230  *
2231  * 1.  read timespec0,tsc0
2232  * 2.                                   | timespec1 = timespec0 + N
2233  *                                      | tsc1 = tsc0 + M
2234  * 3. transition to guest               | transition to guest
2235  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2236  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2237  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2238  *
2239  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2240  *
2241  *      - ret0 < ret1
2242  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2243  *              ...
2244  *      - 0 < N - M => M < N
2245  *
2246  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2247  * always the case (the difference between two distinct xtime instances
2248  * might be smaller then the difference between corresponding TSC reads,
2249  * when updating guest vcpus pvclock areas).
2250  *
2251  * To avoid that problem, do not allow visibility of distinct
2252  * system_timestamp/tsc_timestamp values simultaneously: use a master
2253  * copy of host monotonic time values. Update that master copy
2254  * in lockstep.
2255  *
2256  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2257  *
2258  */
2259
2260 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2261 {
2262 #ifdef CONFIG_X86_64
2263         struct kvm_arch *ka = &kvm->arch;
2264         int vclock_mode;
2265         bool host_tsc_clocksource, vcpus_matched;
2266
2267         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2268                         atomic_read(&kvm->online_vcpus));
2269
2270         /*
2271          * If the host uses TSC clock, then passthrough TSC as stable
2272          * to the guest.
2273          */
2274         host_tsc_clocksource = kvm_get_time_and_clockread(
2275                                         &ka->master_kernel_ns,
2276                                         &ka->master_cycle_now);
2277
2278         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2279                                 && !ka->backwards_tsc_observed
2280                                 && !ka->boot_vcpu_runs_old_kvmclock;
2281
2282         if (ka->use_master_clock)
2283                 atomic_set(&kvm_guest_has_master_clock, 1);
2284
2285         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2286         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2287                                         vcpus_matched);
2288 #endif
2289 }
2290
2291 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2292 {
2293         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2294 }
2295
2296 static void kvm_gen_update_masterclock(struct kvm *kvm)
2297 {
2298 #ifdef CONFIG_X86_64
2299         int i;
2300         struct kvm_vcpu *vcpu;
2301         struct kvm_arch *ka = &kvm->arch;
2302
2303         spin_lock(&ka->pvclock_gtod_sync_lock);
2304         kvm_make_mclock_inprogress_request(kvm);
2305         /* no guest entries from this point */
2306         pvclock_update_vm_gtod_copy(kvm);
2307
2308         kvm_for_each_vcpu(i, vcpu, kvm)
2309                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2310
2311         /* guest entries allowed */
2312         kvm_for_each_vcpu(i, vcpu, kvm)
2313                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2314
2315         spin_unlock(&ka->pvclock_gtod_sync_lock);
2316 #endif
2317 }
2318
2319 u64 get_kvmclock_ns(struct kvm *kvm)
2320 {
2321         struct kvm_arch *ka = &kvm->arch;
2322         struct pvclock_vcpu_time_info hv_clock;
2323         u64 ret;
2324
2325         spin_lock(&ka->pvclock_gtod_sync_lock);
2326         if (!ka->use_master_clock) {
2327                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2328                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2329         }
2330
2331         hv_clock.tsc_timestamp = ka->master_cycle_now;
2332         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2333         spin_unlock(&ka->pvclock_gtod_sync_lock);
2334
2335         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2336         get_cpu();
2337
2338         if (__this_cpu_read(cpu_tsc_khz)) {
2339                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2340                                    &hv_clock.tsc_shift,
2341                                    &hv_clock.tsc_to_system_mul);
2342                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2343         } else
2344                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2345
2346         put_cpu();
2347
2348         return ret;
2349 }
2350
2351 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2352 {
2353         struct kvm_vcpu_arch *vcpu = &v->arch;
2354         struct pvclock_vcpu_time_info guest_hv_clock;
2355
2356         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2357                 &guest_hv_clock, sizeof(guest_hv_clock))))
2358                 return;
2359
2360         /* This VCPU is paused, but it's legal for a guest to read another
2361          * VCPU's kvmclock, so we really have to follow the specification where
2362          * it says that version is odd if data is being modified, and even after
2363          * it is consistent.
2364          *
2365          * Version field updates must be kept separate.  This is because
2366          * kvm_write_guest_cached might use a "rep movs" instruction, and
2367          * writes within a string instruction are weakly ordered.  So there
2368          * are three writes overall.
2369          *
2370          * As a small optimization, only write the version field in the first
2371          * and third write.  The vcpu->pv_time cache is still valid, because the
2372          * version field is the first in the struct.
2373          */
2374         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2375
2376         if (guest_hv_clock.version & 1)
2377                 ++guest_hv_clock.version;  /* first time write, random junk */
2378
2379         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2380         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2381                                 &vcpu->hv_clock,
2382                                 sizeof(vcpu->hv_clock.version));
2383
2384         smp_wmb();
2385
2386         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2387         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2388
2389         if (vcpu->pvclock_set_guest_stopped_request) {
2390                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2391                 vcpu->pvclock_set_guest_stopped_request = false;
2392         }
2393
2394         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2395
2396         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2397                                 &vcpu->hv_clock,
2398                                 sizeof(vcpu->hv_clock));
2399
2400         smp_wmb();
2401
2402         vcpu->hv_clock.version++;
2403         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2404                                 &vcpu->hv_clock,
2405                                 sizeof(vcpu->hv_clock.version));
2406 }
2407
2408 static int kvm_guest_time_update(struct kvm_vcpu *v)
2409 {
2410         unsigned long flags, tgt_tsc_khz;
2411         struct kvm_vcpu_arch *vcpu = &v->arch;
2412         struct kvm_arch *ka = &v->kvm->arch;
2413         s64 kernel_ns;
2414         u64 tsc_timestamp, host_tsc;
2415         u8 pvclock_flags;
2416         bool use_master_clock;
2417
2418         kernel_ns = 0;
2419         host_tsc = 0;
2420
2421         /*
2422          * If the host uses TSC clock, then passthrough TSC as stable
2423          * to the guest.
2424          */
2425         spin_lock(&ka->pvclock_gtod_sync_lock);
2426         use_master_clock = ka->use_master_clock;
2427         if (use_master_clock) {
2428                 host_tsc = ka->master_cycle_now;
2429                 kernel_ns = ka->master_kernel_ns;
2430         }
2431         spin_unlock(&ka->pvclock_gtod_sync_lock);
2432
2433         /* Keep irq disabled to prevent changes to the clock */
2434         local_irq_save(flags);
2435         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2436         if (unlikely(tgt_tsc_khz == 0)) {
2437                 local_irq_restore(flags);
2438                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2439                 return 1;
2440         }
2441         if (!use_master_clock) {
2442                 host_tsc = rdtsc();
2443                 kernel_ns = get_kvmclock_base_ns();
2444         }
2445
2446         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2447
2448         /*
2449          * We may have to catch up the TSC to match elapsed wall clock
2450          * time for two reasons, even if kvmclock is used.
2451          *   1) CPU could have been running below the maximum TSC rate
2452          *   2) Broken TSC compensation resets the base at each VCPU
2453          *      entry to avoid unknown leaps of TSC even when running
2454          *      again on the same CPU.  This may cause apparent elapsed
2455          *      time to disappear, and the guest to stand still or run
2456          *      very slowly.
2457          */
2458         if (vcpu->tsc_catchup) {
2459                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2460                 if (tsc > tsc_timestamp) {
2461                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2462                         tsc_timestamp = tsc;
2463                 }
2464         }
2465
2466         local_irq_restore(flags);
2467
2468         /* With all the info we got, fill in the values */
2469
2470         if (kvm_has_tsc_control)
2471                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2472
2473         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2474                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2475                                    &vcpu->hv_clock.tsc_shift,
2476                                    &vcpu->hv_clock.tsc_to_system_mul);
2477                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2478         }
2479
2480         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2481         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2482         vcpu->last_guest_tsc = tsc_timestamp;
2483
2484         /* If the host uses TSC clocksource, then it is stable */
2485         pvclock_flags = 0;
2486         if (use_master_clock)
2487                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2488
2489         vcpu->hv_clock.flags = pvclock_flags;
2490
2491         if (vcpu->pv_time_enabled)
2492                 kvm_setup_pvclock_page(v);
2493         if (v == kvm_get_vcpu(v->kvm, 0))
2494                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2495         return 0;
2496 }
2497
2498 /*
2499  * kvmclock updates which are isolated to a given vcpu, such as
2500  * vcpu->cpu migration, should not allow system_timestamp from
2501  * the rest of the vcpus to remain static. Otherwise ntp frequency
2502  * correction applies to one vcpu's system_timestamp but not
2503  * the others.
2504  *
2505  * So in those cases, request a kvmclock update for all vcpus.
2506  * We need to rate-limit these requests though, as they can
2507  * considerably slow guests that have a large number of vcpus.
2508  * The time for a remote vcpu to update its kvmclock is bound
2509  * by the delay we use to rate-limit the updates.
2510  */
2511
2512 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2513
2514 static void kvmclock_update_fn(struct work_struct *work)
2515 {
2516         int i;
2517         struct delayed_work *dwork = to_delayed_work(work);
2518         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2519                                            kvmclock_update_work);
2520         struct kvm *kvm = container_of(ka, struct kvm, arch);
2521         struct kvm_vcpu *vcpu;
2522
2523         kvm_for_each_vcpu(i, vcpu, kvm) {
2524                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2525                 kvm_vcpu_kick(vcpu);
2526         }
2527 }
2528
2529 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2530 {
2531         struct kvm *kvm = v->kvm;
2532
2533         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2534         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2535                                         KVMCLOCK_UPDATE_DELAY);
2536 }
2537
2538 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2539
2540 static void kvmclock_sync_fn(struct work_struct *work)
2541 {
2542         struct delayed_work *dwork = to_delayed_work(work);
2543         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2544                                            kvmclock_sync_work);
2545         struct kvm *kvm = container_of(ka, struct kvm, arch);
2546
2547         if (!kvmclock_periodic_sync)
2548                 return;
2549
2550         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2551         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2552                                         KVMCLOCK_SYNC_PERIOD);
2553 }
2554
2555 /*
2556  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2557  */
2558 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2559 {
2560         /* McStatusWrEn enabled? */
2561         if (guest_cpuid_is_amd_or_hygon(vcpu))
2562                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2563
2564         return false;
2565 }
2566
2567 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2568 {
2569         u64 mcg_cap = vcpu->arch.mcg_cap;
2570         unsigned bank_num = mcg_cap & 0xff;
2571         u32 msr = msr_info->index;
2572         u64 data = msr_info->data;
2573
2574         switch (msr) {
2575         case MSR_IA32_MCG_STATUS:
2576                 vcpu->arch.mcg_status = data;
2577                 break;
2578         case MSR_IA32_MCG_CTL:
2579                 if (!(mcg_cap & MCG_CTL_P) &&
2580                     (data || !msr_info->host_initiated))
2581                         return 1;
2582                 if (data != 0 && data != ~(u64)0)
2583                         return 1;
2584                 vcpu->arch.mcg_ctl = data;
2585                 break;
2586         default:
2587                 if (msr >= MSR_IA32_MC0_CTL &&
2588                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2589                         u32 offset = array_index_nospec(
2590                                 msr - MSR_IA32_MC0_CTL,
2591                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2592
2593                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2594                          * some Linux kernels though clear bit 10 in bank 4 to
2595                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2596                          * this to avoid an uncatched #GP in the guest
2597                          */
2598                         if ((offset & 0x3) == 0 &&
2599                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2600                                 return -1;
2601
2602                         /* MCi_STATUS */
2603                         if (!msr_info->host_initiated &&
2604                             (offset & 0x3) == 1 && data != 0) {
2605                                 if (!can_set_mci_status(vcpu))
2606                                         return -1;
2607                         }
2608
2609                         vcpu->arch.mce_banks[offset] = data;
2610                         break;
2611                 }
2612                 return 1;
2613         }
2614         return 0;
2615 }
2616
2617 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2618 {
2619         struct kvm *kvm = vcpu->kvm;
2620         int lm = is_long_mode(vcpu);
2621         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2622                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2623         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2624                 : kvm->arch.xen_hvm_config.blob_size_32;
2625         u32 page_num = data & ~PAGE_MASK;
2626         u64 page_addr = data & PAGE_MASK;
2627         u8 *page;
2628         int r;
2629
2630         r = -E2BIG;
2631         if (page_num >= blob_size)
2632                 goto out;
2633         r = -ENOMEM;
2634         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2635         if (IS_ERR(page)) {
2636                 r = PTR_ERR(page);
2637                 goto out;
2638         }
2639         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2640                 goto out_free;
2641         r = 0;
2642 out_free:
2643         kfree(page);
2644 out:
2645         return r;
2646 }
2647
2648 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2649 {
2650         gpa_t gpa = data & ~0x3f;
2651
2652         /* Bits 3:5 are reserved, Should be zero */
2653         if (data & 0x38)
2654                 return 1;
2655
2656         vcpu->arch.apf.msr_val = data;
2657
2658         if (!(data & KVM_ASYNC_PF_ENABLED)) {
2659                 kvm_clear_async_pf_completion_queue(vcpu);
2660                 kvm_async_pf_hash_reset(vcpu);
2661                 return 0;
2662         }
2663
2664         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2665                                         sizeof(u32)))
2666                 return 1;
2667
2668         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2669         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2670         kvm_async_pf_wakeup_all(vcpu);
2671         return 0;
2672 }
2673
2674 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2675 {
2676         vcpu->arch.pv_time_enabled = false;
2677         vcpu->arch.time = 0;
2678 }
2679
2680 static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2681 {
2682         ++vcpu->stat.tlb_flush;
2683         kvm_x86_ops.tlb_flush(vcpu, invalidate_gpa);
2684 }
2685
2686 static void record_steal_time(struct kvm_vcpu *vcpu)
2687 {
2688         struct kvm_host_map map;
2689         struct kvm_steal_time *st;
2690
2691         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2692                 return;
2693
2694         /* -EAGAIN is returned in atomic context so we can just return. */
2695         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2696                         &map, &vcpu->arch.st.cache, false))
2697                 return;
2698
2699         st = map.hva +
2700                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2701
2702         /*
2703          * Doing a TLB flush here, on the guest's behalf, can avoid
2704          * expensive IPIs.
2705          */
2706         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2707                 st->preempted & KVM_VCPU_FLUSH_TLB);
2708         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2709                 kvm_vcpu_flush_tlb(vcpu, false);
2710
2711         vcpu->arch.st.preempted = 0;
2712
2713         if (st->version & 1)
2714                 st->version += 1;  /* first time write, random junk */
2715
2716         st->version += 1;
2717
2718         smp_wmb();
2719
2720         st->steal += current->sched_info.run_delay -
2721                 vcpu->arch.st.last_steal;
2722         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2723
2724         smp_wmb();
2725
2726         st->version += 1;
2727
2728         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2729 }
2730
2731 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2732 {
2733         bool pr = false;
2734         u32 msr = msr_info->index;
2735         u64 data = msr_info->data;
2736
2737         switch (msr) {
2738         case MSR_AMD64_NB_CFG:
2739         case MSR_IA32_UCODE_WRITE:
2740         case MSR_VM_HSAVE_PA:
2741         case MSR_AMD64_PATCH_LOADER:
2742         case MSR_AMD64_BU_CFG2:
2743         case MSR_AMD64_DC_CFG:
2744         case MSR_F15H_EX_CFG:
2745                 break;
2746
2747         case MSR_IA32_UCODE_REV:
2748                 if (msr_info->host_initiated)
2749                         vcpu->arch.microcode_version = data;
2750                 break;
2751         case MSR_IA32_ARCH_CAPABILITIES:
2752                 if (!msr_info->host_initiated)
2753                         return 1;
2754                 vcpu->arch.arch_capabilities = data;
2755                 break;
2756         case MSR_EFER:
2757                 return set_efer(vcpu, msr_info);
2758         case MSR_K7_HWCR:
2759                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2760                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2761                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2762
2763                 /* Handle McStatusWrEn */
2764                 if (data == BIT_ULL(18)) {
2765                         vcpu->arch.msr_hwcr = data;
2766                 } else if (data != 0) {
2767                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2768                                     data);
2769                         return 1;
2770                 }
2771                 break;
2772         case MSR_FAM10H_MMIO_CONF_BASE:
2773                 if (data != 0) {
2774                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2775                                     "0x%llx\n", data);
2776                         return 1;
2777                 }
2778                 break;
2779         case MSR_IA32_DEBUGCTLMSR:
2780                 if (!data) {
2781                         /* We support the non-activated case already */
2782                         break;
2783                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2784                         /* Values other than LBR and BTF are vendor-specific,
2785                            thus reserved and should throw a #GP */
2786                         return 1;
2787                 }
2788                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2789                             __func__, data);
2790                 break;
2791         case 0x200 ... 0x2ff:
2792                 return kvm_mtrr_set_msr(vcpu, msr, data);
2793         case MSR_IA32_APICBASE:
2794                 return kvm_set_apic_base(vcpu, msr_info);
2795         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2796                 return kvm_x2apic_msr_write(vcpu, msr, data);
2797         case MSR_IA32_TSCDEADLINE:
2798                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2799                 break;
2800         case MSR_IA32_TSC_ADJUST:
2801                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2802                         if (!msr_info->host_initiated) {
2803                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2804                                 adjust_tsc_offset_guest(vcpu, adj);
2805                         }
2806                         vcpu->arch.ia32_tsc_adjust_msr = data;
2807                 }
2808                 break;
2809         case MSR_IA32_MISC_ENABLE:
2810                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2811                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2812                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2813                                 return 1;
2814                         vcpu->arch.ia32_misc_enable_msr = data;
2815                         kvm_update_cpuid(vcpu);
2816                 } else {
2817                         vcpu->arch.ia32_misc_enable_msr = data;
2818                 }
2819                 break;
2820         case MSR_IA32_SMBASE:
2821                 if (!msr_info->host_initiated)
2822                         return 1;
2823                 vcpu->arch.smbase = data;
2824                 break;
2825         case MSR_IA32_POWER_CTL:
2826                 vcpu->arch.msr_ia32_power_ctl = data;
2827                 break;
2828         case MSR_IA32_TSC:
2829                 kvm_write_tsc(vcpu, msr_info);
2830                 break;
2831         case MSR_IA32_XSS:
2832                 if (!msr_info->host_initiated &&
2833                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2834                         return 1;
2835                 /*
2836                  * KVM supports exposing PT to the guest, but does not support
2837                  * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2838                  * XSAVES/XRSTORS to save/restore PT MSRs.
2839                  */
2840                 if (data & ~supported_xss)
2841                         return 1;
2842                 vcpu->arch.ia32_xss = data;
2843                 break;
2844         case MSR_SMI_COUNT:
2845                 if (!msr_info->host_initiated)
2846                         return 1;
2847                 vcpu->arch.smi_count = data;
2848                 break;
2849         case MSR_KVM_WALL_CLOCK_NEW:
2850         case MSR_KVM_WALL_CLOCK:
2851                 vcpu->kvm->arch.wall_clock = data;
2852                 kvm_write_wall_clock(vcpu->kvm, data);
2853                 break;
2854         case MSR_KVM_SYSTEM_TIME_NEW:
2855         case MSR_KVM_SYSTEM_TIME: {
2856                 struct kvm_arch *ka = &vcpu->kvm->arch;
2857
2858                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2859                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2860
2861                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2862                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2863
2864                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2865                 }
2866
2867                 vcpu->arch.time = data;
2868                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2869
2870                 /* we verify if the enable bit is set... */
2871                 vcpu->arch.pv_time_enabled = false;
2872                 if (!(data & 1))
2873                         break;
2874
2875                 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2876                      &vcpu->arch.pv_time, data & ~1ULL,
2877                      sizeof(struct pvclock_vcpu_time_info)))
2878                         vcpu->arch.pv_time_enabled = true;
2879
2880                 break;
2881         }
2882         case MSR_KVM_ASYNC_PF_EN:
2883                 if (kvm_pv_enable_async_pf(vcpu, data))
2884                         return 1;
2885                 break;
2886         case MSR_KVM_STEAL_TIME:
2887
2888                 if (unlikely(!sched_info_on()))
2889                         return 1;
2890
2891                 if (data & KVM_STEAL_RESERVED_MASK)
2892                         return 1;
2893
2894                 vcpu->arch.st.msr_val = data;
2895
2896                 if (!(data & KVM_MSR_ENABLED))
2897                         break;
2898
2899                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2900
2901                 break;
2902         case MSR_KVM_PV_EOI_EN:
2903                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
2904                         return 1;
2905                 break;
2906
2907         case MSR_KVM_POLL_CONTROL:
2908                 /* only enable bit supported */
2909                 if (data & (-1ULL << 1))
2910                         return 1;
2911
2912                 vcpu->arch.msr_kvm_poll_control = data;
2913                 break;
2914
2915         case MSR_IA32_MCG_CTL:
2916         case MSR_IA32_MCG_STATUS:
2917         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
2918                 return set_msr_mce(vcpu, msr_info);
2919
2920         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2921         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2922                 pr = true; /* fall through */
2923         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2924         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
2925                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2926                         return kvm_pmu_set_msr(vcpu, msr_info);
2927
2928                 if (pr || data != 0)
2929                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2930                                     "0x%x data 0x%llx\n", msr, data);
2931                 break;
2932         case MSR_K7_CLK_CTL:
2933                 /*
2934                  * Ignore all writes to this no longer documented MSR.
2935                  * Writes are only relevant for old K7 processors,
2936                  * all pre-dating SVM, but a recommended workaround from
2937                  * AMD for these chips. It is possible to specify the
2938                  * affected processor models on the command line, hence
2939                  * the need to ignore the workaround.
2940                  */
2941                 break;
2942         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2943         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2944         case HV_X64_MSR_CRASH_CTL:
2945         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
2946         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2947         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2948         case HV_X64_MSR_TSC_EMULATION_STATUS:
2949                 return kvm_hv_set_msr_common(vcpu, msr, data,
2950                                              msr_info->host_initiated);
2951         case MSR_IA32_BBL_CR_CTL3:
2952                 /* Drop writes to this legacy MSR -- see rdmsr
2953                  * counterpart for further detail.
2954                  */
2955                 if (report_ignored_msrs)
2956                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2957                                 msr, data);
2958                 break;
2959         case MSR_AMD64_OSVW_ID_LENGTH:
2960                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2961                         return 1;
2962                 vcpu->arch.osvw.length = data;
2963                 break;
2964         case MSR_AMD64_OSVW_STATUS:
2965                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2966                         return 1;
2967                 vcpu->arch.osvw.status = data;
2968                 break;
2969         case MSR_PLATFORM_INFO:
2970                 if (!msr_info->host_initiated ||
2971                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2972                      cpuid_fault_enabled(vcpu)))
2973                         return 1;
2974                 vcpu->arch.msr_platform_info = data;
2975                 break;
2976         case MSR_MISC_FEATURES_ENABLES:
2977                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2978                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2979                      !supports_cpuid_fault(vcpu)))
2980                         return 1;
2981                 vcpu->arch.msr_misc_features_enables = data;
2982                 break;
2983         default:
2984                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2985                         return xen_hvm_config(vcpu, data);
2986                 if (kvm_pmu_is_valid_msr(vcpu, msr))
2987                         return kvm_pmu_set_msr(vcpu, msr_info);
2988                 if (!ignore_msrs) {
2989                         vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
2990                                     msr, data);
2991                         return 1;
2992                 } else {
2993                         if (report_ignored_msrs)
2994                                 vcpu_unimpl(vcpu,
2995                                         "ignored wrmsr: 0x%x data 0x%llx\n",
2996                                         msr, data);
2997                         break;
2998                 }
2999         }
3000         return 0;
3001 }
3002 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3003
3004 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3005 {
3006         u64 data;
3007         u64 mcg_cap = vcpu->arch.mcg_cap;
3008         unsigned bank_num = mcg_cap & 0xff;
3009
3010         switch (msr) {
3011         case MSR_IA32_P5_MC_ADDR:
3012         case MSR_IA32_P5_MC_TYPE:
3013                 data = 0;
3014                 break;
3015         case MSR_IA32_MCG_CAP:
3016                 data = vcpu->arch.mcg_cap;
3017                 break;
3018         case MSR_IA32_MCG_CTL:
3019                 if (!(mcg_cap & MCG_CTL_P) && !host)
3020                         return 1;
3021                 data = vcpu->arch.mcg_ctl;
3022                 break;
3023         case MSR_IA32_MCG_STATUS:
3024                 data = vcpu->arch.mcg_status;
3025                 break;
3026         default:
3027                 if (msr >= MSR_IA32_MC0_CTL &&
3028                     msr < MSR_IA32_MCx_CTL(bank_num)) {
3029                         u32 offset = array_index_nospec(
3030                                 msr - MSR_IA32_MC0_CTL,
3031                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3032
3033                         data = vcpu->arch.mce_banks[offset];
3034                         break;
3035                 }
3036                 return 1;
3037         }
3038         *pdata = data;
3039         return 0;
3040 }
3041
3042 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3043 {
3044         switch (msr_info->index) {
3045         case MSR_IA32_PLATFORM_ID:
3046         case MSR_IA32_EBL_CR_POWERON:
3047         case MSR_IA32_DEBUGCTLMSR:
3048         case MSR_IA32_LASTBRANCHFROMIP:
3049         case MSR_IA32_LASTBRANCHTOIP:
3050         case MSR_IA32_LASTINTFROMIP:
3051         case MSR_IA32_LASTINTTOIP:
3052         case MSR_K8_SYSCFG:
3053         case MSR_K8_TSEG_ADDR:
3054         case MSR_K8_TSEG_MASK:
3055         case MSR_VM_HSAVE_PA:
3056         case MSR_K8_INT_PENDING_MSG:
3057         case MSR_AMD64_NB_CFG:
3058         case MSR_FAM10H_MMIO_CONF_BASE:
3059         case MSR_AMD64_BU_CFG2:
3060         case MSR_IA32_PERF_CTL:
3061         case MSR_AMD64_DC_CFG:
3062         case MSR_F15H_EX_CFG:
3063         /*
3064          * Intel Sandy Bridge CPUs must support the RAPL (running average power
3065          * limit) MSRs. Just return 0, as we do not want to expose the host
3066          * data here. Do not conditionalize this on CPUID, as KVM does not do
3067          * so for existing CPU-specific MSRs.
3068          */
3069         case MSR_RAPL_POWER_UNIT:
3070         case MSR_PP0_ENERGY_STATUS:     /* Power plane 0 (core) */
3071         case MSR_PP1_ENERGY_STATUS:     /* Power plane 1 (graphics uncore) */
3072         case MSR_PKG_ENERGY_STATUS:     /* Total package */
3073         case MSR_DRAM_ENERGY_STATUS:    /* DRAM controller */
3074                 msr_info->data = 0;
3075                 break;
3076         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3077         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3078         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3079         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3080         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3081                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3082                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3083                 msr_info->data = 0;
3084                 break;
3085         case MSR_IA32_UCODE_REV:
3086                 msr_info->data = vcpu->arch.microcode_version;
3087                 break;
3088         case MSR_IA32_ARCH_CAPABILITIES:
3089                 if (!msr_info->host_initiated &&
3090                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3091                         return 1;
3092                 msr_info->data = vcpu->arch.arch_capabilities;
3093                 break;
3094         case MSR_IA32_POWER_CTL:
3095                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3096                 break;
3097         case MSR_IA32_TSC:
3098                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3099                 break;
3100         case MSR_MTRRcap:
3101         case 0x200 ... 0x2ff:
3102                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3103         case 0xcd: /* fsb frequency */
3104                 msr_info->data = 3;
3105                 break;
3106                 /*
3107                  * MSR_EBC_FREQUENCY_ID
3108                  * Conservative value valid for even the basic CPU models.
3109                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3110                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3111                  * and 266MHz for model 3, or 4. Set Core Clock
3112                  * Frequency to System Bus Frequency Ratio to 1 (bits
3113                  * 31:24) even though these are only valid for CPU
3114                  * models > 2, however guests may end up dividing or
3115                  * multiplying by zero otherwise.
3116                  */
3117         case MSR_EBC_FREQUENCY_ID:
3118                 msr_info->data = 1 << 24;
3119                 break;
3120         case MSR_IA32_APICBASE:
3121                 msr_info->data = kvm_get_apic_base(vcpu);
3122                 break;
3123         case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
3124                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3125         case MSR_IA32_TSCDEADLINE:
3126                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3127                 break;
3128         case MSR_IA32_TSC_ADJUST:
3129                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3130                 break;
3131         case MSR_IA32_MISC_ENABLE:
3132                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3133                 break;
3134         case MSR_IA32_SMBASE:
3135                 if (!msr_info->host_initiated)
3136                         return 1;
3137                 msr_info->data = vcpu->arch.smbase;
3138                 break;
3139         case MSR_SMI_COUNT:
3140                 msr_info->data = vcpu->arch.smi_count;
3141                 break;
3142         case MSR_IA32_PERF_STATUS:
3143                 /* TSC increment by tick */
3144                 msr_info->data = 1000ULL;
3145                 /* CPU multiplier */
3146                 msr_info->data |= (((uint64_t)4ULL) << 40);
3147                 break;
3148         case MSR_EFER:
3149                 msr_info->data = vcpu->arch.efer;
3150                 break;
3151         case MSR_KVM_WALL_CLOCK:
3152         case MSR_KVM_WALL_CLOCK_NEW:
3153                 msr_info->data = vcpu->kvm->arch.wall_clock;
3154                 break;
3155         case MSR_KVM_SYSTEM_TIME:
3156         case MSR_KVM_SYSTEM_TIME_NEW:
3157                 msr_info->data = vcpu->arch.time;
3158                 break;
3159         case MSR_KVM_ASYNC_PF_EN:
3160                 msr_info->data = vcpu->arch.apf.msr_val;
3161                 break;
3162         case MSR_KVM_STEAL_TIME:
3163                 msr_info->data = vcpu->arch.st.msr_val;
3164                 break;
3165         case MSR_KVM_PV_EOI_EN:
3166                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3167                 break;
3168         case MSR_KVM_POLL_CONTROL:
3169                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3170                 break;
3171         case MSR_IA32_P5_MC_ADDR:
3172         case MSR_IA32_P5_MC_TYPE:
3173         case MSR_IA32_MCG_CAP:
3174         case MSR_IA32_MCG_CTL:
3175         case MSR_IA32_MCG_STATUS:
3176         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3177                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3178                                    msr_info->host_initiated);
3179         case MSR_IA32_XSS:
3180                 if (!msr_info->host_initiated &&
3181                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3182                         return 1;
3183                 msr_info->data = vcpu->arch.ia32_xss;
3184                 break;
3185         case MSR_K7_CLK_CTL:
3186                 /*
3187                  * Provide expected ramp-up count for K7. All other
3188                  * are set to zero, indicating minimum divisors for
3189                  * every field.
3190                  *
3191                  * This prevents guest kernels on AMD host with CPU
3192                  * type 6, model 8 and higher from exploding due to
3193                  * the rdmsr failing.
3194                  */
3195                 msr_info->data = 0x20000000;
3196                 break;
3197         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3198         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3199         case HV_X64_MSR_CRASH_CTL:
3200         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3201         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3202         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3203         case HV_X64_MSR_TSC_EMULATION_STATUS:
3204                 return kvm_hv_get_msr_common(vcpu,
3205                                              msr_info->index, &msr_info->data,
3206                                              msr_info->host_initiated);
3207         case MSR_IA32_BBL_CR_CTL3:
3208                 /* This legacy MSR exists but isn't fully documented in current
3209                  * silicon.  It is however accessed by winxp in very narrow
3210                  * scenarios where it sets bit #19, itself documented as
3211                  * a "reserved" bit.  Best effort attempt to source coherent
3212                  * read data here should the balance of the register be
3213                  * interpreted by the guest:
3214                  *
3215                  * L2 cache control register 3: 64GB range, 256KB size,
3216                  * enabled, latency 0x1, configured
3217                  */
3218                 msr_info->data = 0xbe702111;
3219                 break;
3220         case MSR_AMD64_OSVW_ID_LENGTH:
3221                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3222                         return 1;
3223                 msr_info->data = vcpu->arch.osvw.length;
3224                 break;
3225         case MSR_AMD64_OSVW_STATUS:
3226                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3227                         return 1;
3228                 msr_info->data = vcpu->arch.osvw.status;
3229                 break;
3230         case MSR_PLATFORM_INFO:
3231                 if (!msr_info->host_initiated &&
3232                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3233                         return 1;
3234                 msr_info->data = vcpu->arch.msr_platform_info;
3235                 break;
3236         case MSR_MISC_FEATURES_ENABLES:
3237                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3238                 break;
3239         case MSR_K7_HWCR:
3240                 msr_info->data = vcpu->arch.msr_hwcr;
3241                 break;
3242         default:
3243                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3244                         return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3245                 if (!ignore_msrs) {
3246                         vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3247                                                msr_info->index);
3248                         return 1;
3249                 } else {
3250                         if (report_ignored_msrs)
3251                                 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3252                                         msr_info->index);
3253                         msr_info->data = 0;
3254                 }
3255                 break;
3256         }
3257         return 0;
3258 }
3259 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3260
3261 /*
3262  * Read or write a bunch of msrs. All parameters are kernel addresses.
3263  *
3264  * @return number of msrs set successfully.
3265  */
3266 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3267                     struct kvm_msr_entry *entries,
3268                     int (*do_msr)(struct kvm_vcpu *vcpu,
3269                                   unsigned index, u64 *data))
3270 {
3271         int i;
3272
3273         for (i = 0; i < msrs->nmsrs; ++i)
3274                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3275                         break;
3276
3277         return i;
3278 }
3279
3280 /*
3281  * Read or write a bunch of msrs. Parameters are user addresses.
3282  *
3283  * @return number of msrs set successfully.
3284  */
3285 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3286                   int (*do_msr)(struct kvm_vcpu *vcpu,
3287                                 unsigned index, u64 *data),
3288                   int writeback)
3289 {
3290         struct kvm_msrs msrs;
3291         struct kvm_msr_entry *entries;
3292         int r, n;
3293         unsigned size;
3294
3295         r = -EFAULT;
3296         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3297                 goto out;
3298
3299         r = -E2BIG;
3300         if (msrs.nmsrs >= MAX_IO_MSRS)
3301                 goto out;
3302
3303         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3304         entries = memdup_user(user_msrs->entries, size);
3305         if (IS_ERR(entries)) {
3306                 r = PTR_ERR(entries);
3307                 goto out;
3308         }
3309
3310         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3311         if (r < 0)
3312                 goto out_free;
3313
3314         r = -EFAULT;
3315         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3316                 goto out_free;
3317
3318         r = n;
3319
3320 out_free:
3321         kfree(entries);
3322 out:
3323         return r;
3324 }
3325
3326 static inline bool kvm_can_mwait_in_guest(void)
3327 {
3328         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3329                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3330                 boot_cpu_has(X86_FEATURE_ARAT);
3331 }
3332
3333 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3334 {
3335         int r = 0;
3336
3337         switch (ext) {
3338         case KVM_CAP_IRQCHIP:
3339         case KVM_CAP_HLT:
3340         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3341         case KVM_CAP_SET_TSS_ADDR:
3342         case KVM_CAP_EXT_CPUID:
3343         case KVM_CAP_EXT_EMUL_CPUID:
3344         case KVM_CAP_CLOCKSOURCE:
3345         case KVM_CAP_PIT:
3346         case KVM_CAP_NOP_IO_DELAY:
3347         case KVM_CAP_MP_STATE:
3348         case KVM_CAP_SYNC_MMU:
3349         case KVM_CAP_USER_NMI:
3350         case KVM_CAP_REINJECT_CONTROL:
3351         case KVM_CAP_IRQ_INJECT_STATUS:
3352         case KVM_CAP_IOEVENTFD:
3353         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3354         case KVM_CAP_PIT2:
3355         case KVM_CAP_PIT_STATE2:
3356         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3357         case KVM_CAP_XEN_HVM:
3358         case KVM_CAP_VCPU_EVENTS:
3359         case KVM_CAP_HYPERV:
3360         case KVM_CAP_HYPERV_VAPIC:
3361         case KVM_CAP_HYPERV_SPIN:
3362         case KVM_CAP_HYPERV_SYNIC:
3363         case KVM_CAP_HYPERV_SYNIC2:
3364         case KVM_CAP_HYPERV_VP_INDEX:
3365         case KVM_CAP_HYPERV_EVENTFD:
3366         case KVM_CAP_HYPERV_TLBFLUSH:
3367         case KVM_CAP_HYPERV_SEND_IPI:
3368         case KVM_CAP_HYPERV_CPUID:
3369         case KVM_CAP_PCI_SEGMENT:
3370         case KVM_CAP_DEBUGREGS:
3371         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3372         case KVM_CAP_XSAVE:
3373         case KVM_CAP_ASYNC_PF:
3374         case KVM_CAP_GET_TSC_KHZ:
3375         case KVM_CAP_KVMCLOCK_CTRL:
3376         case KVM_CAP_READONLY_MEM:
3377         case KVM_CAP_HYPERV_TIME:
3378         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3379         case KVM_CAP_TSC_DEADLINE_TIMER:
3380         case KVM_CAP_DISABLE_QUIRKS:
3381         case KVM_CAP_SET_BOOT_CPU_ID:
3382         case KVM_CAP_SPLIT_IRQCHIP:
3383         case KVM_CAP_IMMEDIATE_EXIT:
3384         case KVM_CAP_PMU_EVENT_FILTER:
3385         case KVM_CAP_GET_MSR_FEATURES:
3386         case KVM_CAP_MSR_PLATFORM_INFO:
3387         case KVM_CAP_EXCEPTION_PAYLOAD:
3388                 r = 1;
3389                 break;
3390         case KVM_CAP_SYNC_REGS:
3391                 r = KVM_SYNC_X86_VALID_FIELDS;
3392                 break;
3393         case KVM_CAP_ADJUST_CLOCK:
3394                 r = KVM_CLOCK_TSC_STABLE;
3395                 break;
3396         case KVM_CAP_X86_DISABLE_EXITS:
3397                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3398                       KVM_X86_DISABLE_EXITS_CSTATE;
3399                 if(kvm_can_mwait_in_guest())
3400                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3401                 break;
3402         case KVM_CAP_X86_SMM:
3403                 /* SMBASE is usually relocated above 1M on modern chipsets,
3404                  * and SMM handlers might indeed rely on 4G segment limits,
3405                  * so do not report SMM to be available if real mode is
3406                  * emulated via vm86 mode.  Still, do not go to great lengths
3407                  * to avoid userspace's usage of the feature, because it is a
3408                  * fringe case that is not enabled except via specific settings
3409                  * of the module parameters.
3410                  */
3411                 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3412                 break;
3413         case KVM_CAP_VAPIC:
3414                 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3415                 break;
3416         case KVM_CAP_NR_VCPUS:
3417                 r = KVM_SOFT_MAX_VCPUS;
3418                 break;
3419         case KVM_CAP_MAX_VCPUS:
3420                 r = KVM_MAX_VCPUS;
3421                 break;
3422         case KVM_CAP_MAX_VCPU_ID:
3423                 r = KVM_MAX_VCPU_ID;
3424                 break;
3425         case KVM_CAP_PV_MMU:    /* obsolete */
3426                 r = 0;
3427                 break;
3428         case KVM_CAP_MCE:
3429                 r = KVM_MAX_MCE_BANKS;
3430                 break;
3431         case KVM_CAP_XCRS:
3432                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3433                 break;
3434         case KVM_CAP_TSC_CONTROL:
3435                 r = kvm_has_tsc_control;
3436                 break;
3437         case KVM_CAP_X2APIC_API:
3438                 r = KVM_X2APIC_API_VALID_FLAGS;
3439                 break;
3440         case KVM_CAP_NESTED_STATE:
3441                 r = kvm_x86_ops.get_nested_state ?
3442                         kvm_x86_ops.get_nested_state(NULL, NULL, 0) : 0;
3443                 break;
3444         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3445                 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3446                 break;
3447         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3448                 r = kvm_x86_ops.nested_enable_evmcs != NULL;
3449                 break;
3450         default:
3451                 break;
3452         }
3453         return r;
3454
3455 }
3456
3457 long kvm_arch_dev_ioctl(struct file *filp,
3458                         unsigned int ioctl, unsigned long arg)
3459 {
3460         void __user *argp = (void __user *)arg;
3461         long r;
3462
3463         switch (ioctl) {
3464         case KVM_GET_MSR_INDEX_LIST: {
3465                 struct kvm_msr_list __user *user_msr_list = argp;
3466                 struct kvm_msr_list msr_list;
3467                 unsigned n;
3468
3469                 r = -EFAULT;
3470                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3471                         goto out;
3472                 n = msr_list.nmsrs;
3473                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3474                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3475                         goto out;
3476                 r = -E2BIG;
3477                 if (n < msr_list.nmsrs)
3478                         goto out;
3479                 r = -EFAULT;
3480                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3481                                  num_msrs_to_save * sizeof(u32)))
3482                         goto out;
3483                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3484                                  &emulated_msrs,
3485                                  num_emulated_msrs * sizeof(u32)))
3486                         goto out;
3487                 r = 0;
3488                 break;
3489         }
3490         case KVM_GET_SUPPORTED_CPUID:
3491         case KVM_GET_EMULATED_CPUID: {
3492                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3493                 struct kvm_cpuid2 cpuid;
3494
3495                 r = -EFAULT;
3496                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3497                         goto out;
3498
3499                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3500                                             ioctl);
3501                 if (r)
3502                         goto out;
3503
3504                 r = -EFAULT;
3505                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3506                         goto out;
3507                 r = 0;
3508                 break;
3509         }
3510         case KVM_X86_GET_MCE_CAP_SUPPORTED:
3511                 r = -EFAULT;
3512                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3513                                  sizeof(kvm_mce_cap_supported)))
3514                         goto out;
3515                 r = 0;
3516                 break;
3517         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3518                 struct kvm_msr_list __user *user_msr_list = argp;
3519                 struct kvm_msr_list msr_list;
3520                 unsigned int n;
3521
3522                 r = -EFAULT;
3523                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3524                         goto out;
3525                 n = msr_list.nmsrs;
3526                 msr_list.nmsrs = num_msr_based_features;
3527                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3528                         goto out;
3529                 r = -E2BIG;
3530                 if (n < msr_list.nmsrs)
3531                         goto out;
3532                 r = -EFAULT;
3533                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3534                                  num_msr_based_features * sizeof(u32)))
3535                         goto out;
3536                 r = 0;
3537                 break;
3538         }
3539         case KVM_GET_MSRS:
3540                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3541                 break;
3542         default:
3543                 r = -EINVAL;
3544                 break;
3545         }
3546 out:
3547         return r;
3548 }
3549
3550 static void wbinvd_ipi(void *garbage)
3551 {
3552         wbinvd();
3553 }
3554
3555 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3556 {
3557         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3558 }
3559
3560 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3561 {
3562         /* Address WBINVD may be executed by guest */
3563         if (need_emulate_wbinvd(vcpu)) {
3564                 if (kvm_x86_ops.has_wbinvd_exit())
3565                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3566                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3567                         smp_call_function_single(vcpu->cpu,
3568                                         wbinvd_ipi, NULL, 1);
3569         }
3570
3571         kvm_x86_ops.vcpu_load(vcpu, cpu);
3572
3573         /* Apply any externally detected TSC adjustments (due to suspend) */
3574         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3575                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3576                 vcpu->arch.tsc_offset_adjustment = 0;
3577                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3578         }
3579
3580         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3581                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3582                                 rdtsc() - vcpu->arch.last_host_tsc;
3583                 if (tsc_delta < 0)
3584                         mark_tsc_unstable("KVM discovered backwards TSC");
3585
3586                 if (kvm_check_tsc_unstable()) {
3587                         u64 offset = kvm_compute_tsc_offset(vcpu,
3588                                                 vcpu->arch.last_guest_tsc);
3589                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3590                         vcpu->arch.tsc_catchup = 1;
3591                 }
3592
3593                 if (kvm_lapic_hv_timer_in_use(vcpu))
3594                         kvm_lapic_restart_hv_timer(vcpu);
3595
3596                 /*
3597                  * On a host with synchronized TSC, there is no need to update
3598                  * kvmclock on vcpu->cpu migration
3599                  */
3600                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3601                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3602                 if (vcpu->cpu != cpu)
3603                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3604                 vcpu->cpu = cpu;
3605         }
3606
3607         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3608 }
3609
3610 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3611 {
3612         struct kvm_host_map map;
3613         struct kvm_steal_time *st;
3614
3615         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3616                 return;
3617
3618         if (vcpu->arch.st.preempted)
3619                 return;
3620
3621         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3622                         &vcpu->arch.st.cache, true))
3623                 return;
3624
3625         st = map.hva +
3626                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3627
3628         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3629
3630         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3631 }
3632
3633 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3634 {
3635         int idx;
3636
3637         if (vcpu->preempted)
3638                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3639
3640         /*
3641          * Disable page faults because we're in atomic context here.
3642          * kvm_write_guest_offset_cached() would call might_fault()
3643          * that relies on pagefault_disable() to tell if there's a
3644          * bug. NOTE: the write to guest memory may not go through if
3645          * during postcopy live migration or if there's heavy guest
3646          * paging.
3647          */
3648         pagefault_disable();
3649         /*
3650          * kvm_memslots() will be called by
3651          * kvm_write_guest_offset_cached() so take the srcu lock.
3652          */
3653         idx = srcu_read_lock(&vcpu->kvm->srcu);
3654         kvm_steal_time_set_preempted(vcpu);
3655         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3656         pagefault_enable();
3657         kvm_x86_ops.vcpu_put(vcpu);
3658         vcpu->arch.last_host_tsc = rdtsc();
3659         /*
3660          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3661          * on every vmexit, but if not, we might have a stale dr6 from the
3662          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3663          */
3664         set_debugreg(0, 6);
3665 }
3666
3667 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3668                                     struct kvm_lapic_state *s)
3669 {
3670         if (vcpu->arch.apicv_active)
3671                 kvm_x86_ops.sync_pir_to_irr(vcpu);
3672
3673         return kvm_apic_get_state(vcpu, s);
3674 }
3675
3676 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3677                                     struct kvm_lapic_state *s)
3678 {
3679         int r;
3680
3681         r = kvm_apic_set_state(vcpu, s);
3682         if (r)
3683                 return r;
3684         update_cr8_intercept(vcpu);
3685
3686         return 0;
3687 }
3688
3689 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3690 {
3691         return (!lapic_in_kernel(vcpu) ||
3692                 kvm_apic_accept_pic_intr(vcpu));
3693 }
3694
3695 /*
3696  * if userspace requested an interrupt window, check that the
3697  * interrupt window is open.
3698  *
3699  * No need to exit to userspace if we already have an interrupt queued.
3700  */
3701 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3702 {
3703         return kvm_arch_interrupt_allowed(vcpu) &&
3704                 !kvm_cpu_has_interrupt(vcpu) &&
3705                 !kvm_event_needs_reinjection(vcpu) &&
3706                 kvm_cpu_accept_dm_intr(vcpu);
3707 }
3708
3709 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3710                                     struct kvm_interrupt *irq)
3711 {
3712         if (irq->irq >= KVM_NR_INTERRUPTS)
3713                 return -EINVAL;
3714
3715         if (!irqchip_in_kernel(vcpu->kvm)) {
3716                 kvm_queue_interrupt(vcpu, irq->irq, false);
3717                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3718                 return 0;
3719         }
3720
3721         /*
3722          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3723          * fail for in-kernel 8259.
3724          */
3725         if (pic_in_kernel(vcpu->kvm))
3726                 return -ENXIO;
3727
3728         if (vcpu->arch.pending_external_vector != -1)
3729                 return -EEXIST;
3730
3731         vcpu->arch.pending_external_vector = irq->irq;
3732         kvm_make_request(KVM_REQ_EVENT, vcpu);
3733         return 0;
3734 }
3735
3736 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3737 {
3738         kvm_inject_nmi(vcpu);
3739
3740         return 0;
3741 }
3742
3743 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3744 {
3745         kvm_make_request(KVM_REQ_SMI, vcpu);
3746
3747         return 0;
3748 }
3749
3750 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3751                                            struct kvm_tpr_access_ctl *tac)
3752 {
3753         if (tac->flags)
3754                 return -EINVAL;
3755         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3756         return 0;
3757 }
3758
3759 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3760                                         u64 mcg_cap)
3761 {
3762         int r;
3763         unsigned bank_num = mcg_cap & 0xff, bank;
3764
3765         r = -EINVAL;
3766         if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
3767                 goto out;
3768         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3769                 goto out;
3770         r = 0;
3771         vcpu->arch.mcg_cap = mcg_cap;
3772         /* Init IA32_MCG_CTL to all 1s */
3773         if (mcg_cap & MCG_CTL_P)
3774                 vcpu->arch.mcg_ctl = ~(u64)0;
3775         /* Init IA32_MCi_CTL to all 1s */
3776         for (bank = 0; bank < bank_num; bank++)
3777                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3778
3779         kvm_x86_ops.setup_mce(vcpu);
3780 out:
3781         return r;
3782 }
3783
3784 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3785                                       struct kvm_x86_mce *mce)
3786 {
3787         u64 mcg_cap = vcpu->arch.mcg_cap;
3788         unsigned bank_num = mcg_cap & 0xff;
3789         u64 *banks = vcpu->arch.mce_banks;
3790
3791         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3792                 return -EINVAL;
3793         /*
3794          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3795          * reporting is disabled
3796          */
3797         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3798             vcpu->arch.mcg_ctl != ~(u64)0)
3799                 return 0;
3800         banks += 4 * mce->bank;
3801         /*
3802          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3803          * reporting is disabled for the bank
3804          */
3805         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3806                 return 0;
3807         if (mce->status & MCI_STATUS_UC) {
3808                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3809                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3810                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3811                         return 0;
3812                 }
3813                 if (banks[1] & MCI_STATUS_VAL)
3814                         mce->status |= MCI_STATUS_OVER;
3815                 banks[2] = mce->addr;
3816                 banks[3] = mce->misc;
3817                 vcpu->arch.mcg_status = mce->mcg_status;
3818                 banks[1] = mce->status;
3819                 kvm_queue_exception(vcpu, MC_VECTOR);
3820         } else if (!(banks[1] & MCI_STATUS_VAL)
3821                    || !(banks[1] & MCI_STATUS_UC)) {
3822                 if (banks[1] & MCI_STATUS_VAL)
3823                         mce->status |= MCI_STATUS_OVER;
3824                 banks[2] = mce->addr;
3825                 banks[3] = mce->misc;
3826                 banks[1] = mce->status;
3827         } else
3828                 banks[1] |= MCI_STATUS_OVER;
3829         return 0;
3830 }
3831
3832 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3833                                                struct kvm_vcpu_events *events)
3834 {
3835         process_nmi(vcpu);
3836
3837         /*
3838          * In guest mode, payload delivery should be deferred,
3839          * so that the L1 hypervisor can intercept #PF before
3840          * CR2 is modified (or intercept #DB before DR6 is
3841          * modified under nVMX). Unless the per-VM capability,
3842          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3843          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3844          * opportunistically defer the exception payload, deliver it if the
3845          * capability hasn't been requested before processing a
3846          * KVM_GET_VCPU_EVENTS.
3847          */
3848         if (!vcpu->kvm->arch.exception_payload_enabled &&
3849             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3850                 kvm_deliver_exception_payload(vcpu);
3851
3852         /*
3853          * The API doesn't provide the instruction length for software
3854          * exceptions, so don't report them. As long as the guest RIP
3855          * isn't advanced, we should expect to encounter the exception
3856          * again.
3857          */
3858         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3859                 events->exception.injected = 0;
3860                 events->exception.pending = 0;
3861         } else {
3862                 events->exception.injected = vcpu->arch.exception.injected;
3863                 events->exception.pending = vcpu->arch.exception.pending;
3864                 /*
3865                  * For ABI compatibility, deliberately conflate
3866                  * pending and injected exceptions when
3867                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3868                  */
3869                 if (!vcpu->kvm->arch.exception_payload_enabled)
3870                         events->exception.injected |=
3871                                 vcpu->arch.exception.pending;
3872         }
3873         events->exception.nr = vcpu->arch.exception.nr;
3874         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3875         events->exception.error_code = vcpu->arch.exception.error_code;
3876         events->exception_has_payload = vcpu->arch.exception.has_payload;
3877         events->exception_payload = vcpu->arch.exception.payload;
3878
3879         events->interrupt.injected =
3880                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3881         events->interrupt.nr = vcpu->arch.interrupt.nr;
3882         events->interrupt.soft = 0;
3883         events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
3884
3885         events->nmi.injected = vcpu->arch.nmi_injected;
3886         events->nmi.pending = vcpu->arch.nmi_pending != 0;
3887         events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
3888         events->nmi.pad = 0;
3889
3890         events->sipi_vector = 0; /* never valid when reporting to user space */
3891
3892         events->smi.smm = is_smm(vcpu);
3893         events->smi.pending = vcpu->arch.smi_pending;
3894         events->smi.smm_inside_nmi =
3895                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3896         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3897
3898         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
3899                          | KVM_VCPUEVENT_VALID_SHADOW
3900                          | KVM_VCPUEVENT_VALID_SMM);
3901         if (vcpu->kvm->arch.exception_payload_enabled)
3902                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3903
3904         memset(&events->reserved, 0, sizeof(events->reserved));
3905 }
3906
3907 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
3908
3909 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3910                                               struct kvm_vcpu_events *events)
3911 {
3912         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
3913                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3914                               | KVM_VCPUEVENT_VALID_SHADOW
3915                               | KVM_VCPUEVENT_VALID_SMM
3916                               | KVM_VCPUEVENT_VALID_PAYLOAD))
3917                 return -EINVAL;
3918
3919         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3920                 if (!vcpu->kvm->arch.exception_payload_enabled)
3921                         return -EINVAL;
3922                 if (events->exception.pending)
3923                         events->exception.injected = 0;
3924                 else
3925                         events->exception_has_payload = 0;
3926         } else {
3927                 events->exception.pending = 0;
3928                 events->exception_has_payload = 0;
3929         }
3930
3931         if ((events->exception.injected || events->exception.pending) &&
3932             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3933                 return -EINVAL;
3934
3935         /* INITs are latched while in SMM */
3936         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3937             (events->smi.smm || events->smi.pending) &&
3938             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3939                 return -EINVAL;
3940
3941         process_nmi(vcpu);
3942         vcpu->arch.exception.injected = events->exception.injected;
3943         vcpu->arch.exception.pending = events->exception.pending;
3944         vcpu->arch.exception.nr = events->exception.nr;
3945         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3946         vcpu->arch.exception.error_code = events->exception.error_code;
3947         vcpu->arch.exception.has_payload = events->exception_has_payload;
3948         vcpu->arch.exception.payload = events->exception_payload;
3949
3950         vcpu->arch.interrupt.injected = events->interrupt.injected;
3951         vcpu->arch.interrupt.nr = events->interrupt.nr;
3952         vcpu->arch.interrupt.soft = events->interrupt.soft;
3953         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3954                 kvm_x86_ops.set_interrupt_shadow(vcpu,
3955                                                   events->interrupt.shadow);
3956
3957         vcpu->arch.nmi_injected = events->nmi.injected;
3958         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3959                 vcpu->arch.nmi_pending = events->nmi.pending;
3960         kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
3961
3962         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3963             lapic_in_kernel(vcpu))
3964                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3965
3966         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3967                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3968                         if (events->smi.smm)
3969                                 vcpu->arch.hflags |= HF_SMM_MASK;
3970                         else
3971                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
3972                         kvm_smm_changed(vcpu);
3973                 }
3974
3975                 vcpu->arch.smi_pending = events->smi.pending;
3976
3977                 if (events->smi.smm) {
3978                         if (events->smi.smm_inside_nmi)
3979                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3980                         else
3981                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3982                 }
3983
3984                 if (lapic_in_kernel(vcpu)) {
3985                         if (events->smi.latched_init)
3986                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3987                         else
3988                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3989                 }
3990         }
3991
3992         kvm_make_request(KVM_REQ_EVENT, vcpu);
3993
3994         return 0;
3995 }
3996
3997 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3998                                              struct kvm_debugregs *dbgregs)
3999 {
4000         unsigned long val;
4001
4002         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4003         kvm_get_dr(vcpu, 6, &val);
4004         dbgregs->dr6 = val;
4005         dbgregs->dr7 = vcpu->arch.dr7;
4006         dbgregs->flags = 0;
4007         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4008 }
4009
4010 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4011                                             struct kvm_debugregs *dbgregs)
4012 {
4013         if (dbgregs->flags)
4014                 return -EINVAL;
4015
4016         if (dbgregs->dr6 & ~0xffffffffull)
4017                 return -EINVAL;
4018         if (dbgregs->dr7 & ~0xffffffffull)
4019                 return -EINVAL;
4020
4021         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4022         kvm_update_dr0123(vcpu);
4023         vcpu->arch.dr6 = dbgregs->dr6;
4024         kvm_update_dr6(vcpu);
4025         vcpu->arch.dr7 = dbgregs->dr7;
4026         kvm_update_dr7(vcpu);
4027
4028         return 0;
4029 }
4030
4031 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4032
4033 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4034 {
4035         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4036         u64 xstate_bv = xsave->header.xfeatures;
4037         u64 valid;
4038
4039         /*
4040          * Copy legacy XSAVE area, to avoid complications with CPUID
4041          * leaves 0 and 1 in the loop below.
4042          */
4043         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4044
4045         /* Set XSTATE_BV */
4046         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4047         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4048
4049         /*
4050          * Copy each region from the possibly compacted offset to the
4051          * non-compacted offset.
4052          */
4053         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4054         while (valid) {
4055                 u64 xfeature_mask = valid & -valid;
4056                 int xfeature_nr = fls64(xfeature_mask) - 1;
4057                 void *src = get_xsave_addr(xsave, xfeature_nr);
4058
4059                 if (src) {
4060                         u32 size, offset, ecx, edx;
4061                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4062                                     &size, &offset, &ecx, &edx);
4063                         if (xfeature_nr == XFEATURE_PKRU)
4064                                 memcpy(dest + offset, &vcpu->arch.pkru,
4065                                        sizeof(vcpu->arch.pkru));
4066                         else
4067                                 memcpy(dest + offset, src, size);
4068
4069                 }
4070
4071                 valid -= xfeature_mask;
4072         }
4073 }
4074
4075 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4076 {
4077         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4078         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4079         u64 valid;
4080
4081         /*
4082          * Copy legacy XSAVE area, to avoid complications with CPUID
4083          * leaves 0 and 1 in the loop below.
4084          */
4085         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4086
4087         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4088         xsave->header.xfeatures = xstate_bv;
4089         if (boot_cpu_has(X86_FEATURE_XSAVES))
4090                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4091
4092         /*
4093          * Copy each region from the non-compacted offset to the
4094          * possibly compacted offset.
4095          */
4096         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4097         while (valid) {
4098                 u64 xfeature_mask = valid & -valid;
4099                 int xfeature_nr = fls64(xfeature_mask) - 1;
4100                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4101
4102                 if (dest) {
4103                         u32 size, offset, ecx, edx;
4104                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4105                                     &size, &offset, &ecx, &edx);
4106                         if (xfeature_nr == XFEATURE_PKRU)
4107                                 memcpy(&vcpu->arch.pkru, src + offset,
4108                                        sizeof(vcpu->arch.pkru));
4109                         else
4110                                 memcpy(dest, src + offset, size);
4111                 }
4112
4113                 valid -= xfeature_mask;
4114         }
4115 }
4116
4117 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4118                                          struct kvm_xsave *guest_xsave)
4119 {
4120         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4121                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4122                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4123         } else {
4124                 memcpy(guest_xsave->region,
4125                         &vcpu->arch.guest_fpu->state.fxsave,
4126                         sizeof(struct fxregs_state));
4127                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4128                         XFEATURE_MASK_FPSSE;
4129         }
4130 }
4131
4132 #define XSAVE_MXCSR_OFFSET 24
4133
4134 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4135                                         struct kvm_xsave *guest_xsave)
4136 {
4137         u64 xstate_bv =
4138                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4139         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4140
4141         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4142                 /*
4143                  * Here we allow setting states that are not present in
4144                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4145                  * with old userspace.
4146                  */
4147                 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4148                         return -EINVAL;
4149                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4150         } else {
4151                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4152                         mxcsr & ~mxcsr_feature_mask)
4153                         return -EINVAL;
4154                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4155                         guest_xsave->region, sizeof(struct fxregs_state));
4156         }
4157         return 0;
4158 }
4159
4160 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4161                                         struct kvm_xcrs *guest_xcrs)
4162 {
4163         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4164                 guest_xcrs->nr_xcrs = 0;
4165                 return;
4166         }
4167
4168         guest_xcrs->nr_xcrs = 1;
4169         guest_xcrs->flags = 0;
4170         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4171         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4172 }
4173
4174 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4175                                        struct kvm_xcrs *guest_xcrs)
4176 {
4177         int i, r = 0;
4178
4179         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4180                 return -EINVAL;
4181
4182         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4183                 return -EINVAL;
4184
4185         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4186                 /* Only support XCR0 currently */
4187                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4188                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4189                                 guest_xcrs->xcrs[i].value);
4190                         break;
4191                 }
4192         if (r)
4193                 r = -EINVAL;
4194         return r;
4195 }
4196
4197 /*
4198  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4199  * stopped by the hypervisor.  This function will be called from the host only.
4200  * EINVAL is returned when the host attempts to set the flag for a guest that
4201  * does not support pv clocks.
4202  */
4203 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4204 {
4205         if (!vcpu->arch.pv_time_enabled)
4206                 return -EINVAL;
4207         vcpu->arch.pvclock_set_guest_stopped_request = true;
4208         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4209         return 0;
4210 }
4211
4212 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4213                                      struct kvm_enable_cap *cap)
4214 {
4215         int r;
4216         uint16_t vmcs_version;
4217         void __user *user_ptr;
4218
4219         if (cap->flags)
4220                 return -EINVAL;
4221
4222         switch (cap->cap) {
4223         case KVM_CAP_HYPERV_SYNIC2:
4224                 if (cap->args[0])
4225                         return -EINVAL;
4226                 /* fall through */
4227
4228         case KVM_CAP_HYPERV_SYNIC:
4229                 if (!irqchip_in_kernel(vcpu->kvm))
4230                         return -EINVAL;
4231                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4232                                              KVM_CAP_HYPERV_SYNIC2);
4233         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4234                 if (!kvm_x86_ops.nested_enable_evmcs)
4235                         return -ENOTTY;
4236                 r = kvm_x86_ops.nested_enable_evmcs(vcpu, &vmcs_version);
4237                 if (!r) {
4238                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4239                         if (copy_to_user(user_ptr, &vmcs_version,
4240                                          sizeof(vmcs_version)))
4241                                 r = -EFAULT;
4242                 }
4243                 return r;
4244         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4245                 if (!kvm_x86_ops.enable_direct_tlbflush)
4246                         return -ENOTTY;
4247
4248                 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4249
4250         default:
4251                 return -EINVAL;
4252         }
4253 }
4254
4255 long kvm_arch_vcpu_ioctl(struct file *filp,
4256                          unsigned int ioctl, unsigned long arg)
4257 {
4258         struct kvm_vcpu *vcpu = filp->private_data;
4259         void __user *argp = (void __user *)arg;
4260         int r;
4261         union {
4262                 struct kvm_lapic_state *lapic;
4263                 struct kvm_xsave *xsave;
4264                 struct kvm_xcrs *xcrs;
4265                 void *buffer;
4266         } u;
4267
4268         vcpu_load(vcpu);
4269
4270         u.buffer = NULL;
4271         switch (ioctl) {
4272         case KVM_GET_LAPIC: {
4273                 r = -EINVAL;
4274                 if (!lapic_in_kernel(vcpu))
4275                         goto out;
4276                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4277                                 GFP_KERNEL_ACCOUNT);
4278
4279                 r = -ENOMEM;
4280                 if (!u.lapic)
4281                         goto out;
4282                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4283                 if (r)
4284                         goto out;
4285                 r = -EFAULT;
4286                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4287                         goto out;
4288                 r = 0;
4289                 break;
4290         }
4291         case KVM_SET_LAPIC: {
4292                 r = -EINVAL;
4293                 if (!lapic_in_kernel(vcpu))
4294                         goto out;
4295                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4296                 if (IS_ERR(u.lapic)) {
4297                         r = PTR_ERR(u.lapic);
4298                         goto out_nofree;
4299                 }
4300
4301                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4302                 break;
4303         }
4304         case KVM_INTERRUPT: {
4305                 struct kvm_interrupt irq;
4306
4307                 r = -EFAULT;
4308                 if (copy_from_user(&irq, argp, sizeof(irq)))
4309                         goto out;
4310                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4311                 break;
4312         }
4313         case KVM_NMI: {
4314                 r = kvm_vcpu_ioctl_nmi(vcpu);
4315                 break;
4316         }
4317         case KVM_SMI: {
4318                 r = kvm_vcpu_ioctl_smi(vcpu);
4319                 break;
4320         }
4321         case KVM_SET_CPUID: {
4322                 struct kvm_cpuid __user *cpuid_arg = argp;
4323                 struct kvm_cpuid cpuid;
4324
4325                 r = -EFAULT;
4326                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4327                         goto out;
4328                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4329                 break;
4330         }
4331         case KVM_SET_CPUID2: {
4332                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4333                 struct kvm_cpuid2 cpuid;
4334
4335                 r = -EFAULT;
4336                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4337                         goto out;
4338                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4339                                               cpuid_arg->entries);
4340                 break;
4341         }
4342         case KVM_GET_CPUID2: {
4343                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4344                 struct kvm_cpuid2 cpuid;
4345
4346                 r = -EFAULT;
4347                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4348                         goto out;
4349                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4350                                               cpuid_arg->entries);
4351                 if (r)
4352                         goto out;
4353                 r = -EFAULT;
4354                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4355                         goto out;
4356                 r = 0;
4357                 break;
4358         }
4359         case KVM_GET_MSRS: {
4360                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4361                 r = msr_io(vcpu, argp, do_get_msr, 1);
4362                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4363                 break;
4364         }
4365         case KVM_SET_MSRS: {
4366                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4367                 r = msr_io(vcpu, argp, do_set_msr, 0);
4368                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4369                 break;
4370         }
4371         case KVM_TPR_ACCESS_REPORTING: {
4372                 struct kvm_tpr_access_ctl tac;
4373
4374                 r = -EFAULT;
4375                 if (copy_from_user(&tac, argp, sizeof(tac)))
4376                         goto out;
4377                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4378                 if (r)
4379                         goto out;
4380                 r = -EFAULT;
4381                 if (copy_to_user(argp, &tac, sizeof(tac)))
4382                         goto out;
4383                 r = 0;
4384                 break;
4385         };
4386         case KVM_SET_VAPIC_ADDR: {
4387                 struct kvm_vapic_addr va;
4388                 int idx;
4389
4390                 r = -EINVAL;
4391                 if (!lapic_in_kernel(vcpu))
4392                         goto out;
4393                 r = -EFAULT;
4394                 if (copy_from_user(&va, argp, sizeof(va)))
4395                         goto out;
4396                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4397                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4398                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4399                 break;
4400         }
4401         case KVM_X86_SETUP_MCE: {
4402                 u64 mcg_cap;
4403
4404                 r = -EFAULT;
4405                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4406                         goto out;
4407                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4408                 break;
4409         }
4410         case KVM_X86_SET_MCE: {
4411                 struct kvm_x86_mce mce;
4412
4413                 r = -EFAULT;
4414                 if (copy_from_user(&mce, argp, sizeof(mce)))
4415                         goto out;
4416                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4417                 break;
4418         }
4419         case KVM_GET_VCPU_EVENTS: {
4420                 struct kvm_vcpu_events events;
4421
4422                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4423
4424                 r = -EFAULT;
4425                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4426                         break;
4427                 r = 0;
4428                 break;
4429         }
4430         case KVM_SET_VCPU_EVENTS: {
4431                 struct kvm_vcpu_events events;
4432
4433                 r = -EFAULT;
4434                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4435                         break;
4436
4437                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4438                 break;
4439         }
4440         case KVM_GET_DEBUGREGS: {
4441                 struct kvm_debugregs dbgregs;
4442
4443                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4444
4445                 r = -EFAULT;
4446                 if (copy_to_user(argp, &dbgregs,
4447                                  sizeof(struct kvm_debugregs)))
4448                         break;
4449                 r = 0;
4450                 break;
4451         }
4452         case KVM_SET_DEBUGREGS: {
4453                 struct kvm_debugregs dbgregs;
4454
4455                 r = -EFAULT;
4456                 if (copy_from_user(&dbgregs, argp,
4457                                    sizeof(struct kvm_debugregs)))
4458                         break;
4459
4460                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4461                 break;
4462         }
4463         case KVM_GET_XSAVE: {
4464                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4465                 r = -ENOMEM;
4466                 if (!u.xsave)
4467                         break;
4468
4469                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4470
4471                 r = -EFAULT;
4472                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4473                         break;
4474                 r = 0;
4475                 break;
4476         }
4477         case KVM_SET_XSAVE: {
4478                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4479                 if (IS_ERR(u.xsave)) {
4480                         r = PTR_ERR(u.xsave);
4481                         goto out_nofree;
4482                 }
4483
4484                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4485                 break;
4486         }
4487         case KVM_GET_XCRS: {
4488                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4489                 r = -ENOMEM;
4490                 if (!u.xcrs)
4491                         break;
4492
4493                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4494
4495                 r = -EFAULT;
4496                 if (copy_to_user(argp, u.xcrs,
4497                                  sizeof(struct kvm_xcrs)))
4498                         break;
4499                 r = 0;
4500                 break;
4501         }
4502         case KVM_SET_XCRS: {
4503                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4504                 if (IS_ERR(u.xcrs)) {
4505                         r = PTR_ERR(u.xcrs);
4506                         goto out_nofree;
4507                 }
4508
4509                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4510                 break;
4511         }
4512         case KVM_SET_TSC_KHZ: {
4513                 u32 user_tsc_khz;
4514
4515                 r = -EINVAL;
4516                 user_tsc_khz = (u32)arg;
4517
4518                 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4519                         goto out;
4520
4521                 if (user_tsc_khz == 0)
4522                         user_tsc_khz = tsc_khz;
4523
4524                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4525                         r = 0;
4526
4527                 goto out;
4528         }
4529         case KVM_GET_TSC_KHZ: {
4530                 r = vcpu->arch.virtual_tsc_khz;
4531                 goto out;
4532         }
4533         case KVM_KVMCLOCK_CTRL: {
4534                 r = kvm_set_guest_paused(vcpu);
4535                 goto out;
4536         }
4537         case KVM_ENABLE_CAP: {
4538                 struct kvm_enable_cap cap;
4539
4540                 r = -EFAULT;
4541                 if (copy_from_user(&cap, argp, sizeof(cap)))
4542                         goto out;
4543                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4544                 break;
4545         }
4546         case KVM_GET_NESTED_STATE: {
4547                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4548                 u32 user_data_size;
4549
4550                 r = -EINVAL;
4551                 if (!kvm_x86_ops.get_nested_state)
4552                         break;
4553
4554                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4555                 r = -EFAULT;
4556                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4557                         break;
4558
4559                 r = kvm_x86_ops.get_nested_state(vcpu, user_kvm_nested_state,
4560                                                   user_data_size);
4561                 if (r < 0)
4562                         break;
4563
4564                 if (r > user_data_size) {
4565                         if (put_user(r, &user_kvm_nested_state->size))
4566                                 r = -EFAULT;
4567                         else
4568                                 r = -E2BIG;
4569                         break;
4570                 }
4571
4572                 r = 0;
4573                 break;
4574         }
4575         case KVM_SET_NESTED_STATE: {
4576                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4577                 struct kvm_nested_state kvm_state;
4578                 int idx;
4579
4580                 r = -EINVAL;
4581                 if (!kvm_x86_ops.set_nested_state)
4582                         break;
4583
4584                 r = -EFAULT;
4585                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4586                         break;
4587
4588                 r = -EINVAL;
4589                 if (kvm_state.size < sizeof(kvm_state))
4590                         break;
4591
4592                 if (kvm_state.flags &
4593                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4594                       | KVM_STATE_NESTED_EVMCS))
4595                         break;
4596
4597                 /* nested_run_pending implies guest_mode.  */
4598                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4599                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4600                         break;
4601
4602                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4603                 r = kvm_x86_ops.set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4604                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4605                 break;
4606         }
4607         case KVM_GET_SUPPORTED_HV_CPUID: {
4608                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4609                 struct kvm_cpuid2 cpuid;
4610
4611                 r = -EFAULT;
4612                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4613                         goto out;
4614
4615                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4616                                                 cpuid_arg->entries);
4617                 if (r)
4618                         goto out;
4619
4620                 r = -EFAULT;
4621                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4622                         goto out;
4623                 r = 0;
4624                 break;
4625         }
4626         default:
4627                 r = -EINVAL;
4628         }
4629 out:
4630         kfree(u.buffer);
4631 out_nofree:
4632         vcpu_put(vcpu);
4633         return r;
4634 }
4635
4636 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4637 {
4638         return VM_FAULT_SIGBUS;
4639 }
4640
4641 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4642 {
4643         int ret;
4644
4645         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4646                 return -EINVAL;
4647         ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4648         return ret;
4649 }
4650
4651 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4652                                               u64 ident_addr)
4653 {
4654         return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4655 }
4656
4657 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4658                                          unsigned long kvm_nr_mmu_pages)
4659 {
4660         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4661                 return -EINVAL;
4662
4663         mutex_lock(&kvm->slots_lock);
4664
4665         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4666         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4667
4668         mutex_unlock(&kvm->slots_lock);
4669         return 0;
4670 }
4671
4672 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4673 {
4674         return kvm->arch.n_max_mmu_pages;
4675 }
4676
4677 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4678 {
4679         struct kvm_pic *pic = kvm->arch.vpic;
4680         int r;
4681
4682         r = 0;
4683         switch (chip->chip_id) {
4684         case KVM_IRQCHIP_PIC_MASTER:
4685                 memcpy(&chip->chip.pic, &pic->pics[0],
4686                         sizeof(struct kvm_pic_state));
4687                 break;
4688         case KVM_IRQCHIP_PIC_SLAVE:
4689                 memcpy(&chip->chip.pic, &pic->pics[1],
4690                         sizeof(struct kvm_pic_state));
4691                 break;
4692         case KVM_IRQCHIP_IOAPIC:
4693                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4694                 break;
4695         default:
4696                 r = -EINVAL;
4697                 break;
4698         }
4699         return r;
4700 }
4701
4702 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4703 {
4704         struct kvm_pic *pic = kvm->arch.vpic;
4705         int r;
4706
4707         r = 0;
4708         switch (chip->chip_id) {
4709         case KVM_IRQCHIP_PIC_MASTER:
4710                 spin_lock(&pic->lock);
4711                 memcpy(&pic->pics[0], &chip->chip.pic,
4712                         sizeof(struct kvm_pic_state));
4713                 spin_unlock(&pic->lock);
4714                 break;
4715         case KVM_IRQCHIP_PIC_SLAVE:
4716                 spin_lock(&pic->lock);
4717                 memcpy(&pic->pics[1], &chip->chip.pic,
4718                         sizeof(struct kvm_pic_state));
4719                 spin_unlock(&pic->lock);
4720                 break;
4721         case KVM_IRQCHIP_IOAPIC:
4722                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4723                 break;
4724         default:
4725                 r = -EINVAL;
4726                 break;
4727         }
4728         kvm_pic_update_irq(pic);
4729         return r;
4730 }
4731
4732 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4733 {
4734         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4735
4736         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4737
4738         mutex_lock(&kps->lock);
4739         memcpy(ps, &kps->channels, sizeof(*ps));
4740         mutex_unlock(&kps->lock);
4741         return 0;
4742 }
4743
4744 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4745 {
4746         int i;
4747         struct kvm_pit *pit = kvm->arch.vpit;
4748
4749         mutex_lock(&pit->pit_state.lock);
4750         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4751         for (i = 0; i < 3; i++)
4752                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4753         mutex_unlock(&pit->pit_state.lock);
4754         return 0;
4755 }
4756
4757 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4758 {
4759         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4760         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4761                 sizeof(ps->channels));
4762         ps->flags = kvm->arch.vpit->pit_state.flags;
4763         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4764         memset(&ps->reserved, 0, sizeof(ps->reserved));
4765         return 0;
4766 }
4767
4768 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4769 {
4770         int start = 0;
4771         int i;
4772         u32 prev_legacy, cur_legacy;
4773         struct kvm_pit *pit = kvm->arch.vpit;
4774
4775         mutex_lock(&pit->pit_state.lock);
4776         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4777         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4778         if (!prev_legacy && cur_legacy)
4779                 start = 1;
4780         memcpy(&pit->pit_state.channels, &ps->channels,
4781                sizeof(pit->pit_state.channels));
4782         pit->pit_state.flags = ps->flags;
4783         for (i = 0; i < 3; i++)
4784                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4785                                    start && i == 0);
4786         mutex_unlock(&pit->pit_state.lock);
4787         return 0;
4788 }
4789
4790 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4791                                  struct kvm_reinject_control *control)
4792 {
4793         struct kvm_pit *pit = kvm->arch.vpit;
4794
4795         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4796          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4797          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4798          */
4799         mutex_lock(&pit->pit_state.lock);
4800         kvm_pit_set_reinject(pit, control->pit_reinject);
4801         mutex_unlock(&pit->pit_state.lock);
4802
4803         return 0;
4804 }
4805
4806 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4807 {
4808         /*
4809          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4810          */
4811         if (kvm_x86_ops.flush_log_dirty)
4812                 kvm_x86_ops.flush_log_dirty(kvm);
4813 }
4814
4815 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4816                         bool line_status)
4817 {
4818         if (!irqchip_in_kernel(kvm))
4819                 return -ENXIO;
4820
4821         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4822                                         irq_event->irq, irq_event->level,
4823                                         line_status);
4824         return 0;
4825 }
4826
4827 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4828                             struct kvm_enable_cap *cap)
4829 {
4830         int r;
4831
4832         if (cap->flags)
4833                 return -EINVAL;
4834
4835         switch (cap->cap) {
4836         case KVM_CAP_DISABLE_QUIRKS:
4837                 kvm->arch.disabled_quirks = cap->args[0];
4838                 r = 0;
4839                 break;
4840         case KVM_CAP_SPLIT_IRQCHIP: {
4841                 mutex_lock(&kvm->lock);
4842                 r = -EINVAL;
4843                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4844                         goto split_irqchip_unlock;
4845                 r = -EEXIST;
4846                 if (irqchip_in_kernel(kvm))
4847                         goto split_irqchip_unlock;
4848                 if (kvm->created_vcpus)
4849                         goto split_irqchip_unlock;
4850                 r = kvm_setup_empty_irq_routing(kvm);
4851                 if (r)
4852                         goto split_irqchip_unlock;
4853                 /* Pairs with irqchip_in_kernel. */
4854                 smp_wmb();
4855                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4856                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4857                 r = 0;
4858 split_irqchip_unlock:
4859                 mutex_unlock(&kvm->lock);
4860                 break;
4861         }
4862         case KVM_CAP_X2APIC_API:
4863                 r = -EINVAL;
4864                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4865                         break;
4866
4867                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4868                         kvm->arch.x2apic_format = true;
4869                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4870                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
4871
4872                 r = 0;
4873                 break;
4874         case KVM_CAP_X86_DISABLE_EXITS:
4875                 r = -EINVAL;
4876                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4877                         break;
4878
4879                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4880                         kvm_can_mwait_in_guest())
4881                         kvm->arch.mwait_in_guest = true;
4882                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
4883                         kvm->arch.hlt_in_guest = true;
4884                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4885                         kvm->arch.pause_in_guest = true;
4886                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4887                         kvm->arch.cstate_in_guest = true;
4888                 r = 0;
4889                 break;
4890         case KVM_CAP_MSR_PLATFORM_INFO:
4891                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4892                 r = 0;
4893                 break;
4894         case KVM_CAP_EXCEPTION_PAYLOAD:
4895                 kvm->arch.exception_payload_enabled = cap->args[0];
4896                 r = 0;
4897                 break;
4898         default:
4899                 r = -EINVAL;
4900                 break;
4901         }
4902         return r;
4903 }
4904
4905 long kvm_arch_vm_ioctl(struct file *filp,
4906                        unsigned int ioctl, unsigned long arg)
4907 {
4908         struct kvm *kvm = filp->private_data;
4909         void __user *argp = (void __user *)arg;
4910         int r = -ENOTTY;
4911         /*
4912          * This union makes it completely explicit to gcc-3.x
4913          * that these two variables' stack usage should be
4914          * combined, not added together.
4915          */
4916         union {
4917                 struct kvm_pit_state ps;
4918                 struct kvm_pit_state2 ps2;
4919                 struct kvm_pit_config pit_config;
4920         } u;
4921
4922         switch (ioctl) {
4923         case KVM_SET_TSS_ADDR:
4924                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
4925                 break;
4926         case KVM_SET_IDENTITY_MAP_ADDR: {
4927                 u64 ident_addr;
4928
4929                 mutex_lock(&kvm->lock);
4930                 r = -EINVAL;
4931                 if (kvm->created_vcpus)
4932                         goto set_identity_unlock;
4933                 r = -EFAULT;
4934                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
4935                         goto set_identity_unlock;
4936                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
4937 set_identity_unlock:
4938                 mutex_unlock(&kvm->lock);
4939                 break;
4940         }
4941         case KVM_SET_NR_MMU_PAGES:
4942                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
4943                 break;
4944         case KVM_GET_NR_MMU_PAGES:
4945                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4946                 break;
4947         case KVM_CREATE_IRQCHIP: {
4948                 mutex_lock(&kvm->lock);
4949
4950                 r = -EEXIST;
4951                 if (irqchip_in_kernel(kvm))
4952                         goto create_irqchip_unlock;
4953
4954                 r = -EINVAL;
4955                 if (kvm->created_vcpus)
4956                         goto create_irqchip_unlock;
4957
4958                 r = kvm_pic_init(kvm);
4959                 if (r)
4960                         goto create_irqchip_unlock;
4961
4962                 r = kvm_ioapic_init(kvm);
4963                 if (r) {
4964                         kvm_pic_destroy(kvm);
4965                         goto create_irqchip_unlock;
4966                 }
4967
4968                 r = kvm_setup_default_irq_routing(kvm);
4969                 if (r) {
4970                         kvm_ioapic_destroy(kvm);
4971                         kvm_pic_destroy(kvm);
4972                         goto create_irqchip_unlock;
4973                 }
4974                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
4975                 smp_wmb();
4976                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
4977         create_irqchip_unlock:
4978                 mutex_unlock(&kvm->lock);
4979                 break;
4980         }
4981         case KVM_CREATE_PIT:
4982                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4983                 goto create_pit;
4984         case KVM_CREATE_PIT2:
4985                 r = -EFAULT;
4986                 if (copy_from_user(&u.pit_config, argp,
4987                                    sizeof(struct kvm_pit_config)))
4988                         goto out;
4989         create_pit:
4990                 mutex_lock(&kvm->lock);
4991                 r = -EEXIST;
4992                 if (kvm->arch.vpit)
4993                         goto create_pit_unlock;
4994                 r = -ENOMEM;
4995                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
4996                 if (kvm->arch.vpit)
4997                         r = 0;
4998         create_pit_unlock:
4999                 mutex_unlock(&kvm->lock);
5000                 break;
5001         case KVM_GET_IRQCHIP: {
5002                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5003                 struct kvm_irqchip *chip;
5004
5005                 chip = memdup_user(argp, sizeof(*chip));
5006                 if (IS_ERR(chip)) {
5007                         r = PTR_ERR(chip);
5008                         goto out;
5009                 }
5010
5011                 r = -ENXIO;
5012                 if (!irqchip_kernel(kvm))
5013                         goto get_irqchip_out;
5014                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5015                 if (r)
5016                         goto get_irqchip_out;
5017                 r = -EFAULT;
5018                 if (copy_to_user(argp, chip, sizeof(*chip)))
5019                         goto get_irqchip_out;
5020                 r = 0;
5021         get_irqchip_out:
5022                 kfree(chip);
5023                 break;
5024         }
5025         case KVM_SET_IRQCHIP: {
5026                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5027                 struct kvm_irqchip *chip;
5028
5029                 chip = memdup_user(argp, sizeof(*chip));
5030                 if (IS_ERR(chip)) {
5031                         r = PTR_ERR(chip);
5032                         goto out;
5033                 }
5034
5035                 r = -ENXIO;
5036                 if (!irqchip_kernel(kvm))
5037                         goto set_irqchip_out;
5038                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5039         set_irqchip_out:
5040                 kfree(chip);
5041                 break;
5042         }
5043         case KVM_GET_PIT: {
5044                 r = -EFAULT;
5045                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5046                         goto out;
5047                 r = -ENXIO;
5048                 if (!kvm->arch.vpit)
5049                         goto out;
5050                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5051                 if (r)
5052                         goto out;
5053                 r = -EFAULT;
5054                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5055                         goto out;
5056                 r = 0;
5057                 break;
5058         }
5059         case KVM_SET_PIT: {
5060                 r = -EFAULT;
5061                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5062                         goto out;
5063                 mutex_lock(&kvm->lock);
5064                 r = -ENXIO;
5065                 if (!kvm->arch.vpit)
5066                         goto set_pit_out;
5067                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5068 set_pit_out:
5069                 mutex_unlock(&kvm->lock);
5070                 break;
5071         }
5072         case KVM_GET_PIT2: {
5073                 r = -ENXIO;
5074                 if (!kvm->arch.vpit)
5075                         goto out;
5076                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5077                 if (r)
5078                         goto out;
5079                 r = -EFAULT;
5080                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5081                         goto out;
5082                 r = 0;
5083                 break;
5084         }
5085         case KVM_SET_PIT2: {
5086                 r = -EFAULT;
5087                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5088                         goto out;
5089                 mutex_lock(&kvm->lock);
5090                 r = -ENXIO;
5091                 if (!kvm->arch.vpit)
5092                         goto set_pit2_out;
5093                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5094 set_pit2_out:
5095                 mutex_unlock(&kvm->lock);
5096                 break;
5097         }
5098         case KVM_REINJECT_CONTROL: {
5099                 struct kvm_reinject_control control;
5100                 r =  -EFAULT;
5101                 if (copy_from_user(&control, argp, sizeof(control)))
5102                         goto out;
5103                 r = -ENXIO;
5104                 if (!kvm->arch.vpit)
5105                         goto out;
5106                 r = kvm_vm_ioctl_reinject(kvm, &control);
5107                 break;
5108         }
5109         case KVM_SET_BOOT_CPU_ID:
5110                 r = 0;
5111                 mutex_lock(&kvm->lock);
5112                 if (kvm->created_vcpus)
5113                         r = -EBUSY;
5114                 else
5115                         kvm->arch.bsp_vcpu_id = arg;
5116                 mutex_unlock(&kvm->lock);
5117                 break;
5118         case KVM_XEN_HVM_CONFIG: {
5119                 struct kvm_xen_hvm_config xhc;
5120                 r = -EFAULT;
5121                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5122                         goto out;
5123                 r = -EINVAL;
5124                 if (xhc.flags)
5125                         goto out;
5126                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5127                 r = 0;
5128                 break;
5129         }
5130         case KVM_SET_CLOCK: {
5131                 struct kvm_clock_data user_ns;
5132                 u64 now_ns;
5133
5134                 r = -EFAULT;
5135                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5136                         goto out;
5137
5138                 r = -EINVAL;
5139                 if (user_ns.flags)
5140                         goto out;
5141
5142                 r = 0;
5143                 /*
5144                  * TODO: userspace has to take care of races with VCPU_RUN, so
5145                  * kvm_gen_update_masterclock() can be cut down to locked
5146                  * pvclock_update_vm_gtod_copy().
5147                  */
5148                 kvm_gen_update_masterclock(kvm);
5149                 now_ns = get_kvmclock_ns(kvm);
5150                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5151                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5152                 break;
5153         }
5154         case KVM_GET_CLOCK: {
5155                 struct kvm_clock_data user_ns;
5156                 u64 now_ns;
5157
5158                 now_ns = get_kvmclock_ns(kvm);
5159                 user_ns.clock = now_ns;
5160                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5161                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5162
5163                 r = -EFAULT;
5164                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5165                         goto out;
5166                 r = 0;
5167                 break;
5168         }
5169         case KVM_MEMORY_ENCRYPT_OP: {
5170                 r = -ENOTTY;
5171                 if (kvm_x86_ops.mem_enc_op)
5172                         r = kvm_x86_ops.mem_enc_op(kvm, argp);
5173                 break;
5174         }
5175         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5176                 struct kvm_enc_region region;
5177
5178                 r = -EFAULT;
5179                 if (copy_from_user(&region, argp, sizeof(region)))
5180                         goto out;
5181
5182                 r = -ENOTTY;
5183                 if (kvm_x86_ops.mem_enc_reg_region)
5184                         r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5185                 break;
5186         }
5187         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5188                 struct kvm_enc_region region;
5189
5190                 r = -EFAULT;
5191                 if (copy_from_user(&region, argp, sizeof(region)))
5192                         goto out;
5193
5194                 r = -ENOTTY;
5195                 if (kvm_x86_ops.mem_enc_unreg_region)
5196                         r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5197                 break;
5198         }
5199         case KVM_HYPERV_EVENTFD: {
5200                 struct kvm_hyperv_eventfd hvevfd;
5201
5202                 r = -EFAULT;
5203                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5204                         goto out;
5205                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5206                 break;
5207         }
5208         case KVM_SET_PMU_EVENT_FILTER:
5209                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5210                 break;
5211         default:
5212                 r = -ENOTTY;
5213         }
5214 out:
5215         return r;
5216 }
5217
5218 static void kvm_init_msr_list(void)
5219 {
5220         struct x86_pmu_capability x86_pmu;
5221         u32 dummy[2];
5222         unsigned i;
5223
5224         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5225                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5226
5227         perf_get_x86_pmu_capability(&x86_pmu);
5228
5229         num_msrs_to_save = 0;
5230         num_emulated_msrs = 0;
5231         num_msr_based_features = 0;
5232
5233         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5234                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5235                         continue;
5236
5237                 /*
5238                  * Even MSRs that are valid in the host may not be exposed
5239                  * to the guests in some cases.
5240                  */
5241                 switch (msrs_to_save_all[i]) {
5242                 case MSR_IA32_BNDCFGS:
5243                         if (!kvm_mpx_supported())
5244                                 continue;
5245                         break;
5246                 case MSR_TSC_AUX:
5247                         if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5248                                 continue;
5249                         break;
5250                 case MSR_IA32_RTIT_CTL:
5251                 case MSR_IA32_RTIT_STATUS:
5252                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5253                                 continue;
5254                         break;
5255                 case MSR_IA32_RTIT_CR3_MATCH:
5256                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5257                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5258                                 continue;
5259                         break;
5260                 case MSR_IA32_RTIT_OUTPUT_BASE:
5261                 case MSR_IA32_RTIT_OUTPUT_MASK:
5262                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5263                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5264                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5265                                 continue;
5266                         break;
5267                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5268                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5269                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5270                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5271                                 continue;
5272                         break;
5273                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5274                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5275                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5276                                 continue;
5277                         break;
5278                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5279                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5280                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5281                                 continue;
5282                 }
5283                 default:
5284                         break;
5285                 }
5286
5287                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5288         }
5289
5290         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5291                 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5292                         continue;
5293
5294                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5295         }
5296
5297         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5298                 struct kvm_msr_entry msr;
5299
5300                 msr.index = msr_based_features_all[i];
5301                 if (kvm_get_msr_feature(&msr))
5302                         continue;
5303
5304                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5305         }
5306 }
5307
5308 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5309                            const void *v)
5310 {
5311         int handled = 0;
5312         int n;
5313
5314         do {
5315                 n = min(len, 8);
5316                 if (!(lapic_in_kernel(vcpu) &&
5317                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5318                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5319                         break;
5320                 handled += n;
5321                 addr += n;
5322                 len -= n;
5323                 v += n;
5324         } while (len);
5325
5326         return handled;
5327 }
5328
5329 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5330 {
5331         int handled = 0;
5332         int n;
5333
5334         do {
5335                 n = min(len, 8);
5336                 if (!(lapic_in_kernel(vcpu) &&
5337                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5338                                          addr, n, v))
5339                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5340                         break;
5341                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5342                 handled += n;
5343                 addr += n;
5344                 len -= n;
5345                 v += n;
5346         } while (len);
5347
5348         return handled;
5349 }
5350
5351 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5352                         struct kvm_segment *var, int seg)
5353 {
5354         kvm_x86_ops.set_segment(vcpu, var, seg);
5355 }
5356
5357 void kvm_get_segment(struct kvm_vcpu *vcpu,
5358                      struct kvm_segment *var, int seg)
5359 {
5360         kvm_x86_ops.get_segment(vcpu, var, seg);
5361 }
5362
5363 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5364                            struct x86_exception *exception)
5365 {
5366         gpa_t t_gpa;
5367
5368         BUG_ON(!mmu_is_nested(vcpu));
5369
5370         /* NPT walks are always user-walks */
5371         access |= PFERR_USER_MASK;
5372         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5373
5374         return t_gpa;
5375 }
5376
5377 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5378                               struct x86_exception *exception)
5379 {
5380         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5381         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5382 }
5383
5384  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5385                                 struct x86_exception *exception)
5386 {
5387         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5388         access |= PFERR_FETCH_MASK;
5389         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5390 }
5391
5392 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5393                                struct x86_exception *exception)
5394 {
5395         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5396         access |= PFERR_WRITE_MASK;
5397         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5398 }
5399
5400 /* uses this to access any guest's mapped memory without checking CPL */
5401 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5402                                 struct x86_exception *exception)
5403 {
5404         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5405 }
5406
5407 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5408                                       struct kvm_vcpu *vcpu, u32 access,
5409                                       struct x86_exception *exception)
5410 {
5411         void *data = val;
5412         int r = X86EMUL_CONTINUE;
5413
5414         while (bytes) {
5415                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5416                                                             exception);
5417                 unsigned offset = addr & (PAGE_SIZE-1);
5418                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5419                 int ret;
5420
5421                 if (gpa == UNMAPPED_GVA)
5422                         return X86EMUL_PROPAGATE_FAULT;
5423                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5424                                                offset, toread);
5425                 if (ret < 0) {
5426                         r = X86EMUL_IO_NEEDED;
5427                         goto out;
5428                 }
5429
5430                 bytes -= toread;
5431                 data += toread;
5432                 addr += toread;
5433         }
5434 out:
5435         return r;
5436 }
5437
5438 /* used for instruction fetching */
5439 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5440                                 gva_t addr, void *val, unsigned int bytes,
5441                                 struct x86_exception *exception)
5442 {
5443         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5444         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5445         unsigned offset;
5446         int ret;
5447
5448         /* Inline kvm_read_guest_virt_helper for speed.  */
5449         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5450                                                     exception);
5451         if (unlikely(gpa == UNMAPPED_GVA))
5452                 return X86EMUL_PROPAGATE_FAULT;
5453
5454         offset = addr & (PAGE_SIZE-1);
5455         if (WARN_ON(offset + bytes > PAGE_SIZE))
5456                 bytes = (unsigned)PAGE_SIZE - offset;
5457         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5458                                        offset, bytes);
5459         if (unlikely(ret < 0))
5460                 return X86EMUL_IO_NEEDED;
5461
5462         return X86EMUL_CONTINUE;
5463 }
5464
5465 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5466                                gva_t addr, void *val, unsigned int bytes,
5467                                struct x86_exception *exception)
5468 {
5469         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5470
5471         /*
5472          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5473          * is returned, but our callers are not ready for that and they blindly
5474          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5475          * uninitialized kernel stack memory into cr2 and error code.
5476          */
5477         memset(exception, 0, sizeof(*exception));
5478         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5479                                           exception);
5480 }
5481 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5482
5483 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5484                              gva_t addr, void *val, unsigned int bytes,
5485                              struct x86_exception *exception, bool system)
5486 {
5487         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5488         u32 access = 0;
5489
5490         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5491                 access |= PFERR_USER_MASK;
5492
5493         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5494 }
5495
5496 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5497                 unsigned long addr, void *val, unsigned int bytes)
5498 {
5499         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5500         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5501
5502         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5503 }
5504
5505 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5506                                       struct kvm_vcpu *vcpu, u32 access,
5507                                       struct x86_exception *exception)
5508 {
5509         void *data = val;
5510         int r = X86EMUL_CONTINUE;
5511
5512         while (bytes) {
5513                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5514                                                              access,
5515                                                              exception);
5516                 unsigned offset = addr & (PAGE_SIZE-1);
5517                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5518                 int ret;
5519
5520                 if (gpa == UNMAPPED_GVA)
5521                         return X86EMUL_PROPAGATE_FAULT;
5522                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5523                 if (ret < 0) {
5524                         r = X86EMUL_IO_NEEDED;
5525                         goto out;
5526                 }
5527
5528                 bytes -= towrite;
5529                 data += towrite;
5530                 addr += towrite;
5531         }
5532 out:
5533         return r;
5534 }
5535
5536 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5537                               unsigned int bytes, struct x86_exception *exception,
5538                               bool system)
5539 {
5540         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5541         u32 access = PFERR_WRITE_MASK;
5542
5543         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5544                 access |= PFERR_USER_MASK;
5545
5546         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5547                                            access, exception);
5548 }
5549
5550 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5551                                 unsigned int bytes, struct x86_exception *exception)
5552 {
5553         /* kvm_write_guest_virt_system can pull in tons of pages. */
5554         vcpu->arch.l1tf_flush_l1d = true;
5555
5556         /*
5557          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5558          * is returned, but our callers are not ready for that and they blindly
5559          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5560          * uninitialized kernel stack memory into cr2 and error code.
5561          */
5562         memset(exception, 0, sizeof(*exception));
5563         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5564                                            PFERR_WRITE_MASK, exception);
5565 }
5566 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5567
5568 int handle_ud(struct kvm_vcpu *vcpu)
5569 {
5570         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5571         int emul_type = EMULTYPE_TRAP_UD;
5572         char sig[5]; /* ud2; .ascii "kvm" */
5573         struct x86_exception e;
5574
5575         if (force_emulation_prefix &&
5576             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5577                                 sig, sizeof(sig), &e) == 0 &&
5578             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5579                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5580                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5581         }
5582
5583         return kvm_emulate_instruction(vcpu, emul_type);
5584 }
5585 EXPORT_SYMBOL_GPL(handle_ud);
5586
5587 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5588                             gpa_t gpa, bool write)
5589 {
5590         /* For APIC access vmexit */
5591         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5592                 return 1;
5593
5594         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5595                 trace_vcpu_match_mmio(gva, gpa, write, true);
5596                 return 1;
5597         }
5598
5599         return 0;
5600 }
5601
5602 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5603                                 gpa_t *gpa, struct x86_exception *exception,
5604                                 bool write)
5605 {
5606         u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5607                 | (write ? PFERR_WRITE_MASK : 0);
5608
5609         /*
5610          * currently PKRU is only applied to ept enabled guest so
5611          * there is no pkey in EPT page table for L1 guest or EPT
5612          * shadow page table for L2 guest.
5613          */
5614         if (vcpu_match_mmio_gva(vcpu, gva)
5615             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5616                                  vcpu->arch.mmio_access, 0, access)) {
5617                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5618                                         (gva & (PAGE_SIZE - 1));
5619                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5620                 return 1;
5621         }
5622
5623         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5624
5625         if (*gpa == UNMAPPED_GVA)
5626                 return -1;
5627
5628         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5629 }
5630
5631 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5632                         const void *val, int bytes)
5633 {
5634         int ret;
5635
5636         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5637         if (ret < 0)
5638                 return 0;
5639         kvm_page_track_write(vcpu, gpa, val, bytes);
5640         return 1;
5641 }
5642
5643 struct read_write_emulator_ops {
5644         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5645                                   int bytes);
5646         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5647                                   void *val, int bytes);
5648         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5649                                int bytes, void *val);
5650         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5651                                     void *val, int bytes);
5652         bool write;
5653 };
5654
5655 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5656 {
5657         if (vcpu->mmio_read_completed) {
5658                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5659                                vcpu->mmio_fragments[0].gpa, val);
5660                 vcpu->mmio_read_completed = 0;
5661                 return 1;
5662         }
5663
5664         return 0;
5665 }
5666
5667 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5668                         void *val, int bytes)
5669 {
5670         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5671 }
5672
5673 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5674                          void *val, int bytes)
5675 {
5676         return emulator_write_phys(vcpu, gpa, val, bytes);
5677 }
5678
5679 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5680 {
5681         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5682         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5683 }
5684
5685 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5686                           void *val, int bytes)
5687 {
5688         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5689         return X86EMUL_IO_NEEDED;
5690 }
5691
5692 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5693                            void *val, int bytes)
5694 {
5695         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5696
5697         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5698         return X86EMUL_CONTINUE;
5699 }
5700
5701 static const struct read_write_emulator_ops read_emultor = {
5702         .read_write_prepare = read_prepare,
5703         .read_write_emulate = read_emulate,
5704         .read_write_mmio = vcpu_mmio_read,
5705         .read_write_exit_mmio = read_exit_mmio,
5706 };
5707
5708 static const struct read_write_emulator_ops write_emultor = {
5709         .read_write_emulate = write_emulate,
5710         .read_write_mmio = write_mmio,
5711         .read_write_exit_mmio = write_exit_mmio,
5712         .write = true,
5713 };
5714
5715 static int emulator_read_write_onepage(unsigned long addr, void *val,
5716                                        unsigned int bytes,
5717                                        struct x86_exception *exception,
5718                                        struct kvm_vcpu *vcpu,
5719                                        const struct read_write_emulator_ops *ops)
5720 {
5721         gpa_t gpa;
5722         int handled, ret;
5723         bool write = ops->write;
5724         struct kvm_mmio_fragment *frag;
5725         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5726
5727         /*
5728          * If the exit was due to a NPF we may already have a GPA.
5729          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5730          * Note, this cannot be used on string operations since string
5731          * operation using rep will only have the initial GPA from the NPF
5732          * occurred.
5733          */
5734         if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5735             (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5736                 gpa = ctxt->gpa_val;
5737                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5738         } else {
5739                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5740                 if (ret < 0)
5741                         return X86EMUL_PROPAGATE_FAULT;
5742         }
5743
5744         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5745                 return X86EMUL_CONTINUE;
5746
5747         /*
5748          * Is this MMIO handled locally?
5749          */
5750         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5751         if (handled == bytes)
5752                 return X86EMUL_CONTINUE;
5753
5754         gpa += handled;
5755         bytes -= handled;
5756         val += handled;
5757
5758         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5759         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5760         frag->gpa = gpa;
5761         frag->data = val;
5762         frag->len = bytes;
5763         return X86EMUL_CONTINUE;
5764 }
5765
5766 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5767                         unsigned long addr,
5768                         void *val, unsigned int bytes,
5769                         struct x86_exception *exception,
5770                         const struct read_write_emulator_ops *ops)
5771 {
5772         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5773         gpa_t gpa;
5774         int rc;
5775
5776         if (ops->read_write_prepare &&
5777                   ops->read_write_prepare(vcpu, val, bytes))
5778                 return X86EMUL_CONTINUE;
5779
5780         vcpu->mmio_nr_fragments = 0;
5781
5782         /* Crossing a page boundary? */
5783         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5784                 int now;
5785
5786                 now = -addr & ~PAGE_MASK;
5787                 rc = emulator_read_write_onepage(addr, val, now, exception,
5788                                                  vcpu, ops);
5789
5790                 if (rc != X86EMUL_CONTINUE)
5791                         return rc;
5792                 addr += now;
5793                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5794                         addr = (u32)addr;
5795                 val += now;
5796                 bytes -= now;
5797         }
5798
5799         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5800                                          vcpu, ops);
5801         if (rc != X86EMUL_CONTINUE)
5802                 return rc;
5803
5804         if (!vcpu->mmio_nr_fragments)
5805                 return rc;
5806
5807         gpa = vcpu->mmio_fragments[0].gpa;
5808
5809         vcpu->mmio_needed = 1;
5810         vcpu->mmio_cur_fragment = 0;
5811
5812         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5813         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5814         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5815         vcpu->run->mmio.phys_addr = gpa;
5816
5817         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5818 }
5819
5820 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5821                                   unsigned long addr,
5822                                   void *val,
5823                                   unsigned int bytes,
5824                                   struct x86_exception *exception)
5825 {
5826         return emulator_read_write(ctxt, addr, val, bytes,
5827                                    exception, &read_emultor);
5828 }
5829
5830 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5831                             unsigned long addr,
5832                             const void *val,
5833                             unsigned int bytes,
5834                             struct x86_exception *exception)
5835 {
5836         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5837                                    exception, &write_emultor);
5838 }
5839
5840 #define CMPXCHG_TYPE(t, ptr, old, new) \
5841         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5842
5843 #ifdef CONFIG_X86_64
5844 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5845 #else
5846 #  define CMPXCHG64(ptr, old, new) \
5847         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5848 #endif
5849
5850 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5851                                      unsigned long addr,
5852                                      const void *old,
5853                                      const void *new,
5854                                      unsigned int bytes,
5855                                      struct x86_exception *exception)
5856 {
5857         struct kvm_host_map map;
5858         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5859         u64 page_line_mask;
5860         gpa_t gpa;
5861         char *kaddr;
5862         bool exchanged;
5863
5864         /* guests cmpxchg8b have to be emulated atomically */
5865         if (bytes > 8 || (bytes & (bytes - 1)))
5866                 goto emul_write;
5867
5868         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
5869
5870         if (gpa == UNMAPPED_GVA ||
5871             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5872                 goto emul_write;
5873
5874         /*
5875          * Emulate the atomic as a straight write to avoid #AC if SLD is
5876          * enabled in the host and the access splits a cache line.
5877          */
5878         if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
5879                 page_line_mask = ~(cache_line_size() - 1);
5880         else
5881                 page_line_mask = PAGE_MASK;
5882
5883         if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
5884                 goto emul_write;
5885
5886         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
5887                 goto emul_write;
5888
5889         kaddr = map.hva + offset_in_page(gpa);
5890
5891         switch (bytes) {
5892         case 1:
5893                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5894                 break;
5895         case 2:
5896                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5897                 break;
5898         case 4:
5899                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5900                 break;
5901         case 8:
5902                 exchanged = CMPXCHG64(kaddr, old, new);
5903                 break;
5904         default:
5905                 BUG();
5906         }
5907
5908         kvm_vcpu_unmap(vcpu, &map, true);
5909
5910         if (!exchanged)
5911                 return X86EMUL_CMPXCHG_FAILED;
5912
5913         kvm_page_track_write(vcpu, gpa, new, bytes);
5914
5915         return X86EMUL_CONTINUE;
5916
5917 emul_write:
5918         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
5919
5920         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
5921 }
5922
5923 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5924 {
5925         int r = 0, i;
5926
5927         for (i = 0; i < vcpu->arch.pio.count; i++) {
5928                 if (vcpu->arch.pio.in)
5929                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5930                                             vcpu->arch.pio.size, pd);
5931                 else
5932                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5933                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
5934                                              pd);
5935                 if (r)
5936                         break;
5937                 pd += vcpu->arch.pio.size;
5938         }
5939         return r;
5940 }
5941
5942 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5943                                unsigned short port, void *val,
5944                                unsigned int count, bool in)
5945 {
5946         vcpu->arch.pio.port = port;
5947         vcpu->arch.pio.in = in;
5948         vcpu->arch.pio.count  = count;
5949         vcpu->arch.pio.size = size;
5950
5951         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
5952                 vcpu->arch.pio.count = 0;
5953                 return 1;
5954         }
5955
5956         vcpu->run->exit_reason = KVM_EXIT_IO;
5957         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
5958         vcpu->run->io.size = size;
5959         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5960         vcpu->run->io.count = count;
5961         vcpu->run->io.port = port;
5962
5963         return 0;
5964 }
5965
5966 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
5967                            unsigned short port, void *val, unsigned int count)
5968 {
5969         int ret;
5970
5971         if (vcpu->arch.pio.count)
5972                 goto data_avail;
5973
5974         memset(vcpu->arch.pio_data, 0, size * count);
5975
5976         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5977         if (ret) {
5978 data_avail:
5979                 memcpy(val, vcpu->arch.pio_data, size * count);
5980                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
5981                 vcpu->arch.pio.count = 0;
5982                 return 1;
5983         }
5984
5985         return 0;
5986 }
5987
5988 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5989                                     int size, unsigned short port, void *val,
5990                                     unsigned int count)
5991 {
5992         return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
5993
5994 }
5995
5996 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
5997                             unsigned short port, const void *val,
5998                             unsigned int count)
5999 {
6000         memcpy(vcpu->arch.pio_data, val, size * count);
6001         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6002         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6003 }
6004
6005 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6006                                      int size, unsigned short port,
6007                                      const void *val, unsigned int count)
6008 {
6009         return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6010 }
6011
6012 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6013 {
6014         return kvm_x86_ops.get_segment_base(vcpu, seg);
6015 }
6016
6017 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6018 {
6019         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6020 }
6021
6022 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6023 {
6024         if (!need_emulate_wbinvd(vcpu))
6025                 return X86EMUL_CONTINUE;
6026
6027         if (kvm_x86_ops.has_wbinvd_exit()) {
6028                 int cpu = get_cpu();
6029
6030                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6031                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6032                                 wbinvd_ipi, NULL, 1);
6033                 put_cpu();
6034                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6035         } else
6036                 wbinvd();
6037         return X86EMUL_CONTINUE;
6038 }
6039
6040 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6041 {
6042         kvm_emulate_wbinvd_noskip(vcpu);
6043         return kvm_skip_emulated_instruction(vcpu);
6044 }
6045 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6046
6047
6048
6049 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6050 {
6051         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6052 }
6053
6054 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6055                            unsigned long *dest)
6056 {
6057         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6058 }
6059
6060 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6061                            unsigned long value)
6062 {
6063
6064         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6065 }
6066
6067 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6068 {
6069         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6070 }
6071
6072 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6073 {
6074         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6075         unsigned long value;
6076
6077         switch (cr) {
6078         case 0:
6079                 value = kvm_read_cr0(vcpu);
6080                 break;
6081         case 2:
6082                 value = vcpu->arch.cr2;
6083                 break;
6084         case 3:
6085                 value = kvm_read_cr3(vcpu);
6086                 break;
6087         case 4:
6088                 value = kvm_read_cr4(vcpu);
6089                 break;
6090         case 8:
6091                 value = kvm_get_cr8(vcpu);
6092                 break;
6093         default:
6094                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6095                 return 0;
6096         }
6097
6098         return value;
6099 }
6100
6101 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6102 {
6103         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6104         int res = 0;
6105
6106         switch (cr) {
6107         case 0:
6108                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6109                 break;
6110         case 2:
6111                 vcpu->arch.cr2 = val;
6112                 break;
6113         case 3:
6114                 res = kvm_set_cr3(vcpu, val);
6115                 break;
6116         case 4:
6117                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6118                 break;
6119         case 8:
6120                 res = kvm_set_cr8(vcpu, val);
6121                 break;
6122         default:
6123                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6124                 res = -1;
6125         }
6126
6127         return res;
6128 }
6129
6130 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6131 {
6132         return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6133 }
6134
6135 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6136 {
6137         kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6138 }
6139
6140 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6141 {
6142         kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6143 }
6144
6145 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6146 {
6147         kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6148 }
6149
6150 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6151 {
6152         kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6153 }
6154
6155 static unsigned long emulator_get_cached_segment_base(
6156         struct x86_emulate_ctxt *ctxt, int seg)
6157 {
6158         return get_segment_base(emul_to_vcpu(ctxt), seg);
6159 }
6160
6161 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6162                                  struct desc_struct *desc, u32 *base3,
6163                                  int seg)
6164 {
6165         struct kvm_segment var;
6166
6167         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6168         *selector = var.selector;
6169
6170         if (var.unusable) {
6171                 memset(desc, 0, sizeof(*desc));
6172                 if (base3)
6173                         *base3 = 0;
6174                 return false;
6175         }
6176
6177         if (var.g)
6178                 var.limit >>= 12;
6179         set_desc_limit(desc, var.limit);
6180         set_desc_base(desc, (unsigned long)var.base);
6181 #ifdef CONFIG_X86_64
6182         if (base3)
6183                 *base3 = var.base >> 32;
6184 #endif
6185         desc->type = var.type;
6186         desc->s = var.s;
6187         desc->dpl = var.dpl;
6188         desc->p = var.present;
6189         desc->avl = var.avl;
6190         desc->l = var.l;
6191         desc->d = var.db;
6192         desc->g = var.g;
6193
6194         return true;
6195 }
6196
6197 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6198                                  struct desc_struct *desc, u32 base3,
6199                                  int seg)
6200 {
6201         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6202         struct kvm_segment var;
6203
6204         var.selector = selector;
6205         var.base = get_desc_base(desc);
6206 #ifdef CONFIG_X86_64
6207         var.base |= ((u64)base3) << 32;
6208 #endif
6209         var.limit = get_desc_limit(desc);
6210         if (desc->g)
6211                 var.limit = (var.limit << 12) | 0xfff;
6212         var.type = desc->type;
6213         var.dpl = desc->dpl;
6214         var.db = desc->d;
6215         var.s = desc->s;
6216         var.l = desc->l;
6217         var.g = desc->g;
6218         var.avl = desc->avl;
6219         var.present = desc->p;
6220         var.unusable = !var.present;
6221         var.padding = 0;
6222
6223         kvm_set_segment(vcpu, &var, seg);
6224         return;
6225 }
6226
6227 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6228                             u32 msr_index, u64 *pdata)
6229 {
6230         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6231 }
6232
6233 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6234                             u32 msr_index, u64 data)
6235 {
6236         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6237 }
6238
6239 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6240 {
6241         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6242
6243         return vcpu->arch.smbase;
6244 }
6245
6246 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6247 {
6248         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6249
6250         vcpu->arch.smbase = smbase;
6251 }
6252
6253 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6254                               u32 pmc)
6255 {
6256         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6257 }
6258
6259 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6260                              u32 pmc, u64 *pdata)
6261 {
6262         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6263 }
6264
6265 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6266 {
6267         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6268 }
6269
6270 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6271                               struct x86_instruction_info *info,
6272                               enum x86_intercept_stage stage)
6273 {
6274         return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6275                                             &ctxt->exception);
6276 }
6277
6278 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6279                               u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6280                               bool exact_only)
6281 {
6282         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6283 }
6284
6285 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6286 {
6287         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6288 }
6289
6290 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6291 {
6292         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6293 }
6294
6295 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6296 {
6297         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6298 }
6299
6300 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6301 {
6302         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6303 }
6304
6305 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6306 {
6307         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6308 }
6309
6310 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6311 {
6312         kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6313 }
6314
6315 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6316 {
6317         return emul_to_vcpu(ctxt)->arch.hflags;
6318 }
6319
6320 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6321 {
6322         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6323 }
6324
6325 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6326                                   const char *smstate)
6327 {
6328         return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6329 }
6330
6331 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6332 {
6333         kvm_smm_changed(emul_to_vcpu(ctxt));
6334 }
6335
6336 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6337 {
6338         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6339 }
6340
6341 static const struct x86_emulate_ops emulate_ops = {
6342         .read_gpr            = emulator_read_gpr,
6343         .write_gpr           = emulator_write_gpr,
6344         .read_std            = emulator_read_std,
6345         .write_std           = emulator_write_std,
6346         .read_phys           = kvm_read_guest_phys_system,
6347         .fetch               = kvm_fetch_guest_virt,
6348         .read_emulated       = emulator_read_emulated,
6349         .write_emulated      = emulator_write_emulated,
6350         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6351         .invlpg              = emulator_invlpg,
6352         .pio_in_emulated     = emulator_pio_in_emulated,
6353         .pio_out_emulated    = emulator_pio_out_emulated,
6354         .get_segment         = emulator_get_segment,
6355         .set_segment         = emulator_set_segment,
6356         .get_cached_segment_base = emulator_get_cached_segment_base,
6357         .get_gdt             = emulator_get_gdt,
6358         .get_idt             = emulator_get_idt,
6359         .set_gdt             = emulator_set_gdt,
6360         .set_idt             = emulator_set_idt,
6361         .get_cr              = emulator_get_cr,
6362         .set_cr              = emulator_set_cr,
6363         .cpl                 = emulator_get_cpl,
6364         .get_dr              = emulator_get_dr,
6365         .set_dr              = emulator_set_dr,
6366         .get_smbase          = emulator_get_smbase,
6367         .set_smbase          = emulator_set_smbase,
6368         .set_msr             = emulator_set_msr,
6369         .get_msr             = emulator_get_msr,
6370         .check_pmc           = emulator_check_pmc,
6371         .read_pmc            = emulator_read_pmc,
6372         .halt                = emulator_halt,
6373         .wbinvd              = emulator_wbinvd,
6374         .fix_hypercall       = emulator_fix_hypercall,
6375         .intercept           = emulator_intercept,
6376         .get_cpuid           = emulator_get_cpuid,
6377         .guest_has_long_mode = emulator_guest_has_long_mode,
6378         .guest_has_movbe     = emulator_guest_has_movbe,
6379         .guest_has_fxsr      = emulator_guest_has_fxsr,
6380         .set_nmi_mask        = emulator_set_nmi_mask,
6381         .get_hflags          = emulator_get_hflags,
6382         .set_hflags          = emulator_set_hflags,
6383         .pre_leave_smm       = emulator_pre_leave_smm,
6384         .post_leave_smm      = emulator_post_leave_smm,
6385         .set_xcr             = emulator_set_xcr,
6386 };
6387
6388 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6389 {
6390         u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6391         /*
6392          * an sti; sti; sequence only disable interrupts for the first
6393          * instruction. So, if the last instruction, be it emulated or
6394          * not, left the system with the INT_STI flag enabled, it
6395          * means that the last instruction is an sti. We should not
6396          * leave the flag on in this case. The same goes for mov ss
6397          */
6398         if (int_shadow & mask)
6399                 mask = 0;
6400         if (unlikely(int_shadow || mask)) {
6401                 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6402                 if (!mask)
6403                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6404         }
6405 }
6406
6407 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6408 {
6409         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6410         if (ctxt->exception.vector == PF_VECTOR)
6411                 return kvm_propagate_fault(vcpu, &ctxt->exception);
6412
6413         if (ctxt->exception.error_code_valid)
6414                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6415                                       ctxt->exception.error_code);
6416         else
6417                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6418         return false;
6419 }
6420
6421 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6422 {
6423         struct x86_emulate_ctxt *ctxt;
6424
6425         ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6426         if (!ctxt) {
6427                 pr_err("kvm: failed to allocate vcpu's emulator\n");
6428                 return NULL;
6429         }
6430
6431         ctxt->vcpu = vcpu;
6432         ctxt->ops = &emulate_ops;
6433         vcpu->arch.emulate_ctxt = ctxt;
6434
6435         return ctxt;
6436 }
6437
6438 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6439 {
6440         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6441         int cs_db, cs_l;
6442
6443         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6444
6445         ctxt->gpa_available = false;
6446         ctxt->eflags = kvm_get_rflags(vcpu);
6447         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6448
6449         ctxt->eip = kvm_rip_read(vcpu);
6450         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6451                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6452                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6453                      cs_db                              ? X86EMUL_MODE_PROT32 :
6454                                                           X86EMUL_MODE_PROT16;
6455         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6456         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6457         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6458
6459         init_decode_cache(ctxt);
6460         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6461 }
6462
6463 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6464 {
6465         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6466         int ret;
6467
6468         init_emulate_ctxt(vcpu);
6469
6470         ctxt->op_bytes = 2;
6471         ctxt->ad_bytes = 2;
6472         ctxt->_eip = ctxt->eip + inc_eip;
6473         ret = emulate_int_real(ctxt, irq);
6474
6475         if (ret != X86EMUL_CONTINUE) {
6476                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6477         } else {
6478                 ctxt->eip = ctxt->_eip;
6479                 kvm_rip_write(vcpu, ctxt->eip);
6480                 kvm_set_rflags(vcpu, ctxt->eflags);
6481         }
6482 }
6483 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6484
6485 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6486 {
6487         ++vcpu->stat.insn_emulation_fail;
6488         trace_kvm_emulate_insn_failed(vcpu);
6489
6490         if (emulation_type & EMULTYPE_VMWARE_GP) {
6491                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6492                 return 1;
6493         }
6494
6495         if (emulation_type & EMULTYPE_SKIP) {
6496                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6497                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6498                 vcpu->run->internal.ndata = 0;
6499                 return 0;
6500         }
6501
6502         kvm_queue_exception(vcpu, UD_VECTOR);
6503
6504         if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6505                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6506                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6507                 vcpu->run->internal.ndata = 0;
6508                 return 0;
6509         }
6510
6511         return 1;
6512 }
6513
6514 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6515                                   bool write_fault_to_shadow_pgtable,
6516                                   int emulation_type)
6517 {
6518         gpa_t gpa = cr2_or_gpa;
6519         kvm_pfn_t pfn;
6520
6521         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6522                 return false;
6523
6524         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6525             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6526                 return false;
6527
6528         if (!vcpu->arch.mmu->direct_map) {
6529                 /*
6530                  * Write permission should be allowed since only
6531                  * write access need to be emulated.
6532                  */
6533                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6534
6535                 /*
6536                  * If the mapping is invalid in guest, let cpu retry
6537                  * it to generate fault.
6538                  */
6539                 if (gpa == UNMAPPED_GVA)
6540                         return true;
6541         }
6542
6543         /*
6544          * Do not retry the unhandleable instruction if it faults on the
6545          * readonly host memory, otherwise it will goto a infinite loop:
6546          * retry instruction -> write #PF -> emulation fail -> retry
6547          * instruction -> ...
6548          */
6549         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6550
6551         /*
6552          * If the instruction failed on the error pfn, it can not be fixed,
6553          * report the error to userspace.
6554          */
6555         if (is_error_noslot_pfn(pfn))
6556                 return false;
6557
6558         kvm_release_pfn_clean(pfn);
6559
6560         /* The instructions are well-emulated on direct mmu. */
6561         if (vcpu->arch.mmu->direct_map) {
6562                 unsigned int indirect_shadow_pages;
6563
6564                 spin_lock(&vcpu->kvm->mmu_lock);
6565                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6566                 spin_unlock(&vcpu->kvm->mmu_lock);
6567
6568                 if (indirect_shadow_pages)
6569                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6570
6571                 return true;
6572         }
6573
6574         /*
6575          * if emulation was due to access to shadowed page table
6576          * and it failed try to unshadow page and re-enter the
6577          * guest to let CPU execute the instruction.
6578          */
6579         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6580
6581         /*
6582          * If the access faults on its page table, it can not
6583          * be fixed by unprotecting shadow page and it should
6584          * be reported to userspace.
6585          */
6586         return !write_fault_to_shadow_pgtable;
6587 }
6588
6589 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6590                               gpa_t cr2_or_gpa,  int emulation_type)
6591 {
6592         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6593         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6594
6595         last_retry_eip = vcpu->arch.last_retry_eip;
6596         last_retry_addr = vcpu->arch.last_retry_addr;
6597
6598         /*
6599          * If the emulation is caused by #PF and it is non-page_table
6600          * writing instruction, it means the VM-EXIT is caused by shadow
6601          * page protected, we can zap the shadow page and retry this
6602          * instruction directly.
6603          *
6604          * Note: if the guest uses a non-page-table modifying instruction
6605          * on the PDE that points to the instruction, then we will unmap
6606          * the instruction and go to an infinite loop. So, we cache the
6607          * last retried eip and the last fault address, if we meet the eip
6608          * and the address again, we can break out of the potential infinite
6609          * loop.
6610          */
6611         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6612
6613         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6614                 return false;
6615
6616         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6617             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6618                 return false;
6619
6620         if (x86_page_table_writing_insn(ctxt))
6621                 return false;
6622
6623         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6624                 return false;
6625
6626         vcpu->arch.last_retry_eip = ctxt->eip;
6627         vcpu->arch.last_retry_addr = cr2_or_gpa;
6628
6629         if (!vcpu->arch.mmu->direct_map)
6630                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6631
6632         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6633
6634         return true;
6635 }
6636
6637 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6638 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6639
6640 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6641 {
6642         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6643                 /* This is a good place to trace that we are exiting SMM.  */
6644                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6645
6646                 /* Process a latched INIT or SMI, if any.  */
6647                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6648         }
6649
6650         kvm_mmu_reset_context(vcpu);
6651 }
6652
6653 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6654                                 unsigned long *db)
6655 {
6656         u32 dr6 = 0;
6657         int i;
6658         u32 enable, rwlen;
6659
6660         enable = dr7;
6661         rwlen = dr7 >> 16;
6662         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6663                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6664                         dr6 |= (1 << i);
6665         return dr6;
6666 }
6667
6668 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6669 {
6670         struct kvm_run *kvm_run = vcpu->run;
6671
6672         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6673                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6674                 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6675                 kvm_run->debug.arch.exception = DB_VECTOR;
6676                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6677                 return 0;
6678         }
6679         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6680         return 1;
6681 }
6682
6683 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6684 {
6685         unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6686         int r;
6687
6688         r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6689         if (unlikely(!r))
6690                 return 0;
6691
6692         /*
6693          * rflags is the old, "raw" value of the flags.  The new value has
6694          * not been saved yet.
6695          *
6696          * This is correct even for TF set by the guest, because "the
6697          * processor will not generate this exception after the instruction
6698          * that sets the TF flag".
6699          */
6700         if (unlikely(rflags & X86_EFLAGS_TF))
6701                 r = kvm_vcpu_do_singlestep(vcpu);
6702         return r;
6703 }
6704 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6705
6706 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6707 {
6708         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6709             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6710                 struct kvm_run *kvm_run = vcpu->run;
6711                 unsigned long eip = kvm_get_linear_rip(vcpu);
6712                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6713                                            vcpu->arch.guest_debug_dr7,
6714                                            vcpu->arch.eff_db);
6715
6716                 if (dr6 != 0) {
6717                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6718                         kvm_run->debug.arch.pc = eip;
6719                         kvm_run->debug.arch.exception = DB_VECTOR;
6720                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6721                         *r = 0;
6722                         return true;
6723                 }
6724         }
6725
6726         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6727             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6728                 unsigned long eip = kvm_get_linear_rip(vcpu);
6729                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6730                                            vcpu->arch.dr7,
6731                                            vcpu->arch.db);
6732
6733                 if (dr6 != 0) {
6734                         vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6735                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
6736                         kvm_queue_exception(vcpu, DB_VECTOR);
6737                         *r = 1;
6738                         return true;
6739                 }
6740         }
6741
6742         return false;
6743 }
6744
6745 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6746 {
6747         switch (ctxt->opcode_len) {
6748         case 1:
6749                 switch (ctxt->b) {
6750                 case 0xe4:      /* IN */
6751                 case 0xe5:
6752                 case 0xec:
6753                 case 0xed:
6754                 case 0xe6:      /* OUT */
6755                 case 0xe7:
6756                 case 0xee:
6757                 case 0xef:
6758                 case 0x6c:      /* INS */
6759                 case 0x6d:
6760                 case 0x6e:      /* OUTS */
6761                 case 0x6f:
6762                         return true;
6763                 }
6764                 break;
6765         case 2:
6766                 switch (ctxt->b) {
6767                 case 0x33:      /* RDPMC */
6768                         return true;
6769                 }
6770                 break;
6771         }
6772
6773         return false;
6774 }
6775
6776 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6777                             int emulation_type, void *insn, int insn_len)
6778 {
6779         int r;
6780         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6781         bool writeback = true;
6782         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6783
6784         vcpu->arch.l1tf_flush_l1d = true;
6785
6786         /*
6787          * Clear write_fault_to_shadow_pgtable here to ensure it is
6788          * never reused.
6789          */
6790         vcpu->arch.write_fault_to_shadow_pgtable = false;
6791         kvm_clear_exception_queue(vcpu);
6792
6793         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6794                 init_emulate_ctxt(vcpu);
6795
6796                 /*
6797                  * We will reenter on the same instruction since
6798                  * we do not set complete_userspace_io.  This does not
6799                  * handle watchpoints yet, those would be handled in
6800                  * the emulate_ops.
6801                  */
6802                 if (!(emulation_type & EMULTYPE_SKIP) &&
6803                     kvm_vcpu_check_breakpoint(vcpu, &r))
6804                         return r;
6805
6806                 ctxt->interruptibility = 0;
6807                 ctxt->have_exception = false;
6808                 ctxt->exception.vector = -1;
6809                 ctxt->perm_ok = false;
6810
6811                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6812
6813                 r = x86_decode_insn(ctxt, insn, insn_len);
6814
6815                 trace_kvm_emulate_insn_start(vcpu);
6816                 ++vcpu->stat.insn_emulation;
6817                 if (r != EMULATION_OK)  {
6818                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6819                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6820                                 kvm_queue_exception(vcpu, UD_VECTOR);
6821                                 return 1;
6822                         }
6823                         if (reexecute_instruction(vcpu, cr2_or_gpa,
6824                                                   write_fault_to_spt,
6825                                                   emulation_type))
6826                                 return 1;
6827                         if (ctxt->have_exception) {
6828                                 /*
6829                                  * #UD should result in just EMULATION_FAILED, and trap-like
6830                                  * exception should not be encountered during decode.
6831                                  */
6832                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6833                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6834                                 inject_emulated_exception(vcpu);
6835                                 return 1;
6836                         }
6837                         return handle_emulation_failure(vcpu, emulation_type);
6838                 }
6839         }
6840
6841         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6842             !is_vmware_backdoor_opcode(ctxt)) {
6843                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6844                 return 1;
6845         }
6846
6847         /*
6848          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6849          * for kvm_skip_emulated_instruction().  The caller is responsible for
6850          * updating interruptibility state and injecting single-step #DBs.
6851          */
6852         if (emulation_type & EMULTYPE_SKIP) {
6853                 kvm_rip_write(vcpu, ctxt->_eip);
6854                 if (ctxt->eflags & X86_EFLAGS_RF)
6855                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6856                 return 1;
6857         }
6858
6859         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6860                 return 1;
6861
6862         /* this is needed for vmware backdoor interface to work since it
6863            changes registers values  during IO operation */
6864         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6865                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6866                 emulator_invalidate_register_cache(ctxt);
6867         }
6868
6869 restart:
6870         if (emulation_type & EMULTYPE_PF) {
6871                 /* Save the faulting GPA (cr2) in the address field */
6872                 ctxt->exception.address = cr2_or_gpa;
6873
6874                 /* With shadow page tables, cr2 contains a GVA or nGPA. */
6875                 if (vcpu->arch.mmu->direct_map) {
6876                         ctxt->gpa_available = true;
6877                         ctxt->gpa_val = cr2_or_gpa;
6878                 }
6879         } else {
6880                 /* Sanitize the address out of an abundance of paranoia. */
6881                 ctxt->exception.address = 0;
6882         }
6883
6884         r = x86_emulate_insn(ctxt);
6885
6886         if (r == EMULATION_INTERCEPTED)
6887                 return 1;
6888
6889         if (r == EMULATION_FAILED) {
6890                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
6891                                         emulation_type))
6892                         return 1;
6893
6894                 return handle_emulation_failure(vcpu, emulation_type);
6895         }
6896
6897         if (ctxt->have_exception) {
6898                 r = 1;
6899                 if (inject_emulated_exception(vcpu))
6900                         return r;
6901         } else if (vcpu->arch.pio.count) {
6902                 if (!vcpu->arch.pio.in) {
6903                         /* FIXME: return into emulator if single-stepping.  */
6904                         vcpu->arch.pio.count = 0;
6905                 } else {
6906                         writeback = false;
6907                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
6908                 }
6909                 r = 0;
6910         } else if (vcpu->mmio_needed) {
6911                 ++vcpu->stat.mmio_exits;
6912
6913                 if (!vcpu->mmio_is_write)
6914                         writeback = false;
6915                 r = 0;
6916                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6917         } else if (r == EMULATION_RESTART)
6918                 goto restart;
6919         else
6920                 r = 1;
6921
6922         if (writeback) {
6923                 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6924                 toggle_interruptibility(vcpu, ctxt->interruptibility);
6925                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6926                 if (!ctxt->have_exception ||
6927                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6928                         kvm_rip_write(vcpu, ctxt->eip);
6929                         if (r && ctxt->tf)
6930                                 r = kvm_vcpu_do_singlestep(vcpu);
6931                         if (kvm_x86_ops.update_emulated_instruction)
6932                                 kvm_x86_ops.update_emulated_instruction(vcpu);
6933                         __kvm_set_rflags(vcpu, ctxt->eflags);
6934                 }
6935
6936                 /*
6937                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6938                  * do nothing, and it will be requested again as soon as
6939                  * the shadow expires.  But we still need to check here,
6940                  * because POPF has no interrupt shadow.
6941                  */
6942                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6943                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6944         } else
6945                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
6946
6947         return r;
6948 }
6949
6950 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6951 {
6952         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6953 }
6954 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6955
6956 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6957                                         void *insn, int insn_len)
6958 {
6959         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6960 }
6961 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
6962
6963 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6964 {
6965         vcpu->arch.pio.count = 0;
6966         return 1;
6967 }
6968
6969 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6970 {
6971         vcpu->arch.pio.count = 0;
6972
6973         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6974                 return 1;
6975
6976         return kvm_skip_emulated_instruction(vcpu);
6977 }
6978
6979 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6980                             unsigned short port)
6981 {
6982         unsigned long val = kvm_rax_read(vcpu);
6983         int ret = emulator_pio_out(vcpu, size, port, &val, 1);
6984
6985         if (ret)
6986                 return ret;
6987
6988         /*
6989          * Workaround userspace that relies on old KVM behavior of %rip being
6990          * incremented prior to exiting to userspace to handle "OUT 0x7e".
6991          */
6992         if (port == 0x7e &&
6993             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6994                 vcpu->arch.complete_userspace_io =
6995                         complete_fast_pio_out_port_0x7e;
6996                 kvm_skip_emulated_instruction(vcpu);
6997         } else {
6998                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6999                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7000         }
7001         return 0;
7002 }
7003
7004 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7005 {
7006         unsigned long val;
7007
7008         /* We should only ever be called with arch.pio.count equal to 1 */
7009         BUG_ON(vcpu->arch.pio.count != 1);
7010
7011         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7012                 vcpu->arch.pio.count = 0;
7013                 return 1;
7014         }
7015
7016         /* For size less than 4 we merge, else we zero extend */
7017         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7018
7019         /*
7020          * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7021          * the copy and tracing
7022          */
7023         emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7024         kvm_rax_write(vcpu, val);
7025
7026         return kvm_skip_emulated_instruction(vcpu);
7027 }
7028
7029 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7030                            unsigned short port)
7031 {
7032         unsigned long val;
7033         int ret;
7034
7035         /* For size less than 4 we merge, else we zero extend */
7036         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7037
7038         ret = emulator_pio_in(vcpu, size, port, &val, 1);
7039         if (ret) {
7040                 kvm_rax_write(vcpu, val);
7041                 return ret;
7042         }
7043
7044         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7045         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7046
7047         return 0;
7048 }
7049
7050 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7051 {
7052         int ret;
7053
7054         if (in)
7055                 ret = kvm_fast_pio_in(vcpu, size, port);
7056         else
7057                 ret = kvm_fast_pio_out(vcpu, size, port);
7058         return ret && kvm_skip_emulated_instruction(vcpu);
7059 }
7060 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7061
7062 static int kvmclock_cpu_down_prep(unsigned int cpu)
7063 {
7064         __this_cpu_write(cpu_tsc_khz, 0);
7065         return 0;
7066 }
7067
7068 static void tsc_khz_changed(void *data)
7069 {
7070         struct cpufreq_freqs *freq = data;
7071         unsigned long khz = 0;
7072
7073         if (data)
7074                 khz = freq->new;
7075         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7076                 khz = cpufreq_quick_get(raw_smp_processor_id());
7077         if (!khz)
7078                 khz = tsc_khz;
7079         __this_cpu_write(cpu_tsc_khz, khz);
7080 }
7081
7082 #ifdef CONFIG_X86_64
7083 static void kvm_hyperv_tsc_notifier(void)
7084 {
7085         struct kvm *kvm;
7086         struct kvm_vcpu *vcpu;
7087         int cpu;
7088
7089         mutex_lock(&kvm_lock);
7090         list_for_each_entry(kvm, &vm_list, vm_list)
7091                 kvm_make_mclock_inprogress_request(kvm);
7092
7093         hyperv_stop_tsc_emulation();
7094
7095         /* TSC frequency always matches when on Hyper-V */
7096         for_each_present_cpu(cpu)
7097                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7098         kvm_max_guest_tsc_khz = tsc_khz;
7099
7100         list_for_each_entry(kvm, &vm_list, vm_list) {
7101                 struct kvm_arch *ka = &kvm->arch;
7102
7103                 spin_lock(&ka->pvclock_gtod_sync_lock);
7104
7105                 pvclock_update_vm_gtod_copy(kvm);
7106
7107                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7108                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7109
7110                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7111                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7112
7113                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7114         }
7115         mutex_unlock(&kvm_lock);
7116 }
7117 #endif
7118
7119 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7120 {
7121         struct kvm *kvm;
7122         struct kvm_vcpu *vcpu;
7123         int i, send_ipi = 0;
7124
7125         /*
7126          * We allow guests to temporarily run on slowing clocks,
7127          * provided we notify them after, or to run on accelerating
7128          * clocks, provided we notify them before.  Thus time never
7129          * goes backwards.
7130          *
7131          * However, we have a problem.  We can't atomically update
7132          * the frequency of a given CPU from this function; it is
7133          * merely a notifier, which can be called from any CPU.
7134          * Changing the TSC frequency at arbitrary points in time
7135          * requires a recomputation of local variables related to
7136          * the TSC for each VCPU.  We must flag these local variables
7137          * to be updated and be sure the update takes place with the
7138          * new frequency before any guests proceed.
7139          *
7140          * Unfortunately, the combination of hotplug CPU and frequency
7141          * change creates an intractable locking scenario; the order
7142          * of when these callouts happen is undefined with respect to
7143          * CPU hotplug, and they can race with each other.  As such,
7144          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7145          * undefined; you can actually have a CPU frequency change take
7146          * place in between the computation of X and the setting of the
7147          * variable.  To protect against this problem, all updates of
7148          * the per_cpu tsc_khz variable are done in an interrupt
7149          * protected IPI, and all callers wishing to update the value
7150          * must wait for a synchronous IPI to complete (which is trivial
7151          * if the caller is on the CPU already).  This establishes the
7152          * necessary total order on variable updates.
7153          *
7154          * Note that because a guest time update may take place
7155          * anytime after the setting of the VCPU's request bit, the
7156          * correct TSC value must be set before the request.  However,
7157          * to ensure the update actually makes it to any guest which
7158          * starts running in hardware virtualization between the set
7159          * and the acquisition of the spinlock, we must also ping the
7160          * CPU after setting the request bit.
7161          *
7162          */
7163
7164         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7165
7166         mutex_lock(&kvm_lock);
7167         list_for_each_entry(kvm, &vm_list, vm_list) {
7168                 kvm_for_each_vcpu(i, vcpu, kvm) {
7169                         if (vcpu->cpu != cpu)
7170                                 continue;
7171                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7172                         if (vcpu->cpu != raw_smp_processor_id())
7173                                 send_ipi = 1;
7174                 }
7175         }
7176         mutex_unlock(&kvm_lock);
7177
7178         if (freq->old < freq->new && send_ipi) {
7179                 /*
7180                  * We upscale the frequency.  Must make the guest
7181                  * doesn't see old kvmclock values while running with
7182                  * the new frequency, otherwise we risk the guest sees
7183                  * time go backwards.
7184                  *
7185                  * In case we update the frequency for another cpu
7186                  * (which might be in guest context) send an interrupt
7187                  * to kick the cpu out of guest context.  Next time
7188                  * guest context is entered kvmclock will be updated,
7189                  * so the guest will not see stale values.
7190                  */
7191                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7192         }
7193 }
7194
7195 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7196                                      void *data)
7197 {
7198         struct cpufreq_freqs *freq = data;
7199         int cpu;
7200
7201         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7202                 return 0;
7203         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7204                 return 0;
7205
7206         for_each_cpu(cpu, freq->policy->cpus)
7207                 __kvmclock_cpufreq_notifier(freq, cpu);
7208
7209         return 0;
7210 }
7211
7212 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7213         .notifier_call  = kvmclock_cpufreq_notifier
7214 };
7215
7216 static int kvmclock_cpu_online(unsigned int cpu)
7217 {
7218         tsc_khz_changed(NULL);
7219         return 0;
7220 }
7221
7222 static void kvm_timer_init(void)
7223 {
7224         max_tsc_khz = tsc_khz;
7225
7226         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7227 #ifdef CONFIG_CPU_FREQ
7228                 struct cpufreq_policy *policy;
7229                 int cpu;
7230
7231                 cpu = get_cpu();
7232                 policy = cpufreq_cpu_get(cpu);
7233                 if (policy) {
7234                         if (policy->cpuinfo.max_freq)
7235                                 max_tsc_khz = policy->cpuinfo.max_freq;
7236                         cpufreq_cpu_put(policy);
7237                 }
7238                 put_cpu();
7239 #endif
7240                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7241                                           CPUFREQ_TRANSITION_NOTIFIER);
7242         }
7243
7244         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7245                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7246 }
7247
7248 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7249 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7250
7251 int kvm_is_in_guest(void)
7252 {
7253         return __this_cpu_read(current_vcpu) != NULL;
7254 }
7255
7256 static int kvm_is_user_mode(void)
7257 {
7258         int user_mode = 3;
7259
7260         if (__this_cpu_read(current_vcpu))
7261                 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7262
7263         return user_mode != 0;
7264 }
7265
7266 static unsigned long kvm_get_guest_ip(void)
7267 {
7268         unsigned long ip = 0;
7269
7270         if (__this_cpu_read(current_vcpu))
7271                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7272
7273         return ip;
7274 }
7275
7276 static void kvm_handle_intel_pt_intr(void)
7277 {
7278         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7279
7280         kvm_make_request(KVM_REQ_PMI, vcpu);
7281         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7282                         (unsigned long *)&vcpu->arch.pmu.global_status);
7283 }
7284
7285 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7286         .is_in_guest            = kvm_is_in_guest,
7287         .is_user_mode           = kvm_is_user_mode,
7288         .get_guest_ip           = kvm_get_guest_ip,
7289         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7290 };
7291
7292 #ifdef CONFIG_X86_64
7293 static void pvclock_gtod_update_fn(struct work_struct *work)
7294 {
7295         struct kvm *kvm;
7296
7297         struct kvm_vcpu *vcpu;
7298         int i;
7299
7300         mutex_lock(&kvm_lock);
7301         list_for_each_entry(kvm, &vm_list, vm_list)
7302                 kvm_for_each_vcpu(i, vcpu, kvm)
7303                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7304         atomic_set(&kvm_guest_has_master_clock, 0);
7305         mutex_unlock(&kvm_lock);
7306 }
7307
7308 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7309
7310 /*
7311  * Notification about pvclock gtod data update.
7312  */
7313 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7314                                void *priv)
7315 {
7316         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7317         struct timekeeper *tk = priv;
7318
7319         update_pvclock_gtod(tk);
7320
7321         /* disable master clock if host does not trust, or does not
7322          * use, TSC based clocksource.
7323          */
7324         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7325             atomic_read(&kvm_guest_has_master_clock) != 0)
7326                 queue_work(system_long_wq, &pvclock_gtod_work);
7327
7328         return 0;
7329 }
7330
7331 static struct notifier_block pvclock_gtod_notifier = {
7332         .notifier_call = pvclock_gtod_notify,
7333 };
7334 #endif
7335
7336 int kvm_arch_init(void *opaque)
7337 {
7338         struct kvm_x86_init_ops *ops = opaque;
7339         int r;
7340
7341         if (kvm_x86_ops.hardware_enable) {
7342                 printk(KERN_ERR "kvm: already loaded the other module\n");
7343                 r = -EEXIST;
7344                 goto out;
7345         }
7346
7347         if (!ops->cpu_has_kvm_support()) {
7348                 pr_err_ratelimited("kvm: no hardware support\n");
7349                 r = -EOPNOTSUPP;
7350                 goto out;
7351         }
7352         if (ops->disabled_by_bios()) {
7353                 pr_err_ratelimited("kvm: disabled by bios\n");
7354                 r = -EOPNOTSUPP;
7355                 goto out;
7356         }
7357
7358         /*
7359          * KVM explicitly assumes that the guest has an FPU and
7360          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7361          * vCPU's FPU state as a fxregs_state struct.
7362          */
7363         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7364                 printk(KERN_ERR "kvm: inadequate fpu\n");
7365                 r = -EOPNOTSUPP;
7366                 goto out;
7367         }
7368
7369         r = -ENOMEM;
7370         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7371                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7372                                           NULL);
7373         if (!x86_fpu_cache) {
7374                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7375                 goto out;
7376         }
7377
7378         x86_emulator_cache = kvm_alloc_emulator_cache();
7379         if (!x86_emulator_cache) {
7380                 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7381                 goto out_free_x86_fpu_cache;
7382         }
7383
7384         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7385         if (!shared_msrs) {
7386                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7387                 goto out_free_x86_emulator_cache;
7388         }
7389
7390         r = kvm_mmu_module_init();
7391         if (r)
7392                 goto out_free_percpu;
7393
7394         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7395                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7396                         PT_PRESENT_MASK, 0, sme_me_mask);
7397         kvm_timer_init();
7398
7399         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7400
7401         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7402                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7403                 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7404         }
7405
7406         kvm_lapic_init();
7407         if (pi_inject_timer == -1)
7408                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7409 #ifdef CONFIG_X86_64
7410         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7411
7412         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7413                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7414 #endif
7415
7416         return 0;
7417
7418 out_free_percpu:
7419         free_percpu(shared_msrs);
7420 out_free_x86_emulator_cache:
7421         kmem_cache_destroy(x86_emulator_cache);
7422 out_free_x86_fpu_cache:
7423         kmem_cache_destroy(x86_fpu_cache);
7424 out:
7425         return r;
7426 }
7427
7428 void kvm_arch_exit(void)
7429 {
7430 #ifdef CONFIG_X86_64
7431         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7432                 clear_hv_tscchange_cb();
7433 #endif
7434         kvm_lapic_exit();
7435         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7436
7437         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7438                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7439                                             CPUFREQ_TRANSITION_NOTIFIER);
7440         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7441 #ifdef CONFIG_X86_64
7442         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7443 #endif
7444         kvm_x86_ops.hardware_enable = NULL;
7445         kvm_mmu_module_exit();
7446         free_percpu(shared_msrs);
7447         kmem_cache_destroy(x86_fpu_cache);
7448 }
7449
7450 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7451 {
7452         ++vcpu->stat.halt_exits;
7453         if (lapic_in_kernel(vcpu)) {
7454                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7455                 return 1;
7456         } else {
7457                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7458                 return 0;
7459         }
7460 }
7461 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7462
7463 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7464 {
7465         int ret = kvm_skip_emulated_instruction(vcpu);
7466         /*
7467          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7468          * KVM_EXIT_DEBUG here.
7469          */
7470         return kvm_vcpu_halt(vcpu) && ret;
7471 }
7472 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7473
7474 #ifdef CONFIG_X86_64
7475 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7476                                 unsigned long clock_type)
7477 {
7478         struct kvm_clock_pairing clock_pairing;
7479         struct timespec64 ts;
7480         u64 cycle;
7481         int ret;
7482
7483         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7484                 return -KVM_EOPNOTSUPP;
7485
7486         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7487                 return -KVM_EOPNOTSUPP;
7488
7489         clock_pairing.sec = ts.tv_sec;
7490         clock_pairing.nsec = ts.tv_nsec;
7491         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7492         clock_pairing.flags = 0;
7493         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7494
7495         ret = 0;
7496         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7497                             sizeof(struct kvm_clock_pairing)))
7498                 ret = -KVM_EFAULT;
7499
7500         return ret;
7501 }
7502 #endif
7503
7504 /*
7505  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7506  *
7507  * @apicid - apicid of vcpu to be kicked.
7508  */
7509 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7510 {
7511         struct kvm_lapic_irq lapic_irq;
7512
7513         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7514         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7515         lapic_irq.level = 0;
7516         lapic_irq.dest_id = apicid;
7517         lapic_irq.msi_redir_hint = false;
7518
7519         lapic_irq.delivery_mode = APIC_DM_REMRD;
7520         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7521 }
7522
7523 bool kvm_apicv_activated(struct kvm *kvm)
7524 {
7525         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7526 }
7527 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7528
7529 void kvm_apicv_init(struct kvm *kvm, bool enable)
7530 {
7531         if (enable)
7532                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7533                           &kvm->arch.apicv_inhibit_reasons);
7534         else
7535                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7536                         &kvm->arch.apicv_inhibit_reasons);
7537 }
7538 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7539
7540 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7541 {
7542         struct kvm_vcpu *target = NULL;
7543         struct kvm_apic_map *map;
7544
7545         rcu_read_lock();
7546         map = rcu_dereference(kvm->arch.apic_map);
7547
7548         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7549                 target = map->phys_map[dest_id]->vcpu;
7550
7551         rcu_read_unlock();
7552
7553         if (target && READ_ONCE(target->ready))
7554                 kvm_vcpu_yield_to(target);
7555 }
7556
7557 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7558 {
7559         unsigned long nr, a0, a1, a2, a3, ret;
7560         int op_64_bit;
7561
7562         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7563                 return kvm_hv_hypercall(vcpu);
7564
7565         nr = kvm_rax_read(vcpu);
7566         a0 = kvm_rbx_read(vcpu);
7567         a1 = kvm_rcx_read(vcpu);
7568         a2 = kvm_rdx_read(vcpu);
7569         a3 = kvm_rsi_read(vcpu);
7570
7571         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7572
7573         op_64_bit = is_64_bit_mode(vcpu);
7574         if (!op_64_bit) {
7575                 nr &= 0xFFFFFFFF;
7576                 a0 &= 0xFFFFFFFF;
7577                 a1 &= 0xFFFFFFFF;
7578                 a2 &= 0xFFFFFFFF;
7579                 a3 &= 0xFFFFFFFF;
7580         }
7581
7582         if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7583                 ret = -KVM_EPERM;
7584                 goto out;
7585         }
7586
7587         switch (nr) {
7588         case KVM_HC_VAPIC_POLL_IRQ:
7589                 ret = 0;
7590                 break;
7591         case KVM_HC_KICK_CPU:
7592                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7593                 kvm_sched_yield(vcpu->kvm, a1);
7594                 ret = 0;
7595                 break;
7596 #ifdef CONFIG_X86_64
7597         case KVM_HC_CLOCK_PAIRING:
7598                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7599                 break;
7600 #endif
7601         case KVM_HC_SEND_IPI:
7602                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7603                 break;
7604         case KVM_HC_SCHED_YIELD:
7605                 kvm_sched_yield(vcpu->kvm, a0);
7606                 ret = 0;
7607                 break;
7608         default:
7609                 ret = -KVM_ENOSYS;
7610                 break;
7611         }
7612 out:
7613         if (!op_64_bit)
7614                 ret = (u32)ret;
7615         kvm_rax_write(vcpu, ret);
7616
7617         ++vcpu->stat.hypercalls;
7618         return kvm_skip_emulated_instruction(vcpu);
7619 }
7620 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7621
7622 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7623 {
7624         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7625         char instruction[3];
7626         unsigned long rip = kvm_rip_read(vcpu);
7627
7628         kvm_x86_ops.patch_hypercall(vcpu, instruction);
7629
7630         return emulator_write_emulated(ctxt, rip, instruction, 3,
7631                 &ctxt->exception);
7632 }
7633
7634 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7635 {
7636         return vcpu->run->request_interrupt_window &&
7637                 likely(!pic_in_kernel(vcpu->kvm));
7638 }
7639
7640 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7641 {
7642         struct kvm_run *kvm_run = vcpu->run;
7643
7644         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7645         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7646         kvm_run->cr8 = kvm_get_cr8(vcpu);
7647         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7648         kvm_run->ready_for_interrupt_injection =
7649                 pic_in_kernel(vcpu->kvm) ||
7650                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7651 }
7652
7653 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7654 {
7655         int max_irr, tpr;
7656
7657         if (!kvm_x86_ops.update_cr8_intercept)
7658                 return;
7659
7660         if (!lapic_in_kernel(vcpu))
7661                 return;
7662
7663         if (vcpu->arch.apicv_active)
7664                 return;
7665
7666         if (!vcpu->arch.apic->vapic_addr)
7667                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7668         else
7669                 max_irr = -1;
7670
7671         if (max_irr != -1)
7672                 max_irr >>= 4;
7673
7674         tpr = kvm_lapic_get_cr8(vcpu);
7675
7676         kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7677 }
7678
7679 static int inject_pending_event(struct kvm_vcpu *vcpu)
7680 {
7681         int r;
7682
7683         /* try to reinject previous events if any */
7684
7685         if (vcpu->arch.exception.injected)
7686                 kvm_x86_ops.queue_exception(vcpu);
7687         /*
7688          * Do not inject an NMI or interrupt if there is a pending
7689          * exception.  Exceptions and interrupts are recognized at
7690          * instruction boundaries, i.e. the start of an instruction.
7691          * Trap-like exceptions, e.g. #DB, have higher priority than
7692          * NMIs and interrupts, i.e. traps are recognized before an
7693          * NMI/interrupt that's pending on the same instruction.
7694          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7695          * priority, but are only generated (pended) during instruction
7696          * execution, i.e. a pending fault-like exception means the
7697          * fault occurred on the *previous* instruction and must be
7698          * serviced prior to recognizing any new events in order to
7699          * fully complete the previous instruction.
7700          */
7701         else if (!vcpu->arch.exception.pending) {
7702                 if (vcpu->arch.nmi_injected)
7703                         kvm_x86_ops.set_nmi(vcpu);
7704                 else if (vcpu->arch.interrupt.injected)
7705                         kvm_x86_ops.set_irq(vcpu);
7706         }
7707
7708         /*
7709          * Call check_nested_events() even if we reinjected a previous event
7710          * in order for caller to determine if it should require immediate-exit
7711          * from L2 to L1 due to pending L1 events which require exit
7712          * from L2 to L1.
7713          */
7714         if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) {
7715                 r = kvm_x86_ops.check_nested_events(vcpu);
7716                 if (r != 0)
7717                         return r;
7718         }
7719
7720         /* try to inject new event if pending */
7721         if (vcpu->arch.exception.pending) {
7722                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7723                                         vcpu->arch.exception.has_error_code,
7724                                         vcpu->arch.exception.error_code);
7725
7726                 WARN_ON_ONCE(vcpu->arch.exception.injected);
7727                 vcpu->arch.exception.pending = false;
7728                 vcpu->arch.exception.injected = true;
7729
7730                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7731                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7732                                              X86_EFLAGS_RF);
7733
7734                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7735                         /*
7736                          * This code assumes that nSVM doesn't use
7737                          * check_nested_events(). If it does, the
7738                          * DR6/DR7 changes should happen before L1
7739                          * gets a #VMEXIT for an intercepted #DB in
7740                          * L2.  (Under VMX, on the other hand, the
7741                          * DR6/DR7 changes should not happen in the
7742                          * event of a VM-exit to L1 for an intercepted
7743                          * #DB in L2.)
7744                          */
7745                         kvm_deliver_exception_payload(vcpu);
7746                         if (vcpu->arch.dr7 & DR7_GD) {
7747                                 vcpu->arch.dr7 &= ~DR7_GD;
7748                                 kvm_update_dr7(vcpu);
7749                         }
7750                 }
7751
7752                 kvm_x86_ops.queue_exception(vcpu);
7753         }
7754
7755         /* Don't consider new event if we re-injected an event */
7756         if (kvm_event_needs_reinjection(vcpu))
7757                 return 0;
7758
7759         if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7760             kvm_x86_ops.smi_allowed(vcpu)) {
7761                 vcpu->arch.smi_pending = false;
7762                 ++vcpu->arch.smi_count;
7763                 enter_smm(vcpu);
7764         } else if (vcpu->arch.nmi_pending && kvm_x86_ops.nmi_allowed(vcpu)) {
7765                 --vcpu->arch.nmi_pending;
7766                 vcpu->arch.nmi_injected = true;
7767                 kvm_x86_ops.set_nmi(vcpu);
7768         } else if (kvm_cpu_has_injectable_intr(vcpu)) {
7769                 /*
7770                  * Because interrupts can be injected asynchronously, we are
7771                  * calling check_nested_events again here to avoid a race condition.
7772                  * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7773                  * proposal and current concerns.  Perhaps we should be setting
7774                  * KVM_REQ_EVENT only on certain events and not unconditionally?
7775                  */
7776                 if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events) {
7777                         r = kvm_x86_ops.check_nested_events(vcpu);
7778                         if (r != 0)
7779                                 return r;
7780                 }
7781                 if (kvm_x86_ops.interrupt_allowed(vcpu)) {
7782                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7783                                             false);
7784                         kvm_x86_ops.set_irq(vcpu);
7785                 }
7786         }
7787
7788         return 0;
7789 }
7790
7791 static void process_nmi(struct kvm_vcpu *vcpu)
7792 {
7793         unsigned limit = 2;
7794
7795         /*
7796          * x86 is limited to one NMI running, and one NMI pending after it.
7797          * If an NMI is already in progress, limit further NMIs to just one.
7798          * Otherwise, allow two (and we'll inject the first one immediately).
7799          */
7800         if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7801                 limit = 1;
7802
7803         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7804         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7805         kvm_make_request(KVM_REQ_EVENT, vcpu);
7806 }
7807
7808 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7809 {
7810         u32 flags = 0;
7811         flags |= seg->g       << 23;
7812         flags |= seg->db      << 22;
7813         flags |= seg->l       << 21;
7814         flags |= seg->avl     << 20;
7815         flags |= seg->present << 15;
7816         flags |= seg->dpl     << 13;
7817         flags |= seg->s       << 12;
7818         flags |= seg->type    << 8;
7819         return flags;
7820 }
7821
7822 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7823 {
7824         struct kvm_segment seg;
7825         int offset;
7826
7827         kvm_get_segment(vcpu, &seg, n);
7828         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7829
7830         if (n < 3)
7831                 offset = 0x7f84 + n * 12;
7832         else
7833                 offset = 0x7f2c + (n - 3) * 12;
7834
7835         put_smstate(u32, buf, offset + 8, seg.base);
7836         put_smstate(u32, buf, offset + 4, seg.limit);
7837         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7838 }
7839
7840 #ifdef CONFIG_X86_64
7841 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
7842 {
7843         struct kvm_segment seg;
7844         int offset;
7845         u16 flags;
7846
7847         kvm_get_segment(vcpu, &seg, n);
7848         offset = 0x7e00 + n * 16;
7849
7850         flags = enter_smm_get_segment_flags(&seg) >> 8;
7851         put_smstate(u16, buf, offset, seg.selector);
7852         put_smstate(u16, buf, offset + 2, flags);
7853         put_smstate(u32, buf, offset + 4, seg.limit);
7854         put_smstate(u64, buf, offset + 8, seg.base);
7855 }
7856 #endif
7857
7858 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
7859 {
7860         struct desc_ptr dt;
7861         struct kvm_segment seg;
7862         unsigned long val;
7863         int i;
7864
7865         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7866         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7867         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7868         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7869
7870         for (i = 0; i < 8; i++)
7871                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7872
7873         kvm_get_dr(vcpu, 6, &val);
7874         put_smstate(u32, buf, 0x7fcc, (u32)val);
7875         kvm_get_dr(vcpu, 7, &val);
7876         put_smstate(u32, buf, 0x7fc8, (u32)val);
7877
7878         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7879         put_smstate(u32, buf, 0x7fc4, seg.selector);
7880         put_smstate(u32, buf, 0x7f64, seg.base);
7881         put_smstate(u32, buf, 0x7f60, seg.limit);
7882         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
7883
7884         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7885         put_smstate(u32, buf, 0x7fc0, seg.selector);
7886         put_smstate(u32, buf, 0x7f80, seg.base);
7887         put_smstate(u32, buf, 0x7f7c, seg.limit);
7888         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
7889
7890         kvm_x86_ops.get_gdt(vcpu, &dt);
7891         put_smstate(u32, buf, 0x7f74, dt.address);
7892         put_smstate(u32, buf, 0x7f70, dt.size);
7893
7894         kvm_x86_ops.get_idt(vcpu, &dt);
7895         put_smstate(u32, buf, 0x7f58, dt.address);
7896         put_smstate(u32, buf, 0x7f54, dt.size);
7897
7898         for (i = 0; i < 6; i++)
7899                 enter_smm_save_seg_32(vcpu, buf, i);
7900
7901         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7902
7903         /* revision id */
7904         put_smstate(u32, buf, 0x7efc, 0x00020000);
7905         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7906 }
7907
7908 #ifdef CONFIG_X86_64
7909 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
7910 {
7911         struct desc_ptr dt;
7912         struct kvm_segment seg;
7913         unsigned long val;
7914         int i;
7915
7916         for (i = 0; i < 16; i++)
7917                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7918
7919         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7920         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7921
7922         kvm_get_dr(vcpu, 6, &val);
7923         put_smstate(u64, buf, 0x7f68, val);
7924         kvm_get_dr(vcpu, 7, &val);
7925         put_smstate(u64, buf, 0x7f60, val);
7926
7927         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7928         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7929         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7930
7931         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7932
7933         /* revision id */
7934         put_smstate(u32, buf, 0x7efc, 0x00020064);
7935
7936         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7937
7938         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7939         put_smstate(u16, buf, 0x7e90, seg.selector);
7940         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
7941         put_smstate(u32, buf, 0x7e94, seg.limit);
7942         put_smstate(u64, buf, 0x7e98, seg.base);
7943
7944         kvm_x86_ops.get_idt(vcpu, &dt);
7945         put_smstate(u32, buf, 0x7e84, dt.size);
7946         put_smstate(u64, buf, 0x7e88, dt.address);
7947
7948         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7949         put_smstate(u16, buf, 0x7e70, seg.selector);
7950         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
7951         put_smstate(u32, buf, 0x7e74, seg.limit);
7952         put_smstate(u64, buf, 0x7e78, seg.base);
7953
7954         kvm_x86_ops.get_gdt(vcpu, &dt);
7955         put_smstate(u32, buf, 0x7e64, dt.size);
7956         put_smstate(u64, buf, 0x7e68, dt.address);
7957
7958         for (i = 0; i < 6; i++)
7959                 enter_smm_save_seg_64(vcpu, buf, i);
7960 }
7961 #endif
7962
7963 static void enter_smm(struct kvm_vcpu *vcpu)
7964 {
7965         struct kvm_segment cs, ds;
7966         struct desc_ptr dt;
7967         char buf[512];
7968         u32 cr0;
7969
7970         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
7971         memset(buf, 0, 512);
7972 #ifdef CONFIG_X86_64
7973         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
7974                 enter_smm_save_state_64(vcpu, buf);
7975         else
7976 #endif
7977                 enter_smm_save_state_32(vcpu, buf);
7978
7979         /*
7980          * Give pre_enter_smm() a chance to make ISA-specific changes to the
7981          * vCPU state (e.g. leave guest mode) after we've saved the state into
7982          * the SMM state-save area.
7983          */
7984         kvm_x86_ops.pre_enter_smm(vcpu, buf);
7985
7986         vcpu->arch.hflags |= HF_SMM_MASK;
7987         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
7988
7989         if (kvm_x86_ops.get_nmi_mask(vcpu))
7990                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7991         else
7992                 kvm_x86_ops.set_nmi_mask(vcpu, true);
7993
7994         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7995         kvm_rip_write(vcpu, 0x8000);
7996
7997         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7998         kvm_x86_ops.set_cr0(vcpu, cr0);
7999         vcpu->arch.cr0 = cr0;
8000
8001         kvm_x86_ops.set_cr4(vcpu, 0);
8002
8003         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
8004         dt.address = dt.size = 0;
8005         kvm_x86_ops.set_idt(vcpu, &dt);
8006
8007         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8008
8009         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8010         cs.base = vcpu->arch.smbase;
8011
8012         ds.selector = 0;
8013         ds.base = 0;
8014
8015         cs.limit    = ds.limit = 0xffffffff;
8016         cs.type     = ds.type = 0x3;
8017         cs.dpl      = ds.dpl = 0;
8018         cs.db       = ds.db = 0;
8019         cs.s        = ds.s = 1;
8020         cs.l        = ds.l = 0;
8021         cs.g        = ds.g = 1;
8022         cs.avl      = ds.avl = 0;
8023         cs.present  = ds.present = 1;
8024         cs.unusable = ds.unusable = 0;
8025         cs.padding  = ds.padding = 0;
8026
8027         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8028         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8029         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8030         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8031         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8032         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8033
8034 #ifdef CONFIG_X86_64
8035         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8036                 kvm_x86_ops.set_efer(vcpu, 0);
8037 #endif
8038
8039         kvm_update_cpuid(vcpu);
8040         kvm_mmu_reset_context(vcpu);
8041 }
8042
8043 static void process_smi(struct kvm_vcpu *vcpu)
8044 {
8045         vcpu->arch.smi_pending = true;
8046         kvm_make_request(KVM_REQ_EVENT, vcpu);
8047 }
8048
8049 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8050                                        unsigned long *vcpu_bitmap)
8051 {
8052         cpumask_var_t cpus;
8053
8054         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8055
8056         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8057                                     vcpu_bitmap, cpus);
8058
8059         free_cpumask_var(cpus);
8060 }
8061
8062 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8063 {
8064         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8065 }
8066
8067 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8068 {
8069         if (!lapic_in_kernel(vcpu))
8070                 return;
8071
8072         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8073         kvm_apic_update_apicv(vcpu);
8074         kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8075 }
8076 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8077
8078 /*
8079  * NOTE: Do not hold any lock prior to calling this.
8080  *
8081  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8082  * locked, because it calls __x86_set_memory_region() which does
8083  * synchronize_srcu(&kvm->srcu).
8084  */
8085 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8086 {
8087         unsigned long old, new, expected;
8088
8089         if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8090             !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8091                 return;
8092
8093         old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8094         do {
8095                 expected = new = old;
8096                 if (activate)
8097                         __clear_bit(bit, &new);
8098                 else
8099                         __set_bit(bit, &new);
8100                 if (new == old)
8101                         break;
8102                 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8103         } while (old != expected);
8104
8105         if (!!old == !!new)
8106                 return;
8107
8108         trace_kvm_apicv_update_request(activate, bit);
8109         if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8110                 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8111         kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
8112 }
8113 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8114
8115 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8116 {
8117         if (!kvm_apic_present(vcpu))
8118                 return;
8119
8120         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8121
8122         if (irqchip_split(vcpu->kvm))
8123                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8124         else {
8125                 if (vcpu->arch.apicv_active)
8126                         kvm_x86_ops.sync_pir_to_irr(vcpu);
8127                 if (ioapic_in_kernel(vcpu->kvm))
8128                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8129         }
8130
8131         if (is_guest_mode(vcpu))
8132                 vcpu->arch.load_eoi_exitmap_pending = true;
8133         else
8134                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8135 }
8136
8137 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8138 {
8139         u64 eoi_exit_bitmap[4];
8140
8141         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8142                 return;
8143
8144         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8145                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8146         kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8147 }
8148
8149 int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8150                 unsigned long start, unsigned long end,
8151                 bool blockable)
8152 {
8153         unsigned long apic_address;
8154
8155         /*
8156          * The physical address of apic access page is stored in the VMCS.
8157          * Update it when it becomes invalid.
8158          */
8159         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8160         if (start <= apic_address && apic_address < end)
8161                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8162
8163         return 0;
8164 }
8165
8166 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8167 {
8168         struct page *page = NULL;
8169
8170         if (!lapic_in_kernel(vcpu))
8171                 return;
8172
8173         if (!kvm_x86_ops.set_apic_access_page_addr)
8174                 return;
8175
8176         page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8177         if (is_error_page(page))
8178                 return;
8179         kvm_x86_ops.set_apic_access_page_addr(vcpu, page_to_phys(page));
8180
8181         /*
8182          * Do not pin apic access page in memory, the MMU notifier
8183          * will call us again if it is migrated or swapped out.
8184          */
8185         put_page(page);
8186 }
8187
8188 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8189 {
8190         smp_send_reschedule(vcpu->cpu);
8191 }
8192 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8193
8194 /*
8195  * Returns 1 to let vcpu_run() continue the guest execution loop without
8196  * exiting to the userspace.  Otherwise, the value will be returned to the
8197  * userspace.
8198  */
8199 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8200 {
8201         int r;
8202         bool req_int_win =
8203                 dm_request_for_irq_injection(vcpu) &&
8204                 kvm_cpu_accept_dm_intr(vcpu);
8205         enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
8206
8207         bool req_immediate_exit = false;
8208
8209         if (kvm_request_pending(vcpu)) {
8210                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8211                         if (unlikely(!kvm_x86_ops.get_vmcs12_pages(vcpu))) {
8212                                 r = 0;
8213                                 goto out;
8214                         }
8215                 }
8216                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8217                         kvm_mmu_unload(vcpu);
8218                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8219                         __kvm_migrate_timers(vcpu);
8220                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8221                         kvm_gen_update_masterclock(vcpu->kvm);
8222                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8223                         kvm_gen_kvmclock_update(vcpu);
8224                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8225                         r = kvm_guest_time_update(vcpu);
8226                         if (unlikely(r))
8227                                 goto out;
8228                 }
8229                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8230                         kvm_mmu_sync_roots(vcpu);
8231                 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8232                         kvm_mmu_load_pgd(vcpu);
8233                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
8234                         kvm_vcpu_flush_tlb(vcpu, true);
8235                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8236                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8237                         r = 0;
8238                         goto out;
8239                 }
8240                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8241                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8242                         vcpu->mmio_needed = 0;
8243                         r = 0;
8244                         goto out;
8245                 }
8246                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8247                         /* Page is swapped out. Do synthetic halt */
8248                         vcpu->arch.apf.halted = true;
8249                         r = 1;
8250                         goto out;
8251                 }
8252                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8253                         record_steal_time(vcpu);
8254                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8255                         process_smi(vcpu);
8256                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8257                         process_nmi(vcpu);
8258                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8259                         kvm_pmu_handle_event(vcpu);
8260                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8261                         kvm_pmu_deliver_pmi(vcpu);
8262                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8263                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8264                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8265                                      vcpu->arch.ioapic_handled_vectors)) {
8266                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8267                                 vcpu->run->eoi.vector =
8268                                                 vcpu->arch.pending_ioapic_eoi;
8269                                 r = 0;
8270                                 goto out;
8271                         }
8272                 }
8273                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8274                         vcpu_scan_ioapic(vcpu);
8275                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8276                         vcpu_load_eoi_exitmap(vcpu);
8277                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8278                         kvm_vcpu_reload_apic_access_page(vcpu);
8279                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8280                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8281                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8282                         r = 0;
8283                         goto out;
8284                 }
8285                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8286                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8287                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8288                         r = 0;
8289                         goto out;
8290                 }
8291                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8292                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8293                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8294                         r = 0;
8295                         goto out;
8296                 }
8297
8298                 /*
8299                  * KVM_REQ_HV_STIMER has to be processed after
8300                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8301                  * depend on the guest clock being up-to-date
8302                  */
8303                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8304                         kvm_hv_process_stimers(vcpu);
8305                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8306                         kvm_vcpu_update_apicv(vcpu);
8307         }
8308
8309         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8310                 ++vcpu->stat.req_event;
8311                 kvm_apic_accept_events(vcpu);
8312                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8313                         r = 1;
8314                         goto out;
8315                 }
8316
8317                 if (inject_pending_event(vcpu) != 0)
8318                         req_immediate_exit = true;
8319                 else {
8320                         /* Enable SMI/NMI/IRQ window open exits if needed.
8321                          *
8322                          * SMIs have three cases:
8323                          * 1) They can be nested, and then there is nothing to
8324                          *    do here because RSM will cause a vmexit anyway.
8325                          * 2) There is an ISA-specific reason why SMI cannot be
8326                          *    injected, and the moment when this changes can be
8327                          *    intercepted.
8328                          * 3) Or the SMI can be pending because
8329                          *    inject_pending_event has completed the injection
8330                          *    of an IRQ or NMI from the previous vmexit, and
8331                          *    then we request an immediate exit to inject the
8332                          *    SMI.
8333                          */
8334                         if (vcpu->arch.smi_pending && !is_smm(vcpu))
8335                                 if (!kvm_x86_ops.enable_smi_window(vcpu))
8336                                         req_immediate_exit = true;
8337                         if (vcpu->arch.nmi_pending)
8338                                 kvm_x86_ops.enable_nmi_window(vcpu);
8339                         if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8340                                 kvm_x86_ops.enable_irq_window(vcpu);
8341                         WARN_ON(vcpu->arch.exception.pending);
8342                 }
8343
8344                 if (kvm_lapic_enabled(vcpu)) {
8345                         update_cr8_intercept(vcpu);
8346                         kvm_lapic_sync_to_vapic(vcpu);
8347                 }
8348         }
8349
8350         r = kvm_mmu_reload(vcpu);
8351         if (unlikely(r)) {
8352                 goto cancel_injection;
8353         }
8354
8355         preempt_disable();
8356
8357         kvm_x86_ops.prepare_guest_switch(vcpu);
8358
8359         /*
8360          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8361          * IPI are then delayed after guest entry, which ensures that they
8362          * result in virtual interrupt delivery.
8363          */
8364         local_irq_disable();
8365         vcpu->mode = IN_GUEST_MODE;
8366
8367         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8368
8369         /*
8370          * 1) We should set ->mode before checking ->requests.  Please see
8371          * the comment in kvm_vcpu_exiting_guest_mode().
8372          *
8373          * 2) For APICv, we should set ->mode before checking PID.ON. This
8374          * pairs with the memory barrier implicit in pi_test_and_set_on
8375          * (see vmx_deliver_posted_interrupt).
8376          *
8377          * 3) This also orders the write to mode from any reads to the page
8378          * tables done while the VCPU is running.  Please see the comment
8379          * in kvm_flush_remote_tlbs.
8380          */
8381         smp_mb__after_srcu_read_unlock();
8382
8383         /*
8384          * This handles the case where a posted interrupt was
8385          * notified with kvm_vcpu_kick.
8386          */
8387         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8388                 kvm_x86_ops.sync_pir_to_irr(vcpu);
8389
8390         if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
8391             || need_resched() || signal_pending(current)) {
8392                 vcpu->mode = OUTSIDE_GUEST_MODE;
8393                 smp_wmb();
8394                 local_irq_enable();
8395                 preempt_enable();
8396                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8397                 r = 1;
8398                 goto cancel_injection;
8399         }
8400
8401         if (req_immediate_exit) {
8402                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8403                 kvm_x86_ops.request_immediate_exit(vcpu);
8404         }
8405
8406         trace_kvm_entry(vcpu->vcpu_id);
8407         guest_enter_irqoff();
8408
8409         fpregs_assert_state_consistent();
8410         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8411                 switch_fpu_return();
8412
8413         if (unlikely(vcpu->arch.switch_db_regs)) {
8414                 set_debugreg(0, 7);
8415                 set_debugreg(vcpu->arch.eff_db[0], 0);
8416                 set_debugreg(vcpu->arch.eff_db[1], 1);
8417                 set_debugreg(vcpu->arch.eff_db[2], 2);
8418                 set_debugreg(vcpu->arch.eff_db[3], 3);
8419                 set_debugreg(vcpu->arch.dr6, 6);
8420                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8421         }
8422
8423         kvm_x86_ops.run(vcpu);
8424
8425         /*
8426          * Do this here before restoring debug registers on the host.  And
8427          * since we do this before handling the vmexit, a DR access vmexit
8428          * can (a) read the correct value of the debug registers, (b) set
8429          * KVM_DEBUGREG_WONT_EXIT again.
8430          */
8431         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8432                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8433                 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8434                 kvm_update_dr0123(vcpu);
8435                 kvm_update_dr6(vcpu);
8436                 kvm_update_dr7(vcpu);
8437                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8438         }
8439
8440         /*
8441          * If the guest has used debug registers, at least dr7
8442          * will be disabled while returning to the host.
8443          * If we don't have active breakpoints in the host, we don't
8444          * care about the messed up debug address registers. But if
8445          * we have some of them active, restore the old state.
8446          */
8447         if (hw_breakpoint_active())
8448                 hw_breakpoint_restore();
8449
8450         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8451
8452         vcpu->mode = OUTSIDE_GUEST_MODE;
8453         smp_wmb();
8454
8455         kvm_x86_ops.handle_exit_irqoff(vcpu, &exit_fastpath);
8456
8457         /*
8458          * Consume any pending interrupts, including the possible source of
8459          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8460          * An instruction is required after local_irq_enable() to fully unblock
8461          * interrupts on processors that implement an interrupt shadow, the
8462          * stat.exits increment will do nicely.
8463          */
8464         kvm_before_interrupt(vcpu);
8465         local_irq_enable();
8466         ++vcpu->stat.exits;
8467         local_irq_disable();
8468         kvm_after_interrupt(vcpu);
8469
8470         guest_exit_irqoff();
8471         if (lapic_in_kernel(vcpu)) {
8472                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8473                 if (delta != S64_MIN) {
8474                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8475                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8476                 }
8477         }
8478
8479         local_irq_enable();
8480         preempt_enable();
8481
8482         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8483
8484         /*
8485          * Profile KVM exit RIPs:
8486          */
8487         if (unlikely(prof_on == KVM_PROFILING)) {
8488                 unsigned long rip = kvm_rip_read(vcpu);
8489                 profile_hit(KVM_PROFILING, (void *)rip);
8490         }
8491
8492         if (unlikely(vcpu->arch.tsc_always_catchup))
8493                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8494
8495         if (vcpu->arch.apic_attention)
8496                 kvm_lapic_sync_from_vapic(vcpu);
8497
8498         r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8499         return r;
8500
8501 cancel_injection:
8502         kvm_x86_ops.cancel_injection(vcpu);
8503         if (unlikely(vcpu->arch.apic_attention))
8504                 kvm_lapic_sync_from_vapic(vcpu);
8505 out:
8506         return r;
8507 }
8508
8509 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8510 {
8511         if (!kvm_arch_vcpu_runnable(vcpu) &&
8512             (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8513                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8514                 kvm_vcpu_block(vcpu);
8515                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8516
8517                 if (kvm_x86_ops.post_block)
8518                         kvm_x86_ops.post_block(vcpu);
8519
8520                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8521                         return 1;
8522         }
8523
8524         kvm_apic_accept_events(vcpu);
8525         switch(vcpu->arch.mp_state) {
8526         case KVM_MP_STATE_HALTED:
8527                 vcpu->arch.pv.pv_unhalted = false;
8528                 vcpu->arch.mp_state =
8529                         KVM_MP_STATE_RUNNABLE;
8530                 /* fall through */
8531         case KVM_MP_STATE_RUNNABLE:
8532                 vcpu->arch.apf.halted = false;
8533                 break;
8534         case KVM_MP_STATE_INIT_RECEIVED:
8535                 break;
8536         default:
8537                 return -EINTR;
8538         }
8539         return 1;
8540 }
8541
8542 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8543 {
8544         if (is_guest_mode(vcpu) && kvm_x86_ops.check_nested_events)
8545                 kvm_x86_ops.check_nested_events(vcpu);
8546
8547         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8548                 !vcpu->arch.apf.halted);
8549 }
8550
8551 static int vcpu_run(struct kvm_vcpu *vcpu)
8552 {
8553         int r;
8554         struct kvm *kvm = vcpu->kvm;
8555
8556         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8557         vcpu->arch.l1tf_flush_l1d = true;
8558
8559         for (;;) {
8560                 if (kvm_vcpu_running(vcpu)) {
8561                         r = vcpu_enter_guest(vcpu);
8562                 } else {
8563                         r = vcpu_block(kvm, vcpu);
8564                 }
8565
8566                 if (r <= 0)
8567                         break;
8568
8569                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8570                 if (kvm_cpu_has_pending_timer(vcpu))
8571                         kvm_inject_pending_timer_irqs(vcpu);
8572
8573                 if (dm_request_for_irq_injection(vcpu) &&
8574                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8575                         r = 0;
8576                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8577                         ++vcpu->stat.request_irq_exits;
8578                         break;
8579                 }
8580
8581                 kvm_check_async_pf_completion(vcpu);
8582
8583                 if (signal_pending(current)) {
8584                         r = -EINTR;
8585                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8586                         ++vcpu->stat.signal_exits;
8587                         break;
8588                 }
8589                 if (need_resched()) {
8590                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8591                         cond_resched();
8592                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8593                 }
8594         }
8595
8596         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8597
8598         return r;
8599 }
8600
8601 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8602 {
8603         int r;
8604
8605         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8606         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8607         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8608         return r;
8609 }
8610
8611 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8612 {
8613         BUG_ON(!vcpu->arch.pio.count);
8614
8615         return complete_emulated_io(vcpu);
8616 }
8617
8618 /*
8619  * Implements the following, as a state machine:
8620  *
8621  * read:
8622  *   for each fragment
8623  *     for each mmio piece in the fragment
8624  *       write gpa, len
8625  *       exit
8626  *       copy data
8627  *   execute insn
8628  *
8629  * write:
8630  *   for each fragment
8631  *     for each mmio piece in the fragment
8632  *       write gpa, len
8633  *       copy data
8634  *       exit
8635  */
8636 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8637 {
8638         struct kvm_run *run = vcpu->run;
8639         struct kvm_mmio_fragment *frag;
8640         unsigned len;
8641
8642         BUG_ON(!vcpu->mmio_needed);
8643
8644         /* Complete previous fragment */
8645         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8646         len = min(8u, frag->len);
8647         if (!vcpu->mmio_is_write)
8648                 memcpy(frag->data, run->mmio.data, len);
8649
8650         if (frag->len <= 8) {
8651                 /* Switch to the next fragment. */
8652                 frag++;
8653                 vcpu->mmio_cur_fragment++;
8654         } else {
8655                 /* Go forward to the next mmio piece. */
8656                 frag->data += len;
8657                 frag->gpa += len;
8658                 frag->len -= len;
8659         }
8660
8661         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8662                 vcpu->mmio_needed = 0;
8663
8664                 /* FIXME: return into emulator if single-stepping.  */
8665                 if (vcpu->mmio_is_write)
8666                         return 1;
8667                 vcpu->mmio_read_completed = 1;
8668                 return complete_emulated_io(vcpu);
8669         }
8670
8671         run->exit_reason = KVM_EXIT_MMIO;
8672         run->mmio.phys_addr = frag->gpa;
8673         if (vcpu->mmio_is_write)
8674                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8675         run->mmio.len = min(8u, frag->len);
8676         run->mmio.is_write = vcpu->mmio_is_write;
8677         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8678         return 0;
8679 }
8680
8681 static void kvm_save_current_fpu(struct fpu *fpu)
8682 {
8683         /*
8684          * If the target FPU state is not resident in the CPU registers, just
8685          * memcpy() from current, else save CPU state directly to the target.
8686          */
8687         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8688                 memcpy(&fpu->state, &current->thread.fpu.state,
8689                        fpu_kernel_xstate_size);
8690         else
8691                 copy_fpregs_to_fpstate(fpu);
8692 }
8693
8694 /* Swap (qemu) user FPU context for the guest FPU context. */
8695 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8696 {
8697         fpregs_lock();
8698
8699         kvm_save_current_fpu(vcpu->arch.user_fpu);
8700
8701         /* PKRU is separately restored in kvm_x86_ops.run.  */
8702         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8703                                 ~XFEATURE_MASK_PKRU);
8704
8705         fpregs_mark_activate();
8706         fpregs_unlock();
8707
8708         trace_kvm_fpu(1);
8709 }
8710
8711 /* When vcpu_run ends, restore user space FPU context. */
8712 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8713 {
8714         fpregs_lock();
8715
8716         kvm_save_current_fpu(vcpu->arch.guest_fpu);
8717
8718         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8719
8720         fpregs_mark_activate();
8721         fpregs_unlock();
8722
8723         ++vcpu->stat.fpu_reload;
8724         trace_kvm_fpu(0);
8725 }
8726
8727 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8728 {
8729         int r;
8730
8731         vcpu_load(vcpu);
8732         kvm_sigset_activate(vcpu);
8733         kvm_load_guest_fpu(vcpu);
8734
8735         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8736                 if (kvm_run->immediate_exit) {
8737                         r = -EINTR;
8738                         goto out;
8739                 }
8740                 kvm_vcpu_block(vcpu);
8741                 kvm_apic_accept_events(vcpu);
8742                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8743                 r = -EAGAIN;
8744                 if (signal_pending(current)) {
8745                         r = -EINTR;
8746                         vcpu->run->exit_reason = KVM_EXIT_INTR;
8747                         ++vcpu->stat.signal_exits;
8748                 }
8749                 goto out;
8750         }
8751
8752         if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8753                 r = -EINVAL;
8754                 goto out;
8755         }
8756
8757         if (vcpu->run->kvm_dirty_regs) {
8758                 r = sync_regs(vcpu);
8759                 if (r != 0)
8760                         goto out;
8761         }
8762
8763         /* re-sync apic's tpr */
8764         if (!lapic_in_kernel(vcpu)) {
8765                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8766                         r = -EINVAL;
8767                         goto out;
8768                 }
8769         }
8770
8771         if (unlikely(vcpu->arch.complete_userspace_io)) {
8772                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8773                 vcpu->arch.complete_userspace_io = NULL;
8774                 r = cui(vcpu);
8775                 if (r <= 0)
8776                         goto out;
8777         } else
8778                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8779
8780         if (kvm_run->immediate_exit)
8781                 r = -EINTR;
8782         else
8783                 r = vcpu_run(vcpu);
8784
8785 out:
8786         kvm_put_guest_fpu(vcpu);
8787         if (vcpu->run->kvm_valid_regs)
8788                 store_regs(vcpu);
8789         post_kvm_run_save(vcpu);
8790         kvm_sigset_deactivate(vcpu);
8791
8792         vcpu_put(vcpu);
8793         return r;
8794 }
8795
8796 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8797 {
8798         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8799                 /*
8800                  * We are here if userspace calls get_regs() in the middle of
8801                  * instruction emulation. Registers state needs to be copied
8802                  * back from emulation context to vcpu. Userspace shouldn't do
8803                  * that usually, but some bad designed PV devices (vmware
8804                  * backdoor interface) need this to work
8805                  */
8806                 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8807                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8808         }
8809         regs->rax = kvm_rax_read(vcpu);
8810         regs->rbx = kvm_rbx_read(vcpu);
8811         regs->rcx = kvm_rcx_read(vcpu);
8812         regs->rdx = kvm_rdx_read(vcpu);
8813         regs->rsi = kvm_rsi_read(vcpu);
8814         regs->rdi = kvm_rdi_read(vcpu);
8815         regs->rsp = kvm_rsp_read(vcpu);
8816         regs->rbp = kvm_rbp_read(vcpu);
8817 #ifdef CONFIG_X86_64
8818         regs->r8 = kvm_r8_read(vcpu);
8819         regs->r9 = kvm_r9_read(vcpu);
8820         regs->r10 = kvm_r10_read(vcpu);
8821         regs->r11 = kvm_r11_read(vcpu);
8822         regs->r12 = kvm_r12_read(vcpu);
8823         regs->r13 = kvm_r13_read(vcpu);
8824         regs->r14 = kvm_r14_read(vcpu);
8825         regs->r15 = kvm_r15_read(vcpu);
8826 #endif
8827
8828         regs->rip = kvm_rip_read(vcpu);
8829         regs->rflags = kvm_get_rflags(vcpu);
8830 }
8831
8832 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8833 {
8834         vcpu_load(vcpu);
8835         __get_regs(vcpu, regs);
8836         vcpu_put(vcpu);
8837         return 0;
8838 }
8839
8840 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8841 {
8842         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8843         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8844
8845         kvm_rax_write(vcpu, regs->rax);
8846         kvm_rbx_write(vcpu, regs->rbx);
8847         kvm_rcx_write(vcpu, regs->rcx);
8848         kvm_rdx_write(vcpu, regs->rdx);
8849         kvm_rsi_write(vcpu, regs->rsi);
8850         kvm_rdi_write(vcpu, regs->rdi);
8851         kvm_rsp_write(vcpu, regs->rsp);
8852         kvm_rbp_write(vcpu, regs->rbp);
8853 #ifdef CONFIG_X86_64
8854         kvm_r8_write(vcpu, regs->r8);
8855         kvm_r9_write(vcpu, regs->r9);
8856         kvm_r10_write(vcpu, regs->r10);
8857         kvm_r11_write(vcpu, regs->r11);
8858         kvm_r12_write(vcpu, regs->r12);
8859         kvm_r13_write(vcpu, regs->r13);
8860         kvm_r14_write(vcpu, regs->r14);
8861         kvm_r15_write(vcpu, regs->r15);
8862 #endif
8863
8864         kvm_rip_write(vcpu, regs->rip);
8865         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
8866
8867         vcpu->arch.exception.pending = false;
8868
8869         kvm_make_request(KVM_REQ_EVENT, vcpu);
8870 }
8871
8872 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8873 {
8874         vcpu_load(vcpu);
8875         __set_regs(vcpu, regs);
8876         vcpu_put(vcpu);
8877         return 0;
8878 }
8879
8880 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8881 {
8882         struct kvm_segment cs;
8883
8884         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8885         *db = cs.db;
8886         *l = cs.l;
8887 }
8888 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8889
8890 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
8891 {
8892         struct desc_ptr dt;
8893
8894         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8895         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8896         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8897         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8898         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8899         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
8900
8901         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8902         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
8903
8904         kvm_x86_ops.get_idt(vcpu, &dt);
8905         sregs->idt.limit = dt.size;
8906         sregs->idt.base = dt.address;
8907         kvm_x86_ops.get_gdt(vcpu, &dt);
8908         sregs->gdt.limit = dt.size;
8909         sregs->gdt.base = dt.address;
8910
8911         sregs->cr0 = kvm_read_cr0(vcpu);
8912         sregs->cr2 = vcpu->arch.cr2;
8913         sregs->cr3 = kvm_read_cr3(vcpu);
8914         sregs->cr4 = kvm_read_cr4(vcpu);
8915         sregs->cr8 = kvm_get_cr8(vcpu);
8916         sregs->efer = vcpu->arch.efer;
8917         sregs->apic_base = kvm_get_apic_base(vcpu);
8918
8919         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
8920
8921         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
8922                 set_bit(vcpu->arch.interrupt.nr,
8923                         (unsigned long *)sregs->interrupt_bitmap);
8924 }
8925
8926 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8927                                   struct kvm_sregs *sregs)
8928 {
8929         vcpu_load(vcpu);
8930         __get_sregs(vcpu, sregs);
8931         vcpu_put(vcpu);
8932         return 0;
8933 }
8934
8935 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8936                                     struct kvm_mp_state *mp_state)
8937 {
8938         vcpu_load(vcpu);
8939         if (kvm_mpx_supported())
8940                 kvm_load_guest_fpu(vcpu);
8941
8942         kvm_apic_accept_events(vcpu);
8943         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8944                                         vcpu->arch.pv.pv_unhalted)
8945                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8946         else
8947                 mp_state->mp_state = vcpu->arch.mp_state;
8948
8949         if (kvm_mpx_supported())
8950                 kvm_put_guest_fpu(vcpu);
8951         vcpu_put(vcpu);
8952         return 0;
8953 }
8954
8955 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8956                                     struct kvm_mp_state *mp_state)
8957 {
8958         int ret = -EINVAL;
8959
8960         vcpu_load(vcpu);
8961
8962         if (!lapic_in_kernel(vcpu) &&
8963             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
8964                 goto out;
8965
8966         /*
8967          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8968          * INIT state; latched init should be reported using
8969          * KVM_SET_VCPU_EVENTS, so reject it here.
8970          */
8971         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
8972             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8973              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
8974                 goto out;
8975
8976         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8977                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8978                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8979         } else
8980                 vcpu->arch.mp_state = mp_state->mp_state;
8981         kvm_make_request(KVM_REQ_EVENT, vcpu);
8982
8983         ret = 0;
8984 out:
8985         vcpu_put(vcpu);
8986         return ret;
8987 }
8988
8989 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8990                     int reason, bool has_error_code, u32 error_code)
8991 {
8992         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8993         int ret;
8994
8995         init_emulate_ctxt(vcpu);
8996
8997         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
8998                                    has_error_code, error_code);
8999         if (ret) {
9000                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9001                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9002                 vcpu->run->internal.ndata = 0;
9003                 return 0;
9004         }
9005
9006         kvm_rip_write(vcpu, ctxt->eip);
9007         kvm_set_rflags(vcpu, ctxt->eflags);
9008         return 1;
9009 }
9010 EXPORT_SYMBOL_GPL(kvm_task_switch);
9011
9012 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9013 {
9014         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9015                 /*
9016                  * When EFER.LME and CR0.PG are set, the processor is in
9017                  * 64-bit mode (though maybe in a 32-bit code segment).
9018                  * CR4.PAE and EFER.LMA must be set.
9019                  */
9020                 if (!(sregs->cr4 & X86_CR4_PAE)
9021                     || !(sregs->efer & EFER_LMA))
9022                         return -EINVAL;
9023         } else {
9024                 /*
9025                  * Not in 64-bit mode: EFER.LMA is clear and the code
9026                  * segment cannot be 64-bit.
9027                  */
9028                 if (sregs->efer & EFER_LMA || sregs->cs.l)
9029                         return -EINVAL;
9030         }
9031
9032         return kvm_valid_cr4(vcpu, sregs->cr4);
9033 }
9034
9035 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9036 {
9037         struct msr_data apic_base_msr;
9038         int mmu_reset_needed = 0;
9039         int cpuid_update_needed = 0;
9040         int pending_vec, max_bits, idx;
9041         struct desc_ptr dt;
9042         int ret = -EINVAL;
9043
9044         if (kvm_valid_sregs(vcpu, sregs))
9045                 goto out;
9046
9047         apic_base_msr.data = sregs->apic_base;
9048         apic_base_msr.host_initiated = true;
9049         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9050                 goto out;
9051
9052         dt.size = sregs->idt.limit;
9053         dt.address = sregs->idt.base;
9054         kvm_x86_ops.set_idt(vcpu, &dt);
9055         dt.size = sregs->gdt.limit;
9056         dt.address = sregs->gdt.base;
9057         kvm_x86_ops.set_gdt(vcpu, &dt);
9058
9059         vcpu->arch.cr2 = sregs->cr2;
9060         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9061         vcpu->arch.cr3 = sregs->cr3;
9062         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9063
9064         kvm_set_cr8(vcpu, sregs->cr8);
9065
9066         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9067         kvm_x86_ops.set_efer(vcpu, sregs->efer);
9068
9069         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9070         kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9071         vcpu->arch.cr0 = sregs->cr0;
9072
9073         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9074         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9075                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9076         kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9077         if (cpuid_update_needed)
9078                 kvm_update_cpuid(vcpu);
9079
9080         idx = srcu_read_lock(&vcpu->kvm->srcu);
9081         if (is_pae_paging(vcpu)) {
9082                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9083                 mmu_reset_needed = 1;
9084         }
9085         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9086
9087         if (mmu_reset_needed)
9088                 kvm_mmu_reset_context(vcpu);
9089
9090         max_bits = KVM_NR_INTERRUPTS;
9091         pending_vec = find_first_bit(
9092                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9093         if (pending_vec < max_bits) {
9094                 kvm_queue_interrupt(vcpu, pending_vec, false);
9095                 pr_debug("Set back pending irq %d\n", pending_vec);
9096         }
9097
9098         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9099         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9100         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9101         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9102         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9103         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9104
9105         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9106         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9107
9108         update_cr8_intercept(vcpu);
9109
9110         /* Older userspace won't unhalt the vcpu on reset. */
9111         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9112             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9113             !is_protmode(vcpu))
9114                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9115
9116         kvm_make_request(KVM_REQ_EVENT, vcpu);
9117
9118         ret = 0;
9119 out:
9120         return ret;
9121 }
9122
9123 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9124                                   struct kvm_sregs *sregs)
9125 {
9126         int ret;
9127
9128         vcpu_load(vcpu);
9129         ret = __set_sregs(vcpu, sregs);
9130         vcpu_put(vcpu);
9131         return ret;
9132 }
9133
9134 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9135                                         struct kvm_guest_debug *dbg)
9136 {
9137         unsigned long rflags;
9138         int i, r;
9139
9140         vcpu_load(vcpu);
9141
9142         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9143                 r = -EBUSY;
9144                 if (vcpu->arch.exception.pending)
9145                         goto out;
9146                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9147                         kvm_queue_exception(vcpu, DB_VECTOR);
9148                 else
9149                         kvm_queue_exception(vcpu, BP_VECTOR);
9150         }
9151
9152         /*
9153          * Read rflags as long as potentially injected trace flags are still
9154          * filtered out.
9155          */
9156         rflags = kvm_get_rflags(vcpu);
9157
9158         vcpu->guest_debug = dbg->control;
9159         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9160                 vcpu->guest_debug = 0;
9161
9162         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9163                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9164                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9165                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9166         } else {
9167                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9168                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9169         }
9170         kvm_update_dr7(vcpu);
9171
9172         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9173                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9174                         get_segment_base(vcpu, VCPU_SREG_CS);
9175
9176         /*
9177          * Trigger an rflags update that will inject or remove the trace
9178          * flags.
9179          */
9180         kvm_set_rflags(vcpu, rflags);
9181
9182         kvm_x86_ops.update_bp_intercept(vcpu);
9183
9184         r = 0;
9185
9186 out:
9187         vcpu_put(vcpu);
9188         return r;
9189 }
9190
9191 /*
9192  * Translate a guest virtual address to a guest physical address.
9193  */
9194 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9195                                     struct kvm_translation *tr)
9196 {
9197         unsigned long vaddr = tr->linear_address;
9198         gpa_t gpa;
9199         int idx;
9200
9201         vcpu_load(vcpu);
9202
9203         idx = srcu_read_lock(&vcpu->kvm->srcu);
9204         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9205         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9206         tr->physical_address = gpa;
9207         tr->valid = gpa != UNMAPPED_GVA;
9208         tr->writeable = 1;
9209         tr->usermode = 0;
9210
9211         vcpu_put(vcpu);
9212         return 0;
9213 }
9214
9215 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9216 {
9217         struct fxregs_state *fxsave;
9218
9219         vcpu_load(vcpu);
9220
9221         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9222         memcpy(fpu->fpr, fxsave->st_space, 128);
9223         fpu->fcw = fxsave->cwd;
9224         fpu->fsw = fxsave->swd;
9225         fpu->ftwx = fxsave->twd;
9226         fpu->last_opcode = fxsave->fop;
9227         fpu->last_ip = fxsave->rip;
9228         fpu->last_dp = fxsave->rdp;
9229         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9230
9231         vcpu_put(vcpu);
9232         return 0;
9233 }
9234
9235 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9236 {
9237         struct fxregs_state *fxsave;
9238
9239         vcpu_load(vcpu);
9240
9241         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9242
9243         memcpy(fxsave->st_space, fpu->fpr, 128);
9244         fxsave->cwd = fpu->fcw;
9245         fxsave->swd = fpu->fsw;
9246         fxsave->twd = fpu->ftwx;
9247         fxsave->fop = fpu->last_opcode;
9248         fxsave->rip = fpu->last_ip;
9249         fxsave->rdp = fpu->last_dp;
9250         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9251
9252         vcpu_put(vcpu);
9253         return 0;
9254 }
9255
9256 static void store_regs(struct kvm_vcpu *vcpu)
9257 {
9258         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9259
9260         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9261                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9262
9263         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9264                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9265
9266         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9267                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9268                                 vcpu, &vcpu->run->s.regs.events);
9269 }
9270
9271 static int sync_regs(struct kvm_vcpu *vcpu)
9272 {
9273         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9274                 return -EINVAL;
9275
9276         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9277                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9278                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9279         }
9280         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9281                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9282                         return -EINVAL;
9283                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9284         }
9285         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9286                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9287                                 vcpu, &vcpu->run->s.regs.events))
9288                         return -EINVAL;
9289                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9290         }
9291
9292         return 0;
9293 }
9294
9295 static void fx_init(struct kvm_vcpu *vcpu)
9296 {
9297         fpstate_init(&vcpu->arch.guest_fpu->state);
9298         if (boot_cpu_has(X86_FEATURE_XSAVES))
9299                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9300                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9301
9302         /*
9303          * Ensure guest xcr0 is valid for loading
9304          */
9305         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9306
9307         vcpu->arch.cr0 |= X86_CR0_ET;
9308 }
9309
9310 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9311 {
9312         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9313                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9314                              "guest TSC will not be reliable\n");
9315
9316         return 0;
9317 }
9318
9319 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9320 {
9321         struct page *page;
9322         int r;
9323
9324         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9325                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9326         else
9327                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9328
9329         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9330
9331         r = kvm_mmu_create(vcpu);
9332         if (r < 0)
9333                 return r;
9334
9335         if (irqchip_in_kernel(vcpu->kvm)) {
9336                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9337                 if (r < 0)
9338                         goto fail_mmu_destroy;
9339                 if (kvm_apicv_activated(vcpu->kvm))
9340                         vcpu->arch.apicv_active = true;
9341         } else
9342                 static_key_slow_inc(&kvm_no_apic_vcpu);
9343
9344         r = -ENOMEM;
9345
9346         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9347         if (!page)
9348                 goto fail_free_lapic;
9349         vcpu->arch.pio_data = page_address(page);
9350
9351         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9352                                        GFP_KERNEL_ACCOUNT);
9353         if (!vcpu->arch.mce_banks)
9354                 goto fail_free_pio_data;
9355         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9356
9357         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9358                                 GFP_KERNEL_ACCOUNT))
9359                 goto fail_free_mce_banks;
9360
9361         if (!alloc_emulate_ctxt(vcpu))
9362                 goto free_wbinvd_dirty_mask;
9363
9364         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9365                                                 GFP_KERNEL_ACCOUNT);
9366         if (!vcpu->arch.user_fpu) {
9367                 pr_err("kvm: failed to allocate userspace's fpu\n");
9368                 goto free_emulate_ctxt;
9369         }
9370
9371         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9372                                                  GFP_KERNEL_ACCOUNT);
9373         if (!vcpu->arch.guest_fpu) {
9374                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9375                 goto free_user_fpu;
9376         }
9377         fx_init(vcpu);
9378
9379         vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9380
9381         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9382
9383         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9384
9385         kvm_async_pf_hash_reset(vcpu);
9386         kvm_pmu_init(vcpu);
9387
9388         vcpu->arch.pending_external_vector = -1;
9389         vcpu->arch.preempted_in_kernel = false;
9390
9391         kvm_hv_vcpu_init(vcpu);
9392
9393         r = kvm_x86_ops.vcpu_create(vcpu);
9394         if (r)
9395                 goto free_guest_fpu;
9396
9397         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9398         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9399         kvm_vcpu_mtrr_init(vcpu);
9400         vcpu_load(vcpu);
9401         kvm_vcpu_reset(vcpu, false);
9402         kvm_init_mmu(vcpu, false);
9403         vcpu_put(vcpu);
9404         return 0;
9405
9406 free_guest_fpu:
9407         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9408 free_user_fpu:
9409         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9410 free_emulate_ctxt:
9411         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9412 free_wbinvd_dirty_mask:
9413         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9414 fail_free_mce_banks:
9415         kfree(vcpu->arch.mce_banks);
9416 fail_free_pio_data:
9417         free_page((unsigned long)vcpu->arch.pio_data);
9418 fail_free_lapic:
9419         kvm_free_lapic(vcpu);
9420 fail_mmu_destroy:
9421         kvm_mmu_destroy(vcpu);
9422         return r;
9423 }
9424
9425 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9426 {
9427         struct msr_data msr;
9428         struct kvm *kvm = vcpu->kvm;
9429
9430         kvm_hv_vcpu_postcreate(vcpu);
9431
9432         if (mutex_lock_killable(&vcpu->mutex))
9433                 return;
9434         vcpu_load(vcpu);
9435         msr.data = 0x0;
9436         msr.index = MSR_IA32_TSC;
9437         msr.host_initiated = true;
9438         kvm_write_tsc(vcpu, &msr);
9439         vcpu_put(vcpu);
9440
9441         /* poll control enabled by default */
9442         vcpu->arch.msr_kvm_poll_control = 1;
9443
9444         mutex_unlock(&vcpu->mutex);
9445
9446         if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9447                 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9448                                                 KVMCLOCK_SYNC_PERIOD);
9449 }
9450
9451 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9452 {
9453         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9454         int idx;
9455
9456         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9457
9458         kvmclock_reset(vcpu);
9459
9460         kvm_x86_ops.vcpu_free(vcpu);
9461
9462         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9463         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9464         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9465         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9466
9467         kvm_hv_vcpu_uninit(vcpu);
9468         kvm_pmu_destroy(vcpu);
9469         kfree(vcpu->arch.mce_banks);
9470         kvm_free_lapic(vcpu);
9471         idx = srcu_read_lock(&vcpu->kvm->srcu);
9472         kvm_mmu_destroy(vcpu);
9473         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9474         free_page((unsigned long)vcpu->arch.pio_data);
9475         if (!lapic_in_kernel(vcpu))
9476                 static_key_slow_dec(&kvm_no_apic_vcpu);
9477 }
9478
9479 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9480 {
9481         kvm_lapic_reset(vcpu, init_event);
9482
9483         vcpu->arch.hflags = 0;
9484
9485         vcpu->arch.smi_pending = 0;
9486         vcpu->arch.smi_count = 0;
9487         atomic_set(&vcpu->arch.nmi_queued, 0);
9488         vcpu->arch.nmi_pending = 0;
9489         vcpu->arch.nmi_injected = false;
9490         kvm_clear_interrupt_queue(vcpu);
9491         kvm_clear_exception_queue(vcpu);
9492
9493         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9494         kvm_update_dr0123(vcpu);
9495         vcpu->arch.dr6 = DR6_INIT;
9496         kvm_update_dr6(vcpu);
9497         vcpu->arch.dr7 = DR7_FIXED_1;
9498         kvm_update_dr7(vcpu);
9499
9500         vcpu->arch.cr2 = 0;
9501
9502         kvm_make_request(KVM_REQ_EVENT, vcpu);
9503         vcpu->arch.apf.msr_val = 0;
9504         vcpu->arch.st.msr_val = 0;
9505
9506         kvmclock_reset(vcpu);
9507
9508         kvm_clear_async_pf_completion_queue(vcpu);
9509         kvm_async_pf_hash_reset(vcpu);
9510         vcpu->arch.apf.halted = false;
9511
9512         if (kvm_mpx_supported()) {
9513                 void *mpx_state_buffer;
9514
9515                 /*
9516                  * To avoid have the INIT path from kvm_apic_has_events() that be
9517                  * called with loaded FPU and does not let userspace fix the state.
9518                  */
9519                 if (init_event)
9520                         kvm_put_guest_fpu(vcpu);
9521                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9522                                         XFEATURE_BNDREGS);
9523                 if (mpx_state_buffer)
9524                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9525                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9526                                         XFEATURE_BNDCSR);
9527                 if (mpx_state_buffer)
9528                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9529                 if (init_event)
9530                         kvm_load_guest_fpu(vcpu);
9531         }
9532
9533         if (!init_event) {
9534                 kvm_pmu_reset(vcpu);
9535                 vcpu->arch.smbase = 0x30000;
9536
9537                 vcpu->arch.msr_misc_features_enables = 0;
9538
9539                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9540         }
9541
9542         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9543         vcpu->arch.regs_avail = ~0;
9544         vcpu->arch.regs_dirty = ~0;
9545
9546         vcpu->arch.ia32_xss = 0;
9547
9548         kvm_x86_ops.vcpu_reset(vcpu, init_event);
9549 }
9550
9551 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9552 {
9553         struct kvm_segment cs;
9554
9555         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9556         cs.selector = vector << 8;
9557         cs.base = vector << 12;
9558         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9559         kvm_rip_write(vcpu, 0);
9560 }
9561
9562 int kvm_arch_hardware_enable(void)
9563 {
9564         struct kvm *kvm;
9565         struct kvm_vcpu *vcpu;
9566         int i;
9567         int ret;
9568         u64 local_tsc;
9569         u64 max_tsc = 0;
9570         bool stable, backwards_tsc = false;
9571
9572         kvm_shared_msr_cpu_online();
9573         ret = kvm_x86_ops.hardware_enable();
9574         if (ret != 0)
9575                 return ret;
9576
9577         local_tsc = rdtsc();
9578         stable = !kvm_check_tsc_unstable();
9579         list_for_each_entry(kvm, &vm_list, vm_list) {
9580                 kvm_for_each_vcpu(i, vcpu, kvm) {
9581                         if (!stable && vcpu->cpu == smp_processor_id())
9582                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9583                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9584                                 backwards_tsc = true;
9585                                 if (vcpu->arch.last_host_tsc > max_tsc)
9586                                         max_tsc = vcpu->arch.last_host_tsc;
9587                         }
9588                 }
9589         }
9590
9591         /*
9592          * Sometimes, even reliable TSCs go backwards.  This happens on
9593          * platforms that reset TSC during suspend or hibernate actions, but
9594          * maintain synchronization.  We must compensate.  Fortunately, we can
9595          * detect that condition here, which happens early in CPU bringup,
9596          * before any KVM threads can be running.  Unfortunately, we can't
9597          * bring the TSCs fully up to date with real time, as we aren't yet far
9598          * enough into CPU bringup that we know how much real time has actually
9599          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9600          * variables that haven't been updated yet.
9601          *
9602          * So we simply find the maximum observed TSC above, then record the
9603          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9604          * the adjustment will be applied.  Note that we accumulate
9605          * adjustments, in case multiple suspend cycles happen before some VCPU
9606          * gets a chance to run again.  In the event that no KVM threads get a
9607          * chance to run, we will miss the entire elapsed period, as we'll have
9608          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9609          * loose cycle time.  This isn't too big a deal, since the loss will be
9610          * uniform across all VCPUs (not to mention the scenario is extremely
9611          * unlikely). It is possible that a second hibernate recovery happens
9612          * much faster than a first, causing the observed TSC here to be
9613          * smaller; this would require additional padding adjustment, which is
9614          * why we set last_host_tsc to the local tsc observed here.
9615          *
9616          * N.B. - this code below runs only on platforms with reliable TSC,
9617          * as that is the only way backwards_tsc is set above.  Also note
9618          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9619          * have the same delta_cyc adjustment applied if backwards_tsc
9620          * is detected.  Note further, this adjustment is only done once,
9621          * as we reset last_host_tsc on all VCPUs to stop this from being
9622          * called multiple times (one for each physical CPU bringup).
9623          *
9624          * Platforms with unreliable TSCs don't have to deal with this, they
9625          * will be compensated by the logic in vcpu_load, which sets the TSC to
9626          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9627          * guarantee that they stay in perfect synchronization.
9628          */
9629         if (backwards_tsc) {
9630                 u64 delta_cyc = max_tsc - local_tsc;
9631                 list_for_each_entry(kvm, &vm_list, vm_list) {
9632                         kvm->arch.backwards_tsc_observed = true;
9633                         kvm_for_each_vcpu(i, vcpu, kvm) {
9634                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9635                                 vcpu->arch.last_host_tsc = local_tsc;
9636                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9637                         }
9638
9639                         /*
9640                          * We have to disable TSC offset matching.. if you were
9641                          * booting a VM while issuing an S4 host suspend....
9642                          * you may have some problem.  Solving this issue is
9643                          * left as an exercise to the reader.
9644                          */
9645                         kvm->arch.last_tsc_nsec = 0;
9646                         kvm->arch.last_tsc_write = 0;
9647                 }
9648
9649         }
9650         return 0;
9651 }
9652
9653 void kvm_arch_hardware_disable(void)
9654 {
9655         kvm_x86_ops.hardware_disable();
9656         drop_user_return_notifiers();
9657 }
9658
9659 int kvm_arch_hardware_setup(void *opaque)
9660 {
9661         struct kvm_x86_init_ops *ops = opaque;
9662         int r;
9663
9664         rdmsrl_safe(MSR_EFER, &host_efer);
9665
9666         if (boot_cpu_has(X86_FEATURE_XSAVES))
9667                 rdmsrl(MSR_IA32_XSS, host_xss);
9668
9669         r = ops->hardware_setup();
9670         if (r != 0)
9671                 return r;
9672
9673         memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9674
9675         if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9676                 supported_xss = 0;
9677
9678         cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9679
9680         if (kvm_has_tsc_control) {
9681                 /*
9682                  * Make sure the user can only configure tsc_khz values that
9683                  * fit into a signed integer.
9684                  * A min value is not calculated because it will always
9685                  * be 1 on all machines.
9686                  */
9687                 u64 max = min(0x7fffffffULL,
9688                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9689                 kvm_max_guest_tsc_khz = max;
9690
9691                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9692         }
9693
9694         kvm_init_msr_list();
9695         return 0;
9696 }
9697
9698 void kvm_arch_hardware_unsetup(void)
9699 {
9700         kvm_x86_ops.hardware_unsetup();
9701 }
9702
9703 int kvm_arch_check_processor_compat(void *opaque)
9704 {
9705         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9706         struct kvm_x86_init_ops *ops = opaque;
9707
9708         WARN_ON(!irqs_disabled());
9709
9710         if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9711                 return -EIO;
9712
9713         return ops->check_processor_compatibility();
9714 }
9715
9716 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9717 {
9718         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9719 }
9720 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9721
9722 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9723 {
9724         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9725 }
9726
9727 struct static_key kvm_no_apic_vcpu __read_mostly;
9728 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9729
9730 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9731 {
9732         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9733
9734         vcpu->arch.l1tf_flush_l1d = true;
9735         if (pmu->version && unlikely(pmu->event_count)) {
9736                 pmu->need_cleanup = true;
9737                 kvm_make_request(KVM_REQ_PMU, vcpu);
9738         }
9739         kvm_x86_ops.sched_in(vcpu, cpu);
9740 }
9741
9742 void kvm_arch_free_vm(struct kvm *kvm)
9743 {
9744         kfree(kvm->arch.hyperv.hv_pa_pg);
9745         vfree(kvm);
9746 }
9747
9748
9749 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9750 {
9751         if (type)
9752                 return -EINVAL;
9753
9754         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9755         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9756         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9757         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9758         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9759         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9760
9761         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9762         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9763         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9764         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9765                 &kvm->arch.irq_sources_bitmap);
9766
9767         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9768         mutex_init(&kvm->arch.apic_map_lock);
9769         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9770
9771         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9772         pvclock_update_vm_gtod_copy(kvm);
9773
9774         kvm->arch.guest_can_read_msr_platform_info = true;
9775
9776         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9777         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9778
9779         kvm_hv_init_vm(kvm);
9780         kvm_page_track_init(kvm);
9781         kvm_mmu_init_vm(kvm);
9782
9783         return kvm_x86_ops.vm_init(kvm);
9784 }
9785
9786 int kvm_arch_post_init_vm(struct kvm *kvm)
9787 {
9788         return kvm_mmu_post_init_vm(kvm);
9789 }
9790
9791 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9792 {
9793         vcpu_load(vcpu);
9794         kvm_mmu_unload(vcpu);
9795         vcpu_put(vcpu);
9796 }
9797
9798 static void kvm_free_vcpus(struct kvm *kvm)
9799 {
9800         unsigned int i;
9801         struct kvm_vcpu *vcpu;
9802
9803         /*
9804          * Unpin any mmu pages first.
9805          */
9806         kvm_for_each_vcpu(i, vcpu, kvm) {
9807                 kvm_clear_async_pf_completion_queue(vcpu);
9808                 kvm_unload_vcpu_mmu(vcpu);
9809         }
9810         kvm_for_each_vcpu(i, vcpu, kvm)
9811                 kvm_vcpu_destroy(vcpu);
9812
9813         mutex_lock(&kvm->lock);
9814         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9815                 kvm->vcpus[i] = NULL;
9816
9817         atomic_set(&kvm->online_vcpus, 0);
9818         mutex_unlock(&kvm->lock);
9819 }
9820
9821 void kvm_arch_sync_events(struct kvm *kvm)
9822 {
9823         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9824         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9825         kvm_free_pit(kvm);
9826 }
9827
9828 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9829 {
9830         int i, r;
9831         unsigned long hva, uninitialized_var(old_npages);
9832         struct kvm_memslots *slots = kvm_memslots(kvm);
9833         struct kvm_memory_slot *slot;
9834
9835         /* Called with kvm->slots_lock held.  */
9836         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9837                 return -EINVAL;
9838
9839         slot = id_to_memslot(slots, id);
9840         if (size) {
9841                 if (slot && slot->npages)
9842                         return -EEXIST;
9843
9844                 /*
9845                  * MAP_SHARED to prevent internal slot pages from being moved
9846                  * by fork()/COW.
9847                  */
9848                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9849                               MAP_SHARED | MAP_ANONYMOUS, 0);
9850                 if (IS_ERR((void *)hva))
9851                         return PTR_ERR((void *)hva);
9852         } else {
9853                 if (!slot || !slot->npages)
9854                         return 0;
9855
9856                 /*
9857                  * Stuff a non-canonical value to catch use-after-delete.  This
9858                  * ends up being 0 on 32-bit KVM, but there's no better
9859                  * alternative.
9860                  */
9861                 hva = (unsigned long)(0xdeadull << 48);
9862                 old_npages = slot->npages;
9863         }
9864
9865         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
9866                 struct kvm_userspace_memory_region m;
9867
9868                 m.slot = id | (i << 16);
9869                 m.flags = 0;
9870                 m.guest_phys_addr = gpa;
9871                 m.userspace_addr = hva;
9872                 m.memory_size = size;
9873                 r = __kvm_set_memory_region(kvm, &m);
9874                 if (r < 0)
9875                         return r;
9876         }
9877
9878         if (!size)
9879                 vm_munmap(hva, old_npages * PAGE_SIZE);
9880
9881         return 0;
9882 }
9883 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9884
9885 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9886 {
9887         kvm_mmu_pre_destroy_vm(kvm);
9888 }
9889
9890 void kvm_arch_destroy_vm(struct kvm *kvm)
9891 {
9892         if (current->mm == kvm->mm) {
9893                 /*
9894                  * Free memory regions allocated on behalf of userspace,
9895                  * unless the the memory map has changed due to process exit
9896                  * or fd copying.
9897                  */
9898                 mutex_lock(&kvm->slots_lock);
9899                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9900                                         0, 0);
9901                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9902                                         0, 0);
9903                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9904                 mutex_unlock(&kvm->slots_lock);
9905         }
9906         if (kvm_x86_ops.vm_destroy)
9907                 kvm_x86_ops.vm_destroy(kvm);
9908         kvm_pic_destroy(kvm);
9909         kvm_ioapic_destroy(kvm);
9910         kvm_free_vcpus(kvm);
9911         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
9912         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
9913         kvm_mmu_uninit_vm(kvm);
9914         kvm_page_track_cleanup(kvm);
9915         kvm_hv_destroy_vm(kvm);
9916 }
9917
9918 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
9919 {
9920         int i;
9921
9922         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9923                 kvfree(slot->arch.rmap[i]);
9924                 slot->arch.rmap[i] = NULL;
9925
9926                 if (i == 0)
9927                         continue;
9928
9929                 kvfree(slot->arch.lpage_info[i - 1]);
9930                 slot->arch.lpage_info[i - 1] = NULL;
9931         }
9932
9933         kvm_page_track_free_memslot(slot);
9934 }
9935
9936 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
9937                                       unsigned long npages)
9938 {
9939         int i;
9940
9941         /*
9942          * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
9943          * old arrays will be freed by __kvm_set_memory_region() if installing
9944          * the new memslot is successful.
9945          */
9946         memset(&slot->arch, 0, sizeof(slot->arch));
9947
9948         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9949                 struct kvm_lpage_info *linfo;
9950                 unsigned long ugfn;
9951                 int lpages;
9952                 int level = i + 1;
9953
9954                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9955                                       slot->base_gfn, level) + 1;
9956
9957                 slot->arch.rmap[i] =
9958                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9959                                  GFP_KERNEL_ACCOUNT);
9960                 if (!slot->arch.rmap[i])
9961                         goto out_free;
9962                 if (i == 0)
9963                         continue;
9964
9965                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
9966                 if (!linfo)
9967                         goto out_free;
9968
9969                 slot->arch.lpage_info[i - 1] = linfo;
9970
9971                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
9972                         linfo[0].disallow_lpage = 1;
9973                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
9974                         linfo[lpages - 1].disallow_lpage = 1;
9975                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9976                 /*
9977                  * If the gfn and userspace address are not aligned wrt each
9978                  * other, disable large page support for this slot.
9979                  */
9980                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
9981                         unsigned long j;
9982
9983                         for (j = 0; j < lpages; ++j)
9984                                 linfo[j].disallow_lpage = 1;
9985                 }
9986         }
9987
9988         if (kvm_page_track_create_memslot(slot, npages))
9989                 goto out_free;
9990
9991         return 0;
9992
9993 out_free:
9994         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9995                 kvfree(slot->arch.rmap[i]);
9996                 slot->arch.rmap[i] = NULL;
9997                 if (i == 0)
9998                         continue;
9999
10000                 kvfree(slot->arch.lpage_info[i - 1]);
10001                 slot->arch.lpage_info[i - 1] = NULL;
10002         }
10003         return -ENOMEM;
10004 }
10005
10006 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10007 {
10008         struct kvm_vcpu *vcpu;
10009         int i;
10010
10011         /*
10012          * memslots->generation has been incremented.
10013          * mmio generation may have reached its maximum value.
10014          */
10015         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10016
10017         /* Force re-initialization of steal_time cache */
10018         kvm_for_each_vcpu(i, vcpu, kvm)
10019                 kvm_vcpu_kick(vcpu);
10020 }
10021
10022 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10023                                 struct kvm_memory_slot *memslot,
10024                                 const struct kvm_userspace_memory_region *mem,
10025                                 enum kvm_mr_change change)
10026 {
10027         if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10028                 return kvm_alloc_memslot_metadata(memslot,
10029                                                   mem->memory_size >> PAGE_SHIFT);
10030         return 0;
10031 }
10032
10033 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10034                                      struct kvm_memory_slot *new)
10035 {
10036         /* Still write protect RO slot */
10037         if (new->flags & KVM_MEM_READONLY) {
10038                 kvm_mmu_slot_remove_write_access(kvm, new, PT_PAGE_TABLE_LEVEL);
10039                 return;
10040         }
10041
10042         /*
10043          * Call kvm_x86_ops dirty logging hooks when they are valid.
10044          *
10045          * kvm_x86_ops.slot_disable_log_dirty is called when:
10046          *
10047          *  - KVM_MR_CREATE with dirty logging is disabled
10048          *  - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
10049          *
10050          * The reason is, in case of PML, we need to set D-bit for any slots
10051          * with dirty logging disabled in order to eliminate unnecessary GPA
10052          * logging in PML buffer (and potential PML buffer full VMEXIT). This
10053          * guarantees leaving PML enabled during guest's lifetime won't have
10054          * any additional overhead from PML when guest is running with dirty
10055          * logging disabled for memory slots.
10056          *
10057          * kvm_x86_ops.slot_enable_log_dirty is called when switching new slot
10058          * to dirty logging mode.
10059          *
10060          * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
10061          *
10062          * In case of write protect:
10063          *
10064          * Write protect all pages for dirty logging.
10065          *
10066          * All the sptes including the large sptes which point to this
10067          * slot are set to readonly. We can not create any new large
10068          * spte on this slot until the end of the logging.
10069          *
10070          * See the comments in fast_page_fault().
10071          */
10072         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10073                 if (kvm_x86_ops.slot_enable_log_dirty) {
10074                         kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10075                 } else {
10076                         int level =
10077                                 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10078                                 PT_DIRECTORY_LEVEL : PT_PAGE_TABLE_LEVEL;
10079
10080                         /*
10081                          * If we're with initial-all-set, we don't need
10082                          * to write protect any small page because
10083                          * they're reported as dirty already.  However
10084                          * we still need to write-protect huge pages
10085                          * so that the page split can happen lazily on
10086                          * the first write to the huge page.
10087                          */
10088                         kvm_mmu_slot_remove_write_access(kvm, new, level);
10089                 }
10090         } else {
10091                 if (kvm_x86_ops.slot_disable_log_dirty)
10092                         kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10093         }
10094 }
10095
10096 void kvm_arch_commit_memory_region(struct kvm *kvm,
10097                                 const struct kvm_userspace_memory_region *mem,
10098                                 struct kvm_memory_slot *old,
10099                                 const struct kvm_memory_slot *new,
10100                                 enum kvm_mr_change change)
10101 {
10102         if (!kvm->arch.n_requested_mmu_pages)
10103                 kvm_mmu_change_mmu_pages(kvm,
10104                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10105
10106         /*
10107          * Dirty logging tracks sptes in 4k granularity, meaning that large
10108          * sptes have to be split.  If live migration is successful, the guest
10109          * in the source machine will be destroyed and large sptes will be
10110          * created in the destination. However, if the guest continues to run
10111          * in the source machine (for example if live migration fails), small
10112          * sptes will remain around and cause bad performance.
10113          *
10114          * Scan sptes if dirty logging has been stopped, dropping those
10115          * which can be collapsed into a single large-page spte.  Later
10116          * page faults will create the large-page sptes.
10117          *
10118          * There is no need to do this in any of the following cases:
10119          * CREATE:      No dirty mappings will already exist.
10120          * MOVE/DELETE: The old mappings will already have been cleaned up by
10121          *              kvm_arch_flush_shadow_memslot()
10122          */
10123         if (change == KVM_MR_FLAGS_ONLY &&
10124                 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10125                 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10126                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10127
10128         /*
10129          * Set up write protection and/or dirty logging for the new slot.
10130          *
10131          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
10132          * been zapped so no dirty logging staff is needed for old slot. For
10133          * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
10134          * new and it's also covered when dealing with the new slot.
10135          *
10136          * FIXME: const-ify all uses of struct kvm_memory_slot.
10137          */
10138         if (change != KVM_MR_DELETE)
10139                 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
10140
10141         /* Free the arrays associated with the old memslot. */
10142         if (change == KVM_MR_MOVE)
10143                 kvm_arch_free_memslot(kvm, old);
10144 }
10145
10146 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10147 {
10148         kvm_mmu_zap_all(kvm);
10149 }
10150
10151 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10152                                    struct kvm_memory_slot *slot)
10153 {
10154         kvm_page_track_flush_slot(kvm, slot);
10155 }
10156
10157 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10158 {
10159         return (is_guest_mode(vcpu) &&
10160                         kvm_x86_ops.guest_apic_has_interrupt &&
10161                         kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10162 }
10163
10164 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10165 {
10166         if (!list_empty_careful(&vcpu->async_pf.done))
10167                 return true;
10168
10169         if (kvm_apic_has_events(vcpu))
10170                 return true;
10171
10172         if (vcpu->arch.pv.pv_unhalted)
10173                 return true;
10174
10175         if (vcpu->arch.exception.pending)
10176                 return true;
10177
10178         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10179             (vcpu->arch.nmi_pending &&
10180              kvm_x86_ops.nmi_allowed(vcpu)))
10181                 return true;
10182
10183         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10184             (vcpu->arch.smi_pending && !is_smm(vcpu)))
10185                 return true;
10186
10187         if (kvm_arch_interrupt_allowed(vcpu) &&
10188             (kvm_cpu_has_interrupt(vcpu) ||
10189             kvm_guest_apic_has_interrupt(vcpu)))
10190                 return true;
10191
10192         if (kvm_hv_has_stimer_pending(vcpu))
10193                 return true;
10194
10195         return false;
10196 }
10197
10198 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10199 {
10200         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10201 }
10202
10203 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10204 {
10205         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10206                 return true;
10207
10208         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10209                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10210                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10211                 return true;
10212
10213         if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10214                 return true;
10215
10216         return false;
10217 }
10218
10219 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10220 {
10221         return vcpu->arch.preempted_in_kernel;
10222 }
10223
10224 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10225 {
10226         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10227 }
10228
10229 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10230 {
10231         return kvm_x86_ops.interrupt_allowed(vcpu);
10232 }
10233
10234 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10235 {
10236         if (is_64_bit_mode(vcpu))
10237                 return kvm_rip_read(vcpu);
10238         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10239                      kvm_rip_read(vcpu));
10240 }
10241 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10242
10243 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10244 {
10245         return kvm_get_linear_rip(vcpu) == linear_rip;
10246 }
10247 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10248
10249 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10250 {
10251         unsigned long rflags;
10252
10253         rflags = kvm_x86_ops.get_rflags(vcpu);
10254         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10255                 rflags &= ~X86_EFLAGS_TF;
10256         return rflags;
10257 }
10258 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10259
10260 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10261 {
10262         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10263             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10264                 rflags |= X86_EFLAGS_TF;
10265         kvm_x86_ops.set_rflags(vcpu, rflags);
10266 }
10267
10268 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10269 {
10270         __kvm_set_rflags(vcpu, rflags);
10271         kvm_make_request(KVM_REQ_EVENT, vcpu);
10272 }
10273 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10274
10275 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10276 {
10277         int r;
10278
10279         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10280               work->wakeup_all)
10281                 return;
10282
10283         r = kvm_mmu_reload(vcpu);
10284         if (unlikely(r))
10285                 return;
10286
10287         if (!vcpu->arch.mmu->direct_map &&
10288               work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10289                 return;
10290
10291         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10292 }
10293
10294 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10295 {
10296         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10297 }
10298
10299 static inline u32 kvm_async_pf_next_probe(u32 key)
10300 {
10301         return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10302 }
10303
10304 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10305 {
10306         u32 key = kvm_async_pf_hash_fn(gfn);
10307
10308         while (vcpu->arch.apf.gfns[key] != ~0)
10309                 key = kvm_async_pf_next_probe(key);
10310
10311         vcpu->arch.apf.gfns[key] = gfn;
10312 }
10313
10314 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10315 {
10316         int i;
10317         u32 key = kvm_async_pf_hash_fn(gfn);
10318
10319         for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
10320                      (vcpu->arch.apf.gfns[key] != gfn &&
10321                       vcpu->arch.apf.gfns[key] != ~0); i++)
10322                 key = kvm_async_pf_next_probe(key);
10323
10324         return key;
10325 }
10326
10327 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10328 {
10329         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10330 }
10331
10332 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10333 {
10334         u32 i, j, k;
10335
10336         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10337         while (true) {
10338                 vcpu->arch.apf.gfns[i] = ~0;
10339                 do {
10340                         j = kvm_async_pf_next_probe(j);
10341                         if (vcpu->arch.apf.gfns[j] == ~0)
10342                                 return;
10343                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10344                         /*
10345                          * k lies cyclically in ]i,j]
10346                          * |    i.k.j |
10347                          * |....j i.k.| or  |.k..j i...|
10348                          */
10349                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10350                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10351                 i = j;
10352         }
10353 }
10354
10355 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10356 {
10357
10358         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10359                                       sizeof(val));
10360 }
10361
10362 static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10363 {
10364
10365         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10366                                       sizeof(u32));
10367 }
10368
10369 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10370 {
10371         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10372                 return false;
10373
10374         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10375             (vcpu->arch.apf.send_user_only &&
10376              kvm_x86_ops.get_cpl(vcpu) == 0))
10377                 return false;
10378
10379         return true;
10380 }
10381
10382 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10383 {
10384         if (unlikely(!lapic_in_kernel(vcpu) ||
10385                      kvm_event_needs_reinjection(vcpu) ||
10386                      vcpu->arch.exception.pending))
10387                 return false;
10388
10389         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10390                 return false;
10391
10392         /*
10393          * If interrupts are off we cannot even use an artificial
10394          * halt state.
10395          */
10396         return kvm_x86_ops.interrupt_allowed(vcpu);
10397 }
10398
10399 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10400                                      struct kvm_async_pf *work)
10401 {
10402         struct x86_exception fault;
10403
10404         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10405         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10406
10407         if (kvm_can_deliver_async_pf(vcpu) &&
10408             !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
10409                 fault.vector = PF_VECTOR;
10410                 fault.error_code_valid = true;
10411                 fault.error_code = 0;
10412                 fault.nested_page_fault = false;
10413                 fault.address = work->arch.token;
10414                 fault.async_page_fault = true;
10415                 kvm_inject_page_fault(vcpu, &fault);
10416         } else {
10417                 /*
10418                  * It is not possible to deliver a paravirtualized asynchronous
10419                  * page fault, but putting the guest in an artificial halt state
10420                  * can be beneficial nevertheless: if an interrupt arrives, we
10421                  * can deliver it timely and perhaps the guest will schedule
10422                  * another process.  When the instruction that triggered a page
10423                  * fault is retried, hopefully the page will be ready in the host.
10424                  */
10425                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10426         }
10427 }
10428
10429 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10430                                  struct kvm_async_pf *work)
10431 {
10432         struct x86_exception fault;
10433         u32 val;
10434
10435         if (work->wakeup_all)
10436                 work->arch.token = ~0; /* broadcast wakeup */
10437         else
10438                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10439         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10440
10441         if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10442             !apf_get_user(vcpu, &val)) {
10443                 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10444                     vcpu->arch.exception.pending &&
10445                     vcpu->arch.exception.nr == PF_VECTOR &&
10446                     !apf_put_user(vcpu, 0)) {
10447                         vcpu->arch.exception.injected = false;
10448                         vcpu->arch.exception.pending = false;
10449                         vcpu->arch.exception.nr = 0;
10450                         vcpu->arch.exception.has_error_code = false;
10451                         vcpu->arch.exception.error_code = 0;
10452                         vcpu->arch.exception.has_payload = false;
10453                         vcpu->arch.exception.payload = 0;
10454                 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10455                         fault.vector = PF_VECTOR;
10456                         fault.error_code_valid = true;
10457                         fault.error_code = 0;
10458                         fault.nested_page_fault = false;
10459                         fault.address = work->arch.token;
10460                         fault.async_page_fault = true;
10461                         kvm_inject_page_fault(vcpu, &fault);
10462                 }
10463         }
10464         vcpu->arch.apf.halted = false;
10465         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10466 }
10467
10468 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10469 {
10470         if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10471                 return true;
10472         else
10473                 return kvm_can_do_async_pf(vcpu);
10474 }
10475
10476 void kvm_arch_start_assignment(struct kvm *kvm)
10477 {
10478         atomic_inc(&kvm->arch.assigned_device_count);
10479 }
10480 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10481
10482 void kvm_arch_end_assignment(struct kvm *kvm)
10483 {
10484         atomic_dec(&kvm->arch.assigned_device_count);
10485 }
10486 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10487
10488 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10489 {
10490         return atomic_read(&kvm->arch.assigned_device_count);
10491 }
10492 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10493
10494 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10495 {
10496         atomic_inc(&kvm->arch.noncoherent_dma_count);
10497 }
10498 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10499
10500 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10501 {
10502         atomic_dec(&kvm->arch.noncoherent_dma_count);
10503 }
10504 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10505
10506 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10507 {
10508         return atomic_read(&kvm->arch.noncoherent_dma_count);
10509 }
10510 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10511
10512 bool kvm_arch_has_irq_bypass(void)
10513 {
10514         return true;
10515 }
10516
10517 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10518                                       struct irq_bypass_producer *prod)
10519 {
10520         struct kvm_kernel_irqfd *irqfd =
10521                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10522
10523         irqfd->producer = prod;
10524
10525         return kvm_x86_ops.update_pi_irte(irqfd->kvm,
10526                                            prod->irq, irqfd->gsi, 1);
10527 }
10528
10529 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10530                                       struct irq_bypass_producer *prod)
10531 {
10532         int ret;
10533         struct kvm_kernel_irqfd *irqfd =
10534                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10535
10536         WARN_ON(irqfd->producer != prod);
10537         irqfd->producer = NULL;
10538
10539         /*
10540          * When producer of consumer is unregistered, we change back to
10541          * remapped mode, so we can re-use the current implementation
10542          * when the irq is masked/disabled or the consumer side (KVM
10543          * int this case doesn't want to receive the interrupts.
10544         */
10545         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10546         if (ret)
10547                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10548                        " fails: %d\n", irqfd->consumer.token, ret);
10549 }
10550
10551 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10552                                    uint32_t guest_irq, bool set)
10553 {
10554         return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10555 }
10556
10557 bool kvm_vector_hashing_enabled(void)
10558 {
10559         return vector_hashing;
10560 }
10561
10562 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10563 {
10564         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10565 }
10566 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10567
10568 u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10569 {
10570         uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10571
10572         /* The STIBP bit doesn't fault even if it's not advertised */
10573         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10574             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10575                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10576         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10577             !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10578                 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10579
10580         if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10581             !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10582                 bits &= ~SPEC_CTRL_SSBD;
10583         if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10584             !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10585                 bits &= ~SPEC_CTRL_SSBD;
10586
10587         return bits;
10588 }
10589 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
10590
10591 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10592 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10593 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10594 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10595 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10596 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10597 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10598 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10599 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10600 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10601 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10602 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10603 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10604 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10605 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10606 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10607 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10608 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10609 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10610 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10611 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10612 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);