arch/x86/kvm/x86.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * derived from drivers/kvm/kvm_main.c
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright (C) 2008 Qumranet, Inc.
   9  * Copyright IBM Corporation, 2008
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Amit Shah    <amit.shah@qumranet.com>
  16  *   Ben-Ami Yassour <benami@il.ibm.com>
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include "irq.h"
  21 #include "ioapic.h"
  22 #include "mmu.h"
  23 #include "i8254.h"
  24 #include "tss.h"
  25 #include "kvm_cache_regs.h"
  26 #include "kvm_emulate.h"
  27 #include "x86.h"
  28 #include "cpuid.h"
  29 #include "pmu.h"
  30 #include "hyperv.h"
  31 #include "lapic.h"
  32
  33 #include <linux/clocksource.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/kvm.h>
  36 #include <linux/fs.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/export.h>
  39 #include <linux/moduleparam.h>
  40 #include <linux/mman.h>
  41 #include <linux/highmem.h>
  42 #include <linux/iommu.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/cpufreq.h>
  45 #include <linux/user-return-notifier.h>
  46 #include <linux/srcu.h>
  47 #include <linux/slab.h>
  48 #include <linux/perf_event.h>
  49 #include <linux/uaccess.h>
  50 #include <linux/hash.h>
  51 #include <linux/pci.h>
  52 #include <linux/timekeeper_internal.h>
  53 #include <linux/pvclock_gtod.h>
  54 #include <linux/kvm_irqfd.h>
  55 #include <linux/irqbypass.h>
  56 #include <linux/sched/stat.h>
  57 #include <linux/sched/isolation.h>
  58 #include <linux/mem_encrypt.h>
  59 #include <linux/entry-kvm.h>
  60
  61 #include <trace/events/kvm.h>
  62
  63 #include <asm/debugreg.h>
  64 #include <asm/msr.h>
  65 #include <asm/desc.h>
  66 #include <asm/mce.h>
  67 #include <linux/kernel_stat.h>
  68 #include <asm/fpu/internal.h> /* Ugh! */
  69 #include <asm/pvclock.h>
  70 #include <asm/div64.h>
  71 #include <asm/irq_remapping.h>
  72 #include <asm/mshyperv.h>
  73 #include <asm/hypervisor.h>
  74 #include <asm/intel_pt.h>
  75 #include <asm/emulate_prefix.h>
  76 #include <clocksource/hyperv_timer.h>
  77
  78 #define CREATE_TRACE_POINTS
  79 #include "trace.h"
  80
  81 #define MAX_IO_MSRS 256
  82 #define KVM_MAX_MCE_BANKS 32
  83 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
  84 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
  85
  86 #define emul_to_vcpu(ctxt) \
  87         ((struct kvm_vcpu *)(ctxt)->vcpu)
  88
  89 /* EFER defaults:
  90  * - enable syscall per default because its emulated by KVM
  91  * - enable LME and LMA per default on 64 bit KVM
  92  */
  93 #ifdef CONFIG_X86_64
  94 static
  95 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
  96 #else
  97 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
  98 #endif
  99
 100 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
 101
 102 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
 103                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
 104
 105 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 106 static void process_nmi(struct kvm_vcpu *vcpu);
 107 static void enter_smm(struct kvm_vcpu *vcpu);
 108 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 109 static void store_regs(struct kvm_vcpu *vcpu);
 110 static int sync_regs(struct kvm_vcpu *vcpu);
 111
 112 struct kvm_x86_ops kvm_x86_ops __read_mostly;
 113 EXPORT_SYMBOL_GPL(kvm_x86_ops);
 114
 115 static bool __read_mostly ignore_msrs = 0;
 116 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
 117
 118 static bool __read_mostly report_ignored_msrs = true;
 119 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
 120
 121 unsigned int min_timer_period_us = 200;
 122 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
 123
 124 static bool __read_mostly kvmclock_periodic_sync = true;
 125 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
 126
 127 bool __read_mostly kvm_has_tsc_control;
 128 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
 129 u32  __read_mostly kvm_max_guest_tsc_khz;
 130 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
 131 u8   __read_mostly kvm_tsc_scaling_ratio_frac_bits;
 132 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
 133 u64  __read_mostly kvm_max_tsc_scaling_ratio;
 134 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
 135 u64 __read_mostly kvm_default_tsc_scaling_ratio;
 136 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
 137
 138 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
 139 static u32 __read_mostly tsc_tolerance_ppm = 250;
 140 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
 141
 142 /*
 143  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
 144  * adaptive tuning starting from default advancment of 1000ns.  '0' disables
 145  * advancement entirely.  Any other value is used as-is and disables adaptive
 146  * tuning, i.e. allows priveleged userspace to set an exact advancement time.
 147  */
 148 static int __read_mostly lapic_timer_advance_ns = -1;
 149 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
 150
 151 static bool __read_mostly vector_hashing = true;
 152 module_param(vector_hashing, bool, S_IRUGO);
 153
 154 bool __read_mostly enable_vmware_backdoor = false;
 155 module_param(enable_vmware_backdoor, bool, S_IRUGO);
 156 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
 157
 158 static bool __read_mostly force_emulation_prefix = false;
 159 module_param(force_emulation_prefix, bool, S_IRUGO);
 160
 161 int __read_mostly pi_inject_timer = -1;
 162 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
 163
 164 #define KVM_NR_SHARED_MSRS 16
 165
 166 struct kvm_shared_msrs_global {
 167         int nr;
 168         u32 msrs[KVM_NR_SHARED_MSRS];
 169 };
 170
 171 struct kvm_shared_msrs {
 172         struct user_return_notifier urn;
 173         bool registered;
 174         struct kvm_shared_msr_values {
 175                 u64 host;
 176                 u64 curr;
 177         } values[KVM_NR_SHARED_MSRS];
 178 };
 179
 180 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
 181 static struct kvm_shared_msrs __percpu *shared_msrs;
 182
 183 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
 184                                 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
 185                                 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
 186                                 | XFEATURE_MASK_PKRU)
 187
 188 u64 __read_mostly host_efer;
 189 EXPORT_SYMBOL_GPL(host_efer);
 190
 191 bool __read_mostly allow_smaller_maxphyaddr;
 192 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
 193
 194 static u64 __read_mostly host_xss;
 195 u64 __read_mostly supported_xss;
 196 EXPORT_SYMBOL_GPL(supported_xss);
 197
 198 struct kvm_stats_debugfs_item debugfs_entries[] = {
 199         VCPU_STAT("pf_fixed", pf_fixed),
 200         VCPU_STAT("pf_guest", pf_guest),
 201         VCPU_STAT("tlb_flush", tlb_flush),
 202         VCPU_STAT("invlpg", invlpg),
 203         VCPU_STAT("exits", exits),
 204         VCPU_STAT("io_exits", io_exits),
 205         VCPU_STAT("mmio_exits", mmio_exits),
 206         VCPU_STAT("signal_exits", signal_exits),
 207         VCPU_STAT("irq_window", irq_window_exits),
 208         VCPU_STAT("nmi_window", nmi_window_exits),
 209         VCPU_STAT("halt_exits", halt_exits),
 210         VCPU_STAT("halt_successful_poll", halt_successful_poll),
 211         VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
 212         VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
 213         VCPU_STAT("halt_wakeup", halt_wakeup),
 214         VCPU_STAT("hypercalls", hypercalls),
 215         VCPU_STAT("request_irq", request_irq_exits),
 216         VCPU_STAT("irq_exits", irq_exits),
 217         VCPU_STAT("host_state_reload", host_state_reload),
 218         VCPU_STAT("fpu_reload", fpu_reload),
 219         VCPU_STAT("insn_emulation", insn_emulation),
 220         VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
 221         VCPU_STAT("irq_injections", irq_injections),
 222         VCPU_STAT("nmi_injections", nmi_injections),
 223         VCPU_STAT("req_event", req_event),
 224         VCPU_STAT("l1d_flush", l1d_flush),
 225         VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
 226         VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
 227         VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
 228         VM_STAT("mmu_pte_write", mmu_pte_write),
 229         VM_STAT("mmu_pte_updated", mmu_pte_updated),
 230         VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
 231         VM_STAT("mmu_flooded", mmu_flooded),
 232         VM_STAT("mmu_recycled", mmu_recycled),
 233         VM_STAT("mmu_cache_miss", mmu_cache_miss),
 234         VM_STAT("mmu_unsync", mmu_unsync),
 235         VM_STAT("remote_tlb_flush", remote_tlb_flush),
 236         VM_STAT("largepages", lpages, .mode = 0444),
 237         VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
 238         VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
 239         { NULL }
 240 };
 241
 242 u64 __read_mostly host_xcr0;
 243 u64 __read_mostly supported_xcr0;
 244 EXPORT_SYMBOL_GPL(supported_xcr0);
 245
 246 static struct kmem_cache *x86_fpu_cache;
 247
 248 static struct kmem_cache *x86_emulator_cache;
 249
 250 /*
 251  * When called, it means the previous get/set msr reached an invalid msr.
 252  * Return 0 if we want to ignore/silent this failed msr access, or 1 if we want
 253  * to fail the caller.
 254  */
 255 static int kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
 256                                  u64 data, bool write)
 257 {
 258         const char *op = write ? "wrmsr" : "rdmsr";
 259
 260         if (ignore_msrs) {
 261                 if (report_ignored_msrs)
 262                         vcpu_unimpl(vcpu, "ignored %s: 0x%x data 0x%llx\n",
 263                                     op, msr, data);
 264                 /* Mask the error */
 265                 return 0;
 266         } else {
 267                 vcpu_debug_ratelimited(vcpu, "unhandled %s: 0x%x data 0x%llx\n",
 268                                        op, msr, data);
 269                 return 1;
 270         }
 271 }
 272
 273 static struct kmem_cache *kvm_alloc_emulator_cache(void)
 274 {
 275         unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
 276         unsigned int size = sizeof(struct x86_emulate_ctxt);
 277
 278         return kmem_cache_create_usercopy("x86_emulator", size,
 279                                           __alignof__(struct x86_emulate_ctxt),
 280                                           SLAB_ACCOUNT, useroffset,
 281                                           size - useroffset, NULL);
 282 }
 283
 284 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 285
 286 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 287 {
 288         int i;
 289         for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
 290                 vcpu->arch.apf.gfns[i] = ~0;
 291 }
 292
 293 static void kvm_on_user_return(struct user_return_notifier *urn)
 294 {
 295         unsigned slot;
 296         struct kvm_shared_msrs *locals
 297                 = container_of(urn, struct kvm_shared_msrs, urn);
 298         struct kvm_shared_msr_values *values;
 299         unsigned long flags;
 300
 301         /*
 302          * Disabling irqs at this point since the following code could be
 303          * interrupted and executed through kvm_arch_hardware_disable()
 304          */
 305         local_irq_save(flags);
 306         if (locals->registered) {
 307                 locals->registered = false;
 308                 user_return_notifier_unregister(urn);
 309         }
 310         local_irq_restore(flags);
 311         for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
 312                 values = &locals->values[slot];
 313                 if (values->host != values->curr) {
 314                         wrmsrl(shared_msrs_global.msrs[slot], values->host);
 315                         values->curr = values->host;
 316                 }
 317         }
 318 }
 319
 320 void kvm_define_shared_msr(unsigned slot, u32 msr)
 321 {
 322         BUG_ON(slot >= KVM_NR_SHARED_MSRS);
 323         shared_msrs_global.msrs[slot] = msr;
 324         if (slot >= shared_msrs_global.nr)
 325                 shared_msrs_global.nr = slot + 1;
 326 }
 327 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
 328
 329 static void kvm_shared_msr_cpu_online(void)
 330 {
 331         unsigned int cpu = smp_processor_id();
 332         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 333         u64 value;
 334         int i;
 335
 336         for (i = 0; i < shared_msrs_global.nr; ++i) {
 337                 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
 338                 smsr->values[i].host = value;
 339                 smsr->values[i].curr = value;
 340         }
 341 }
 342
 343 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
 344 {
 345         unsigned int cpu = smp_processor_id();
 346         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 347         int err;
 348
 349         value = (value & mask) | (smsr->values[slot].host & ~mask);
 350         if (value == smsr->values[slot].curr)
 351                 return 0;
 352         err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
 353         if (err)
 354                 return 1;
 355
 356         smsr->values[slot].curr = value;
 357         if (!smsr->registered) {
 358                 smsr->urn.on_user_return = kvm_on_user_return;
 359                 user_return_notifier_register(&smsr->urn);
 360                 smsr->registered = true;
 361         }
 362         return 0;
 363 }
 364 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
 365
 366 static void drop_user_return_notifiers(void)
 367 {
 368         unsigned int cpu = smp_processor_id();
 369         struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
 370
 371         if (smsr->registered)
 372                 kvm_on_user_return(&smsr->urn);
 373 }
 374
 375 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
 376 {
 377         return vcpu->arch.apic_base;
 378 }
 379 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
 380
 381 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
 382 {
 383         return kvm_apic_mode(kvm_get_apic_base(vcpu));
 384 }
 385 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
 386
 387 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 388 {
 389         enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
 390         enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
 391         u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
 392                 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
 393
 394         if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
 395                 return 1;
 396         if (!msr_info->host_initiated) {
 397                 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
 398                         return 1;
 399                 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
 400                         return 1;
 401         }
 402
 403         kvm_lapic_set_base(vcpu, msr_info->data);
 404         kvm_recalculate_apic_map(vcpu->kvm);
 405         return 0;
 406 }
 407 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 408
 409 asmlinkage __visible noinstr void kvm_spurious_fault(void)
 410 {
 411         /* Fault while not rebooting.  We want the trace. */
 412         BUG_ON(!kvm_rebooting);
 413 }
 414 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
 415
 416 #define EXCPT_BENIGN            0
 417 #define EXCPT_CONTRIBUTORY      1
 418 #define EXCPT_PF                2
 419
 420 static int exception_class(int vector)
 421 {
 422         switch (vector) {
 423         case PF_VECTOR:
 424                 return EXCPT_PF;
 425         case DE_VECTOR:
 426         case TS_VECTOR:
 427         case NP_VECTOR:
 428         case SS_VECTOR:
 429         case GP_VECTOR:
 430                 return EXCPT_CONTRIBUTORY;
 431         default:
 432                 break;
 433         }
 434         return EXCPT_BENIGN;
 435 }
 436
 437 #define EXCPT_FAULT             0
 438 #define EXCPT_TRAP              1
 439 #define EXCPT_ABORT             2
 440 #define EXCPT_INTERRUPT         3
 441
 442 static int exception_type(int vector)
 443 {
 444         unsigned int mask;
 445
 446         if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
 447                 return EXCPT_INTERRUPT;
 448
 449         mask = 1 << vector;
 450
 451         /* #DB is trap, as instruction watchpoints are handled elsewhere */
 452         if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
 453                 return EXCPT_TRAP;
 454
 455         if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
 456                 return EXCPT_ABORT;
 457
 458         /* Reserved exceptions will result in fault */
 459         return EXCPT_FAULT;
 460 }
 461
 462 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
 463 {
 464         unsigned nr = vcpu->arch.exception.nr;
 465         bool has_payload = vcpu->arch.exception.has_payload;
 466         unsigned long payload = vcpu->arch.exception.payload;
 467
 468         if (!has_payload)
 469                 return;
 470
 471         switch (nr) {
 472         case DB_VECTOR:
 473                 /*
 474                  * "Certain debug exceptions may clear bit 0-3.  The
 475                  * remaining contents of the DR6 register are never
 476                  * cleared by the processor".
 477                  */
 478                 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
 479                 /*
 480                  * DR6.RTM is set by all #DB exceptions that don't clear it.
 481                  */
 482                 vcpu->arch.dr6 |= DR6_RTM;
 483                 vcpu->arch.dr6 |= payload;
 484                 /*
 485                  * Bit 16 should be set in the payload whenever the #DB
 486                  * exception should clear DR6.RTM. This makes the payload
 487                  * compatible with the pending debug exceptions under VMX.
 488                  * Though not currently documented in the SDM, this also
 489                  * makes the payload compatible with the exit qualification
 490                  * for #DB exceptions under VMX.
 491                  */
 492                 vcpu->arch.dr6 ^= payload & DR6_RTM;
 493
 494                 /*
 495                  * The #DB payload is defined as compatible with the 'pending
 496                  * debug exceptions' field under VMX, not DR6. While bit 12 is
 497                  * defined in the 'pending debug exceptions' field (enabled
 498                  * breakpoint), it is reserved and must be zero in DR6.
 499                  */
 500                 vcpu->arch.dr6 &= ~BIT(12);
 501                 break;
 502         case PF_VECTOR:
 503                 vcpu->arch.cr2 = payload;
 504                 break;
 505         }
 506
 507         vcpu->arch.exception.has_payload = false;
 508         vcpu->arch.exception.payload = 0;
 509 }
 510 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
 511
 512 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
 513                 unsigned nr, bool has_error, u32 error_code,
 514                 bool has_payload, unsigned long payload, bool reinject)
 515 {
 516         u32 prev_nr;
 517         int class1, class2;
 518
 519         kvm_make_request(KVM_REQ_EVENT, vcpu);
 520
 521         if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
 522         queue:
 523                 if (has_error && !is_protmode(vcpu))
 524                         has_error = false;
 525                 if (reinject) {
 526                         /*
 527                          * On vmentry, vcpu->arch.exception.pending is only
 528                          * true if an event injection was blocked by
 529                          * nested_run_pending.  In that case, however,
 530                          * vcpu_enter_guest requests an immediate exit,
 531                          * and the guest shouldn't proceed far enough to
 532                          * need reinjection.
 533                          */
 534                         WARN_ON_ONCE(vcpu->arch.exception.pending);
 535                         vcpu->arch.exception.injected = true;
 536                         if (WARN_ON_ONCE(has_payload)) {
 537                                 /*
 538                                  * A reinjected event has already
 539                                  * delivered its payload.
 540                                  */
 541                                 has_payload = false;
 542                                 payload = 0;
 543                         }
 544                 } else {
 545                         vcpu->arch.exception.pending = true;
 546                         vcpu->arch.exception.injected = false;
 547                 }
 548                 vcpu->arch.exception.has_error_code = has_error;
 549                 vcpu->arch.exception.nr = nr;
 550                 vcpu->arch.exception.error_code = error_code;
 551                 vcpu->arch.exception.has_payload = has_payload;
 552                 vcpu->arch.exception.payload = payload;
 553                 if (!is_guest_mode(vcpu))
 554                         kvm_deliver_exception_payload(vcpu);
 555                 return;
 556         }
 557
 558         /* to check exception */
 559         prev_nr = vcpu->arch.exception.nr;
 560         if (prev_nr == DF_VECTOR) {
 561                 /* triple fault -> shutdown */
 562                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
 563                 return;
 564         }
 565         class1 = exception_class(prev_nr);
 566         class2 = exception_class(nr);
 567         if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
 568                 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
 569                 /*
 570                  * Generate double fault per SDM Table 5-5.  Set
 571                  * exception.pending = true so that the double fault
 572                  * can trigger a nested vmexit.
 573                  */
 574                 vcpu->arch.exception.pending = true;
 575                 vcpu->arch.exception.injected = false;
 576                 vcpu->arch.exception.has_error_code = true;
 577                 vcpu->arch.exception.nr = DF_VECTOR;
 578                 vcpu->arch.exception.error_code = 0;
 579                 vcpu->arch.exception.has_payload = false;
 580                 vcpu->arch.exception.payload = 0;
 581         } else
 582                 /* replace previous exception with a new one in a hope
 583                    that instruction re-execution will regenerate lost
 584                    exception */
 585                 goto queue;
 586 }
 587
 588 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 589 {
 590         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
 591 }
 592 EXPORT_SYMBOL_GPL(kvm_queue_exception);
 593
 594 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
 595 {
 596         kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
 597 }
 598 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
 599
 600 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
 601                            unsigned long payload)
 602 {
 603         kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
 604 }
 605 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
 606
 607 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
 608                                     u32 error_code, unsigned long payload)
 609 {
 610         kvm_multiple_exception(vcpu, nr, true, error_code,
 611                                true, payload, false);
 612 }
 613
 614 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
 615 {
 616         if (err)
 617                 kvm_inject_gp(vcpu, 0);
 618         else
 619                 return kvm_skip_emulated_instruction(vcpu);
 620
 621         return 1;
 622 }
 623 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
 624
 625 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
 626 {
 627         ++vcpu->stat.pf_guest;
 628         vcpu->arch.exception.nested_apf =
 629                 is_guest_mode(vcpu) && fault->async_page_fault;
 630         if (vcpu->arch.exception.nested_apf) {
 631                 vcpu->arch.apf.nested_apf_token = fault->address;
 632                 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
 633         } else {
 634                 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
 635                                         fault->address);
 636         }
 637 }
 638 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
 639
 640 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
 641                                     struct x86_exception *fault)
 642 {
 643         struct kvm_mmu *fault_mmu;
 644         WARN_ON_ONCE(fault->vector != PF_VECTOR);
 645
 646         fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
 647                                                vcpu->arch.walk_mmu;
 648
 649         /*
 650          * Invalidate the TLB entry for the faulting address, if it exists,
 651          * else the access will fault indefinitely (and to emulate hardware).
 652          */
 653         if ((fault->error_code & PFERR_PRESENT_MASK) &&
 654             !(fault->error_code & PFERR_RSVD_MASK))
 655                 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
 656                                        fault_mmu->root_hpa);
 657
 658         fault_mmu->inject_page_fault(vcpu, fault);
 659         return fault->nested_page_fault;
 660 }
 661 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
 662
 663 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
 664 {
 665         atomic_inc(&vcpu->arch.nmi_queued);
 666         kvm_make_request(KVM_REQ_NMI, vcpu);
 667 }
 668 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
 669
 670 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 671 {
 672         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
 673 }
 674 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
 675
 676 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 677 {
 678         kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
 679 }
 680 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
 681
 682 /*
 683  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
 684  * a #GP and return false.
 685  */
 686 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 687 {
 688         if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
 689                 return true;
 690         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
 691         return false;
 692 }
 693 EXPORT_SYMBOL_GPL(kvm_require_cpl);
 694
 695 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
 696 {
 697         if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
 698                 return true;
 699
 700         kvm_queue_exception(vcpu, UD_VECTOR);
 701         return false;
 702 }
 703 EXPORT_SYMBOL_GPL(kvm_require_dr);
 704
 705 /*
 706  * This function will be used to read from the physical memory of the currently
 707  * running guest. The difference to kvm_vcpu_read_guest_page is that this function
 708  * can read from guest physical or from the guest's guest physical memory.
 709  */
 710 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 711                             gfn_t ngfn, void *data, int offset, int len,
 712                             u32 access)
 713 {
 714         struct x86_exception exception;
 715         gfn_t real_gfn;
 716         gpa_t ngpa;
 717
 718         ngpa     = gfn_to_gpa(ngfn);
 719         real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
 720         if (real_gfn == UNMAPPED_GVA)
 721                 return -EFAULT;
 722
 723         real_gfn = gpa_to_gfn(real_gfn);
 724
 725         return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
 726 }
 727 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
 728
 729 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
 730                                void *data, int offset, int len, u32 access)
 731 {
 732         return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
 733                                        data, offset, len, access);
 734 }
 735
 736 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
 737 {
 738         return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
 739                rsvd_bits(1, 2);
 740 }
 741
 742 /*
 743  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
 744  */
 745 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
 746 {
 747         gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
 748         unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
 749         int i;
 750         int ret;
 751         u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
 752
 753         ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
 754                                       offset * sizeof(u64), sizeof(pdpte),
 755                                       PFERR_USER_MASK|PFERR_WRITE_MASK);
 756         if (ret < 0) {
 757                 ret = 0;
 758                 goto out;
 759         }
 760         for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
 761                 if ((pdpte[i] & PT_PRESENT_MASK) &&
 762                     (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
 763                         ret = 0;
 764                         goto out;
 765                 }
 766         }
 767         ret = 1;
 768
 769         memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
 770         kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
 771
 772 out:
 773
 774         return ret;
 775 }
 776 EXPORT_SYMBOL_GPL(load_pdptrs);
 777
 778 bool pdptrs_changed(struct kvm_vcpu *vcpu)
 779 {
 780         u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
 781         int offset;
 782         gfn_t gfn;
 783         int r;
 784
 785         if (!is_pae_paging(vcpu))
 786                 return false;
 787
 788         if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
 789                 return true;
 790
 791         gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
 792         offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
 793         r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
 794                                        PFERR_USER_MASK | PFERR_WRITE_MASK);
 795         if (r < 0)
 796                 return true;
 797
 798         return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
 799 }
 800 EXPORT_SYMBOL_GPL(pdptrs_changed);
 801
 802 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 803 {
 804         unsigned long old_cr0 = kvm_read_cr0(vcpu);
 805         unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
 806         unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
 807
 808         cr0 |= X86_CR0_ET;
 809
 810 #ifdef CONFIG_X86_64
 811         if (cr0 & 0xffffffff00000000UL)
 812                 return 1;
 813 #endif
 814
 815         cr0 &= ~CR0_RESERVED_BITS;
 816
 817         if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
 818                 return 1;
 819
 820         if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
 821                 return 1;
 822
 823 #ifdef CONFIG_X86_64
 824         if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
 825             (cr0 & X86_CR0_PG)) {
 826                 int cs_db, cs_l;
 827
 828                 if (!is_pae(vcpu))
 829                         return 1;
 830                 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
 831                 if (cs_l)
 832                         return 1;
 833         }
 834 #endif
 835         if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
 836             is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
 837             !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
 838                 return 1;
 839
 840         if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
 841                 return 1;
 842
 843         kvm_x86_ops.set_cr0(vcpu, cr0);
 844
 845         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
 846                 kvm_clear_async_pf_completion_queue(vcpu);
 847                 kvm_async_pf_hash_reset(vcpu);
 848         }
 849
 850         if ((cr0 ^ old_cr0) & update_bits)
 851                 kvm_mmu_reset_context(vcpu);
 852
 853         if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
 854             kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
 855             !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
 856                 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
 857
 858         return 0;
 859 }
 860 EXPORT_SYMBOL_GPL(kvm_set_cr0);
 861
 862 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 863 {
 864         (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
 865 }
 866 EXPORT_SYMBOL_GPL(kvm_lmsw);
 867
 868 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
 869 {
 870         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 871
 872                 if (vcpu->arch.xcr0 != host_xcr0)
 873                         xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
 874
 875                 if (vcpu->arch.xsaves_enabled &&
 876                     vcpu->arch.ia32_xss != host_xss)
 877                         wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
 878         }
 879
 880         if (static_cpu_has(X86_FEATURE_PKU) &&
 881             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 882              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
 883             vcpu->arch.pkru != vcpu->arch.host_pkru)
 884                 __write_pkru(vcpu->arch.pkru);
 885 }
 886 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
 887
 888 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
 889 {
 890         if (static_cpu_has(X86_FEATURE_PKU) &&
 891             (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
 892              (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
 893                 vcpu->arch.pkru = rdpkru();
 894                 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
 895                         __write_pkru(vcpu->arch.host_pkru);
 896         }
 897
 898         if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
 899
 900                 if (vcpu->arch.xcr0 != host_xcr0)
 901                         xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
 902
 903                 if (vcpu->arch.xsaves_enabled &&
 904                     vcpu->arch.ia32_xss != host_xss)
 905                         wrmsrl(MSR_IA32_XSS, host_xss);
 906         }
 907
 908 }
 909 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
 910
 911 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 912 {
 913         u64 xcr0 = xcr;
 914         u64 old_xcr0 = vcpu->arch.xcr0;
 915         u64 valid_bits;
 916
 917         /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
 918         if (index != XCR_XFEATURE_ENABLED_MASK)
 919                 return 1;
 920         if (!(xcr0 & XFEATURE_MASK_FP))
 921                 return 1;
 922         if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
 923                 return 1;
 924
 925         /*
 926          * Do not allow the guest to set bits that we do not support
 927          * saving.  However, xcr0 bit 0 is always set, even if the
 928          * emulated CPU does not support XSAVE (see fx_init).
 929          */
 930         valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
 931         if (xcr0 & ~valid_bits)
 932                 return 1;
 933
 934         if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
 935             (!(xcr0 & XFEATURE_MASK_BNDCSR)))
 936                 return 1;
 937
 938         if (xcr0 & XFEATURE_MASK_AVX512) {
 939                 if (!(xcr0 & XFEATURE_MASK_YMM))
 940                         return 1;
 941                 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
 942                         return 1;
 943         }
 944         vcpu->arch.xcr0 = xcr0;
 945
 946         if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
 947                 kvm_update_cpuid_runtime(vcpu);
 948         return 0;
 949 }
 950
 951 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 952 {
 953         if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
 954             __kvm_set_xcr(vcpu, index, xcr)) {
 955                 kvm_inject_gp(vcpu, 0);
 956                 return 1;
 957         }
 958         return 0;
 959 }
 960 EXPORT_SYMBOL_GPL(kvm_set_xcr);
 961
 962 int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 963 {
 964         if (cr4 & cr4_reserved_bits)
 965                 return -EINVAL;
 966
 967         if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
 968                 return -EINVAL;
 969
 970         return 0;
 971 }
 972 EXPORT_SYMBOL_GPL(kvm_valid_cr4);
 973
 974 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 975 {
 976         unsigned long old_cr4 = kvm_read_cr4(vcpu);
 977         unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
 978                                    X86_CR4_SMEP;
 979
 980         if (kvm_valid_cr4(vcpu, cr4))
 981                 return 1;
 982
 983         if (is_long_mode(vcpu)) {
 984                 if (!(cr4 & X86_CR4_PAE))
 985                         return 1;
 986                 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
 987                         return 1;
 988         } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
 989                    && ((cr4 ^ old_cr4) & pdptr_bits)
 990                    && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
 991                                    kvm_read_cr3(vcpu)))
 992                 return 1;
 993
 994         if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
 995                 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
 996                         return 1;
 997
 998                 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
 999                 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1000                         return 1;
1001         }
1002
1003         if (kvm_x86_ops.set_cr4(vcpu, cr4))
1004                 return 1;
1005
1006         if (((cr4 ^ old_cr4) & pdptr_bits) ||
1007             (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1008                 kvm_mmu_reset_context(vcpu);
1009
1010         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1011                 kvm_update_cpuid_runtime(vcpu);
1012
1013         return 0;
1014 }
1015 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1016
1017 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1018 {
1019         bool skip_tlb_flush = false;
1020 #ifdef CONFIG_X86_64
1021         bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1022
1023         if (pcid_enabled) {
1024                 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1025                 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1026         }
1027 #endif
1028
1029         if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1030                 if (!skip_tlb_flush) {
1031                         kvm_mmu_sync_roots(vcpu);
1032                         kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1033                 }
1034                 return 0;
1035         }
1036
1037         if (is_long_mode(vcpu) &&
1038             (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
1039                 return 1;
1040         else if (is_pae_paging(vcpu) &&
1041                  !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1042                 return 1;
1043
1044         kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1045         vcpu->arch.cr3 = cr3;
1046         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1047
1048         return 0;
1049 }
1050 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1051
1052 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1053 {
1054         if (cr8 & CR8_RESERVED_BITS)
1055                 return 1;
1056         if (lapic_in_kernel(vcpu))
1057                 kvm_lapic_set_tpr(vcpu, cr8);
1058         else
1059                 vcpu->arch.cr8 = cr8;
1060         return 0;
1061 }
1062 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1063
1064 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1065 {
1066         if (lapic_in_kernel(vcpu))
1067                 return kvm_lapic_get_cr8(vcpu);
1068         else
1069                 return vcpu->arch.cr8;
1070 }
1071 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1072
1073 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1074 {
1075         int i;
1076
1077         if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1078                 for (i = 0; i < KVM_NR_DB_REGS; i++)
1079                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1080                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1081         }
1082 }
1083
1084 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1085 {
1086         unsigned long dr7;
1087
1088         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1089                 dr7 = vcpu->arch.guest_debug_dr7;
1090         else
1091                 dr7 = vcpu->arch.dr7;
1092         kvm_x86_ops.set_dr7(vcpu, dr7);
1093         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1094         if (dr7 & DR7_BP_EN_MASK)
1095                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1096 }
1097 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1098
1099 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1100 {
1101         u64 fixed = DR6_FIXED_1;
1102
1103         if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1104                 fixed |= DR6_RTM;
1105         return fixed;
1106 }
1107
1108 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1109 {
1110         size_t size = ARRAY_SIZE(vcpu->arch.db);
1111
1112         switch (dr) {
1113         case 0 ... 3:
1114                 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1115                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1116                         vcpu->arch.eff_db[dr] = val;
1117                 break;
1118         case 4:
1119         case 6:
1120                 if (!kvm_dr6_valid(val))
1121                         return -1; /* #GP */
1122                 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1123                 break;
1124         case 5:
1125         default: /* 7 */
1126                 if (!kvm_dr7_valid(val))
1127                         return -1; /* #GP */
1128                 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1129                 kvm_update_dr7(vcpu);
1130                 break;
1131         }
1132
1133         return 0;
1134 }
1135
1136 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1137 {
1138         if (__kvm_set_dr(vcpu, dr, val)) {
1139                 kvm_inject_gp(vcpu, 0);
1140                 return 1;
1141         }
1142         return 0;
1143 }
1144 EXPORT_SYMBOL_GPL(kvm_set_dr);
1145
1146 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1147 {
1148         size_t size = ARRAY_SIZE(vcpu->arch.db);
1149
1150         switch (dr) {
1151         case 0 ... 3:
1152                 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1153                 break;
1154         case 4:
1155         case 6:
1156                 *val = vcpu->arch.dr6;
1157                 break;
1158         case 5:
1159         default: /* 7 */
1160                 *val = vcpu->arch.dr7;
1161                 break;
1162         }
1163         return 0;
1164 }
1165 EXPORT_SYMBOL_GPL(kvm_get_dr);
1166
1167 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1168 {
1169         u32 ecx = kvm_rcx_read(vcpu);
1170         u64 data;
1171         int err;
1172
1173         err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1174         if (err)
1175                 return err;
1176         kvm_rax_write(vcpu, (u32)data);
1177         kvm_rdx_write(vcpu, data >> 32);
1178         return err;
1179 }
1180 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1181
1182 /*
1183  * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1184  * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1185  *
1186  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1187  * extract the supported MSRs from the related const lists.
1188  * msrs_to_save is selected from the msrs_to_save_all to reflect the
1189  * capabilities of the host cpu. This capabilities test skips MSRs that are
1190  * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1191  * may depend on host virtualization features rather than host cpu features.
1192  */
1193
1194 static const u32 msrs_to_save_all[] = {
1195         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1196         MSR_STAR,
1197 #ifdef CONFIG_X86_64
1198         MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1199 #endif
1200         MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1201         MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1202         MSR_IA32_SPEC_CTRL,
1203         MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1204         MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1205         MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1206         MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1207         MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1208         MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1209         MSR_IA32_UMWAIT_CONTROL,
1210
1211         MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1212         MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1213         MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1214         MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1215         MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1216         MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1217         MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1218         MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1219         MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1220         MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1221         MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1222         MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1223         MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1224         MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1225         MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1226         MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1227         MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1228         MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1229         MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1230         MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1231         MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1232         MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1233 };
1234
1235 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1236 static unsigned num_msrs_to_save;
1237
1238 static const u32 emulated_msrs_all[] = {
1239         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1240         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1241         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1242         HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1243         HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1244         HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1245         HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1246         HV_X64_MSR_RESET,
1247         HV_X64_MSR_VP_INDEX,
1248         HV_X64_MSR_VP_RUNTIME,
1249         HV_X64_MSR_SCONTROL,
1250         HV_X64_MSR_STIMER0_CONFIG,
1251         HV_X64_MSR_VP_ASSIST_PAGE,
1252         HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1253         HV_X64_MSR_TSC_EMULATION_STATUS,
1254         HV_X64_MSR_SYNDBG_OPTIONS,
1255         HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1256         HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1257         HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1258
1259         MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1260         MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1261
1262         MSR_IA32_TSC_ADJUST,
1263         MSR_IA32_TSCDEADLINE,
1264         MSR_IA32_ARCH_CAPABILITIES,
1265         MSR_IA32_PERF_CAPABILITIES,
1266         MSR_IA32_MISC_ENABLE,
1267         MSR_IA32_MCG_STATUS,
1268         MSR_IA32_MCG_CTL,
1269         MSR_IA32_MCG_EXT_CTL,
1270         MSR_IA32_SMBASE,
1271         MSR_SMI_COUNT,
1272         MSR_PLATFORM_INFO,
1273         MSR_MISC_FEATURES_ENABLES,
1274         MSR_AMD64_VIRT_SPEC_CTRL,
1275         MSR_IA32_POWER_CTL,
1276         MSR_IA32_UCODE_REV,
1277
1278         /*
1279          * The following list leaves out MSRs whose values are determined
1280          * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1281          * We always support the "true" VMX control MSRs, even if the host
1282          * processor does not, so I am putting these registers here rather
1283          * than in msrs_to_save_all.
1284          */
1285         MSR_IA32_VMX_BASIC,
1286         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1287         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1288         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1289         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1290         MSR_IA32_VMX_MISC,
1291         MSR_IA32_VMX_CR0_FIXED0,
1292         MSR_IA32_VMX_CR4_FIXED0,
1293         MSR_IA32_VMX_VMCS_ENUM,
1294         MSR_IA32_VMX_PROCBASED_CTLS2,
1295         MSR_IA32_VMX_EPT_VPID_CAP,
1296         MSR_IA32_VMX_VMFUNC,
1297
1298         MSR_K7_HWCR,
1299         MSR_KVM_POLL_CONTROL,
1300 };
1301
1302 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1303 static unsigned num_emulated_msrs;
1304
1305 /*
1306  * List of msr numbers which are used to expose MSR-based features that
1307  * can be used by a hypervisor to validate requested CPU features.
1308  */
1309 static const u32 msr_based_features_all[] = {
1310         MSR_IA32_VMX_BASIC,
1311         MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1312         MSR_IA32_VMX_PINBASED_CTLS,
1313         MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1314         MSR_IA32_VMX_PROCBASED_CTLS,
1315         MSR_IA32_VMX_TRUE_EXIT_CTLS,
1316         MSR_IA32_VMX_EXIT_CTLS,
1317         MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1318         MSR_IA32_VMX_ENTRY_CTLS,
1319         MSR_IA32_VMX_MISC,
1320         MSR_IA32_VMX_CR0_FIXED0,
1321         MSR_IA32_VMX_CR0_FIXED1,
1322         MSR_IA32_VMX_CR4_FIXED0,
1323         MSR_IA32_VMX_CR4_FIXED1,
1324         MSR_IA32_VMX_VMCS_ENUM,
1325         MSR_IA32_VMX_PROCBASED_CTLS2,
1326         MSR_IA32_VMX_EPT_VPID_CAP,
1327         MSR_IA32_VMX_VMFUNC,
1328
1329         MSR_F10H_DECFG,
1330         MSR_IA32_UCODE_REV,
1331         MSR_IA32_ARCH_CAPABILITIES,
1332         MSR_IA32_PERF_CAPABILITIES,
1333 };
1334
1335 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1336 static unsigned int num_msr_based_features;
1337
1338 static u64 kvm_get_arch_capabilities(void)
1339 {
1340         u64 data = 0;
1341
1342         if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1343                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1344
1345         /*
1346          * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1347          * the nested hypervisor runs with NX huge pages.  If it is not,
1348          * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1349          * L1 guests, so it need not worry about its own (L2) guests.
1350          */
1351         data |= ARCH_CAP_PSCHANGE_MC_NO;
1352
1353         /*
1354          * If we're doing cache flushes (either "always" or "cond")
1355          * we will do one whenever the guest does a vmlaunch/vmresume.
1356          * If an outer hypervisor is doing the cache flush for us
1357          * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1358          * capability to the guest too, and if EPT is disabled we're not
1359          * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1360          * require a nested hypervisor to do a flush of its own.
1361          */
1362         if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1363                 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1364
1365         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1366                 data |= ARCH_CAP_RDCL_NO;
1367         if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1368                 data |= ARCH_CAP_SSB_NO;
1369         if (!boot_cpu_has_bug(X86_BUG_MDS))
1370                 data |= ARCH_CAP_MDS_NO;
1371
1372         /*
1373          * On TAA affected systems:
1374          *      - nothing to do if TSX is disabled on the host.
1375          *      - we emulate TSX_CTRL if present on the host.
1376          *        This lets the guest use VERW to clear CPU buffers.
1377          */
1378         if (!boot_cpu_has(X86_FEATURE_RTM))
1379                 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1380         else if (!boot_cpu_has_bug(X86_BUG_TAA))
1381                 data |= ARCH_CAP_TAA_NO;
1382
1383         return data;
1384 }
1385
1386 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1387 {
1388         switch (msr->index) {
1389         case MSR_IA32_ARCH_CAPABILITIES:
1390                 msr->data = kvm_get_arch_capabilities();
1391                 break;
1392         case MSR_IA32_UCODE_REV:
1393                 rdmsrl_safe(msr->index, &msr->data);
1394                 break;
1395         default:
1396                 return kvm_x86_ops.get_msr_feature(msr);
1397         }
1398         return 0;
1399 }
1400
1401 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1402 {
1403         struct kvm_msr_entry msr;
1404         int r;
1405
1406         msr.index = index;
1407         r = kvm_get_msr_feature(&msr);
1408
1409         if (r == KVM_MSR_RET_INVALID) {
1410                 /* Unconditionally clear the output for simplicity */
1411                 *data = 0;
1412                 r = kvm_msr_ignored_check(vcpu, index, 0, false);
1413         }
1414
1415         if (r)
1416                 return r;
1417
1418         *data = msr.data;
1419
1420         return 0;
1421 }
1422
1423 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1424 {
1425         if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1426                 return false;
1427
1428         if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1429                 return false;
1430
1431         if (efer & (EFER_LME | EFER_LMA) &&
1432             !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1433                 return false;
1434
1435         if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1436                 return false;
1437
1438         return true;
1439
1440 }
1441 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1442 {
1443         if (efer & efer_reserved_bits)
1444                 return false;
1445
1446         return __kvm_valid_efer(vcpu, efer);
1447 }
1448 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1449
1450 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1451 {
1452         u64 old_efer = vcpu->arch.efer;
1453         u64 efer = msr_info->data;
1454
1455         if (efer & efer_reserved_bits)
1456                 return 1;
1457
1458         if (!msr_info->host_initiated) {
1459                 if (!__kvm_valid_efer(vcpu, efer))
1460                         return 1;
1461
1462                 if (is_paging(vcpu) &&
1463                     (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1464                         return 1;
1465         }
1466
1467         efer &= ~EFER_LMA;
1468         efer |= vcpu->arch.efer & EFER_LMA;
1469
1470         kvm_x86_ops.set_efer(vcpu, efer);
1471
1472         /* Update reserved bits */
1473         if ((efer ^ old_efer) & EFER_NX)
1474                 kvm_mmu_reset_context(vcpu);
1475
1476         return 0;
1477 }
1478
1479 void kvm_enable_efer_bits(u64 mask)
1480 {
1481        efer_reserved_bits &= ~mask;
1482 }
1483 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1484
1485 /*
1486  * Write @data into the MSR specified by @index.  Select MSR specific fault
1487  * checks are bypassed if @host_initiated is %true.
1488  * Returns 0 on success, non-0 otherwise.
1489  * Assumes vcpu_load() was already called.
1490  */
1491 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1492                          bool host_initiated)
1493 {
1494         struct msr_data msr;
1495
1496         switch (index) {
1497         case MSR_FS_BASE:
1498         case MSR_GS_BASE:
1499         case MSR_KERNEL_GS_BASE:
1500         case MSR_CSTAR:
1501         case MSR_LSTAR:
1502                 if (is_noncanonical_address(data, vcpu))
1503                         return 1;
1504                 break;
1505         case MSR_IA32_SYSENTER_EIP:
1506         case MSR_IA32_SYSENTER_ESP:
1507                 /*
1508                  * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1509                  * non-canonical address is written on Intel but not on
1510                  * AMD (which ignores the top 32-bits, because it does
1511                  * not implement 64-bit SYSENTER).
1512                  *
1513                  * 64-bit code should hence be able to write a non-canonical
1514                  * value on AMD.  Making the address canonical ensures that
1515                  * vmentry does not fail on Intel after writing a non-canonical
1516                  * value, and that something deterministic happens if the guest
1517                  * invokes 64-bit SYSENTER.
1518                  */
1519                 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1520         }
1521
1522         msr.data = data;
1523         msr.index = index;
1524         msr.host_initiated = host_initiated;
1525
1526         return kvm_x86_ops.set_msr(vcpu, &msr);
1527 }
1528
1529 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1530                                      u32 index, u64 data, bool host_initiated)
1531 {
1532         int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1533
1534         if (ret == KVM_MSR_RET_INVALID)
1535                 ret = kvm_msr_ignored_check(vcpu, index, data, true);
1536
1537         return ret;
1538 }
1539
1540 /*
1541  * Read the MSR specified by @index into @data.  Select MSR specific fault
1542  * checks are bypassed if @host_initiated is %true.
1543  * Returns 0 on success, non-0 otherwise.
1544  * Assumes vcpu_load() was already called.
1545  */
1546 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1547                   bool host_initiated)
1548 {
1549         struct msr_data msr;
1550         int ret;
1551
1552         msr.index = index;
1553         msr.host_initiated = host_initiated;
1554
1555         ret = kvm_x86_ops.get_msr(vcpu, &msr);
1556         if (!ret)
1557                 *data = msr.data;
1558         return ret;
1559 }
1560
1561 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1562                                      u32 index, u64 *data, bool host_initiated)
1563 {
1564         int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1565
1566         if (ret == KVM_MSR_RET_INVALID) {
1567                 /* Unconditionally clear *data for simplicity */
1568                 *data = 0;
1569                 ret = kvm_msr_ignored_check(vcpu, index, 0, false);
1570         }
1571
1572         return ret;
1573 }
1574
1575 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1576 {
1577         return kvm_get_msr_ignored_check(vcpu, index, data, false);
1578 }
1579 EXPORT_SYMBOL_GPL(kvm_get_msr);
1580
1581 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1582 {
1583         return kvm_set_msr_ignored_check(vcpu, index, data, false);
1584 }
1585 EXPORT_SYMBOL_GPL(kvm_set_msr);
1586
1587 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1588 {
1589         u32 ecx = kvm_rcx_read(vcpu);
1590         u64 data;
1591
1592         if (kvm_get_msr(vcpu, ecx, &data)) {
1593                 trace_kvm_msr_read_ex(ecx);
1594                 kvm_inject_gp(vcpu, 0);
1595                 return 1;
1596         }
1597
1598         trace_kvm_msr_read(ecx, data);
1599
1600         kvm_rax_write(vcpu, data & -1u);
1601         kvm_rdx_write(vcpu, (data >> 32) & -1u);
1602         return kvm_skip_emulated_instruction(vcpu);
1603 }
1604 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1605
1606 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1607 {
1608         u32 ecx = kvm_rcx_read(vcpu);
1609         u64 data = kvm_read_edx_eax(vcpu);
1610
1611         if (kvm_set_msr(vcpu, ecx, data)) {
1612                 trace_kvm_msr_write_ex(ecx, data);
1613                 kvm_inject_gp(vcpu, 0);
1614                 return 1;
1615         }
1616
1617         trace_kvm_msr_write(ecx, data);
1618         return kvm_skip_emulated_instruction(vcpu);
1619 }
1620 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1621
1622 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1623 {
1624         return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1625                 xfer_to_guest_mode_work_pending();
1626 }
1627 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1628
1629 /*
1630  * The fast path for frequent and performance sensitive wrmsr emulation,
1631  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1632  * the latency of virtual IPI by avoiding the expensive bits of transitioning
1633  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1634  * other cases which must be called after interrupts are enabled on the host.
1635  */
1636 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1637 {
1638         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1639                 return 1;
1640
1641         if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1642                 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1643                 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1644                 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1645
1646                 data &= ~(1 << 12);
1647                 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1648                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1649                 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1650                 trace_kvm_apic_write(APIC_ICR, (u32)data);
1651                 return 0;
1652         }
1653
1654         return 1;
1655 }
1656
1657 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1658 {
1659         if (!kvm_can_use_hv_timer(vcpu))
1660                 return 1;
1661
1662         kvm_set_lapic_tscdeadline_msr(vcpu, data);
1663         return 0;
1664 }
1665
1666 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1667 {
1668         u32 msr = kvm_rcx_read(vcpu);
1669         u64 data;
1670         fastpath_t ret = EXIT_FASTPATH_NONE;
1671
1672         switch (msr) {
1673         case APIC_BASE_MSR + (APIC_ICR >> 4):
1674                 data = kvm_read_edx_eax(vcpu);
1675                 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1676                         kvm_skip_emulated_instruction(vcpu);
1677                         ret = EXIT_FASTPATH_EXIT_HANDLED;
1678                 }
1679                 break;
1680         case MSR_IA32_TSCDEADLINE:
1681                 data = kvm_read_edx_eax(vcpu);
1682                 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1683                         kvm_skip_emulated_instruction(vcpu);
1684                         ret = EXIT_FASTPATH_REENTER_GUEST;
1685                 }
1686                 break;
1687         default:
1688                 break;
1689         }
1690
1691         if (ret != EXIT_FASTPATH_NONE)
1692                 trace_kvm_msr_write(msr, data);
1693
1694         return ret;
1695 }
1696 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1697
1698 /*
1699  * Adapt set_msr() to msr_io()'s calling convention
1700  */
1701 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1702 {
1703         return kvm_get_msr_ignored_check(vcpu, index, data, true);
1704 }
1705
1706 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1707 {
1708         return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1709 }
1710
1711 #ifdef CONFIG_X86_64
1712 struct pvclock_clock {
1713         int vclock_mode;
1714         u64 cycle_last;
1715         u64 mask;
1716         u32 mult;
1717         u32 shift;
1718         u64 base_cycles;
1719         u64 offset;
1720 };
1721
1722 struct pvclock_gtod_data {
1723         seqcount_t      seq;
1724
1725         struct pvclock_clock clock; /* extract of a clocksource struct */
1726         struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1727
1728         ktime_t         offs_boot;
1729         u64             wall_time_sec;
1730 };
1731
1732 static struct pvclock_gtod_data pvclock_gtod_data;
1733
1734 static void update_pvclock_gtod(struct timekeeper *tk)
1735 {
1736         struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1737
1738         write_seqcount_begin(&vdata->seq);
1739
1740         /* copy pvclock gtod data */
1741         vdata->clock.vclock_mode        = tk->tkr_mono.clock->vdso_clock_mode;
1742         vdata->clock.cycle_last         = tk->tkr_mono.cycle_last;
1743         vdata->clock.mask               = tk->tkr_mono.mask;
1744         vdata->clock.mult               = tk->tkr_mono.mult;
1745         vdata->clock.shift              = tk->tkr_mono.shift;
1746         vdata->clock.base_cycles        = tk->tkr_mono.xtime_nsec;
1747         vdata->clock.offset             = tk->tkr_mono.base;
1748
1749         vdata->raw_clock.vclock_mode    = tk->tkr_raw.clock->vdso_clock_mode;
1750         vdata->raw_clock.cycle_last     = tk->tkr_raw.cycle_last;
1751         vdata->raw_clock.mask           = tk->tkr_raw.mask;
1752         vdata->raw_clock.mult           = tk->tkr_raw.mult;
1753         vdata->raw_clock.shift          = tk->tkr_raw.shift;
1754         vdata->raw_clock.base_cycles    = tk->tkr_raw.xtime_nsec;
1755         vdata->raw_clock.offset         = tk->tkr_raw.base;
1756
1757         vdata->wall_time_sec            = tk->xtime_sec;
1758
1759         vdata->offs_boot                = tk->offs_boot;
1760
1761         write_seqcount_end(&vdata->seq);
1762 }
1763
1764 static s64 get_kvmclock_base_ns(void)
1765 {
1766         /* Count up from boot time, but with the frequency of the raw clock.  */
1767         return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1768 }
1769 #else
1770 static s64 get_kvmclock_base_ns(void)
1771 {
1772         /* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
1773         return ktime_get_boottime_ns();
1774 }
1775 #endif
1776
1777 void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1778 {
1779         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1780         kvm_vcpu_kick(vcpu);
1781 }
1782
1783 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1784 {
1785         int version;
1786         int r;
1787         struct pvclock_wall_clock wc;
1788         u64 wall_nsec;
1789
1790         if (!wall_clock)
1791                 return;
1792
1793         r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1794         if (r)
1795                 return;
1796
1797         if (version & 1)
1798                 ++version;  /* first time write, random junk */
1799
1800         ++version;
1801
1802         if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1803                 return;
1804
1805         /*
1806          * The guest calculates current wall clock time by adding
1807          * system time (updated by kvm_guest_time_update below) to the
1808          * wall clock specified here.  We do the reverse here.
1809          */
1810         wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1811
1812         wc.nsec = do_div(wall_nsec, 1000000000);
1813         wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1814         wc.version = version;
1815
1816         kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1817
1818         version++;
1819         kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1820 }
1821
1822 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1823 {
1824         do_shl32_div32(dividend, divisor);
1825         return dividend;
1826 }
1827
1828 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1829                                s8 *pshift, u32 *pmultiplier)
1830 {
1831         uint64_t scaled64;
1832         int32_t  shift = 0;
1833         uint64_t tps64;
1834         uint32_t tps32;
1835
1836         tps64 = base_hz;
1837         scaled64 = scaled_hz;
1838         while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1839                 tps64 >>= 1;
1840                 shift--;
1841         }
1842
1843         tps32 = (uint32_t)tps64;
1844         while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1845                 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1846                         scaled64 >>= 1;
1847                 else
1848                         tps32 <<= 1;
1849                 shift++;
1850         }
1851
1852         *pshift = shift;
1853         *pmultiplier = div_frac(scaled64, tps32);
1854 }
1855
1856 #ifdef CONFIG_X86_64
1857 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1858 #endif
1859
1860 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1861 static unsigned long max_tsc_khz;
1862
1863 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1864 {
1865         u64 v = (u64)khz * (1000000 + ppm);
1866         do_div(v, 1000000);
1867         return v;
1868 }
1869
1870 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1871 {
1872         u64 ratio;
1873
1874         /* Guest TSC same frequency as host TSC? */
1875         if (!scale) {
1876                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1877                 return 0;
1878         }
1879
1880         /* TSC scaling supported? */
1881         if (!kvm_has_tsc_control) {
1882                 if (user_tsc_khz > tsc_khz) {
1883                         vcpu->arch.tsc_catchup = 1;
1884                         vcpu->arch.tsc_always_catchup = 1;
1885                         return 0;
1886                 } else {
1887                         pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
1888                         return -1;
1889                 }
1890         }
1891
1892         /* TSC scaling required  - calculate ratio */
1893         ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1894                                 user_tsc_khz, tsc_khz);
1895
1896         if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1897                 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1898                                     user_tsc_khz);
1899                 return -1;
1900         }
1901
1902         vcpu->arch.tsc_scaling_ratio = ratio;
1903         return 0;
1904 }
1905
1906 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1907 {
1908         u32 thresh_lo, thresh_hi;
1909         int use_scaling = 0;
1910
1911         /* tsc_khz can be zero if TSC calibration fails */
1912         if (user_tsc_khz == 0) {
1913                 /* set tsc_scaling_ratio to a safe value */
1914                 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1915                 return -1;
1916         }
1917
1918         /* Compute a scale to convert nanoseconds in TSC cycles */
1919         kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
1920                            &vcpu->arch.virtual_tsc_shift,
1921                            &vcpu->arch.virtual_tsc_mult);
1922         vcpu->arch.virtual_tsc_khz = user_tsc_khz;
1923
1924         /*
1925          * Compute the variation in TSC rate which is acceptable
1926          * within the range of tolerance and decide if the
1927          * rate being applied is within that bounds of the hardware
1928          * rate.  If so, no scaling or compensation need be done.
1929          */
1930         thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1931         thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1932         if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1933                 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
1934                 use_scaling = 1;
1935         }
1936         return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
1937 }
1938
1939 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1940 {
1941         u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1942                                       vcpu->arch.virtual_tsc_mult,
1943                                       vcpu->arch.virtual_tsc_shift);
1944         tsc += vcpu->arch.this_tsc_write;
1945         return tsc;
1946 }
1947
1948 static inline int gtod_is_based_on_tsc(int mode)
1949 {
1950         return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
1951 }
1952
1953 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1954 {
1955 #ifdef CONFIG_X86_64
1956         bool vcpus_matched;
1957         struct kvm_arch *ka = &vcpu->kvm->arch;
1958         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1959
1960         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1961                          atomic_read(&vcpu->kvm->online_vcpus));
1962
1963         /*
1964          * Once the masterclock is enabled, always perform request in
1965          * order to update it.
1966          *
1967          * In order to enable masterclock, the host clocksource must be TSC
1968          * and the vcpus need to have matched TSCs.  When that happens,
1969          * perform request to enable masterclock.
1970          */
1971         if (ka->use_master_clock ||
1972             (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
1973                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1974
1975         trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1976                             atomic_read(&vcpu->kvm->online_vcpus),
1977                             ka->use_master_clock, gtod->clock.vclock_mode);
1978 #endif
1979 }
1980
1981 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1982 {
1983         u64 curr_offset = vcpu->arch.l1_tsc_offset;
1984         vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1985 }
1986
1987 /*
1988  * Multiply tsc by a fixed point number represented by ratio.
1989  *
1990  * The most significant 64-N bits (mult) of ratio represent the
1991  * integral part of the fixed point number; the remaining N bits
1992  * (frac) represent the fractional part, ie. ratio represents a fixed
1993  * point number (mult + frac * 2^(-N)).
1994  *
1995  * N equals to kvm_tsc_scaling_ratio_frac_bits.
1996  */
1997 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1998 {
1999         return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2000 }
2001
2002 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2003 {
2004         u64 _tsc = tsc;
2005         u64 ratio = vcpu->arch.tsc_scaling_ratio;
2006
2007         if (ratio != kvm_default_tsc_scaling_ratio)
2008                 _tsc = __scale_tsc(ratio, tsc);
2009
2010         return _tsc;
2011 }
2012 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2013
2014 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2015 {
2016         u64 tsc;
2017
2018         tsc = kvm_scale_tsc(vcpu, rdtsc());
2019
2020         return target_tsc - tsc;
2021 }
2022
2023 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2024 {
2025         return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2026 }
2027 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2028
2029 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2030 {
2031         vcpu->arch.l1_tsc_offset = offset;
2032         vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2033 }
2034
2035 static inline bool kvm_check_tsc_unstable(void)
2036 {
2037 #ifdef CONFIG_X86_64
2038         /*
2039          * TSC is marked unstable when we're running on Hyper-V,
2040          * 'TSC page' clocksource is good.
2041          */
2042         if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2043                 return false;
2044 #endif
2045         return check_tsc_unstable();
2046 }
2047
2048 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
2049 {
2050         struct kvm *kvm = vcpu->kvm;
2051         u64 offset, ns, elapsed;
2052         unsigned long flags;
2053         bool matched;
2054         bool already_matched;
2055         u64 data = msr->data;
2056         bool synchronizing = false;
2057
2058         raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2059         offset = kvm_compute_tsc_offset(vcpu, data);
2060         ns = get_kvmclock_base_ns();
2061         elapsed = ns - kvm->arch.last_tsc_nsec;
2062
2063         if (vcpu->arch.virtual_tsc_khz) {
2064                 if (data == 0 && msr->host_initiated) {
2065                         /*
2066                          * detection of vcpu initialization -- need to sync
2067                          * with other vCPUs. This particularly helps to keep
2068                          * kvm_clock stable after CPU hotplug
2069                          */
2070                         synchronizing = true;
2071                 } else {
2072                         u64 tsc_exp = kvm->arch.last_tsc_write +
2073                                                 nsec_to_cycles(vcpu, elapsed);
2074                         u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2075                         /*
2076                          * Special case: TSC write with a small delta (1 second)
2077                          * of virtual cycle time against real time is
2078                          * interpreted as an attempt to synchronize the CPU.
2079                          */
2080                         synchronizing = data < tsc_exp + tsc_hz &&
2081                                         data + tsc_hz > tsc_exp;
2082                 }
2083         }
2084
2085         /*
2086          * For a reliable TSC, we can match TSC offsets, and for an unstable
2087          * TSC, we add elapsed time in this computation.  We could let the
2088          * compensation code attempt to catch up if we fall behind, but
2089          * it's better to try to match offsets from the beginning.
2090          */
2091         if (synchronizing &&
2092             vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2093                 if (!kvm_check_tsc_unstable()) {
2094                         offset = kvm->arch.cur_tsc_offset;
2095                 } else {
2096                         u64 delta = nsec_to_cycles(vcpu, elapsed);
2097                         data += delta;
2098                         offset = kvm_compute_tsc_offset(vcpu, data);
2099                 }
2100                 matched = true;
2101                 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2102         } else {
2103                 /*
2104                  * We split periods of matched TSC writes into generations.
2105                  * For each generation, we track the original measured
2106                  * nanosecond time, offset, and write, so if TSCs are in
2107                  * sync, we can match exact offset, and if not, we can match
2108                  * exact software computation in compute_guest_tsc()
2109                  *
2110                  * These values are tracked in kvm->arch.cur_xxx variables.
2111                  */
2112                 kvm->arch.cur_tsc_generation++;
2113                 kvm->arch.cur_tsc_nsec = ns;
2114                 kvm->arch.cur_tsc_write = data;
2115                 kvm->arch.cur_tsc_offset = offset;
2116                 matched = false;
2117         }
2118
2119         /*
2120          * We also track th most recent recorded KHZ, write and time to
2121          * allow the matching interval to be extended at each write.
2122          */
2123         kvm->arch.last_tsc_nsec = ns;
2124         kvm->arch.last_tsc_write = data;
2125         kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2126
2127         vcpu->arch.last_guest_tsc = data;
2128
2129         /* Keep track of which generation this VCPU has synchronized to */
2130         vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2131         vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2132         vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2133
2134         if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
2135                 update_ia32_tsc_adjust_msr(vcpu, offset);
2136
2137         kvm_vcpu_write_tsc_offset(vcpu, offset);
2138         raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2139
2140         spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2141         if (!matched) {
2142                 kvm->arch.nr_vcpus_matched_tsc = 0;
2143         } else if (!already_matched) {
2144                 kvm->arch.nr_vcpus_matched_tsc++;
2145         }
2146
2147         kvm_track_tsc_matching(vcpu);
2148         spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2149 }
2150
2151 EXPORT_SYMBOL_GPL(kvm_write_tsc);
2152
2153 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2154                                            s64 adjustment)
2155 {
2156         u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2157         kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2158 }
2159
2160 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2161 {
2162         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2163                 WARN_ON(adjustment < 0);
2164         adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2165         adjust_tsc_offset_guest(vcpu, adjustment);
2166 }
2167
2168 #ifdef CONFIG_X86_64
2169
2170 static u64 read_tsc(void)
2171 {
2172         u64 ret = (u64)rdtsc_ordered();
2173         u64 last = pvclock_gtod_data.clock.cycle_last;
2174
2175         if (likely(ret >= last))
2176                 return ret;
2177
2178         /*
2179          * GCC likes to generate cmov here, but this branch is extremely
2180          * predictable (it's just a function of time and the likely is
2181          * very likely) and there's a data dependence, so force GCC
2182          * to generate a branch instead.  I don't barrier() because
2183          * we don't actually need a barrier, and if this function
2184          * ever gets inlined it will generate worse code.
2185          */
2186         asm volatile ("");
2187         return last;
2188 }
2189
2190 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2191                           int *mode)
2192 {
2193         long v;
2194         u64 tsc_pg_val;
2195
2196         switch (clock->vclock_mode) {
2197         case VDSO_CLOCKMODE_HVCLOCK:
2198                 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2199                                                   tsc_timestamp);
2200                 if (tsc_pg_val != U64_MAX) {
2201                         /* TSC page valid */
2202                         *mode = VDSO_CLOCKMODE_HVCLOCK;
2203                         v = (tsc_pg_val - clock->cycle_last) &
2204                                 clock->mask;
2205                 } else {
2206                         /* TSC page invalid */
2207                         *mode = VDSO_CLOCKMODE_NONE;
2208                 }
2209                 break;
2210         case VDSO_CLOCKMODE_TSC:
2211                 *mode = VDSO_CLOCKMODE_TSC;
2212                 *tsc_timestamp = read_tsc();
2213                 v = (*tsc_timestamp - clock->cycle_last) &
2214                         clock->mask;
2215                 break;
2216         default:
2217                 *mode = VDSO_CLOCKMODE_NONE;
2218         }
2219
2220         if (*mode == VDSO_CLOCKMODE_NONE)
2221                 *tsc_timestamp = v = 0;
2222
2223         return v * clock->mult;
2224 }
2225
2226 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2227 {
2228         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2229         unsigned long seq;
2230         int mode;
2231         u64 ns;
2232
2233         do {
2234                 seq = read_seqcount_begin(&gtod->seq);
2235                 ns = gtod->raw_clock.base_cycles;
2236                 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2237                 ns >>= gtod->raw_clock.shift;
2238                 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2239         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2240         *t = ns;
2241
2242         return mode;
2243 }
2244
2245 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2246 {
2247         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2248         unsigned long seq;
2249         int mode;
2250         u64 ns;
2251
2252         do {
2253                 seq = read_seqcount_begin(&gtod->seq);
2254                 ts->tv_sec = gtod->wall_time_sec;
2255                 ns = gtod->clock.base_cycles;
2256                 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2257                 ns >>= gtod->clock.shift;
2258         } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2259
2260         ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2261         ts->tv_nsec = ns;
2262
2263         return mode;
2264 }
2265
2266 /* returns true if host is using TSC based clocksource */
2267 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2268 {
2269         /* checked again under seqlock below */
2270         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2271                 return false;
2272
2273         return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2274                                                       tsc_timestamp));
2275 }
2276
2277 /* returns true if host is using TSC based clocksource */
2278 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2279                                            u64 *tsc_timestamp)
2280 {
2281         /* checked again under seqlock below */
2282         if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2283                 return false;
2284
2285         return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2286 }
2287 #endif
2288
2289 /*
2290  *
2291  * Assuming a stable TSC across physical CPUS, and a stable TSC
2292  * across virtual CPUs, the following condition is possible.
2293  * Each numbered line represents an event visible to both
2294  * CPUs at the next numbered event.
2295  *
2296  * "timespecX" represents host monotonic time. "tscX" represents
2297  * RDTSC value.
2298  *
2299  *              VCPU0 on CPU0           |       VCPU1 on CPU1
2300  *
2301  * 1.  read timespec0,tsc0
2302  * 2.                                   | timespec1 = timespec0 + N
2303  *                                      | tsc1 = tsc0 + M
2304  * 3. transition to guest               | transition to guest
2305  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2306  * 5.                                   | ret1 = timespec1 + (rdtsc - tsc1)
2307  *                                      | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2308  *
2309  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2310  *
2311  *      - ret0 < ret1
2312  *      - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2313  *              ...
2314  *      - 0 < N - M => M < N
2315  *
2316  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2317  * always the case (the difference between two distinct xtime instances
2318  * might be smaller then the difference between corresponding TSC reads,
2319  * when updating guest vcpus pvclock areas).
2320  *
2321  * To avoid that problem, do not allow visibility of distinct
2322  * system_timestamp/tsc_timestamp values simultaneously: use a master
2323  * copy of host monotonic time values. Update that master copy
2324  * in lockstep.
2325  *
2326  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2327  *
2328  */
2329
2330 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2331 {
2332 #ifdef CONFIG_X86_64
2333         struct kvm_arch *ka = &kvm->arch;
2334         int vclock_mode;
2335         bool host_tsc_clocksource, vcpus_matched;
2336
2337         vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2338                         atomic_read(&kvm->online_vcpus));
2339
2340         /*
2341          * If the host uses TSC clock, then passthrough TSC as stable
2342          * to the guest.
2343          */
2344         host_tsc_clocksource = kvm_get_time_and_clockread(
2345                                         &ka->master_kernel_ns,
2346                                         &ka->master_cycle_now);
2347
2348         ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2349                                 && !ka->backwards_tsc_observed
2350                                 && !ka->boot_vcpu_runs_old_kvmclock;
2351
2352         if (ka->use_master_clock)
2353                 atomic_set(&kvm_guest_has_master_clock, 1);
2354
2355         vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2356         trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2357                                         vcpus_matched);
2358 #endif
2359 }
2360
2361 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2362 {
2363         kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2364 }
2365
2366 static void kvm_gen_update_masterclock(struct kvm *kvm)
2367 {
2368 #ifdef CONFIG_X86_64
2369         int i;
2370         struct kvm_vcpu *vcpu;
2371         struct kvm_arch *ka = &kvm->arch;
2372
2373         spin_lock(&ka->pvclock_gtod_sync_lock);
2374         kvm_make_mclock_inprogress_request(kvm);
2375         /* no guest entries from this point */
2376         pvclock_update_vm_gtod_copy(kvm);
2377
2378         kvm_for_each_vcpu(i, vcpu, kvm)
2379                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2380
2381         /* guest entries allowed */
2382         kvm_for_each_vcpu(i, vcpu, kvm)
2383                 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2384
2385         spin_unlock(&ka->pvclock_gtod_sync_lock);
2386 #endif
2387 }
2388
2389 u64 get_kvmclock_ns(struct kvm *kvm)
2390 {
2391         struct kvm_arch *ka = &kvm->arch;
2392         struct pvclock_vcpu_time_info hv_clock;
2393         u64 ret;
2394
2395         spin_lock(&ka->pvclock_gtod_sync_lock);
2396         if (!ka->use_master_clock) {
2397                 spin_unlock(&ka->pvclock_gtod_sync_lock);
2398                 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2399         }
2400
2401         hv_clock.tsc_timestamp = ka->master_cycle_now;
2402         hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2403         spin_unlock(&ka->pvclock_gtod_sync_lock);
2404
2405         /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2406         get_cpu();
2407
2408         if (__this_cpu_read(cpu_tsc_khz)) {
2409                 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2410                                    &hv_clock.tsc_shift,
2411                                    &hv_clock.tsc_to_system_mul);
2412                 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2413         } else
2414                 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2415
2416         put_cpu();
2417
2418         return ret;
2419 }
2420
2421 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2422 {
2423         struct kvm_vcpu_arch *vcpu = &v->arch;
2424         struct pvclock_vcpu_time_info guest_hv_clock;
2425
2426         if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2427                 &guest_hv_clock, sizeof(guest_hv_clock))))
2428                 return;
2429
2430         /* This VCPU is paused, but it's legal for a guest to read another
2431          * VCPU's kvmclock, so we really have to follow the specification where
2432          * it says that version is odd if data is being modified, and even after
2433          * it is consistent.
2434          *
2435          * Version field updates must be kept separate.  This is because
2436          * kvm_write_guest_cached might use a "rep movs" instruction, and
2437          * writes within a string instruction are weakly ordered.  So there
2438          * are three writes overall.
2439          *
2440          * As a small optimization, only write the version field in the first
2441          * and third write.  The vcpu->pv_time cache is still valid, because the
2442          * version field is the first in the struct.
2443          */
2444         BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2445
2446         if (guest_hv_clock.version & 1)
2447                 ++guest_hv_clock.version;  /* first time write, random junk */
2448
2449         vcpu->hv_clock.version = guest_hv_clock.version + 1;
2450         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2451                                 &vcpu->hv_clock,
2452                                 sizeof(vcpu->hv_clock.version));
2453
2454         smp_wmb();
2455
2456         /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2457         vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2458
2459         if (vcpu->pvclock_set_guest_stopped_request) {
2460                 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2461                 vcpu->pvclock_set_guest_stopped_request = false;
2462         }
2463
2464         trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2465
2466         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2467                                 &vcpu->hv_clock,
2468                                 sizeof(vcpu->hv_clock));
2469
2470         smp_wmb();
2471
2472         vcpu->hv_clock.version++;
2473         kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2474                                 &vcpu->hv_clock,
2475                                 sizeof(vcpu->hv_clock.version));
2476 }
2477
2478 static int kvm_guest_time_update(struct kvm_vcpu *v)
2479 {
2480         unsigned long flags, tgt_tsc_khz;
2481         struct kvm_vcpu_arch *vcpu = &v->arch;
2482         struct kvm_arch *ka = &v->kvm->arch;
2483         s64 kernel_ns;
2484         u64 tsc_timestamp, host_tsc;
2485         u8 pvclock_flags;
2486         bool use_master_clock;
2487
2488         kernel_ns = 0;
2489         host_tsc = 0;
2490
2491         /*
2492          * If the host uses TSC clock, then passthrough TSC as stable
2493          * to the guest.
2494          */
2495         spin_lock(&ka->pvclock_gtod_sync_lock);
2496         use_master_clock = ka->use_master_clock;
2497         if (use_master_clock) {
2498                 host_tsc = ka->master_cycle_now;
2499                 kernel_ns = ka->master_kernel_ns;
2500         }
2501         spin_unlock(&ka->pvclock_gtod_sync_lock);
2502
2503         /* Keep irq disabled to prevent changes to the clock */
2504         local_irq_save(flags);
2505         tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2506         if (unlikely(tgt_tsc_khz == 0)) {
2507                 local_irq_restore(flags);
2508                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2509                 return 1;
2510         }
2511         if (!use_master_clock) {
2512                 host_tsc = rdtsc();
2513                 kernel_ns = get_kvmclock_base_ns();
2514         }
2515
2516         tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2517
2518         /*
2519          * We may have to catch up the TSC to match elapsed wall clock
2520          * time for two reasons, even if kvmclock is used.
2521          *   1) CPU could have been running below the maximum TSC rate
2522          *   2) Broken TSC compensation resets the base at each VCPU
2523          *      entry to avoid unknown leaps of TSC even when running
2524          *      again on the same CPU.  This may cause apparent elapsed
2525          *      time to disappear, and the guest to stand still or run
2526          *      very slowly.
2527          */
2528         if (vcpu->tsc_catchup) {
2529                 u64 tsc = compute_guest_tsc(v, kernel_ns);
2530                 if (tsc > tsc_timestamp) {
2531                         adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2532                         tsc_timestamp = tsc;
2533                 }
2534         }
2535
2536         local_irq_restore(flags);
2537
2538         /* With all the info we got, fill in the values */
2539
2540         if (kvm_has_tsc_control)
2541                 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2542
2543         if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2544                 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2545                                    &vcpu->hv_clock.tsc_shift,
2546                                    &vcpu->hv_clock.tsc_to_system_mul);
2547                 vcpu->hw_tsc_khz = tgt_tsc_khz;
2548         }
2549
2550         vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2551         vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2552         vcpu->last_guest_tsc = tsc_timestamp;
2553
2554         /* If the host uses TSC clocksource, then it is stable */
2555         pvclock_flags = 0;
2556         if (use_master_clock)
2557                 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2558
2559         vcpu->hv_clock.flags = pvclock_flags;
2560
2561         if (vcpu->pv_time_enabled)
2562                 kvm_setup_pvclock_page(v);
2563         if (v == kvm_get_vcpu(v->kvm, 0))
2564                 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2565         return 0;
2566 }
2567
2568 /*
2569  * kvmclock updates which are isolated to a given vcpu, such as
2570  * vcpu->cpu migration, should not allow system_timestamp from
2571  * the rest of the vcpus to remain static. Otherwise ntp frequency
2572  * correction applies to one vcpu's system_timestamp but not
2573  * the others.
2574  *
2575  * So in those cases, request a kvmclock update for all vcpus.
2576  * We need to rate-limit these requests though, as they can
2577  * considerably slow guests that have a large number of vcpus.
2578  * The time for a remote vcpu to update its kvmclock is bound
2579  * by the delay we use to rate-limit the updates.
2580  */
2581
2582 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2583
2584 static void kvmclock_update_fn(struct work_struct *work)
2585 {
2586         int i;
2587         struct delayed_work *dwork = to_delayed_work(work);
2588         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2589                                            kvmclock_update_work);
2590         struct kvm *kvm = container_of(ka, struct kvm, arch);
2591         struct kvm_vcpu *vcpu;
2592
2593         kvm_for_each_vcpu(i, vcpu, kvm) {
2594                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2595                 kvm_vcpu_kick(vcpu);
2596         }
2597 }
2598
2599 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2600 {
2601         struct kvm *kvm = v->kvm;
2602
2603         kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2604         schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2605                                         KVMCLOCK_UPDATE_DELAY);
2606 }
2607
2608 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2609
2610 static void kvmclock_sync_fn(struct work_struct *work)
2611 {
2612         struct delayed_work *dwork = to_delayed_work(work);
2613         struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2614                                            kvmclock_sync_work);
2615         struct kvm *kvm = container_of(ka, struct kvm, arch);
2616
2617         if (!kvmclock_periodic_sync)
2618                 return;
2619
2620         schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2621         schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2622                                         KVMCLOCK_SYNC_PERIOD);
2623 }
2624
2625 /*
2626  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2627  */
2628 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2629 {
2630         /* McStatusWrEn enabled? */
2631         if (guest_cpuid_is_amd_or_hygon(vcpu))
2632                 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2633
2634         return false;
2635 }
2636
2637 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2638 {
2639         u64 mcg_cap = vcpu->arch.mcg_cap;
2640         unsigned bank_num = mcg_cap & 0xff;
2641         u32 msr = msr_info->index;
2642         u64 data = msr_info->data;
2643
2644         switch (msr) {
2645         case MSR_IA32_MCG_STATUS:
2646                 vcpu->arch.mcg_status = data;
2647                 break;
2648         case MSR_IA32_MCG_CTL:
2649                 if (!(mcg_cap & MCG_CTL_P) &&
2650                     (data || !msr_info->host_initiated))
2651                         return 1;
2652                 if (data != 0 && data != ~(u64)0)
2653                         return 1;
2654                 vcpu->arch.mcg_ctl = data;
2655                 break;
2656         default:
2657                 if (msr >= MSR_IA32_MC0_CTL &&
2658                     msr < MSR_IA32_MCx_CTL(bank_num)) {
2659                         u32 offset = array_index_nospec(
2660                                 msr - MSR_IA32_MC0_CTL,
2661                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2662
2663                         /* only 0 or all 1s can be written to IA32_MCi_CTL
2664                          * some Linux kernels though clear bit 10 in bank 4 to
2665                          * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2666                          * this to avoid an uncatched #GP in the guest
2667                          */
2668                         if ((offset & 0x3) == 0 &&
2669                             data != 0 && (data | (1 << 10)) != ~(u64)0)
2670                                 return -1;
2671
2672                         /* MCi_STATUS */
2673                         if (!msr_info->host_initiated &&
2674                             (offset & 0x3) == 1 && data != 0) {
2675                                 if (!can_set_mci_status(vcpu))
2676                                         return -1;
2677                         }
2678
2679                         vcpu->arch.mce_banks[offset] = data;
2680                         break;
2681                 }
2682                 return 1;
2683         }
2684         return 0;
2685 }
2686
2687 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2688 {
2689         struct kvm *kvm = vcpu->kvm;
2690         int lm = is_long_mode(vcpu);
2691         u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2692                 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2693         u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2694                 : kvm->arch.xen_hvm_config.blob_size_32;
2695         u32 page_num = data & ~PAGE_MASK;
2696         u64 page_addr = data & PAGE_MASK;
2697         u8 *page;
2698         int r;
2699
2700         r = -E2BIG;
2701         if (page_num >= blob_size)
2702                 goto out;
2703         r = -ENOMEM;
2704         page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2705         if (IS_ERR(page)) {
2706                 r = PTR_ERR(page);
2707                 goto out;
2708         }
2709         if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
2710                 goto out_free;
2711         r = 0;
2712 out_free:
2713         kfree(page);
2714 out:
2715         return r;
2716 }
2717
2718 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2719 {
2720         u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2721
2722         return (vcpu->arch.apf.msr_en_val & mask) == mask;
2723 }
2724
2725 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2726 {
2727         gpa_t gpa = data & ~0x3f;
2728
2729         /* Bits 4:5 are reserved, Should be zero */
2730         if (data & 0x30)
2731                 return 1;
2732
2733         if (!lapic_in_kernel(vcpu))
2734                 return 1;
2735
2736         vcpu->arch.apf.msr_en_val = data;
2737
2738         if (!kvm_pv_async_pf_enabled(vcpu)) {
2739                 kvm_clear_async_pf_completion_queue(vcpu);
2740                 kvm_async_pf_hash_reset(vcpu);
2741                 return 0;
2742         }
2743
2744         if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2745                                         sizeof(u64)))
2746                 return 1;
2747
2748         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2749         vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2750
2751         kvm_async_pf_wakeup_all(vcpu);
2752
2753         return 0;
2754 }
2755
2756 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2757 {
2758         /* Bits 8-63 are reserved */
2759         if (data >> 8)
2760                 return 1;
2761
2762         if (!lapic_in_kernel(vcpu))
2763                 return 1;
2764
2765         vcpu->arch.apf.msr_int_val = data;
2766
2767         vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2768
2769         return 0;
2770 }
2771
2772 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2773 {
2774         vcpu->arch.pv_time_enabled = false;
2775         vcpu->arch.time = 0;
2776 }
2777
2778 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2779 {
2780         ++vcpu->stat.tlb_flush;
2781         kvm_x86_ops.tlb_flush_all(vcpu);
2782 }
2783
2784 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2785 {
2786         ++vcpu->stat.tlb_flush;
2787         kvm_x86_ops.tlb_flush_guest(vcpu);
2788 }
2789
2790 static void record_steal_time(struct kvm_vcpu *vcpu)
2791 {
2792         struct kvm_host_map map;
2793         struct kvm_steal_time *st;
2794
2795         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2796                 return;
2797
2798         /* -EAGAIN is returned in atomic context so we can just return. */
2799         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2800                         &map, &vcpu->arch.st.cache, false))
2801                 return;
2802
2803         st = map.hva +
2804                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2805
2806         /*
2807          * Doing a TLB flush here, on the guest's behalf, can avoid
2808          * expensive IPIs.
2809          */
2810         trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2811                 st->preempted & KVM_VCPU_FLUSH_TLB);
2812         if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2813                 kvm_vcpu_flush_tlb_guest(vcpu);
2814
2815         vcpu->arch.st.preempted = 0;
2816
2817         if (st->version & 1)
2818                 st->version += 1;  /* first time write, random junk */
2819
2820         st->version += 1;
2821
2822         smp_wmb();
2823
2824         st->steal += current->sched_info.run_delay -
2825                 vcpu->arch.st.last_steal;
2826         vcpu->arch.st.last_steal = current->sched_info.run_delay;
2827
2828         smp_wmb();
2829
2830         st->version += 1;
2831
2832         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2833 }
2834
2835 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2836 {
2837         bool pr = false;
2838         u32 msr = msr_info->index;
2839         u64 data = msr_info->data;
2840
2841         switch (msr) {
2842         case MSR_AMD64_NB_CFG:
2843         case MSR_IA32_UCODE_WRITE:
2844         case MSR_VM_HSAVE_PA:
2845         case MSR_AMD64_PATCH_LOADER:
2846         case MSR_AMD64_BU_CFG2:
2847         case MSR_AMD64_DC_CFG:
2848         case MSR_F15H_EX_CFG:
2849                 break;
2850
2851         case MSR_IA32_UCODE_REV:
2852                 if (msr_info->host_initiated)
2853                         vcpu->arch.microcode_version = data;
2854                 break;
2855         case MSR_IA32_ARCH_CAPABILITIES:
2856                 if (!msr_info->host_initiated)
2857                         return 1;
2858                 vcpu->arch.arch_capabilities = data;
2859                 break;
2860         case MSR_IA32_PERF_CAPABILITIES: {
2861                 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
2862
2863                 if (!msr_info->host_initiated)
2864                         return 1;
2865                 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
2866                         return 1;
2867                 if (data & ~msr_ent.data)
2868                         return 1;
2869
2870                 vcpu->arch.perf_capabilities = data;
2871
2872                 return 0;
2873                 }
2874         case MSR_EFER:
2875                 return set_efer(vcpu, msr_info);
2876         case MSR_K7_HWCR:
2877                 data &= ~(u64)0x40;     /* ignore flush filter disable */
2878                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
2879                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
2880
2881                 /* Handle McStatusWrEn */
2882                 if (data == BIT_ULL(18)) {
2883                         vcpu->arch.msr_hwcr = data;
2884                 } else if (data != 0) {
2885                         vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2886                                     data);
2887                         return 1;
2888                 }
2889                 break;
2890         case MSR_FAM10H_MMIO_CONF_BASE:
2891                 if (data != 0) {
2892                         vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2893                                     "0x%llx\n", data);
2894                         return 1;
2895                 }
2896                 break;
2897         case MSR_IA32_DEBUGCTLMSR:
2898                 if (!data) {
2899                         /* We support the non-activated case already */
2900                         break;
2901                 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2902                         /* Values other than LBR and BTF are vendor-specific,
2903                            thus reserved and should throw a #GP */
2904                         return 1;
2905                 }
2906                 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2907                             __func__, data);
2908                 break;
2909         case 0x200 ... 0x2ff:
2910                 return kvm_mtrr_set_msr(vcpu, msr, data);
2911         case MSR_IA32_APICBASE:
2912                 return kvm_set_apic_base(vcpu, msr_info);
2913         case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
2914                 return kvm_x2apic_msr_write(vcpu, msr, data);
2915         case MSR_IA32_TSCDEADLINE:
2916                 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2917                 break;
2918         case MSR_IA32_TSC_ADJUST:
2919                 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
2920                         if (!msr_info->host_initiated) {
2921                                 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2922                                 adjust_tsc_offset_guest(vcpu, adj);
2923                         }
2924                         vcpu->arch.ia32_tsc_adjust_msr = data;
2925                 }
2926                 break;
2927         case MSR_IA32_MISC_ENABLE:
2928                 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2929                     ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2930                         if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2931                                 return 1;
2932                         vcpu->arch.ia32_misc_enable_msr = data;
2933                         kvm_update_cpuid_runtime(vcpu);
2934                 } else {
2935                         vcpu->arch.ia32_misc_enable_msr = data;
2936                 }
2937                 break;
2938         case MSR_IA32_SMBASE:
2939                 if (!msr_info->host_initiated)
2940                         return 1;
2941                 vcpu->arch.smbase = data;
2942                 break;
2943         case MSR_IA32_POWER_CTL:
2944                 vcpu->arch.msr_ia32_power_ctl = data;
2945                 break;
2946         case MSR_IA32_TSC:
2947                 kvm_write_tsc(vcpu, msr_info);
2948                 break;
2949         case MSR_IA32_XSS:
2950                 if (!msr_info->host_initiated &&
2951                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2952                         return 1;
2953                 /*
2954                  * KVM supports exposing PT to the guest, but does not support
2955                  * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
2956                  * XSAVES/XRSTORS to save/restore PT MSRs.
2957                  */
2958                 if (data & ~supported_xss)
2959                         return 1;
2960                 vcpu->arch.ia32_xss = data;
2961                 break;
2962         case MSR_SMI_COUNT:
2963                 if (!msr_info->host_initiated)
2964                         return 1;
2965                 vcpu->arch.smi_count = data;
2966                 break;
2967         case MSR_KVM_WALL_CLOCK_NEW:
2968         case MSR_KVM_WALL_CLOCK:
2969                 vcpu->kvm->arch.wall_clock = data;
2970                 kvm_write_wall_clock(vcpu->kvm, data);
2971                 break;
2972         case MSR_KVM_SYSTEM_TIME_NEW:
2973         case MSR_KVM_SYSTEM_TIME: {
2974                 struct kvm_arch *ka = &vcpu->kvm->arch;
2975
2976                 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2977                         bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2978
2979                         if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2980                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2981
2982                         ka->boot_vcpu_runs_old_kvmclock = tmp;
2983                 }
2984
2985                 vcpu->arch.time = data;
2986                 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2987
2988                 /* we verify if the enable bit is set... */
2989                 vcpu->arch.pv_time_enabled = false;
2990                 if (!(data & 1))
2991                         break;
2992
2993                 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2994                      &vcpu->arch.pv_time, data & ~1ULL,
2995                      sizeof(struct pvclock_vcpu_time_info)))
2996                         vcpu->arch.pv_time_enabled = true;
2997
2998                 break;
2999         }
3000         case MSR_KVM_ASYNC_PF_EN:
3001                 if (kvm_pv_enable_async_pf(vcpu, data))
3002                         return 1;
3003                 break;
3004         case MSR_KVM_ASYNC_PF_INT:
3005                 if (kvm_pv_enable_async_pf_int(vcpu, data))
3006                         return 1;
3007                 break;
3008         case MSR_KVM_ASYNC_PF_ACK:
3009                 if (data & 0x1) {
3010                         vcpu->arch.apf.pageready_pending = false;
3011                         kvm_check_async_pf_completion(vcpu);
3012                 }
3013                 break;
3014         case MSR_KVM_STEAL_TIME:
3015
3016                 if (unlikely(!sched_info_on()))
3017                         return 1;
3018
3019                 if (data & KVM_STEAL_RESERVED_MASK)
3020                         return 1;
3021
3022                 vcpu->arch.st.msr_val = data;
3023
3024                 if (!(data & KVM_MSR_ENABLED))
3025                         break;
3026
3027                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3028
3029                 break;
3030         case MSR_KVM_PV_EOI_EN:
3031                 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3032                         return 1;
3033                 break;
3034
3035         case MSR_KVM_POLL_CONTROL:
3036                 /* only enable bit supported */
3037                 if (data & (-1ULL << 1))
3038                         return 1;
3039
3040                 vcpu->arch.msr_kvm_poll_control = data;
3041                 break;
3042
3043         case MSR_IA32_MCG_CTL:
3044         case MSR_IA32_MCG_STATUS:
3045         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3046                 return set_msr_mce(vcpu, msr_info);
3047
3048         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3049         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3050                 pr = true;
3051                 fallthrough;
3052         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3053         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3054                 if (kvm_pmu_is_valid_msr(vcpu, msr))
3055                         return kvm_pmu_set_msr(vcpu, msr_info);
3056
3057                 if (pr || data != 0)
3058                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3059                                     "0x%x data 0x%llx\n", msr, data);
3060                 break;
3061         case MSR_K7_CLK_CTL:
3062                 /*
3063                  * Ignore all writes to this no longer documented MSR.
3064                  * Writes are only relevant for old K7 processors,
3065                  * all pre-dating SVM, but a recommended workaround from
3066                  * AMD for these chips. It is possible to specify the
3067                  * affected processor models on the command line, hence
3068                  * the need to ignore the workaround.
3069                  */
3070                 break;
3071         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3072         case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3073         case HV_X64_MSR_SYNDBG_OPTIONS:
3074         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3075         case HV_X64_MSR_CRASH_CTL:
3076         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3077         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3078         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3079         case HV_X64_MSR_TSC_EMULATION_STATUS:
3080                 return kvm_hv_set_msr_common(vcpu, msr, data,
3081                                              msr_info->host_initiated);
3082         case MSR_IA32_BBL_CR_CTL3:
3083                 /* Drop writes to this legacy MSR -- see rdmsr
3084                  * counterpart for further detail.
3085                  */
3086                 if (report_ignored_msrs)
3087                         vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3088                                 msr, data);
3089                 break;
3090         case MSR_AMD64_OSVW_ID_LENGTH:
3091                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3092                         return 1;
3093                 vcpu->arch.osvw.length = data;
3094                 break;
3095         case MSR_AMD64_OSVW_STATUS:
3096                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3097                         return 1;
3098                 vcpu->arch.osvw.status = data;
3099                 break;
3100         case MSR_PLATFORM_INFO:
3101                 if (!msr_info->host_initiated ||
3102                     (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3103                      cpuid_fault_enabled(vcpu)))
3104                         return 1;
3105                 vcpu->arch.msr_platform_info = data;
3106                 break;
3107         case MSR_MISC_FEATURES_ENABLES:
3108                 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3109                     (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3110                      !supports_cpuid_fault(vcpu)))
3111                         return 1;
3112                 vcpu->arch.msr_misc_features_enables = data;
3113                 break;
3114         default:
3115                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3116                         return xen_hvm_config(vcpu, data);
3117                 if (kvm_pmu_is_valid_msr(vcpu, msr))
3118                         return kvm_pmu_set_msr(vcpu, msr_info);
3119                 return KVM_MSR_RET_INVALID;
3120         }
3121         return 0;
3122 }
3123 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3124
3125 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3126 {
3127         u64 data;
3128         u64 mcg_cap = vcpu->arch.mcg_cap;
3129         unsigned bank_num = mcg_cap & 0xff;
3130
3131         switch (msr) {
3132         case MSR_IA32_P5_MC_ADDR:
3133         case MSR_IA32_P5_MC_TYPE:
3134                 data = 0;
3135                 break;
3136         case MSR_IA32_MCG_CAP:
3137                 data = vcpu->arch.mcg_cap;
3138                 break;
3139         case MSR_IA32_MCG_CTL:
3140                 if (!(mcg_cap & MCG_CTL_P) && !host)
3141                         return 1;
3142                 data = vcpu->arch.mcg_ctl;
3143                 break;
3144         case MSR_IA32_MCG_STATUS:
3145                 data = vcpu->arch.mcg_status;
3146                 break;
3147         default:
3148                 if (msr >= MSR_IA32_MC0_CTL &&
3149                     msr < MSR_IA32_MCx_CTL(bank_num)) {
3150                         u32 offset = array_index_nospec(
3151                                 msr - MSR_IA32_MC0_CTL,
3152                                 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3153
3154                         data = vcpu->arch.mce_banks[offset];
3155                         break;
3156                 }
3157                 return 1;
3158         }
3159         *pdata = data;
3160         return 0;
3161 }
3162
3163 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3164 {
3165         switch (msr_info->index) {
3166         case MSR_IA32_PLATFORM_ID:
3167         case MSR_IA32_EBL_CR_POWERON:
3168         case MSR_IA32_DEBUGCTLMSR:
3169         case MSR_IA32_LASTBRANCHFROMIP:
3170         case MSR_IA32_LASTBRANCHTOIP:
3171         case MSR_IA32_LASTINTFROMIP:
3172         case MSR_IA32_LASTINTTOIP:
3173         case MSR_K8_SYSCFG:
3174         case MSR_K8_TSEG_ADDR:
3175         case MSR_K8_TSEG_MASK:
3176         case MSR_VM_HSAVE_PA:
3177         case MSR_K8_INT_PENDING_MSG:
3178         case MSR_AMD64_NB_CFG:
3179         case MSR_FAM10H_MMIO_CONF_BASE:
3180         case MSR_AMD64_BU_CFG2:
3181         case MSR_IA32_PERF_CTL:
3182         case MSR_AMD64_DC_CFG:
3183         case MSR_F15H_EX_CFG:
3184         /*
3185          * Intel Sandy Bridge CPUs must support the RAPL (running average power
3186          * limit) MSRs. Just return 0, as we do not want to expose the host
3187          * data here. Do not conditionalize this on CPUID, as KVM does not do
3188          * so for existing CPU-specific MSRs.
3189          */
3190         case MSR_RAPL_POWER_UNIT:
3191         case MSR_PP0_ENERGY_STATUS:     /* Power plane 0 (core) */
3192         case MSR_PP1_ENERGY_STATUS:     /* Power plane 1 (graphics uncore) */
3193         case MSR_PKG_ENERGY_STATUS:     /* Total package */
3194         case MSR_DRAM_ENERGY_STATUS:    /* DRAM controller */
3195                 msr_info->data = 0;
3196                 break;
3197         case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3198         case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3199         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3200         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3201         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3202                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3203                         return kvm_pmu_get_msr(vcpu, msr_info);
3204                 msr_info->data = 0;
3205                 break;
3206         case MSR_IA32_UCODE_REV:
3207                 msr_info->data = vcpu->arch.microcode_version;
3208                 break;
3209         case MSR_IA32_ARCH_CAPABILITIES:
3210                 if (!msr_info->host_initiated &&
3211                     !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3212                         return 1;
3213                 msr_info->data = vcpu->arch.arch_capabilities;
3214                 break;
3215         case MSR_IA32_PERF_CAPABILITIES:
3216                 if (!msr_info->host_initiated &&
3217                     !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3218                         return 1;
3219                 msr_info->data = vcpu->arch.perf_capabilities;
3220                 break;
3221         case MSR_IA32_POWER_CTL:
3222                 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3223                 break;
3224         case MSR_IA32_TSC:
3225                 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3226                 break;
3227         case MSR_MTRRcap:
3228         case 0x200 ... 0x2ff:
3229                 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3230         case 0xcd: /* fsb frequency */
3231                 msr_info->data = 3;
3232                 break;
3233                 /*
3234                  * MSR_EBC_FREQUENCY_ID
3235                  * Conservative value valid for even the basic CPU models.
3236                  * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3237                  * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3238                  * and 266MHz for model 3, or 4. Set Core Clock
3239                  * Frequency to System Bus Frequency Ratio to 1 (bits
3240                  * 31:24) even though these are only valid for CPU
3241                  * models > 2, however guests may end up dividing or
3242                  * multiplying by zero otherwise.
3243                  */
3244         case MSR_EBC_FREQUENCY_ID:
3245                 msr_info->data = 1 << 24;
3246                 break;
3247         case MSR_IA32_APICBASE:
3248                 msr_info->data = kvm_get_apic_base(vcpu);
3249                 break;
3250         case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3251                 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3252         case MSR_IA32_TSCDEADLINE:
3253                 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3254                 break;
3255         case MSR_IA32_TSC_ADJUST:
3256                 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3257                 break;
3258         case MSR_IA32_MISC_ENABLE:
3259                 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3260                 break;
3261         case MSR_IA32_SMBASE:
3262                 if (!msr_info->host_initiated)
3263                         return 1;
3264                 msr_info->data = vcpu->arch.smbase;
3265                 break;
3266         case MSR_SMI_COUNT:
3267                 msr_info->data = vcpu->arch.smi_count;
3268                 break;
3269         case MSR_IA32_PERF_STATUS:
3270                 /* TSC increment by tick */
3271                 msr_info->data = 1000ULL;
3272                 /* CPU multiplier */
3273                 msr_info->data |= (((uint64_t)4ULL) << 40);
3274                 break;
3275         case MSR_EFER:
3276                 msr_info->data = vcpu->arch.efer;
3277                 break;
3278         case MSR_KVM_WALL_CLOCK:
3279         case MSR_KVM_WALL_CLOCK_NEW:
3280                 msr_info->data = vcpu->kvm->arch.wall_clock;
3281                 break;
3282         case MSR_KVM_SYSTEM_TIME:
3283         case MSR_KVM_SYSTEM_TIME_NEW:
3284                 msr_info->data = vcpu->arch.time;
3285                 break;
3286         case MSR_KVM_ASYNC_PF_EN:
3287                 msr_info->data = vcpu->arch.apf.msr_en_val;
3288                 break;
3289         case MSR_KVM_ASYNC_PF_INT:
3290                 msr_info->data = vcpu->arch.apf.msr_int_val;
3291                 break;
3292         case MSR_KVM_ASYNC_PF_ACK:
3293                 msr_info->data = 0;
3294                 break;
3295         case MSR_KVM_STEAL_TIME:
3296                 msr_info->data = vcpu->arch.st.msr_val;
3297                 break;
3298         case MSR_KVM_PV_EOI_EN:
3299                 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3300                 break;
3301         case MSR_KVM_POLL_CONTROL:
3302                 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3303                 break;
3304         case MSR_IA32_P5_MC_ADDR:
3305         case MSR_IA32_P5_MC_TYPE:
3306         case MSR_IA32_MCG_CAP:
3307         case MSR_IA32_MCG_CTL:
3308         case MSR_IA32_MCG_STATUS:
3309         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3310                 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3311                                    msr_info->host_initiated);
3312         case MSR_IA32_XSS:
3313                 if (!msr_info->host_initiated &&
3314                     !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3315                         return 1;
3316                 msr_info->data = vcpu->arch.ia32_xss;
3317                 break;
3318         case MSR_K7_CLK_CTL:
3319                 /*
3320                  * Provide expected ramp-up count for K7. All other
3321                  * are set to zero, indicating minimum divisors for
3322                  * every field.
3323                  *
3324                  * This prevents guest kernels on AMD host with CPU
3325                  * type 6, model 8 and higher from exploding due to
3326                  * the rdmsr failing.
3327                  */
3328                 msr_info->data = 0x20000000;
3329                 break;
3330         case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3331         case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3332         case HV_X64_MSR_SYNDBG_OPTIONS:
3333         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3334         case HV_X64_MSR_CRASH_CTL:
3335         case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3336         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3337         case HV_X64_MSR_TSC_EMULATION_CONTROL:
3338         case HV_X64_MSR_TSC_EMULATION_STATUS:
3339                 return kvm_hv_get_msr_common(vcpu,
3340                                              msr_info->index, &msr_info->data,
3341                                              msr_info->host_initiated);
3342         case MSR_IA32_BBL_CR_CTL3:
3343                 /* This legacy MSR exists but isn't fully documented in current
3344                  * silicon.  It is however accessed by winxp in very narrow
3345                  * scenarios where it sets bit #19, itself documented as
3346                  * a "reserved" bit.  Best effort attempt to source coherent
3347                  * read data here should the balance of the register be
3348                  * interpreted by the guest:
3349                  *
3350                  * L2 cache control register 3: 64GB range, 256KB size,
3351                  * enabled, latency 0x1, configured
3352                  */
3353                 msr_info->data = 0xbe702111;
3354                 break;
3355         case MSR_AMD64_OSVW_ID_LENGTH:
3356                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3357                         return 1;
3358                 msr_info->data = vcpu->arch.osvw.length;
3359                 break;
3360         case MSR_AMD64_OSVW_STATUS:
3361                 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3362                         return 1;
3363                 msr_info->data = vcpu->arch.osvw.status;
3364                 break;
3365         case MSR_PLATFORM_INFO:
3366                 if (!msr_info->host_initiated &&
3367                     !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3368                         return 1;
3369                 msr_info->data = vcpu->arch.msr_platform_info;
3370                 break;
3371         case MSR_MISC_FEATURES_ENABLES:
3372                 msr_info->data = vcpu->arch.msr_misc_features_enables;
3373                 break;
3374         case MSR_K7_HWCR:
3375                 msr_info->data = vcpu->arch.msr_hwcr;
3376                 break;
3377         default:
3378                 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3379                         return kvm_pmu_get_msr(vcpu, msr_info);
3380                 return KVM_MSR_RET_INVALID;
3381         }
3382         return 0;
3383 }
3384 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3385
3386 /*
3387  * Read or write a bunch of msrs. All parameters are kernel addresses.
3388  *
3389  * @return number of msrs set successfully.
3390  */
3391 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3392                     struct kvm_msr_entry *entries,
3393                     int (*do_msr)(struct kvm_vcpu *vcpu,
3394                                   unsigned index, u64 *data))
3395 {
3396         int i;
3397
3398         for (i = 0; i < msrs->nmsrs; ++i)
3399                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3400                         break;
3401
3402         return i;
3403 }
3404
3405 /*
3406  * Read or write a bunch of msrs. Parameters are user addresses.
3407  *
3408  * @return number of msrs set successfully.
3409  */
3410 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3411                   int (*do_msr)(struct kvm_vcpu *vcpu,
3412                                 unsigned index, u64 *data),
3413                   int writeback)
3414 {
3415         struct kvm_msrs msrs;
3416         struct kvm_msr_entry *entries;
3417         int r, n;
3418         unsigned size;
3419
3420         r = -EFAULT;
3421         if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3422                 goto out;
3423
3424         r = -E2BIG;
3425         if (msrs.nmsrs >= MAX_IO_MSRS)
3426                 goto out;
3427
3428         size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3429         entries = memdup_user(user_msrs->entries, size);
3430         if (IS_ERR(entries)) {
3431                 r = PTR_ERR(entries);
3432                 goto out;
3433         }
3434
3435         r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3436         if (r < 0)
3437                 goto out_free;
3438
3439         r = -EFAULT;
3440         if (writeback && copy_to_user(user_msrs->entries, entries, size))
3441                 goto out_free;
3442
3443         r = n;
3444
3445 out_free:
3446         kfree(entries);
3447 out:
3448         return r;
3449 }
3450
3451 static inline bool kvm_can_mwait_in_guest(void)
3452 {
3453         return boot_cpu_has(X86_FEATURE_MWAIT) &&
3454                 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3455                 boot_cpu_has(X86_FEATURE_ARAT);
3456 }
3457
3458 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3459 {
3460         int r = 0;
3461
3462         switch (ext) {
3463         case KVM_CAP_IRQCHIP:
3464         case KVM_CAP_HLT:
3465         case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3466         case KVM_CAP_SET_TSS_ADDR:
3467         case KVM_CAP_EXT_CPUID:
3468         case KVM_CAP_EXT_EMUL_CPUID:
3469         case KVM_CAP_CLOCKSOURCE:
3470         case KVM_CAP_PIT:
3471         case KVM_CAP_NOP_IO_DELAY:
3472         case KVM_CAP_MP_STATE:
3473         case KVM_CAP_SYNC_MMU:
3474         case KVM_CAP_USER_NMI:
3475         case KVM_CAP_REINJECT_CONTROL:
3476         case KVM_CAP_IRQ_INJECT_STATUS:
3477         case KVM_CAP_IOEVENTFD:
3478         case KVM_CAP_IOEVENTFD_NO_LENGTH:
3479         case KVM_CAP_PIT2:
3480         case KVM_CAP_PIT_STATE2:
3481         case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3482         case KVM_CAP_XEN_HVM:
3483         case KVM_CAP_VCPU_EVENTS:
3484         case KVM_CAP_HYPERV:
3485         case KVM_CAP_HYPERV_VAPIC:
3486         case KVM_CAP_HYPERV_SPIN:
3487         case KVM_CAP_HYPERV_SYNIC:
3488         case KVM_CAP_HYPERV_SYNIC2:
3489         case KVM_CAP_HYPERV_VP_INDEX:
3490         case KVM_CAP_HYPERV_EVENTFD:
3491         case KVM_CAP_HYPERV_TLBFLUSH:
3492         case KVM_CAP_HYPERV_SEND_IPI:
3493         case KVM_CAP_HYPERV_CPUID:
3494         case KVM_CAP_PCI_SEGMENT:
3495         case KVM_CAP_DEBUGREGS:
3496         case KVM_CAP_X86_ROBUST_SINGLESTEP:
3497         case KVM_CAP_XSAVE:
3498         case KVM_CAP_ASYNC_PF:
3499         case KVM_CAP_ASYNC_PF_INT:
3500         case KVM_CAP_GET_TSC_KHZ:
3501         case KVM_CAP_KVMCLOCK_CTRL:
3502         case KVM_CAP_READONLY_MEM:
3503         case KVM_CAP_HYPERV_TIME:
3504         case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3505         case KVM_CAP_TSC_DEADLINE_TIMER:
3506         case KVM_CAP_DISABLE_QUIRKS:
3507         case KVM_CAP_SET_BOOT_CPU_ID:
3508         case KVM_CAP_SPLIT_IRQCHIP:
3509         case KVM_CAP_IMMEDIATE_EXIT:
3510         case KVM_CAP_PMU_EVENT_FILTER:
3511         case KVM_CAP_GET_MSR_FEATURES:
3512         case KVM_CAP_MSR_PLATFORM_INFO:
3513         case KVM_CAP_EXCEPTION_PAYLOAD:
3514         case KVM_CAP_SET_GUEST_DEBUG:
3515         case KVM_CAP_LAST_CPU:
3516                 r = 1;
3517                 break;
3518         case KVM_CAP_SYNC_REGS:
3519                 r = KVM_SYNC_X86_VALID_FIELDS;
3520                 break;
3521         case KVM_CAP_ADJUST_CLOCK:
3522                 r = KVM_CLOCK_TSC_STABLE;
3523                 break;
3524         case KVM_CAP_X86_DISABLE_EXITS:
3525                 r |=  KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3526                       KVM_X86_DISABLE_EXITS_CSTATE;
3527                 if(kvm_can_mwait_in_guest())
3528                         r |= KVM_X86_DISABLE_EXITS_MWAIT;
3529                 break;
3530         case KVM_CAP_X86_SMM:
3531                 /* SMBASE is usually relocated above 1M on modern chipsets,
3532                  * and SMM handlers might indeed rely on 4G segment limits,
3533                  * so do not report SMM to be available if real mode is
3534                  * emulated via vm86 mode.  Still, do not go to great lengths
3535                  * to avoid userspace's usage of the feature, because it is a
3536                  * fringe case that is not enabled except via specific settings
3537                  * of the module parameters.
3538                  */
3539                 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3540                 break;
3541         case KVM_CAP_VAPIC:
3542                 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3543                 break;
3544         case KVM_CAP_NR_VCPUS:
3545                 r = KVM_SOFT_MAX_VCPUS;
3546                 break;
3547         case KVM_CAP_MAX_VCPUS:
3548                 r = KVM_MAX_VCPUS;
3549                 break;
3550         case KVM_CAP_MAX_VCPU_ID:
3551                 r = KVM_MAX_VCPU_ID;
3552                 break;
3553         case KVM_CAP_PV_MMU:    /* obsolete */
3554                 r = 0;
3555                 break;
3556         case KVM_CAP_MCE:
3557                 r = KVM_MAX_MCE_BANKS;
3558                 break;
3559         case KVM_CAP_XCRS:
3560                 r = boot_cpu_has(X86_FEATURE_XSAVE);
3561                 break;
3562         case KVM_CAP_TSC_CONTROL:
3563                 r = kvm_has_tsc_control;
3564                 break;
3565         case KVM_CAP_X2APIC_API:
3566                 r = KVM_X2APIC_API_VALID_FLAGS;
3567                 break;
3568         case KVM_CAP_NESTED_STATE:
3569                 r = kvm_x86_ops.nested_ops->get_state ?
3570                         kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3571                 break;
3572         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3573                 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3574                 break;
3575         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3576                 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3577                 break;
3578         case KVM_CAP_SMALLER_MAXPHYADDR:
3579                 r = (int) allow_smaller_maxphyaddr;
3580                 break;
3581         case KVM_CAP_STEAL_TIME:
3582                 r = sched_info_on();
3583                 break;
3584         default:
3585                 break;
3586         }
3587         return r;
3588
3589 }
3590
3591 long kvm_arch_dev_ioctl(struct file *filp,
3592                         unsigned int ioctl, unsigned long arg)
3593 {
3594         void __user *argp = (void __user *)arg;
3595         long r;
3596
3597         switch (ioctl) {
3598         case KVM_GET_MSR_INDEX_LIST: {
3599                 struct kvm_msr_list __user *user_msr_list = argp;
3600                 struct kvm_msr_list msr_list;
3601                 unsigned n;
3602
3603                 r = -EFAULT;
3604                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3605                         goto out;
3606                 n = msr_list.nmsrs;
3607                 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3608                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3609                         goto out;
3610                 r = -E2BIG;
3611                 if (n < msr_list.nmsrs)
3612                         goto out;
3613                 r = -EFAULT;
3614                 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3615                                  num_msrs_to_save * sizeof(u32)))
3616                         goto out;
3617                 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3618                                  &emulated_msrs,
3619                                  num_emulated_msrs * sizeof(u32)))
3620                         goto out;
3621                 r = 0;
3622                 break;
3623         }
3624         case KVM_GET_SUPPORTED_CPUID:
3625         case KVM_GET_EMULATED_CPUID: {
3626                 struct kvm_cpuid2 __user *cpuid_arg = argp;
3627                 struct kvm_cpuid2 cpuid;
3628
3629                 r = -EFAULT;
3630                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3631                         goto out;
3632
3633                 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3634                                             ioctl);
3635                 if (r)
3636                         goto out;
3637
3638                 r = -EFAULT;
3639                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3640                         goto out;
3641                 r = 0;
3642                 break;
3643         }
3644         case KVM_X86_GET_MCE_CAP_SUPPORTED:
3645                 r = -EFAULT;
3646                 if (copy_to_user(argp, &kvm_mce_cap_supported,
3647                                  sizeof(kvm_mce_cap_supported)))
3648                         goto out;
3649                 r = 0;
3650                 break;
3651         case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3652                 struct kvm_msr_list __user *user_msr_list = argp;
3653                 struct kvm_msr_list msr_list;
3654                 unsigned int n;
3655
3656                 r = -EFAULT;
3657                 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3658                         goto out;
3659                 n = msr_list.nmsrs;
3660                 msr_list.nmsrs = num_msr_based_features;
3661                 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3662                         goto out;
3663                 r = -E2BIG;
3664                 if (n < msr_list.nmsrs)
3665                         goto out;
3666                 r = -EFAULT;
3667                 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3668                                  num_msr_based_features * sizeof(u32)))
3669                         goto out;
3670                 r = 0;
3671                 break;
3672         }
3673         case KVM_GET_MSRS:
3674                 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3675                 break;
3676         default:
3677                 r = -EINVAL;
3678                 break;
3679         }
3680 out:
3681         return r;
3682 }
3683
3684 static void wbinvd_ipi(void *garbage)
3685 {
3686         wbinvd();
3687 }
3688
3689 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3690 {
3691         return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3692 }
3693
3694 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3695 {
3696         /* Address WBINVD may be executed by guest */
3697         if (need_emulate_wbinvd(vcpu)) {
3698                 if (kvm_x86_ops.has_wbinvd_exit())
3699                         cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3700                 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3701                         smp_call_function_single(vcpu->cpu,
3702                                         wbinvd_ipi, NULL, 1);
3703         }
3704
3705         kvm_x86_ops.vcpu_load(vcpu, cpu);
3706
3707         /* Save host pkru register if supported */
3708         vcpu->arch.host_pkru = read_pkru();
3709
3710         /* Apply any externally detected TSC adjustments (due to suspend) */
3711         if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3712                 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3713                 vcpu->arch.tsc_offset_adjustment = 0;
3714                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3715         }
3716
3717         if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3718                 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3719                                 rdtsc() - vcpu->arch.last_host_tsc;
3720                 if (tsc_delta < 0)
3721                         mark_tsc_unstable("KVM discovered backwards TSC");
3722
3723                 if (kvm_check_tsc_unstable()) {
3724                         u64 offset = kvm_compute_tsc_offset(vcpu,
3725                                                 vcpu->arch.last_guest_tsc);
3726                         kvm_vcpu_write_tsc_offset(vcpu, offset);
3727                         vcpu->arch.tsc_catchup = 1;
3728                 }
3729
3730                 if (kvm_lapic_hv_timer_in_use(vcpu))
3731                         kvm_lapic_restart_hv_timer(vcpu);
3732
3733                 /*
3734                  * On a host with synchronized TSC, there is no need to update
3735                  * kvmclock on vcpu->cpu migration
3736                  */
3737                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3738                         kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3739                 if (vcpu->cpu != cpu)
3740                         kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3741                 vcpu->cpu = cpu;
3742         }
3743
3744         kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3745 }
3746
3747 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3748 {
3749         struct kvm_host_map map;
3750         struct kvm_steal_time *st;
3751
3752         if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3753                 return;
3754
3755         if (vcpu->arch.st.preempted)
3756                 return;
3757
3758         if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3759                         &vcpu->arch.st.cache, true))
3760                 return;
3761
3762         st = map.hva +
3763                 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
3764
3765         st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
3766
3767         kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
3768 }
3769
3770 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3771 {
3772         int idx;
3773
3774         if (vcpu->preempted)
3775                 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
3776
3777         /*
3778          * Disable page faults because we're in atomic context here.
3779          * kvm_write_guest_offset_cached() would call might_fault()
3780          * that relies on pagefault_disable() to tell if there's a
3781          * bug. NOTE: the write to guest memory may not go through if
3782          * during postcopy live migration or if there's heavy guest
3783          * paging.
3784          */
3785         pagefault_disable();
3786         /*
3787          * kvm_memslots() will be called by
3788          * kvm_write_guest_offset_cached() so take the srcu lock.
3789          */
3790         idx = srcu_read_lock(&vcpu->kvm->srcu);
3791         kvm_steal_time_set_preempted(vcpu);
3792         srcu_read_unlock(&vcpu->kvm->srcu, idx);
3793         pagefault_enable();
3794         kvm_x86_ops.vcpu_put(vcpu);
3795         vcpu->arch.last_host_tsc = rdtsc();
3796         /*
3797          * If userspace has set any breakpoints or watchpoints, dr6 is restored
3798          * on every vmexit, but if not, we might have a stale dr6 from the
3799          * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3800          */
3801         set_debugreg(0, 6);
3802 }
3803
3804 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3805                                     struct kvm_lapic_state *s)
3806 {
3807         if (vcpu->arch.apicv_active)
3808                 kvm_x86_ops.sync_pir_to_irr(vcpu);
3809
3810         return kvm_apic_get_state(vcpu, s);
3811 }
3812
3813 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3814                                     struct kvm_lapic_state *s)
3815 {
3816         int r;
3817
3818         r = kvm_apic_set_state(vcpu, s);
3819         if (r)
3820                 return r;
3821         update_cr8_intercept(vcpu);
3822
3823         return 0;
3824 }
3825
3826 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3827 {
3828         return (!lapic_in_kernel(vcpu) ||
3829                 kvm_apic_accept_pic_intr(vcpu));
3830 }
3831
3832 /*
3833  * if userspace requested an interrupt window, check that the
3834  * interrupt window is open.
3835  *
3836  * No need to exit to userspace if we already have an interrupt queued.
3837  */
3838 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3839 {
3840         return kvm_arch_interrupt_allowed(vcpu) &&
3841                 !kvm_cpu_has_interrupt(vcpu) &&
3842                 !kvm_event_needs_reinjection(vcpu) &&
3843                 kvm_cpu_accept_dm_intr(vcpu);
3844 }
3845
3846 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3847                                     struct kvm_interrupt *irq)
3848 {
3849         if (irq->irq >= KVM_NR_INTERRUPTS)
3850                 return -EINVAL;
3851
3852         if (!irqchip_in_kernel(vcpu->kvm)) {
3853                 kvm_queue_interrupt(vcpu, irq->irq, false);
3854                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3855                 return 0;
3856         }
3857
3858         /*
3859          * With in-kernel LAPIC, we only use this to inject EXTINT, so
3860          * fail for in-kernel 8259.
3861          */
3862         if (pic_in_kernel(vcpu->kvm))
3863                 return -ENXIO;
3864
3865         if (vcpu->arch.pending_external_vector != -1)
3866                 return -EEXIST;
3867
3868         vcpu->arch.pending_external_vector = irq->irq;
3869         kvm_make_request(KVM_REQ_EVENT, vcpu);
3870         return 0;
3871 }
3872
3873 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3874 {
3875         kvm_inject_nmi(vcpu);
3876
3877         return 0;
3878 }
3879
3880 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3881 {
3882         kvm_make_request(KVM_REQ_SMI, vcpu);
3883
3884         return 0;
3885 }
3886
3887 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3888                                            struct kvm_tpr_access_ctl *tac)
3889 {
3890         if (tac->flags)
3891                 return -EINVAL;
3892         vcpu->arch.tpr_access_reporting = !!tac->enabled;
3893         return 0;
3894 }
3895
3896 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3897                                         u64 mcg_cap)
3898 {
3899         int r;
3900         unsigned bank_num = mcg_cap & 0xff, bank;
3901
3902         r = -EINVAL;
3903         if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
3904                 goto out;
3905         if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
3906                 goto out;
3907         r = 0;
3908         vcpu->arch.mcg_cap = mcg_cap;
3909         /* Init IA32_MCG_CTL to all 1s */
3910         if (mcg_cap & MCG_CTL_P)
3911                 vcpu->arch.mcg_ctl = ~(u64)0;
3912         /* Init IA32_MCi_CTL to all 1s */
3913         for (bank = 0; bank < bank_num; bank++)
3914                 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3915
3916         kvm_x86_ops.setup_mce(vcpu);
3917 out:
3918         return r;
3919 }
3920
3921 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3922                                       struct kvm_x86_mce *mce)
3923 {
3924         u64 mcg_cap = vcpu->arch.mcg_cap;
3925         unsigned bank_num = mcg_cap & 0xff;
3926         u64 *banks = vcpu->arch.mce_banks;
3927
3928         if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3929                 return -EINVAL;
3930         /*
3931          * if IA32_MCG_CTL is not all 1s, the uncorrected error
3932          * reporting is disabled
3933          */
3934         if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3935             vcpu->arch.mcg_ctl != ~(u64)0)
3936                 return 0;
3937         banks += 4 * mce->bank;
3938         /*
3939          * if IA32_MCi_CTL is not all 1s, the uncorrected error
3940          * reporting is disabled for the bank
3941          */
3942         if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3943                 return 0;
3944         if (mce->status & MCI_STATUS_UC) {
3945                 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
3946                     !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
3947                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3948                         return 0;
3949                 }
3950                 if (banks[1] & MCI_STATUS_VAL)
3951                         mce->status |= MCI_STATUS_OVER;
3952                 banks[2] = mce->addr;
3953                 banks[3] = mce->misc;
3954                 vcpu->arch.mcg_status = mce->mcg_status;
3955                 banks[1] = mce->status;
3956                 kvm_queue_exception(vcpu, MC_VECTOR);
3957         } else if (!(banks[1] & MCI_STATUS_VAL)
3958                    || !(banks[1] & MCI_STATUS_UC)) {
3959                 if (banks[1] & MCI_STATUS_VAL)
3960                         mce->status |= MCI_STATUS_OVER;
3961                 banks[2] = mce->addr;
3962                 banks[3] = mce->misc;
3963                 banks[1] = mce->status;
3964         } else
3965                 banks[1] |= MCI_STATUS_OVER;
3966         return 0;
3967 }
3968
3969 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3970                                                struct kvm_vcpu_events *events)
3971 {
3972         process_nmi(vcpu);
3973
3974         /*
3975          * In guest mode, payload delivery should be deferred,
3976          * so that the L1 hypervisor can intercept #PF before
3977          * CR2 is modified (or intercept #DB before DR6 is
3978          * modified under nVMX). Unless the per-VM capability,
3979          * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
3980          * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
3981          * opportunistically defer the exception payload, deliver it if the
3982          * capability hasn't been requested before processing a
3983          * KVM_GET_VCPU_EVENTS.
3984          */
3985         if (!vcpu->kvm->arch.exception_payload_enabled &&
3986             vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
3987                 kvm_deliver_exception_payload(vcpu);
3988
3989         /*
3990          * The API doesn't provide the instruction length for software
3991          * exceptions, so don't report them. As long as the guest RIP
3992          * isn't advanced, we should expect to encounter the exception
3993          * again.
3994          */
3995         if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3996                 events->exception.injected = 0;
3997                 events->exception.pending = 0;
3998         } else {
3999                 events->exception.injected = vcpu->arch.exception.injected;
4000                 events->exception.pending = vcpu->arch.exception.pending;
4001                 /*
4002                  * For ABI compatibility, deliberately conflate
4003                  * pending and injected exceptions when
4004                  * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4005                  */
4006                 if (!vcpu->kvm->arch.exception_payload_enabled)
4007                         events->exception.injected |=
4008                                 vcpu->arch.exception.pending;
4009         }
4010         events->exception.nr = vcpu->arch.exception.nr;
4011         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4012         events->exception.error_code = vcpu->arch.exception.error_code;
4013         events->exception_has_payload = vcpu->arch.exception.has_payload;
4014         events->exception_payload = vcpu->arch.exception.payload;
4015
4016         events->interrupt.injected =
4017                 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4018         events->interrupt.nr = vcpu->arch.interrupt.nr;
4019         events->interrupt.soft = 0;
4020         events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4021
4022         events->nmi.injected = vcpu->arch.nmi_injected;
4023         events->nmi.pending = vcpu->arch.nmi_pending != 0;
4024         events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4025         events->nmi.pad = 0;
4026
4027         events->sipi_vector = 0; /* never valid when reporting to user space */
4028
4029         events->smi.smm = is_smm(vcpu);
4030         events->smi.pending = vcpu->arch.smi_pending;
4031         events->smi.smm_inside_nmi =
4032                 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4033         events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4034
4035         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4036                          | KVM_VCPUEVENT_VALID_SHADOW
4037                          | KVM_VCPUEVENT_VALID_SMM);
4038         if (vcpu->kvm->arch.exception_payload_enabled)
4039                 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4040
4041         memset(&events->reserved, 0, sizeof(events->reserved));
4042 }
4043
4044 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4045
4046 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4047                                               struct kvm_vcpu_events *events)
4048 {
4049         if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4050                               | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4051                               | KVM_VCPUEVENT_VALID_SHADOW
4052                               | KVM_VCPUEVENT_VALID_SMM
4053                               | KVM_VCPUEVENT_VALID_PAYLOAD))
4054                 return -EINVAL;
4055
4056         if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4057                 if (!vcpu->kvm->arch.exception_payload_enabled)
4058                         return -EINVAL;
4059                 if (events->exception.pending)
4060                         events->exception.injected = 0;
4061                 else
4062                         events->exception_has_payload = 0;
4063         } else {
4064                 events->exception.pending = 0;
4065                 events->exception_has_payload = 0;
4066         }
4067
4068         if ((events->exception.injected || events->exception.pending) &&
4069             (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4070                 return -EINVAL;
4071
4072         /* INITs are latched while in SMM */
4073         if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4074             (events->smi.smm || events->smi.pending) &&
4075             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4076                 return -EINVAL;
4077
4078         process_nmi(vcpu);
4079         vcpu->arch.exception.injected = events->exception.injected;
4080         vcpu->arch.exception.pending = events->exception.pending;
4081         vcpu->arch.exception.nr = events->exception.nr;
4082         vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4083         vcpu->arch.exception.error_code = events->exception.error_code;
4084         vcpu->arch.exception.has_payload = events->exception_has_payload;
4085         vcpu->arch.exception.payload = events->exception_payload;
4086
4087         vcpu->arch.interrupt.injected = events->interrupt.injected;
4088         vcpu->arch.interrupt.nr = events->interrupt.nr;
4089         vcpu->arch.interrupt.soft = events->interrupt.soft;
4090         if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4091                 kvm_x86_ops.set_interrupt_shadow(vcpu,
4092                                                   events->interrupt.shadow);
4093
4094         vcpu->arch.nmi_injected = events->nmi.injected;
4095         if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4096                 vcpu->arch.nmi_pending = events->nmi.pending;
4097         kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4098
4099         if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4100             lapic_in_kernel(vcpu))
4101                 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4102
4103         if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4104                 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4105                         if (events->smi.smm)
4106                                 vcpu->arch.hflags |= HF_SMM_MASK;
4107                         else
4108                                 vcpu->arch.hflags &= ~HF_SMM_MASK;
4109                         kvm_smm_changed(vcpu);
4110                 }
4111
4112                 vcpu->arch.smi_pending = events->smi.pending;
4113
4114                 if (events->smi.smm) {
4115                         if (events->smi.smm_inside_nmi)
4116                                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4117                         else
4118                                 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4119                 }
4120
4121                 if (lapic_in_kernel(vcpu)) {
4122                         if (events->smi.latched_init)
4123                                 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4124                         else
4125                                 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4126                 }
4127         }
4128
4129         kvm_make_request(KVM_REQ_EVENT, vcpu);
4130
4131         return 0;
4132 }
4133
4134 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4135                                              struct kvm_debugregs *dbgregs)
4136 {
4137         unsigned long val;
4138
4139         memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4140         kvm_get_dr(vcpu, 6, &val);
4141         dbgregs->dr6 = val;
4142         dbgregs->dr7 = vcpu->arch.dr7;
4143         dbgregs->flags = 0;
4144         memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4145 }
4146
4147 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4148                                             struct kvm_debugregs *dbgregs)
4149 {
4150         if (dbgregs->flags)
4151                 return -EINVAL;
4152
4153         if (dbgregs->dr6 & ~0xffffffffull)
4154                 return -EINVAL;
4155         if (dbgregs->dr7 & ~0xffffffffull)
4156                 return -EINVAL;
4157
4158         memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4159         kvm_update_dr0123(vcpu);
4160         vcpu->arch.dr6 = dbgregs->dr6;
4161         vcpu->arch.dr7 = dbgregs->dr7;
4162         kvm_update_dr7(vcpu);
4163
4164         return 0;
4165 }
4166
4167 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4168
4169 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4170 {
4171         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4172         u64 xstate_bv = xsave->header.xfeatures;
4173         u64 valid;
4174
4175         /*
4176          * Copy legacy XSAVE area, to avoid complications with CPUID
4177          * leaves 0 and 1 in the loop below.
4178          */
4179         memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4180
4181         /* Set XSTATE_BV */
4182         xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4183         *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4184
4185         /*
4186          * Copy each region from the possibly compacted offset to the
4187          * non-compacted offset.
4188          */
4189         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4190         while (valid) {
4191                 u64 xfeature_mask = valid & -valid;
4192                 int xfeature_nr = fls64(xfeature_mask) - 1;
4193                 void *src = get_xsave_addr(xsave, xfeature_nr);
4194
4195                 if (src) {
4196                         u32 size, offset, ecx, edx;
4197                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4198                                     &size, &offset, &ecx, &edx);
4199                         if (xfeature_nr == XFEATURE_PKRU)
4200                                 memcpy(dest + offset, &vcpu->arch.pkru,
4201                                        sizeof(vcpu->arch.pkru));
4202                         else
4203                                 memcpy(dest + offset, src, size);
4204
4205                 }
4206
4207                 valid -= xfeature_mask;
4208         }
4209 }
4210
4211 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4212 {
4213         struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4214         u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4215         u64 valid;
4216
4217         /*
4218          * Copy legacy XSAVE area, to avoid complications with CPUID
4219          * leaves 0 and 1 in the loop below.
4220          */
4221         memcpy(xsave, src, XSAVE_HDR_OFFSET);
4222
4223         /* Set XSTATE_BV and possibly XCOMP_BV.  */
4224         xsave->header.xfeatures = xstate_bv;
4225         if (boot_cpu_has(X86_FEATURE_XSAVES))
4226                 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4227
4228         /*
4229          * Copy each region from the non-compacted offset to the
4230          * possibly compacted offset.
4231          */
4232         valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4233         while (valid) {
4234                 u64 xfeature_mask = valid & -valid;
4235                 int xfeature_nr = fls64(xfeature_mask) - 1;
4236                 void *dest = get_xsave_addr(xsave, xfeature_nr);
4237
4238                 if (dest) {
4239                         u32 size, offset, ecx, edx;
4240                         cpuid_count(XSTATE_CPUID, xfeature_nr,
4241                                     &size, &offset, &ecx, &edx);
4242                         if (xfeature_nr == XFEATURE_PKRU)
4243                                 memcpy(&vcpu->arch.pkru, src + offset,
4244                                        sizeof(vcpu->arch.pkru));
4245                         else
4246                                 memcpy(dest, src + offset, size);
4247                 }
4248
4249                 valid -= xfeature_mask;
4250         }
4251 }
4252
4253 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4254                                          struct kvm_xsave *guest_xsave)
4255 {
4256         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4257                 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4258                 fill_xsave((u8 *) guest_xsave->region, vcpu);
4259         } else {
4260                 memcpy(guest_xsave->region,
4261                         &vcpu->arch.guest_fpu->state.fxsave,
4262                         sizeof(struct fxregs_state));
4263                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4264                         XFEATURE_MASK_FPSSE;
4265         }
4266 }
4267
4268 #define XSAVE_MXCSR_OFFSET 24
4269
4270 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4271                                         struct kvm_xsave *guest_xsave)
4272 {
4273         u64 xstate_bv =
4274                 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4275         u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4276
4277         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4278                 /*
4279                  * Here we allow setting states that are not present in
4280                  * CPUID leaf 0xD, index 0, EDX:EAX.  This is for compatibility
4281                  * with old userspace.
4282                  */
4283                 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4284                         return -EINVAL;
4285                 load_xsave(vcpu, (u8 *)guest_xsave->region);
4286         } else {
4287                 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4288                         mxcsr & ~mxcsr_feature_mask)
4289                         return -EINVAL;
4290                 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4291                         guest_xsave->region, sizeof(struct fxregs_state));
4292         }
4293         return 0;
4294 }
4295
4296 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4297                                         struct kvm_xcrs *guest_xcrs)
4298 {
4299         if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4300                 guest_xcrs->nr_xcrs = 0;
4301                 return;
4302         }
4303
4304         guest_xcrs->nr_xcrs = 1;
4305         guest_xcrs->flags = 0;
4306         guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4307         guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4308 }
4309
4310 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4311                                        struct kvm_xcrs *guest_xcrs)
4312 {
4313         int i, r = 0;
4314
4315         if (!boot_cpu_has(X86_FEATURE_XSAVE))
4316                 return -EINVAL;
4317
4318         if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4319                 return -EINVAL;
4320
4321         for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4322                 /* Only support XCR0 currently */
4323                 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4324                         r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4325                                 guest_xcrs->xcrs[i].value);
4326                         break;
4327                 }
4328         if (r)
4329                 r = -EINVAL;
4330         return r;
4331 }
4332
4333 /*
4334  * kvm_set_guest_paused() indicates to the guest kernel that it has been
4335  * stopped by the hypervisor.  This function will be called from the host only.
4336  * EINVAL is returned when the host attempts to set the flag for a guest that
4337  * does not support pv clocks.
4338  */
4339 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4340 {
4341         if (!vcpu->arch.pv_time_enabled)
4342                 return -EINVAL;
4343         vcpu->arch.pvclock_set_guest_stopped_request = true;
4344         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4345         return 0;
4346 }
4347
4348 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4349                                      struct kvm_enable_cap *cap)
4350 {
4351         int r;
4352         uint16_t vmcs_version;
4353         void __user *user_ptr;
4354
4355         if (cap->flags)
4356                 return -EINVAL;
4357
4358         switch (cap->cap) {
4359         case KVM_CAP_HYPERV_SYNIC2:
4360                 if (cap->args[0])
4361                         return -EINVAL;
4362                 fallthrough;
4363
4364         case KVM_CAP_HYPERV_SYNIC:
4365                 if (!irqchip_in_kernel(vcpu->kvm))
4366                         return -EINVAL;
4367                 return kvm_hv_activate_synic(vcpu, cap->cap ==
4368                                              KVM_CAP_HYPERV_SYNIC2);
4369         case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4370                 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4371                         return -ENOTTY;
4372                 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4373                 if (!r) {
4374                         user_ptr = (void __user *)(uintptr_t)cap->args[0];
4375                         if (copy_to_user(user_ptr, &vmcs_version,
4376                                          sizeof(vmcs_version)))
4377                                 r = -EFAULT;
4378                 }
4379                 return r;
4380         case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4381                 if (!kvm_x86_ops.enable_direct_tlbflush)
4382                         return -ENOTTY;
4383
4384                 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4385
4386         default:
4387                 return -EINVAL;
4388         }
4389 }
4390
4391 long kvm_arch_vcpu_ioctl(struct file *filp,
4392                          unsigned int ioctl, unsigned long arg)
4393 {
4394         struct kvm_vcpu *vcpu = filp->private_data;
4395         void __user *argp = (void __user *)arg;
4396         int r;
4397         union {
4398                 struct kvm_lapic_state *lapic;
4399                 struct kvm_xsave *xsave;
4400                 struct kvm_xcrs *xcrs;
4401                 void *buffer;
4402         } u;
4403
4404         vcpu_load(vcpu);
4405
4406         u.buffer = NULL;
4407         switch (ioctl) {
4408         case KVM_GET_LAPIC: {
4409                 r = -EINVAL;
4410                 if (!lapic_in_kernel(vcpu))
4411                         goto out;
4412                 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4413                                 GFP_KERNEL_ACCOUNT);
4414
4415                 r = -ENOMEM;
4416                 if (!u.lapic)
4417                         goto out;
4418                 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4419                 if (r)
4420                         goto out;
4421                 r = -EFAULT;
4422                 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4423                         goto out;
4424                 r = 0;
4425                 break;
4426         }
4427         case KVM_SET_LAPIC: {
4428                 r = -EINVAL;
4429                 if (!lapic_in_kernel(vcpu))
4430                         goto out;
4431                 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4432                 if (IS_ERR(u.lapic)) {
4433                         r = PTR_ERR(u.lapic);
4434                         goto out_nofree;
4435                 }
4436
4437                 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4438                 break;
4439         }
4440         case KVM_INTERRUPT: {
4441                 struct kvm_interrupt irq;
4442
4443                 r = -EFAULT;
4444                 if (copy_from_user(&irq, argp, sizeof(irq)))
4445                         goto out;
4446                 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4447                 break;
4448         }
4449         case KVM_NMI: {
4450                 r = kvm_vcpu_ioctl_nmi(vcpu);
4451                 break;
4452         }
4453         case KVM_SMI: {
4454                 r = kvm_vcpu_ioctl_smi(vcpu);
4455                 break;
4456         }
4457         case KVM_SET_CPUID: {
4458                 struct kvm_cpuid __user *cpuid_arg = argp;
4459                 struct kvm_cpuid cpuid;
4460
4461                 r = -EFAULT;
4462                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4463                         goto out;
4464                 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4465                 break;
4466         }
4467         case KVM_SET_CPUID2: {
4468                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4469                 struct kvm_cpuid2 cpuid;
4470
4471                 r = -EFAULT;
4472                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4473                         goto out;
4474                 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4475                                               cpuid_arg->entries);
4476                 break;
4477         }
4478         case KVM_GET_CPUID2: {
4479                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4480                 struct kvm_cpuid2 cpuid;
4481
4482                 r = -EFAULT;
4483                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4484                         goto out;
4485                 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4486                                               cpuid_arg->entries);
4487                 if (r)
4488                         goto out;
4489                 r = -EFAULT;
4490                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4491                         goto out;
4492                 r = 0;
4493                 break;
4494         }
4495         case KVM_GET_MSRS: {
4496                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4497                 r = msr_io(vcpu, argp, do_get_msr, 1);
4498                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4499                 break;
4500         }
4501         case KVM_SET_MSRS: {
4502                 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4503                 r = msr_io(vcpu, argp, do_set_msr, 0);
4504                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4505                 break;
4506         }
4507         case KVM_TPR_ACCESS_REPORTING: {
4508                 struct kvm_tpr_access_ctl tac;
4509
4510                 r = -EFAULT;
4511                 if (copy_from_user(&tac, argp, sizeof(tac)))
4512                         goto out;
4513                 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4514                 if (r)
4515                         goto out;
4516                 r = -EFAULT;
4517                 if (copy_to_user(argp, &tac, sizeof(tac)))
4518                         goto out;
4519                 r = 0;
4520                 break;
4521         };
4522         case KVM_SET_VAPIC_ADDR: {
4523                 struct kvm_vapic_addr va;
4524                 int idx;
4525
4526                 r = -EINVAL;
4527                 if (!lapic_in_kernel(vcpu))
4528                         goto out;
4529                 r = -EFAULT;
4530                 if (copy_from_user(&va, argp, sizeof(va)))
4531                         goto out;
4532                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4533                 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4534                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4535                 break;
4536         }
4537         case KVM_X86_SETUP_MCE: {
4538                 u64 mcg_cap;
4539
4540                 r = -EFAULT;
4541                 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4542                         goto out;
4543                 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4544                 break;
4545         }
4546         case KVM_X86_SET_MCE: {
4547                 struct kvm_x86_mce mce;
4548
4549                 r = -EFAULT;
4550                 if (copy_from_user(&mce, argp, sizeof(mce)))
4551                         goto out;
4552                 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4553                 break;
4554         }
4555         case KVM_GET_VCPU_EVENTS: {
4556                 struct kvm_vcpu_events events;
4557
4558                 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4559
4560                 r = -EFAULT;
4561                 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4562                         break;
4563                 r = 0;
4564                 break;
4565         }
4566         case KVM_SET_VCPU_EVENTS: {
4567                 struct kvm_vcpu_events events;
4568
4569                 r = -EFAULT;
4570                 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4571                         break;
4572
4573                 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4574                 break;
4575         }
4576         case KVM_GET_DEBUGREGS: {
4577                 struct kvm_debugregs dbgregs;
4578
4579                 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4580
4581                 r = -EFAULT;
4582                 if (copy_to_user(argp, &dbgregs,
4583                                  sizeof(struct kvm_debugregs)))
4584                         break;
4585                 r = 0;
4586                 break;
4587         }
4588         case KVM_SET_DEBUGREGS: {
4589                 struct kvm_debugregs dbgregs;
4590
4591                 r = -EFAULT;
4592                 if (copy_from_user(&dbgregs, argp,
4593                                    sizeof(struct kvm_debugregs)))
4594                         break;
4595
4596                 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4597                 break;
4598         }
4599         case KVM_GET_XSAVE: {
4600                 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4601                 r = -ENOMEM;
4602                 if (!u.xsave)
4603                         break;
4604
4605                 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4606
4607                 r = -EFAULT;
4608                 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4609                         break;
4610                 r = 0;
4611                 break;
4612         }
4613         case KVM_SET_XSAVE: {
4614                 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4615                 if (IS_ERR(u.xsave)) {
4616                         r = PTR_ERR(u.xsave);
4617                         goto out_nofree;
4618                 }
4619
4620                 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4621                 break;
4622         }
4623         case KVM_GET_XCRS: {
4624                 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4625                 r = -ENOMEM;
4626                 if (!u.xcrs)
4627                         break;
4628
4629                 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4630
4631                 r = -EFAULT;
4632                 if (copy_to_user(argp, u.xcrs,
4633                                  sizeof(struct kvm_xcrs)))
4634                         break;
4635                 r = 0;
4636                 break;
4637         }
4638         case KVM_SET_XCRS: {
4639                 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4640                 if (IS_ERR(u.xcrs)) {
4641                         r = PTR_ERR(u.xcrs);
4642                         goto out_nofree;
4643                 }
4644
4645                 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4646                 break;
4647         }
4648         case KVM_SET_TSC_KHZ: {
4649                 u32 user_tsc_khz;
4650
4651                 r = -EINVAL;
4652                 user_tsc_khz = (u32)arg;
4653
4654                 if (kvm_has_tsc_control &&
4655                     user_tsc_khz >= kvm_max_guest_tsc_khz)
4656                         goto out;
4657
4658                 if (user_tsc_khz == 0)
4659                         user_tsc_khz = tsc_khz;
4660
4661                 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4662                         r = 0;
4663
4664                 goto out;
4665         }
4666         case KVM_GET_TSC_KHZ: {
4667                 r = vcpu->arch.virtual_tsc_khz;
4668                 goto out;
4669         }
4670         case KVM_KVMCLOCK_CTRL: {
4671                 r = kvm_set_guest_paused(vcpu);
4672                 goto out;
4673         }
4674         case KVM_ENABLE_CAP: {
4675                 struct kvm_enable_cap cap;
4676
4677                 r = -EFAULT;
4678                 if (copy_from_user(&cap, argp, sizeof(cap)))
4679                         goto out;
4680                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4681                 break;
4682         }
4683         case KVM_GET_NESTED_STATE: {
4684                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4685                 u32 user_data_size;
4686
4687                 r = -EINVAL;
4688                 if (!kvm_x86_ops.nested_ops->get_state)
4689                         break;
4690
4691                 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4692                 r = -EFAULT;
4693                 if (get_user(user_data_size, &user_kvm_nested_state->size))
4694                         break;
4695
4696                 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4697                                                      user_data_size);
4698                 if (r < 0)
4699                         break;
4700
4701                 if (r > user_data_size) {
4702                         if (put_user(r, &user_kvm_nested_state->size))
4703                                 r = -EFAULT;
4704                         else
4705                                 r = -E2BIG;
4706                         break;
4707                 }
4708
4709                 r = 0;
4710                 break;
4711         }
4712         case KVM_SET_NESTED_STATE: {
4713                 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4714                 struct kvm_nested_state kvm_state;
4715                 int idx;
4716
4717                 r = -EINVAL;
4718                 if (!kvm_x86_ops.nested_ops->set_state)
4719                         break;
4720
4721                 r = -EFAULT;
4722                 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4723                         break;
4724
4725                 r = -EINVAL;
4726                 if (kvm_state.size < sizeof(kvm_state))
4727                         break;
4728
4729                 if (kvm_state.flags &
4730                     ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4731                       | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4732                       | KVM_STATE_NESTED_GIF_SET))
4733                         break;
4734
4735                 /* nested_run_pending implies guest_mode.  */
4736                 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4737                     && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4738                         break;
4739
4740                 idx = srcu_read_lock(&vcpu->kvm->srcu);
4741                 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4742                 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4743                 break;
4744         }
4745         case KVM_GET_SUPPORTED_HV_CPUID: {
4746                 struct kvm_cpuid2 __user *cpuid_arg = argp;
4747                 struct kvm_cpuid2 cpuid;
4748
4749                 r = -EFAULT;
4750                 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4751                         goto out;
4752
4753                 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4754                                                 cpuid_arg->entries);
4755                 if (r)
4756                         goto out;
4757
4758                 r = -EFAULT;
4759                 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4760                         goto out;
4761                 r = 0;
4762                 break;
4763         }
4764         default:
4765                 r = -EINVAL;
4766         }
4767 out:
4768         kfree(u.buffer);
4769 out_nofree:
4770         vcpu_put(vcpu);
4771         return r;
4772 }
4773
4774 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
4775 {
4776         return VM_FAULT_SIGBUS;
4777 }
4778
4779 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4780 {
4781         int ret;
4782
4783         if (addr > (unsigned int)(-3 * PAGE_SIZE))
4784                 return -EINVAL;
4785         ret = kvm_x86_ops.set_tss_addr(kvm, addr);
4786         return ret;
4787 }
4788
4789 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4790                                               u64 ident_addr)
4791 {
4792         return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
4793 }
4794
4795 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4796                                          unsigned long kvm_nr_mmu_pages)
4797 {
4798         if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4799                 return -EINVAL;
4800
4801         mutex_lock(&kvm->slots_lock);
4802
4803         kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
4804         kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
4805
4806         mutex_unlock(&kvm->slots_lock);
4807         return 0;
4808 }
4809
4810 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4811 {
4812         return kvm->arch.n_max_mmu_pages;
4813 }
4814
4815 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4816 {
4817         struct kvm_pic *pic = kvm->arch.vpic;
4818         int r;
4819
4820         r = 0;
4821         switch (chip->chip_id) {
4822         case KVM_IRQCHIP_PIC_MASTER:
4823                 memcpy(&chip->chip.pic, &pic->pics[0],
4824                         sizeof(struct kvm_pic_state));
4825                 break;
4826         case KVM_IRQCHIP_PIC_SLAVE:
4827                 memcpy(&chip->chip.pic, &pic->pics[1],
4828                         sizeof(struct kvm_pic_state));
4829                 break;
4830         case KVM_IRQCHIP_IOAPIC:
4831                 kvm_get_ioapic(kvm, &chip->chip.ioapic);
4832                 break;
4833         default:
4834                 r = -EINVAL;
4835                 break;
4836         }
4837         return r;
4838 }
4839
4840 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4841 {
4842         struct kvm_pic *pic = kvm->arch.vpic;
4843         int r;
4844
4845         r = 0;
4846         switch (chip->chip_id) {
4847         case KVM_IRQCHIP_PIC_MASTER:
4848                 spin_lock(&pic->lock);
4849                 memcpy(&pic->pics[0], &chip->chip.pic,
4850                         sizeof(struct kvm_pic_state));
4851                 spin_unlock(&pic->lock);
4852                 break;
4853         case KVM_IRQCHIP_PIC_SLAVE:
4854                 spin_lock(&pic->lock);
4855                 memcpy(&pic->pics[1], &chip->chip.pic,
4856                         sizeof(struct kvm_pic_state));
4857                 spin_unlock(&pic->lock);
4858                 break;
4859         case KVM_IRQCHIP_IOAPIC:
4860                 kvm_set_ioapic(kvm, &chip->chip.ioapic);
4861                 break;
4862         default:
4863                 r = -EINVAL;
4864                 break;
4865         }
4866         kvm_pic_update_irq(pic);
4867         return r;
4868 }
4869
4870 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4871 {
4872         struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4873
4874         BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4875
4876         mutex_lock(&kps->lock);
4877         memcpy(ps, &kps->channels, sizeof(*ps));
4878         mutex_unlock(&kps->lock);
4879         return 0;
4880 }
4881
4882 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4883 {
4884         int i;
4885         struct kvm_pit *pit = kvm->arch.vpit;
4886
4887         mutex_lock(&pit->pit_state.lock);
4888         memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
4889         for (i = 0; i < 3; i++)
4890                 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4891         mutex_unlock(&pit->pit_state.lock);
4892         return 0;
4893 }
4894
4895 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4896 {
4897         mutex_lock(&kvm->arch.vpit->pit_state.lock);
4898         memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4899                 sizeof(ps->channels));
4900         ps->flags = kvm->arch.vpit->pit_state.flags;
4901         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
4902         memset(&ps->reserved, 0, sizeof(ps->reserved));
4903         return 0;
4904 }
4905
4906 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4907 {
4908         int start = 0;
4909         int i;
4910         u32 prev_legacy, cur_legacy;
4911         struct kvm_pit *pit = kvm->arch.vpit;
4912
4913         mutex_lock(&pit->pit_state.lock);
4914         prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
4915         cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4916         if (!prev_legacy && cur_legacy)
4917                 start = 1;
4918         memcpy(&pit->pit_state.channels, &ps->channels,
4919                sizeof(pit->pit_state.channels));
4920         pit->pit_state.flags = ps->flags;
4921         for (i = 0; i < 3; i++)
4922                 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
4923                                    start && i == 0);
4924         mutex_unlock(&pit->pit_state.lock);
4925         return 0;
4926 }
4927
4928 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4929                                  struct kvm_reinject_control *control)
4930 {
4931         struct kvm_pit *pit = kvm->arch.vpit;
4932
4933         /* pit->pit_state.lock was overloaded to prevent userspace from getting
4934          * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4935          * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
4936          */
4937         mutex_lock(&pit->pit_state.lock);
4938         kvm_pit_set_reinject(pit, control->pit_reinject);
4939         mutex_unlock(&pit->pit_state.lock);
4940
4941         return 0;
4942 }
4943
4944 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
4945 {
4946         /*
4947          * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4948          */
4949         if (kvm_x86_ops.flush_log_dirty)
4950                 kvm_x86_ops.flush_log_dirty(kvm);
4951 }
4952
4953 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4954                         bool line_status)
4955 {
4956         if (!irqchip_in_kernel(kvm))
4957                 return -ENXIO;
4958
4959         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
4960                                         irq_event->irq, irq_event->level,
4961                                         line_status);
4962         return 0;
4963 }
4964
4965 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4966                             struct kvm_enable_cap *cap)
4967 {
4968         int r;
4969
4970         if (cap->flags)
4971                 return -EINVAL;
4972
4973         switch (cap->cap) {
4974         case KVM_CAP_DISABLE_QUIRKS:
4975                 kvm->arch.disabled_quirks = cap->args[0];
4976                 r = 0;
4977                 break;
4978         case KVM_CAP_SPLIT_IRQCHIP: {
4979                 mutex_lock(&kvm->lock);
4980                 r = -EINVAL;
4981                 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4982                         goto split_irqchip_unlock;
4983                 r = -EEXIST;
4984                 if (irqchip_in_kernel(kvm))
4985                         goto split_irqchip_unlock;
4986                 if (kvm->created_vcpus)
4987                         goto split_irqchip_unlock;
4988                 r = kvm_setup_empty_irq_routing(kvm);
4989                 if (r)
4990                         goto split_irqchip_unlock;
4991                 /* Pairs with irqchip_in_kernel. */
4992                 smp_wmb();
4993                 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
4994                 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
4995                 r = 0;
4996 split_irqchip_unlock:
4997                 mutex_unlock(&kvm->lock);
4998                 break;
4999         }
5000         case KVM_CAP_X2APIC_API:
5001                 r = -EINVAL;
5002                 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5003                         break;
5004
5005                 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5006                         kvm->arch.x2apic_format = true;
5007                 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5008                         kvm->arch.x2apic_broadcast_quirk_disabled = true;
5009
5010                 r = 0;
5011                 break;
5012         case KVM_CAP_X86_DISABLE_EXITS:
5013                 r = -EINVAL;
5014                 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5015                         break;
5016
5017                 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5018                         kvm_can_mwait_in_guest())
5019                         kvm->arch.mwait_in_guest = true;
5020                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5021                         kvm->arch.hlt_in_guest = true;
5022                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5023                         kvm->arch.pause_in_guest = true;
5024                 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5025                         kvm->arch.cstate_in_guest = true;
5026                 r = 0;
5027                 break;
5028         case KVM_CAP_MSR_PLATFORM_INFO:
5029                 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5030                 r = 0;
5031                 break;
5032         case KVM_CAP_EXCEPTION_PAYLOAD:
5033                 kvm->arch.exception_payload_enabled = cap->args[0];
5034                 r = 0;
5035                 break;
5036         default:
5037                 r = -EINVAL;
5038                 break;
5039         }
5040         return r;
5041 }
5042
5043 long kvm_arch_vm_ioctl(struct file *filp,
5044                        unsigned int ioctl, unsigned long arg)
5045 {
5046         struct kvm *kvm = filp->private_data;
5047         void __user *argp = (void __user *)arg;
5048         int r = -ENOTTY;
5049         /*
5050          * This union makes it completely explicit to gcc-3.x
5051          * that these two variables' stack usage should be
5052          * combined, not added together.
5053          */
5054         union {
5055                 struct kvm_pit_state ps;
5056                 struct kvm_pit_state2 ps2;
5057                 struct kvm_pit_config pit_config;
5058         } u;
5059
5060         switch (ioctl) {
5061         case KVM_SET_TSS_ADDR:
5062                 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5063                 break;
5064         case KVM_SET_IDENTITY_MAP_ADDR: {
5065                 u64 ident_addr;
5066
5067                 mutex_lock(&kvm->lock);
5068                 r = -EINVAL;
5069                 if (kvm->created_vcpus)
5070                         goto set_identity_unlock;
5071                 r = -EFAULT;
5072                 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5073                         goto set_identity_unlock;
5074                 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5075 set_identity_unlock:
5076                 mutex_unlock(&kvm->lock);
5077                 break;
5078         }
5079         case KVM_SET_NR_MMU_PAGES:
5080                 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5081                 break;
5082         case KVM_GET_NR_MMU_PAGES:
5083                 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5084                 break;
5085         case KVM_CREATE_IRQCHIP: {
5086                 mutex_lock(&kvm->lock);
5087
5088                 r = -EEXIST;
5089                 if (irqchip_in_kernel(kvm))
5090                         goto create_irqchip_unlock;
5091
5092                 r = -EINVAL;
5093                 if (kvm->created_vcpus)
5094                         goto create_irqchip_unlock;
5095
5096                 r = kvm_pic_init(kvm);
5097                 if (r)
5098                         goto create_irqchip_unlock;
5099
5100                 r = kvm_ioapic_init(kvm);
5101                 if (r) {
5102                         kvm_pic_destroy(kvm);
5103                         goto create_irqchip_unlock;
5104                 }
5105
5106                 r = kvm_setup_default_irq_routing(kvm);
5107                 if (r) {
5108                         kvm_ioapic_destroy(kvm);
5109                         kvm_pic_destroy(kvm);
5110                         goto create_irqchip_unlock;
5111                 }
5112                 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5113                 smp_wmb();
5114                 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5115         create_irqchip_unlock:
5116                 mutex_unlock(&kvm->lock);
5117                 break;
5118         }
5119         case KVM_CREATE_PIT:
5120                 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5121                 goto create_pit;
5122         case KVM_CREATE_PIT2:
5123                 r = -EFAULT;
5124                 if (copy_from_user(&u.pit_config, argp,
5125                                    sizeof(struct kvm_pit_config)))
5126                         goto out;
5127         create_pit:
5128                 mutex_lock(&kvm->lock);
5129                 r = -EEXIST;
5130                 if (kvm->arch.vpit)
5131                         goto create_pit_unlock;
5132                 r = -ENOMEM;
5133                 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5134                 if (kvm->arch.vpit)
5135                         r = 0;
5136         create_pit_unlock:
5137                 mutex_unlock(&kvm->lock);
5138                 break;
5139         case KVM_GET_IRQCHIP: {
5140                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5141                 struct kvm_irqchip *chip;
5142
5143                 chip = memdup_user(argp, sizeof(*chip));
5144                 if (IS_ERR(chip)) {
5145                         r = PTR_ERR(chip);
5146                         goto out;
5147                 }
5148
5149                 r = -ENXIO;
5150                 if (!irqchip_kernel(kvm))
5151                         goto get_irqchip_out;
5152                 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5153                 if (r)
5154                         goto get_irqchip_out;
5155                 r = -EFAULT;
5156                 if (copy_to_user(argp, chip, sizeof(*chip)))
5157                         goto get_irqchip_out;
5158                 r = 0;
5159         get_irqchip_out:
5160                 kfree(chip);
5161                 break;
5162         }
5163         case KVM_SET_IRQCHIP: {
5164                 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5165                 struct kvm_irqchip *chip;
5166
5167                 chip = memdup_user(argp, sizeof(*chip));
5168                 if (IS_ERR(chip)) {
5169                         r = PTR_ERR(chip);
5170                         goto out;
5171                 }
5172
5173                 r = -ENXIO;
5174                 if (!irqchip_kernel(kvm))
5175                         goto set_irqchip_out;
5176                 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5177         set_irqchip_out:
5178                 kfree(chip);
5179                 break;
5180         }
5181         case KVM_GET_PIT: {
5182                 r = -EFAULT;
5183                 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5184                         goto out;
5185                 r = -ENXIO;
5186                 if (!kvm->arch.vpit)
5187                         goto out;
5188                 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5189                 if (r)
5190                         goto out;
5191                 r = -EFAULT;
5192                 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5193                         goto out;
5194                 r = 0;
5195                 break;
5196         }
5197         case KVM_SET_PIT: {
5198                 r = -EFAULT;
5199                 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5200                         goto out;
5201                 mutex_lock(&kvm->lock);
5202                 r = -ENXIO;
5203                 if (!kvm->arch.vpit)
5204                         goto set_pit_out;
5205                 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5206 set_pit_out:
5207                 mutex_unlock(&kvm->lock);
5208                 break;
5209         }
5210         case KVM_GET_PIT2: {
5211                 r = -ENXIO;
5212                 if (!kvm->arch.vpit)
5213                         goto out;
5214                 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5215                 if (r)
5216                         goto out;
5217                 r = -EFAULT;
5218                 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5219                         goto out;
5220                 r = 0;
5221                 break;
5222         }
5223         case KVM_SET_PIT2: {
5224                 r = -EFAULT;
5225                 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5226                         goto out;
5227                 mutex_lock(&kvm->lock);
5228                 r = -ENXIO;
5229                 if (!kvm->arch.vpit)
5230                         goto set_pit2_out;
5231                 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5232 set_pit2_out:
5233                 mutex_unlock(&kvm->lock);
5234                 break;
5235         }
5236         case KVM_REINJECT_CONTROL: {
5237                 struct kvm_reinject_control control;
5238                 r =  -EFAULT;
5239                 if (copy_from_user(&control, argp, sizeof(control)))
5240                         goto out;
5241                 r = -ENXIO;
5242                 if (!kvm->arch.vpit)
5243                         goto out;
5244                 r = kvm_vm_ioctl_reinject(kvm, &control);
5245                 break;
5246         }
5247         case KVM_SET_BOOT_CPU_ID:
5248                 r = 0;
5249                 mutex_lock(&kvm->lock);
5250                 if (kvm->created_vcpus)
5251                         r = -EBUSY;
5252                 else
5253                         kvm->arch.bsp_vcpu_id = arg;
5254                 mutex_unlock(&kvm->lock);
5255                 break;
5256         case KVM_XEN_HVM_CONFIG: {
5257                 struct kvm_xen_hvm_config xhc;
5258                 r = -EFAULT;
5259                 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5260                         goto out;
5261                 r = -EINVAL;
5262                 if (xhc.flags)
5263                         goto out;
5264                 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5265                 r = 0;
5266                 break;
5267         }
5268         case KVM_SET_CLOCK: {
5269                 struct kvm_clock_data user_ns;
5270                 u64 now_ns;
5271
5272                 r = -EFAULT;
5273                 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5274                         goto out;
5275
5276                 r = -EINVAL;
5277                 if (user_ns.flags)
5278                         goto out;
5279
5280                 r = 0;
5281                 /*
5282                  * TODO: userspace has to take care of races with VCPU_RUN, so
5283                  * kvm_gen_update_masterclock() can be cut down to locked
5284                  * pvclock_update_vm_gtod_copy().
5285                  */
5286                 kvm_gen_update_masterclock(kvm);
5287                 now_ns = get_kvmclock_ns(kvm);
5288                 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5289                 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5290                 break;
5291         }
5292         case KVM_GET_CLOCK: {
5293                 struct kvm_clock_data user_ns;
5294                 u64 now_ns;
5295
5296                 now_ns = get_kvmclock_ns(kvm);
5297                 user_ns.clock = now_ns;
5298                 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5299                 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5300
5301                 r = -EFAULT;
5302                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5303                         goto out;
5304                 r = 0;
5305                 break;
5306         }
5307         case KVM_MEMORY_ENCRYPT_OP: {
5308                 r = -ENOTTY;
5309                 if (kvm_x86_ops.mem_enc_op)
5310                         r = kvm_x86_ops.mem_enc_op(kvm, argp);
5311                 break;
5312         }
5313         case KVM_MEMORY_ENCRYPT_REG_REGION: {
5314                 struct kvm_enc_region region;
5315
5316                 r = -EFAULT;
5317                 if (copy_from_user(&region, argp, sizeof(region)))
5318                         goto out;
5319
5320                 r = -ENOTTY;
5321                 if (kvm_x86_ops.mem_enc_reg_region)
5322                         r = kvm_x86_ops.mem_enc_reg_region(kvm, &region);
5323                 break;
5324         }
5325         case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5326                 struct kvm_enc_region region;
5327
5328                 r = -EFAULT;
5329                 if (copy_from_user(&region, argp, sizeof(region)))
5330                         goto out;
5331
5332                 r = -ENOTTY;
5333                 if (kvm_x86_ops.mem_enc_unreg_region)
5334                         r = kvm_x86_ops.mem_enc_unreg_region(kvm, &region);
5335                 break;
5336         }
5337         case KVM_HYPERV_EVENTFD: {
5338                 struct kvm_hyperv_eventfd hvevfd;
5339
5340                 r = -EFAULT;
5341                 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5342                         goto out;
5343                 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5344                 break;
5345         }
5346         case KVM_SET_PMU_EVENT_FILTER:
5347                 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5348                 break;
5349         default:
5350                 r = -ENOTTY;
5351         }
5352 out:
5353         return r;
5354 }
5355
5356 static void kvm_init_msr_list(void)
5357 {
5358         struct x86_pmu_capability x86_pmu;
5359         u32 dummy[2];
5360         unsigned i;
5361
5362         BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5363                          "Please update the fixed PMCs in msrs_to_saved_all[]");
5364
5365         perf_get_x86_pmu_capability(&x86_pmu);
5366
5367         num_msrs_to_save = 0;
5368         num_emulated_msrs = 0;
5369         num_msr_based_features = 0;
5370
5371         for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5372                 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5373                         continue;
5374
5375                 /*
5376                  * Even MSRs that are valid in the host may not be exposed
5377                  * to the guests in some cases.
5378                  */
5379                 switch (msrs_to_save_all[i]) {
5380                 case MSR_IA32_BNDCFGS:
5381                         if (!kvm_mpx_supported())
5382                                 continue;
5383                         break;
5384                 case MSR_TSC_AUX:
5385                         if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5386                                 continue;
5387                         break;
5388                 case MSR_IA32_UMWAIT_CONTROL:
5389                         if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5390                                 continue;
5391                         break;
5392                 case MSR_IA32_RTIT_CTL:
5393                 case MSR_IA32_RTIT_STATUS:
5394                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5395                                 continue;
5396                         break;
5397                 case MSR_IA32_RTIT_CR3_MATCH:
5398                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5399                             !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5400                                 continue;
5401                         break;
5402                 case MSR_IA32_RTIT_OUTPUT_BASE:
5403                 case MSR_IA32_RTIT_OUTPUT_MASK:
5404                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5405                                 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5406                                  !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5407                                 continue;
5408                         break;
5409                 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5410                         if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5411                                 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5412                                 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5413                                 continue;
5414                         break;
5415                 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5416                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5417                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5418                                 continue;
5419                         break;
5420                 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5421                         if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5422                             min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5423                                 continue;
5424                         break;
5425                 default:
5426                         break;
5427                 }
5428
5429                 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5430         }
5431
5432         for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5433                 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5434                         continue;
5435
5436                 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5437         }
5438
5439         for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5440                 struct kvm_msr_entry msr;
5441
5442                 msr.index = msr_based_features_all[i];
5443                 if (kvm_get_msr_feature(&msr))
5444                         continue;
5445
5446                 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5447         }
5448 }
5449
5450 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5451                            const void *v)
5452 {
5453         int handled = 0;
5454         int n;
5455
5456         do {
5457                 n = min(len, 8);
5458                 if (!(lapic_in_kernel(vcpu) &&
5459                       !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5460                     && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5461                         break;
5462                 handled += n;
5463                 addr += n;
5464                 len -= n;
5465                 v += n;
5466         } while (len);
5467
5468         return handled;
5469 }
5470
5471 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5472 {
5473         int handled = 0;
5474         int n;
5475
5476         do {
5477                 n = min(len, 8);
5478                 if (!(lapic_in_kernel(vcpu) &&
5479                       !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5480                                          addr, n, v))
5481                     && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5482                         break;
5483                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5484                 handled += n;
5485                 addr += n;
5486                 len -= n;
5487                 v += n;
5488         } while (len);
5489
5490         return handled;
5491 }
5492
5493 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5494                         struct kvm_segment *var, int seg)
5495 {
5496         kvm_x86_ops.set_segment(vcpu, var, seg);
5497 }
5498
5499 void kvm_get_segment(struct kvm_vcpu *vcpu,
5500                      struct kvm_segment *var, int seg)
5501 {
5502         kvm_x86_ops.get_segment(vcpu, var, seg);
5503 }
5504
5505 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5506                            struct x86_exception *exception)
5507 {
5508         gpa_t t_gpa;
5509
5510         BUG_ON(!mmu_is_nested(vcpu));
5511
5512         /* NPT walks are always user-walks */
5513         access |= PFERR_USER_MASK;
5514         t_gpa  = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5515
5516         return t_gpa;
5517 }
5518
5519 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5520                               struct x86_exception *exception)
5521 {
5522         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5523         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5524 }
5525
5526  gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5527                                 struct x86_exception *exception)
5528 {
5529         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5530         access |= PFERR_FETCH_MASK;
5531         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5532 }
5533
5534 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5535                                struct x86_exception *exception)
5536 {
5537         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5538         access |= PFERR_WRITE_MASK;
5539         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5540 }
5541
5542 /* uses this to access any guest's mapped memory without checking CPL */
5543 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5544                                 struct x86_exception *exception)
5545 {
5546         return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5547 }
5548
5549 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5550                                       struct kvm_vcpu *vcpu, u32 access,
5551                                       struct x86_exception *exception)
5552 {
5553         void *data = val;
5554         int r = X86EMUL_CONTINUE;
5555
5556         while (bytes) {
5557                 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5558                                                             exception);
5559                 unsigned offset = addr & (PAGE_SIZE-1);
5560                 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5561                 int ret;
5562
5563                 if (gpa == UNMAPPED_GVA)
5564                         return X86EMUL_PROPAGATE_FAULT;
5565                 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5566                                                offset, toread);
5567                 if (ret < 0) {
5568                         r = X86EMUL_IO_NEEDED;
5569                         goto out;
5570                 }
5571
5572                 bytes -= toread;
5573                 data += toread;
5574                 addr += toread;
5575         }
5576 out:
5577         return r;
5578 }
5579
5580 /* used for instruction fetching */
5581 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5582                                 gva_t addr, void *val, unsigned int bytes,
5583                                 struct x86_exception *exception)
5584 {
5585         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5586         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5587         unsigned offset;
5588         int ret;
5589
5590         /* Inline kvm_read_guest_virt_helper for speed.  */
5591         gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5592                                                     exception);
5593         if (unlikely(gpa == UNMAPPED_GVA))
5594                 return X86EMUL_PROPAGATE_FAULT;
5595
5596         offset = addr & (PAGE_SIZE-1);
5597         if (WARN_ON(offset + bytes > PAGE_SIZE))
5598                 bytes = (unsigned)PAGE_SIZE - offset;
5599         ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5600                                        offset, bytes);
5601         if (unlikely(ret < 0))
5602                 return X86EMUL_IO_NEEDED;
5603
5604         return X86EMUL_CONTINUE;
5605 }
5606
5607 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5608                                gva_t addr, void *val, unsigned int bytes,
5609                                struct x86_exception *exception)
5610 {
5611         u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5612
5613         /*
5614          * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5615          * is returned, but our callers are not ready for that and they blindly
5616          * call kvm_inject_page_fault.  Ensure that they at least do not leak
5617          * uninitialized kernel stack memory into cr2 and error code.
5618          */
5619         memset(exception, 0, sizeof(*exception));
5620         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5621                                           exception);
5622 }
5623 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5624
5625 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5626                              gva_t addr, void *val, unsigned int bytes,
5627                              struct x86_exception *exception, bool system)
5628 {
5629         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5630         u32 access = 0;
5631
5632         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5633                 access |= PFERR_USER_MASK;
5634
5635         return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5636 }
5637
5638 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5639                 unsigned long addr, void *val, unsigned int bytes)
5640 {
5641         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5642         int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5643
5644         return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5645 }
5646
5647 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5648                                       struct kvm_vcpu *vcpu, u32 access,
5649                                       struct x86_exception *exception)
5650 {
5651         void *data = val;
5652         int r = X86EMUL_CONTINUE;
5653
5654         while (bytes) {
5655                 gpa_t gpa =  vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5656                                                              access,
5657                                                              exception);
5658                 unsigned offset = addr & (PAGE_SIZE-1);
5659                 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5660                 int ret;
5661
5662                 if (gpa == UNMAPPED_GVA)
5663                         return X86EMUL_PROPAGATE_FAULT;
5664                 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
5665                 if (ret < 0) {
5666                         r = X86EMUL_IO_NEEDED;
5667                         goto out;
5668                 }
5669
5670                 bytes -= towrite;
5671                 data += towrite;
5672                 addr += towrite;
5673         }
5674 out:
5675         return r;
5676 }
5677
5678 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
5679                               unsigned int bytes, struct x86_exception *exception,
5680                               bool system)
5681 {
5682         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5683         u32 access = PFERR_WRITE_MASK;
5684
5685         if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5686                 access |= PFERR_USER_MASK;
5687
5688         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5689                                            access, exception);
5690 }
5691
5692 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5693                                 unsigned int bytes, struct x86_exception *exception)
5694 {
5695         /* kvm_write_guest_virt_system can pull in tons of pages. */
5696         vcpu->arch.l1tf_flush_l1d = true;
5697
5698         return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5699                                            PFERR_WRITE_MASK, exception);
5700 }
5701 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
5702
5703 int handle_ud(struct kvm_vcpu *vcpu)
5704 {
5705         static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
5706         int emul_type = EMULTYPE_TRAP_UD;
5707         char sig[5]; /* ud2; .ascii "kvm" */
5708         struct x86_exception e;
5709
5710         if (force_emulation_prefix &&
5711             kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5712                                 sig, sizeof(sig), &e) == 0 &&
5713             memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
5714                 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5715                 emul_type = EMULTYPE_TRAP_UD_FORCED;
5716         }
5717
5718         return kvm_emulate_instruction(vcpu, emul_type);
5719 }
5720 EXPORT_SYMBOL_GPL(handle_ud);
5721
5722 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5723                             gpa_t gpa, bool write)
5724 {
5725         /* For APIC access vmexit */
5726         if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5727                 return 1;
5728
5729         if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5730                 trace_vcpu_match_mmio(gva, gpa, write, true);
5731                 return 1;
5732         }
5733
5734         return 0;
5735 }
5736
5737 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5738                                 gpa_t *gpa, struct x86_exception *exception,
5739                                 bool write)
5740 {
5741         u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5742                 | (write ? PFERR_WRITE_MASK : 0);
5743
5744         /*
5745          * currently PKRU is only applied to ept enabled guest so
5746          * there is no pkey in EPT page table for L1 guest or EPT
5747          * shadow page table for L2 guest.
5748          */
5749         if (vcpu_match_mmio_gva(vcpu, gva)
5750             && !permission_fault(vcpu, vcpu->arch.walk_mmu,
5751                                  vcpu->arch.mmio_access, 0, access)) {
5752                 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5753                                         (gva & (PAGE_SIZE - 1));
5754                 trace_vcpu_match_mmio(gva, *gpa, write, false);
5755                 return 1;
5756         }
5757
5758         *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5759
5760         if (*gpa == UNMAPPED_GVA)
5761                 return -1;
5762
5763         return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
5764 }
5765
5766 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
5767                         const void *val, int bytes)
5768 {
5769         int ret;
5770
5771         ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
5772         if (ret < 0)
5773                 return 0;
5774         kvm_page_track_write(vcpu, gpa, val, bytes);
5775         return 1;
5776 }
5777
5778 struct read_write_emulator_ops {
5779         int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5780                                   int bytes);
5781         int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5782                                   void *val, int bytes);
5783         int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5784                                int bytes, void *val);
5785         int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5786                                     void *val, int bytes);
5787         bool write;
5788 };
5789
5790 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5791 {
5792         if (vcpu->mmio_read_completed) {
5793                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
5794                                vcpu->mmio_fragments[0].gpa, val);
5795                 vcpu->mmio_read_completed = 0;
5796                 return 1;
5797         }
5798
5799         return 0;
5800 }
5801
5802 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5803                         void *val, int bytes)
5804 {
5805         return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
5806 }
5807
5808 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5809                          void *val, int bytes)
5810 {
5811         return emulator_write_phys(vcpu, gpa, val, bytes);
5812 }
5813
5814 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5815 {
5816         trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
5817         return vcpu_mmio_write(vcpu, gpa, bytes, val);
5818 }
5819
5820 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5821                           void *val, int bytes)
5822 {
5823         trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
5824         return X86EMUL_IO_NEEDED;
5825 }
5826
5827 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5828                            void *val, int bytes)
5829 {
5830         struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5831
5832         memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
5833         return X86EMUL_CONTINUE;
5834 }
5835
5836 static const struct read_write_emulator_ops read_emultor = {
5837         .read_write_prepare = read_prepare,
5838         .read_write_emulate = read_emulate,
5839         .read_write_mmio = vcpu_mmio_read,
5840         .read_write_exit_mmio = read_exit_mmio,
5841 };
5842
5843 static const struct read_write_emulator_ops write_emultor = {
5844         .read_write_emulate = write_emulate,
5845         .read_write_mmio = write_mmio,
5846         .read_write_exit_mmio = write_exit_mmio,
5847         .write = true,
5848 };
5849
5850 static int emulator_read_write_onepage(unsigned long addr, void *val,
5851                                        unsigned int bytes,
5852                                        struct x86_exception *exception,
5853                                        struct kvm_vcpu *vcpu,
5854                                        const struct read_write_emulator_ops *ops)
5855 {
5856         gpa_t gpa;
5857         int handled, ret;
5858         bool write = ops->write;
5859         struct kvm_mmio_fragment *frag;
5860         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
5861
5862         /*
5863          * If the exit was due to a NPF we may already have a GPA.
5864          * If the GPA is present, use it to avoid the GVA to GPA table walk.
5865          * Note, this cannot be used on string operations since string
5866          * operation using rep will only have the initial GPA from the NPF
5867          * occurred.
5868          */
5869         if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
5870             (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
5871                 gpa = ctxt->gpa_val;
5872                 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5873         } else {
5874                 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5875                 if (ret < 0)
5876                         return X86EMUL_PROPAGATE_FAULT;
5877         }
5878
5879         if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
5880                 return X86EMUL_CONTINUE;
5881
5882         /*
5883          * Is this MMIO handled locally?
5884          */
5885         handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
5886         if (handled == bytes)
5887                 return X86EMUL_CONTINUE;
5888
5889         gpa += handled;
5890         bytes -= handled;
5891         val += handled;
5892
5893         WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5894         frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5895         frag->gpa = gpa;
5896         frag->data = val;
5897         frag->len = bytes;
5898         return X86EMUL_CONTINUE;
5899 }
5900
5901 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5902                         unsigned long addr,
5903                         void *val, unsigned int bytes,
5904                         struct x86_exception *exception,
5905                         const struct read_write_emulator_ops *ops)
5906 {
5907         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5908         gpa_t gpa;
5909         int rc;
5910
5911         if (ops->read_write_prepare &&
5912                   ops->read_write_prepare(vcpu, val, bytes))
5913                 return X86EMUL_CONTINUE;
5914
5915         vcpu->mmio_nr_fragments = 0;
5916
5917         /* Crossing a page boundary? */
5918         if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
5919                 int now;
5920
5921                 now = -addr & ~PAGE_MASK;
5922                 rc = emulator_read_write_onepage(addr, val, now, exception,
5923                                                  vcpu, ops);
5924
5925                 if (rc != X86EMUL_CONTINUE)
5926                         return rc;
5927                 addr += now;
5928                 if (ctxt->mode != X86EMUL_MODE_PROT64)
5929                         addr = (u32)addr;
5930                 val += now;
5931                 bytes -= now;
5932         }
5933
5934         rc = emulator_read_write_onepage(addr, val, bytes, exception,
5935                                          vcpu, ops);
5936         if (rc != X86EMUL_CONTINUE)
5937                 return rc;
5938
5939         if (!vcpu->mmio_nr_fragments)
5940                 return rc;
5941
5942         gpa = vcpu->mmio_fragments[0].gpa;
5943
5944         vcpu->mmio_needed = 1;
5945         vcpu->mmio_cur_fragment = 0;
5946
5947         vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
5948         vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5949         vcpu->run->exit_reason = KVM_EXIT_MMIO;
5950         vcpu->run->mmio.phys_addr = gpa;
5951
5952         return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
5953 }
5954
5955 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5956                                   unsigned long addr,
5957                                   void *val,
5958                                   unsigned int bytes,
5959                                   struct x86_exception *exception)
5960 {
5961         return emulator_read_write(ctxt, addr, val, bytes,
5962                                    exception, &read_emultor);
5963 }
5964
5965 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
5966                             unsigned long addr,
5967                             const void *val,
5968                             unsigned int bytes,
5969                             struct x86_exception *exception)
5970 {
5971         return emulator_read_write(ctxt, addr, (void *)val, bytes,
5972                                    exception, &write_emultor);
5973 }
5974
5975 #define CMPXCHG_TYPE(t, ptr, old, new) \
5976         (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5977
5978 #ifdef CONFIG_X86_64
5979 #  define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5980 #else
5981 #  define CMPXCHG64(ptr, old, new) \
5982         (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
5983 #endif
5984
5985 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5986                                      unsigned long addr,
5987                                      const void *old,
5988                                      const void *new,
5989                                      unsigned int bytes,
5990                                      struct x86_exception *exception)
5991 {
5992         struct kvm_host_map map;
5993         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5994         u64 page_line_mask;
5995         gpa_t gpa;
5996         char *kaddr;
5997         bool exchanged;
5998
5999         /* guests cmpxchg8b have to be emulated atomically */
6000         if (bytes > 8 || (bytes & (bytes - 1)))
6001                 goto emul_write;
6002
6003         gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6004
6005         if (gpa == UNMAPPED_GVA ||
6006             (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6007                 goto emul_write;
6008
6009         /*
6010          * Emulate the atomic as a straight write to avoid #AC if SLD is
6011          * enabled in the host and the access splits a cache line.
6012          */
6013         if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6014                 page_line_mask = ~(cache_line_size() - 1);
6015         else
6016                 page_line_mask = PAGE_MASK;
6017
6018         if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6019                 goto emul_write;
6020
6021         if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6022                 goto emul_write;
6023
6024         kaddr = map.hva + offset_in_page(gpa);
6025
6026         switch (bytes) {
6027         case 1:
6028                 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6029                 break;
6030         case 2:
6031                 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6032                 break;
6033         case 4:
6034                 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6035                 break;
6036         case 8:
6037                 exchanged = CMPXCHG64(kaddr, old, new);
6038                 break;
6039         default:
6040                 BUG();
6041         }
6042
6043         kvm_vcpu_unmap(vcpu, &map, true);
6044
6045         if (!exchanged)
6046                 return X86EMUL_CMPXCHG_FAILED;
6047
6048         kvm_page_track_write(vcpu, gpa, new, bytes);
6049
6050         return X86EMUL_CONTINUE;
6051
6052 emul_write:
6053         printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6054
6055         return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6056 }
6057
6058 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6059 {
6060         int r = 0, i;
6061
6062         for (i = 0; i < vcpu->arch.pio.count; i++) {
6063                 if (vcpu->arch.pio.in)
6064                         r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6065                                             vcpu->arch.pio.size, pd);
6066                 else
6067                         r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6068                                              vcpu->arch.pio.port, vcpu->arch.pio.size,
6069                                              pd);
6070                 if (r)
6071                         break;
6072                 pd += vcpu->arch.pio.size;
6073         }
6074         return r;
6075 }
6076
6077 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6078                                unsigned short port, void *val,
6079                                unsigned int count, bool in)
6080 {
6081         vcpu->arch.pio.port = port;
6082         vcpu->arch.pio.in = in;
6083         vcpu->arch.pio.count  = count;
6084         vcpu->arch.pio.size = size;
6085
6086         if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6087                 vcpu->arch.pio.count = 0;
6088                 return 1;
6089         }
6090
6091         vcpu->run->exit_reason = KVM_EXIT_IO;
6092         vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6093         vcpu->run->io.size = size;
6094         vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6095         vcpu->run->io.count = count;
6096         vcpu->run->io.port = port;
6097
6098         return 0;
6099 }
6100
6101 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6102                            unsigned short port, void *val, unsigned int count)
6103 {
6104         int ret;
6105
6106         if (vcpu->arch.pio.count)
6107                 goto data_avail;
6108
6109         memset(vcpu->arch.pio_data, 0, size * count);
6110
6111         ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6112         if (ret) {
6113 data_avail:
6114                 memcpy(val, vcpu->arch.pio_data, size * count);
6115                 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6116                 vcpu->arch.pio.count = 0;
6117                 return 1;
6118         }
6119
6120         return 0;
6121 }
6122
6123 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6124                                     int size, unsigned short port, void *val,
6125                                     unsigned int count)
6126 {
6127         return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6128
6129 }
6130
6131 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6132                             unsigned short port, const void *val,
6133                             unsigned int count)
6134 {
6135         memcpy(vcpu->arch.pio_data, val, size * count);
6136         trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6137         return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6138 }
6139
6140 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6141                                      int size, unsigned short port,
6142                                      const void *val, unsigned int count)
6143 {
6144         return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6145 }
6146
6147 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6148 {
6149         return kvm_x86_ops.get_segment_base(vcpu, seg);
6150 }
6151
6152 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6153 {
6154         kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6155 }
6156
6157 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6158 {
6159         if (!need_emulate_wbinvd(vcpu))
6160                 return X86EMUL_CONTINUE;
6161
6162         if (kvm_x86_ops.has_wbinvd_exit()) {
6163                 int cpu = get_cpu();
6164
6165                 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6166                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6167                                 wbinvd_ipi, NULL, 1);
6168                 put_cpu();
6169                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6170         } else
6171                 wbinvd();
6172         return X86EMUL_CONTINUE;
6173 }
6174
6175 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6176 {
6177         kvm_emulate_wbinvd_noskip(vcpu);
6178         return kvm_skip_emulated_instruction(vcpu);
6179 }
6180 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6181
6182
6183
6184 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6185 {
6186         kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6187 }
6188
6189 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6190                            unsigned long *dest)
6191 {
6192         return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6193 }
6194
6195 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6196                            unsigned long value)
6197 {
6198
6199         return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6200 }
6201
6202 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6203 {
6204         return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6205 }
6206
6207 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6208 {
6209         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6210         unsigned long value;
6211
6212         switch (cr) {
6213         case 0:
6214                 value = kvm_read_cr0(vcpu);
6215                 break;
6216         case 2:
6217                 value = vcpu->arch.cr2;
6218                 break;
6219         case 3:
6220                 value = kvm_read_cr3(vcpu);
6221                 break;
6222         case 4:
6223                 value = kvm_read_cr4(vcpu);
6224                 break;
6225         case 8:
6226                 value = kvm_get_cr8(vcpu);
6227                 break;
6228         default:
6229                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6230                 return 0;
6231         }
6232
6233         return value;
6234 }
6235
6236 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6237 {
6238         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6239         int res = 0;
6240
6241         switch (cr) {
6242         case 0:
6243                 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6244                 break;
6245         case 2:
6246                 vcpu->arch.cr2 = val;
6247                 break;
6248         case 3:
6249                 res = kvm_set_cr3(vcpu, val);
6250                 break;
6251         case 4:
6252                 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6253                 break;
6254         case 8:
6255                 res = kvm_set_cr8(vcpu, val);
6256                 break;
6257         default:
6258                 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6259                 res = -1;
6260         }
6261
6262         return res;
6263 }
6264
6265 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6266 {
6267         return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6268 }
6269
6270 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6271 {
6272         kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6273 }
6274
6275 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6276 {
6277         kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6278 }
6279
6280 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6281 {
6282         kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6283 }
6284
6285 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6286 {
6287         kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6288 }
6289
6290 static unsigned long emulator_get_cached_segment_base(
6291         struct x86_emulate_ctxt *ctxt, int seg)
6292 {
6293         return get_segment_base(emul_to_vcpu(ctxt), seg);
6294 }
6295
6296 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6297                                  struct desc_struct *desc, u32 *base3,
6298                                  int seg)
6299 {
6300         struct kvm_segment var;
6301
6302         kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6303         *selector = var.selector;
6304
6305         if (var.unusable) {
6306                 memset(desc, 0, sizeof(*desc));
6307                 if (base3)
6308                         *base3 = 0;
6309                 return false;
6310         }
6311
6312         if (var.g)
6313                 var.limit >>= 12;
6314         set_desc_limit(desc, var.limit);
6315         set_desc_base(desc, (unsigned long)var.base);
6316 #ifdef CONFIG_X86_64
6317         if (base3)
6318                 *base3 = var.base >> 32;
6319 #endif
6320         desc->type = var.type;
6321         desc->s = var.s;
6322         desc->dpl = var.dpl;
6323         desc->p = var.present;
6324         desc->avl = var.avl;
6325         desc->l = var.l;
6326         desc->d = var.db;
6327         desc->g = var.g;
6328
6329         return true;
6330 }
6331
6332 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6333                                  struct desc_struct *desc, u32 base3,
6334                                  int seg)
6335 {
6336         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6337         struct kvm_segment var;
6338
6339         var.selector = selector;
6340         var.base = get_desc_base(desc);
6341 #ifdef CONFIG_X86_64
6342         var.base |= ((u64)base3) << 32;
6343 #endif
6344         var.limit = get_desc_limit(desc);
6345         if (desc->g)
6346                 var.limit = (var.limit << 12) | 0xfff;
6347         var.type = desc->type;
6348         var.dpl = desc->dpl;
6349         var.db = desc->d;
6350         var.s = desc->s;
6351         var.l = desc->l;
6352         var.g = desc->g;
6353         var.avl = desc->avl;
6354         var.present = desc->p;
6355         var.unusable = !var.present;
6356         var.padding = 0;
6357
6358         kvm_set_segment(vcpu, &var, seg);
6359         return;
6360 }
6361
6362 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6363                             u32 msr_index, u64 *pdata)
6364 {
6365         return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
6366 }
6367
6368 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6369                             u32 msr_index, u64 data)
6370 {
6371         return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
6372 }
6373
6374 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6375 {
6376         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6377
6378         return vcpu->arch.smbase;
6379 }
6380
6381 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6382 {
6383         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6384
6385         vcpu->arch.smbase = smbase;
6386 }
6387
6388 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6389                               u32 pmc)
6390 {
6391         return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6392 }
6393
6394 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6395                              u32 pmc, u64 *pdata)
6396 {
6397         return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6398 }
6399
6400 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6401 {
6402         emul_to_vcpu(ctxt)->arch.halt_request = 1;
6403 }
6404
6405 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6406                               struct x86_instruction_info *info,
6407                               enum x86_intercept_stage stage)
6408 {
6409         return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6410                                             &ctxt->exception);
6411 }
6412
6413 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6414                               u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6415                               bool exact_only)
6416 {
6417         return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6418 }
6419
6420 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6421 {
6422         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6423 }
6424
6425 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6426 {
6427         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6428 }
6429
6430 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6431 {
6432         return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6433 }
6434
6435 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6436 {
6437         return kvm_register_read(emul_to_vcpu(ctxt), reg);
6438 }
6439
6440 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6441 {
6442         kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6443 }
6444
6445 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6446 {
6447         kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6448 }
6449
6450 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6451 {
6452         return emul_to_vcpu(ctxt)->arch.hflags;
6453 }
6454
6455 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6456 {
6457         emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6458 }
6459
6460 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6461                                   const char *smstate)
6462 {
6463         return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6464 }
6465
6466 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6467 {
6468         kvm_smm_changed(emul_to_vcpu(ctxt));
6469 }
6470
6471 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6472 {
6473         return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6474 }
6475
6476 static const struct x86_emulate_ops emulate_ops = {
6477         .read_gpr            = emulator_read_gpr,
6478         .write_gpr           = emulator_write_gpr,
6479         .read_std            = emulator_read_std,
6480         .write_std           = emulator_write_std,
6481         .read_phys           = kvm_read_guest_phys_system,
6482         .fetch               = kvm_fetch_guest_virt,
6483         .read_emulated       = emulator_read_emulated,
6484         .write_emulated      = emulator_write_emulated,
6485         .cmpxchg_emulated    = emulator_cmpxchg_emulated,
6486         .invlpg              = emulator_invlpg,
6487         .pio_in_emulated     = emulator_pio_in_emulated,
6488         .pio_out_emulated    = emulator_pio_out_emulated,
6489         .get_segment         = emulator_get_segment,
6490         .set_segment         = emulator_set_segment,
6491         .get_cached_segment_base = emulator_get_cached_segment_base,
6492         .get_gdt             = emulator_get_gdt,
6493         .get_idt             = emulator_get_idt,
6494         .set_gdt             = emulator_set_gdt,
6495         .set_idt             = emulator_set_idt,
6496         .get_cr              = emulator_get_cr,
6497         .set_cr              = emulator_set_cr,
6498         .cpl                 = emulator_get_cpl,
6499         .get_dr              = emulator_get_dr,
6500         .set_dr              = emulator_set_dr,
6501         .get_smbase          = emulator_get_smbase,
6502         .set_smbase          = emulator_set_smbase,
6503         .set_msr             = emulator_set_msr,
6504         .get_msr             = emulator_get_msr,
6505         .check_pmc           = emulator_check_pmc,
6506         .read_pmc            = emulator_read_pmc,
6507         .halt                = emulator_halt,
6508         .wbinvd              = emulator_wbinvd,
6509         .fix_hypercall       = emulator_fix_hypercall,
6510         .intercept           = emulator_intercept,
6511         .get_cpuid           = emulator_get_cpuid,
6512         .guest_has_long_mode = emulator_guest_has_long_mode,
6513         .guest_has_movbe     = emulator_guest_has_movbe,
6514         .guest_has_fxsr      = emulator_guest_has_fxsr,
6515         .set_nmi_mask        = emulator_set_nmi_mask,
6516         .get_hflags          = emulator_get_hflags,
6517         .set_hflags          = emulator_set_hflags,
6518         .pre_leave_smm       = emulator_pre_leave_smm,
6519         .post_leave_smm      = emulator_post_leave_smm,
6520         .set_xcr             = emulator_set_xcr,
6521 };
6522
6523 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6524 {
6525         u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6526         /*
6527          * an sti; sti; sequence only disable interrupts for the first
6528          * instruction. So, if the last instruction, be it emulated or
6529          * not, left the system with the INT_STI flag enabled, it
6530          * means that the last instruction is an sti. We should not
6531          * leave the flag on in this case. The same goes for mov ss
6532          */
6533         if (int_shadow & mask)
6534                 mask = 0;
6535         if (unlikely(int_shadow || mask)) {
6536                 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6537                 if (!mask)
6538                         kvm_make_request(KVM_REQ_EVENT, vcpu);
6539         }
6540 }
6541
6542 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6543 {
6544         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6545         if (ctxt->exception.vector == PF_VECTOR)
6546                 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6547
6548         if (ctxt->exception.error_code_valid)
6549                 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6550                                       ctxt->exception.error_code);
6551         else
6552                 kvm_queue_exception(vcpu, ctxt->exception.vector);
6553         return false;
6554 }
6555
6556 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6557 {
6558         struct x86_emulate_ctxt *ctxt;
6559
6560         ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6561         if (!ctxt) {
6562                 pr_err("kvm: failed to allocate vcpu's emulator\n");
6563                 return NULL;
6564         }
6565
6566         ctxt->vcpu = vcpu;
6567         ctxt->ops = &emulate_ops;
6568         vcpu->arch.emulate_ctxt = ctxt;
6569
6570         return ctxt;
6571 }
6572
6573 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6574 {
6575         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6576         int cs_db, cs_l;
6577
6578         kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6579
6580         ctxt->gpa_available = false;
6581         ctxt->eflags = kvm_get_rflags(vcpu);
6582         ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6583
6584         ctxt->eip = kvm_rip_read(vcpu);
6585         ctxt->mode = (!is_protmode(vcpu))               ? X86EMUL_MODE_REAL :
6586                      (ctxt->eflags & X86_EFLAGS_VM)     ? X86EMUL_MODE_VM86 :
6587                      (cs_l && is_long_mode(vcpu))       ? X86EMUL_MODE_PROT64 :
6588                      cs_db                              ? X86EMUL_MODE_PROT32 :
6589                                                           X86EMUL_MODE_PROT16;
6590         BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6591         BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6592         BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6593
6594         init_decode_cache(ctxt);
6595         vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6596 }
6597
6598 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6599 {
6600         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6601         int ret;
6602
6603         init_emulate_ctxt(vcpu);
6604
6605         ctxt->op_bytes = 2;
6606         ctxt->ad_bytes = 2;
6607         ctxt->_eip = ctxt->eip + inc_eip;
6608         ret = emulate_int_real(ctxt, irq);
6609
6610         if (ret != X86EMUL_CONTINUE) {
6611                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6612         } else {
6613                 ctxt->eip = ctxt->_eip;
6614                 kvm_rip_write(vcpu, ctxt->eip);
6615                 kvm_set_rflags(vcpu, ctxt->eflags);
6616         }
6617 }
6618 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6619
6620 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6621 {
6622         ++vcpu->stat.insn_emulation_fail;
6623         trace_kvm_emulate_insn_failed(vcpu);
6624
6625         if (emulation_type & EMULTYPE_VMWARE_GP) {
6626                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6627                 return 1;
6628         }
6629
6630         if (emulation_type & EMULTYPE_SKIP) {
6631                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6632                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6633                 vcpu->run->internal.ndata = 0;
6634                 return 0;
6635         }
6636
6637         kvm_queue_exception(vcpu, UD_VECTOR);
6638
6639         if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
6640                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6641                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6642                 vcpu->run->internal.ndata = 0;
6643                 return 0;
6644         }
6645
6646         return 1;
6647 }
6648
6649 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6650                                   bool write_fault_to_shadow_pgtable,
6651                                   int emulation_type)
6652 {
6653         gpa_t gpa = cr2_or_gpa;
6654         kvm_pfn_t pfn;
6655
6656         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6657                 return false;
6658
6659         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6660             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6661                 return false;
6662
6663         if (!vcpu->arch.mmu->direct_map) {
6664                 /*
6665                  * Write permission should be allowed since only
6666                  * write access need to be emulated.
6667                  */
6668                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6669
6670                 /*
6671                  * If the mapping is invalid in guest, let cpu retry
6672                  * it to generate fault.
6673                  */
6674                 if (gpa == UNMAPPED_GVA)
6675                         return true;
6676         }
6677
6678         /*
6679          * Do not retry the unhandleable instruction if it faults on the
6680          * readonly host memory, otherwise it will goto a infinite loop:
6681          * retry instruction -> write #PF -> emulation fail -> retry
6682          * instruction -> ...
6683          */
6684         pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
6685
6686         /*
6687          * If the instruction failed on the error pfn, it can not be fixed,
6688          * report the error to userspace.
6689          */
6690         if (is_error_noslot_pfn(pfn))
6691                 return false;
6692
6693         kvm_release_pfn_clean(pfn);
6694
6695         /* The instructions are well-emulated on direct mmu. */
6696         if (vcpu->arch.mmu->direct_map) {
6697                 unsigned int indirect_shadow_pages;
6698
6699                 spin_lock(&vcpu->kvm->mmu_lock);
6700                 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6701                 spin_unlock(&vcpu->kvm->mmu_lock);
6702
6703                 if (indirect_shadow_pages)
6704                         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6705
6706                 return true;
6707         }
6708
6709         /*
6710          * if emulation was due to access to shadowed page table
6711          * and it failed try to unshadow page and re-enter the
6712          * guest to let CPU execute the instruction.
6713          */
6714         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6715
6716         /*
6717          * If the access faults on its page table, it can not
6718          * be fixed by unprotecting shadow page and it should
6719          * be reported to userspace.
6720          */
6721         return !write_fault_to_shadow_pgtable;
6722 }
6723
6724 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6725                               gpa_t cr2_or_gpa,  int emulation_type)
6726 {
6727         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6728         unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
6729
6730         last_retry_eip = vcpu->arch.last_retry_eip;
6731         last_retry_addr = vcpu->arch.last_retry_addr;
6732
6733         /*
6734          * If the emulation is caused by #PF and it is non-page_table
6735          * writing instruction, it means the VM-EXIT is caused by shadow
6736          * page protected, we can zap the shadow page and retry this
6737          * instruction directly.
6738          *
6739          * Note: if the guest uses a non-page-table modifying instruction
6740          * on the PDE that points to the instruction, then we will unmap
6741          * the instruction and go to an infinite loop. So, we cache the
6742          * last retried eip and the last fault address, if we meet the eip
6743          * and the address again, we can break out of the potential infinite
6744          * loop.
6745          */
6746         vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6747
6748         if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
6749                 return false;
6750
6751         if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
6752             WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
6753                 return false;
6754
6755         if (x86_page_table_writing_insn(ctxt))
6756                 return false;
6757
6758         if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
6759                 return false;
6760
6761         vcpu->arch.last_retry_eip = ctxt->eip;
6762         vcpu->arch.last_retry_addr = cr2_or_gpa;
6763
6764         if (!vcpu->arch.mmu->direct_map)
6765                 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
6766
6767         kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6768
6769         return true;
6770 }
6771
6772 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6773 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6774
6775 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
6776 {
6777         if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
6778                 /* This is a good place to trace that we are exiting SMM.  */
6779                 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6780
6781                 /* Process a latched INIT or SMI, if any.  */
6782                 kvm_make_request(KVM_REQ_EVENT, vcpu);
6783         }
6784
6785         kvm_mmu_reset_context(vcpu);
6786 }
6787
6788 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6789                                 unsigned long *db)
6790 {
6791         u32 dr6 = 0;
6792         int i;
6793         u32 enable, rwlen;
6794
6795         enable = dr7;
6796         rwlen = dr7 >> 16;
6797         for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6798                 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6799                         dr6 |= (1 << i);
6800         return dr6;
6801 }
6802
6803 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
6804 {
6805         struct kvm_run *kvm_run = vcpu->run;
6806
6807         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6808                 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6809                 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
6810                 kvm_run->debug.arch.exception = DB_VECTOR;
6811                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6812                 return 0;
6813         }
6814         kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
6815         return 1;
6816 }
6817
6818 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6819 {
6820         unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
6821         int r;
6822
6823         r = kvm_x86_ops.skip_emulated_instruction(vcpu);
6824         if (unlikely(!r))
6825                 return 0;
6826
6827         /*
6828          * rflags is the old, "raw" value of the flags.  The new value has
6829          * not been saved yet.
6830          *
6831          * This is correct even for TF set by the guest, because "the
6832          * processor will not generate this exception after the instruction
6833          * that sets the TF flag".
6834          */
6835         if (unlikely(rflags & X86_EFLAGS_TF))
6836                 r = kvm_vcpu_do_singlestep(vcpu);
6837         return r;
6838 }
6839 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6840
6841 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6842 {
6843         if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6844             (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
6845                 struct kvm_run *kvm_run = vcpu->run;
6846                 unsigned long eip = kvm_get_linear_rip(vcpu);
6847                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6848                                            vcpu->arch.guest_debug_dr7,
6849                                            vcpu->arch.eff_db);
6850
6851                 if (dr6 != 0) {
6852                         kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
6853                         kvm_run->debug.arch.pc = eip;
6854                         kvm_run->debug.arch.exception = DB_VECTOR;
6855                         kvm_run->exit_reason = KVM_EXIT_DEBUG;
6856                         *r = 0;
6857                         return true;
6858                 }
6859         }
6860
6861         if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6862             !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
6863                 unsigned long eip = kvm_get_linear_rip(vcpu);
6864                 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
6865                                            vcpu->arch.dr7,
6866                                            vcpu->arch.db);
6867
6868                 if (dr6 != 0) {
6869                         kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
6870                         *r = 1;
6871                         return true;
6872                 }
6873         }
6874
6875         return false;
6876 }
6877
6878 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6879 {
6880         switch (ctxt->opcode_len) {
6881         case 1:
6882                 switch (ctxt->b) {
6883                 case 0xe4:      /* IN */
6884                 case 0xe5:
6885                 case 0xec:
6886                 case 0xed:
6887                 case 0xe6:      /* OUT */
6888                 case 0xe7:
6889                 case 0xee:
6890                 case 0xef:
6891                 case 0x6c:      /* INS */
6892                 case 0x6d:
6893                 case 0x6e:      /* OUTS */
6894                 case 0x6f:
6895                         return true;
6896                 }
6897                 break;
6898         case 2:
6899                 switch (ctxt->b) {
6900                 case 0x33:      /* RDPMC */
6901                         return true;
6902                 }
6903                 break;
6904         }
6905
6906         return false;
6907 }
6908
6909 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6910                             int emulation_type, void *insn, int insn_len)
6911 {
6912         int r;
6913         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6914         bool writeback = true;
6915         bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
6916
6917         vcpu->arch.l1tf_flush_l1d = true;
6918
6919         /*
6920          * Clear write_fault_to_shadow_pgtable here to ensure it is
6921          * never reused.
6922          */
6923         vcpu->arch.write_fault_to_shadow_pgtable = false;
6924         kvm_clear_exception_queue(vcpu);
6925
6926         if (!(emulation_type & EMULTYPE_NO_DECODE)) {
6927                 init_emulate_ctxt(vcpu);
6928
6929                 /*
6930                  * We will reenter on the same instruction since
6931                  * we do not set complete_userspace_io.  This does not
6932                  * handle watchpoints yet, those would be handled in
6933                  * the emulate_ops.
6934                  */
6935                 if (!(emulation_type & EMULTYPE_SKIP) &&
6936                     kvm_vcpu_check_breakpoint(vcpu, &r))
6937                         return r;
6938
6939                 ctxt->interruptibility = 0;
6940                 ctxt->have_exception = false;
6941                 ctxt->exception.vector = -1;
6942                 ctxt->perm_ok = false;
6943
6944                 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
6945
6946                 r = x86_decode_insn(ctxt, insn, insn_len);
6947
6948                 trace_kvm_emulate_insn_start(vcpu);
6949                 ++vcpu->stat.insn_emulation;
6950                 if (r != EMULATION_OK)  {
6951                         if ((emulation_type & EMULTYPE_TRAP_UD) ||
6952                             (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6953                                 kvm_queue_exception(vcpu, UD_VECTOR);
6954                                 return 1;
6955                         }
6956                         if (reexecute_instruction(vcpu, cr2_or_gpa,
6957                                                   write_fault_to_spt,
6958                                                   emulation_type))
6959                                 return 1;
6960                         if (ctxt->have_exception) {
6961                                 /*
6962                                  * #UD should result in just EMULATION_FAILED, and trap-like
6963                                  * exception should not be encountered during decode.
6964                                  */
6965                                 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6966                                              exception_type(ctxt->exception.vector) == EXCPT_TRAP);
6967                                 inject_emulated_exception(vcpu);
6968                                 return 1;
6969                         }
6970                         return handle_emulation_failure(vcpu, emulation_type);
6971                 }
6972         }
6973
6974         if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6975             !is_vmware_backdoor_opcode(ctxt)) {
6976                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6977                 return 1;
6978         }
6979
6980         /*
6981          * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6982          * for kvm_skip_emulated_instruction().  The caller is responsible for
6983          * updating interruptibility state and injecting single-step #DBs.
6984          */
6985         if (emulation_type & EMULTYPE_SKIP) {
6986                 kvm_rip_write(vcpu, ctxt->_eip);
6987                 if (ctxt->eflags & X86_EFLAGS_RF)
6988                         kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
6989                 return 1;
6990         }
6991
6992         if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
6993                 return 1;
6994
6995         /* this is needed for vmware backdoor interface to work since it
6996            changes registers values  during IO operation */
6997         if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6998                 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6999                 emulator_invalidate_register_cache(ctxt);
7000         }
7001
7002 restart:
7003         if (emulation_type & EMULTYPE_PF) {
7004                 /* Save the faulting GPA (cr2) in the address field */
7005                 ctxt->exception.address = cr2_or_gpa;
7006
7007                 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7008                 if (vcpu->arch.mmu->direct_map) {
7009                         ctxt->gpa_available = true;
7010                         ctxt->gpa_val = cr2_or_gpa;
7011                 }
7012         } else {
7013                 /* Sanitize the address out of an abundance of paranoia. */
7014                 ctxt->exception.address = 0;
7015         }
7016
7017         r = x86_emulate_insn(ctxt);
7018
7019         if (r == EMULATION_INTERCEPTED)
7020                 return 1;
7021
7022         if (r == EMULATION_FAILED) {
7023                 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7024                                         emulation_type))
7025                         return 1;
7026
7027                 return handle_emulation_failure(vcpu, emulation_type);
7028         }
7029
7030         if (ctxt->have_exception) {
7031                 r = 1;
7032                 if (inject_emulated_exception(vcpu))
7033                         return r;
7034         } else if (vcpu->arch.pio.count) {
7035                 if (!vcpu->arch.pio.in) {
7036                         /* FIXME: return into emulator if single-stepping.  */
7037                         vcpu->arch.pio.count = 0;
7038                 } else {
7039                         writeback = false;
7040                         vcpu->arch.complete_userspace_io = complete_emulated_pio;
7041                 }
7042                 r = 0;
7043         } else if (vcpu->mmio_needed) {
7044                 ++vcpu->stat.mmio_exits;
7045
7046                 if (!vcpu->mmio_is_write)
7047                         writeback = false;
7048                 r = 0;
7049                 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7050         } else if (r == EMULATION_RESTART)
7051                 goto restart;
7052         else
7053                 r = 1;
7054
7055         if (writeback) {
7056                 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7057                 toggle_interruptibility(vcpu, ctxt->interruptibility);
7058                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7059                 if (!ctxt->have_exception ||
7060                     exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7061                         kvm_rip_write(vcpu, ctxt->eip);
7062                         if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7063                                 r = kvm_vcpu_do_singlestep(vcpu);
7064                         if (kvm_x86_ops.update_emulated_instruction)
7065                                 kvm_x86_ops.update_emulated_instruction(vcpu);
7066                         __kvm_set_rflags(vcpu, ctxt->eflags);
7067                 }
7068
7069                 /*
7070                  * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7071                  * do nothing, and it will be requested again as soon as
7072                  * the shadow expires.  But we still need to check here,
7073                  * because POPF has no interrupt shadow.
7074                  */
7075                 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7076                         kvm_make_request(KVM_REQ_EVENT, vcpu);
7077         } else
7078                 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7079
7080         return r;
7081 }
7082
7083 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7084 {
7085         return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7086 }
7087 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7088
7089 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7090                                         void *insn, int insn_len)
7091 {
7092         return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7093 }
7094 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7095
7096 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7097 {
7098         vcpu->arch.pio.count = 0;
7099         return 1;
7100 }
7101
7102 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7103 {
7104         vcpu->arch.pio.count = 0;
7105
7106         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7107                 return 1;
7108
7109         return kvm_skip_emulated_instruction(vcpu);
7110 }
7111
7112 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7113                             unsigned short port)
7114 {
7115         unsigned long val = kvm_rax_read(vcpu);
7116         int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7117
7118         if (ret)
7119                 return ret;
7120
7121         /*
7122          * Workaround userspace that relies on old KVM behavior of %rip being
7123          * incremented prior to exiting to userspace to handle "OUT 0x7e".
7124          */
7125         if (port == 0x7e &&
7126             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7127                 vcpu->arch.complete_userspace_io =
7128                         complete_fast_pio_out_port_0x7e;
7129                 kvm_skip_emulated_instruction(vcpu);
7130         } else {
7131                 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7132                 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7133         }
7134         return 0;
7135 }
7136
7137 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7138 {
7139         unsigned long val;
7140
7141         /* We should only ever be called with arch.pio.count equal to 1 */
7142         BUG_ON(vcpu->arch.pio.count != 1);
7143
7144         if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7145                 vcpu->arch.pio.count = 0;
7146                 return 1;
7147         }
7148
7149         /* For size less than 4 we merge, else we zero extend */
7150         val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7151
7152         /*
7153          * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7154          * the copy and tracing
7155          */
7156         emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7157         kvm_rax_write(vcpu, val);
7158
7159         return kvm_skip_emulated_instruction(vcpu);
7160 }
7161
7162 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7163                            unsigned short port)
7164 {
7165         unsigned long val;
7166         int ret;
7167
7168         /* For size less than 4 we merge, else we zero extend */
7169         val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7170
7171         ret = emulator_pio_in(vcpu, size, port, &val, 1);
7172         if (ret) {
7173                 kvm_rax_write(vcpu, val);
7174                 return ret;
7175         }
7176
7177         vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7178         vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7179
7180         return 0;
7181 }
7182
7183 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7184 {
7185         int ret;
7186
7187         if (in)
7188                 ret = kvm_fast_pio_in(vcpu, size, port);
7189         else
7190                 ret = kvm_fast_pio_out(vcpu, size, port);
7191         return ret && kvm_skip_emulated_instruction(vcpu);
7192 }
7193 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7194
7195 static int kvmclock_cpu_down_prep(unsigned int cpu)
7196 {
7197         __this_cpu_write(cpu_tsc_khz, 0);
7198         return 0;
7199 }
7200
7201 static void tsc_khz_changed(void *data)
7202 {
7203         struct cpufreq_freqs *freq = data;
7204         unsigned long khz = 0;
7205
7206         if (data)
7207                 khz = freq->new;
7208         else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7209                 khz = cpufreq_quick_get(raw_smp_processor_id());
7210         if (!khz)
7211                 khz = tsc_khz;
7212         __this_cpu_write(cpu_tsc_khz, khz);
7213 }
7214
7215 #ifdef CONFIG_X86_64
7216 static void kvm_hyperv_tsc_notifier(void)
7217 {
7218         struct kvm *kvm;
7219         struct kvm_vcpu *vcpu;
7220         int cpu;
7221
7222         mutex_lock(&kvm_lock);
7223         list_for_each_entry(kvm, &vm_list, vm_list)
7224                 kvm_make_mclock_inprogress_request(kvm);
7225
7226         hyperv_stop_tsc_emulation();
7227
7228         /* TSC frequency always matches when on Hyper-V */
7229         for_each_present_cpu(cpu)
7230                 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7231         kvm_max_guest_tsc_khz = tsc_khz;
7232
7233         list_for_each_entry(kvm, &vm_list, vm_list) {
7234                 struct kvm_arch *ka = &kvm->arch;
7235
7236                 spin_lock(&ka->pvclock_gtod_sync_lock);
7237
7238                 pvclock_update_vm_gtod_copy(kvm);
7239
7240                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7241                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7242
7243                 kvm_for_each_vcpu(cpu, vcpu, kvm)
7244                         kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7245
7246                 spin_unlock(&ka->pvclock_gtod_sync_lock);
7247         }
7248         mutex_unlock(&kvm_lock);
7249 }
7250 #endif
7251
7252 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7253 {
7254         struct kvm *kvm;
7255         struct kvm_vcpu *vcpu;
7256         int i, send_ipi = 0;
7257
7258         /*
7259          * We allow guests to temporarily run on slowing clocks,
7260          * provided we notify them after, or to run on accelerating
7261          * clocks, provided we notify them before.  Thus time never
7262          * goes backwards.
7263          *
7264          * However, we have a problem.  We can't atomically update
7265          * the frequency of a given CPU from this function; it is
7266          * merely a notifier, which can be called from any CPU.
7267          * Changing the TSC frequency at arbitrary points in time
7268          * requires a recomputation of local variables related to
7269          * the TSC for each VCPU.  We must flag these local variables
7270          * to be updated and be sure the update takes place with the
7271          * new frequency before any guests proceed.
7272          *
7273          * Unfortunately, the combination of hotplug CPU and frequency
7274          * change creates an intractable locking scenario; the order
7275          * of when these callouts happen is undefined with respect to
7276          * CPU hotplug, and they can race with each other.  As such,
7277          * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7278          * undefined; you can actually have a CPU frequency change take
7279          * place in between the computation of X and the setting of the
7280          * variable.  To protect against this problem, all updates of
7281          * the per_cpu tsc_khz variable are done in an interrupt
7282          * protected IPI, and all callers wishing to update the value
7283          * must wait for a synchronous IPI to complete (which is trivial
7284          * if the caller is on the CPU already).  This establishes the
7285          * necessary total order on variable updates.
7286          *
7287          * Note that because a guest time update may take place
7288          * anytime after the setting of the VCPU's request bit, the
7289          * correct TSC value must be set before the request.  However,
7290          * to ensure the update actually makes it to any guest which
7291          * starts running in hardware virtualization between the set
7292          * and the acquisition of the spinlock, we must also ping the
7293          * CPU after setting the request bit.
7294          *
7295          */
7296
7297         smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7298
7299         mutex_lock(&kvm_lock);
7300         list_for_each_entry(kvm, &vm_list, vm_list) {
7301                 kvm_for_each_vcpu(i, vcpu, kvm) {
7302                         if (vcpu->cpu != cpu)
7303                                 continue;
7304                         kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7305                         if (vcpu->cpu != raw_smp_processor_id())
7306                                 send_ipi = 1;
7307                 }
7308         }
7309         mutex_unlock(&kvm_lock);
7310
7311         if (freq->old < freq->new && send_ipi) {
7312                 /*
7313                  * We upscale the frequency.  Must make the guest
7314                  * doesn't see old kvmclock values while running with
7315                  * the new frequency, otherwise we risk the guest sees
7316                  * time go backwards.
7317                  *
7318                  * In case we update the frequency for another cpu
7319                  * (which might be in guest context) send an interrupt
7320                  * to kick the cpu out of guest context.  Next time
7321                  * guest context is entered kvmclock will be updated,
7322                  * so the guest will not see stale values.
7323                  */
7324                 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7325         }
7326 }
7327
7328 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7329                                      void *data)
7330 {
7331         struct cpufreq_freqs *freq = data;
7332         int cpu;
7333
7334         if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7335                 return 0;
7336         if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7337                 return 0;
7338
7339         for_each_cpu(cpu, freq->policy->cpus)
7340                 __kvmclock_cpufreq_notifier(freq, cpu);
7341
7342         return 0;
7343 }
7344
7345 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7346         .notifier_call  = kvmclock_cpufreq_notifier
7347 };
7348
7349 static int kvmclock_cpu_online(unsigned int cpu)
7350 {
7351         tsc_khz_changed(NULL);
7352         return 0;
7353 }
7354
7355 static void kvm_timer_init(void)
7356 {
7357         max_tsc_khz = tsc_khz;
7358
7359         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7360 #ifdef CONFIG_CPU_FREQ
7361                 struct cpufreq_policy *policy;
7362                 int cpu;
7363
7364                 cpu = get_cpu();
7365                 policy = cpufreq_cpu_get(cpu);
7366                 if (policy) {
7367                         if (policy->cpuinfo.max_freq)
7368                                 max_tsc_khz = policy->cpuinfo.max_freq;
7369                         cpufreq_cpu_put(policy);
7370                 }
7371                 put_cpu();
7372 #endif
7373                 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7374                                           CPUFREQ_TRANSITION_NOTIFIER);
7375         }
7376
7377         cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7378                           kvmclock_cpu_online, kvmclock_cpu_down_prep);
7379 }
7380
7381 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7382 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7383
7384 int kvm_is_in_guest(void)
7385 {
7386         return __this_cpu_read(current_vcpu) != NULL;
7387 }
7388
7389 static int kvm_is_user_mode(void)
7390 {
7391         int user_mode = 3;
7392
7393         if (__this_cpu_read(current_vcpu))
7394                 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7395
7396         return user_mode != 0;
7397 }
7398
7399 static unsigned long kvm_get_guest_ip(void)
7400 {
7401         unsigned long ip = 0;
7402
7403         if (__this_cpu_read(current_vcpu))
7404                 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7405
7406         return ip;
7407 }
7408
7409 static void kvm_handle_intel_pt_intr(void)
7410 {
7411         struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7412
7413         kvm_make_request(KVM_REQ_PMI, vcpu);
7414         __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7415                         (unsigned long *)&vcpu->arch.pmu.global_status);
7416 }
7417
7418 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7419         .is_in_guest            = kvm_is_in_guest,
7420         .is_user_mode           = kvm_is_user_mode,
7421         .get_guest_ip           = kvm_get_guest_ip,
7422         .handle_intel_pt_intr   = kvm_handle_intel_pt_intr,
7423 };
7424
7425 #ifdef CONFIG_X86_64
7426 static void pvclock_gtod_update_fn(struct work_struct *work)
7427 {
7428         struct kvm *kvm;
7429
7430         struct kvm_vcpu *vcpu;
7431         int i;
7432
7433         mutex_lock(&kvm_lock);
7434         list_for_each_entry(kvm, &vm_list, vm_list)
7435                 kvm_for_each_vcpu(i, vcpu, kvm)
7436                         kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7437         atomic_set(&kvm_guest_has_master_clock, 0);
7438         mutex_unlock(&kvm_lock);
7439 }
7440
7441 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7442
7443 /*
7444  * Notification about pvclock gtod data update.
7445  */
7446 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7447                                void *priv)
7448 {
7449         struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7450         struct timekeeper *tk = priv;
7451
7452         update_pvclock_gtod(tk);
7453
7454         /* disable master clock if host does not trust, or does not
7455          * use, TSC based clocksource.
7456          */
7457         if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7458             atomic_read(&kvm_guest_has_master_clock) != 0)
7459                 queue_work(system_long_wq, &pvclock_gtod_work);
7460
7461         return 0;
7462 }
7463
7464 static struct notifier_block pvclock_gtod_notifier = {
7465         .notifier_call = pvclock_gtod_notify,
7466 };
7467 #endif
7468
7469 int kvm_arch_init(void *opaque)
7470 {
7471         struct kvm_x86_init_ops *ops = opaque;
7472         int r;
7473
7474         if (kvm_x86_ops.hardware_enable) {
7475                 printk(KERN_ERR "kvm: already loaded the other module\n");
7476                 r = -EEXIST;
7477                 goto out;
7478         }
7479
7480         if (!ops->cpu_has_kvm_support()) {
7481                 pr_err_ratelimited("kvm: no hardware support\n");
7482                 r = -EOPNOTSUPP;
7483                 goto out;
7484         }
7485         if (ops->disabled_by_bios()) {
7486                 pr_err_ratelimited("kvm: disabled by bios\n");
7487                 r = -EOPNOTSUPP;
7488                 goto out;
7489         }
7490
7491         /*
7492          * KVM explicitly assumes that the guest has an FPU and
7493          * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7494          * vCPU's FPU state as a fxregs_state struct.
7495          */
7496         if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7497                 printk(KERN_ERR "kvm: inadequate fpu\n");
7498                 r = -EOPNOTSUPP;
7499                 goto out;
7500         }
7501
7502         r = -ENOMEM;
7503         x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7504                                           __alignof__(struct fpu), SLAB_ACCOUNT,
7505                                           NULL);
7506         if (!x86_fpu_cache) {
7507                 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7508                 goto out;
7509         }
7510
7511         x86_emulator_cache = kvm_alloc_emulator_cache();
7512         if (!x86_emulator_cache) {
7513                 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7514                 goto out_free_x86_fpu_cache;
7515         }
7516
7517         shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7518         if (!shared_msrs) {
7519                 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
7520                 goto out_free_x86_emulator_cache;
7521         }
7522
7523         r = kvm_mmu_module_init();
7524         if (r)
7525                 goto out_free_percpu;
7526
7527         kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7528                         PT_DIRTY_MASK, PT64_NX_MASK, 0,
7529                         PT_PRESENT_MASK, 0, sme_me_mask);
7530         kvm_timer_init();
7531
7532         perf_register_guest_info_callbacks(&kvm_guest_cbs);
7533
7534         if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7535                 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7536                 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7537         }
7538
7539         kvm_lapic_init();
7540         if (pi_inject_timer == -1)
7541                 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7542 #ifdef CONFIG_X86_64
7543         pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7544
7545         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7546                 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7547 #endif
7548
7549         return 0;
7550
7551 out_free_percpu:
7552         free_percpu(shared_msrs);
7553 out_free_x86_emulator_cache:
7554         kmem_cache_destroy(x86_emulator_cache);
7555 out_free_x86_fpu_cache:
7556         kmem_cache_destroy(x86_fpu_cache);
7557 out:
7558         return r;
7559 }
7560
7561 void kvm_arch_exit(void)
7562 {
7563 #ifdef CONFIG_X86_64
7564         if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7565                 clear_hv_tscchange_cb();
7566 #endif
7567         kvm_lapic_exit();
7568         perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7569
7570         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7571                 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7572                                             CPUFREQ_TRANSITION_NOTIFIER);
7573         cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7574 #ifdef CONFIG_X86_64
7575         pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7576 #endif
7577         kvm_x86_ops.hardware_enable = NULL;
7578         kvm_mmu_module_exit();
7579         free_percpu(shared_msrs);
7580         kmem_cache_destroy(x86_fpu_cache);
7581 }
7582
7583 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7584 {
7585         ++vcpu->stat.halt_exits;
7586         if (lapic_in_kernel(vcpu)) {
7587                 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7588                 return 1;
7589         } else {
7590                 vcpu->run->exit_reason = KVM_EXIT_HLT;
7591                 return 0;
7592         }
7593 }
7594 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7595
7596 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7597 {
7598         int ret = kvm_skip_emulated_instruction(vcpu);
7599         /*
7600          * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7601          * KVM_EXIT_DEBUG here.
7602          */
7603         return kvm_vcpu_halt(vcpu) && ret;
7604 }
7605 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7606
7607 #ifdef CONFIG_X86_64
7608 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7609                                 unsigned long clock_type)
7610 {
7611         struct kvm_clock_pairing clock_pairing;
7612         struct timespec64 ts;
7613         u64 cycle;
7614         int ret;
7615
7616         if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7617                 return -KVM_EOPNOTSUPP;
7618
7619         if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7620                 return -KVM_EOPNOTSUPP;
7621
7622         clock_pairing.sec = ts.tv_sec;
7623         clock_pairing.nsec = ts.tv_nsec;
7624         clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7625         clock_pairing.flags = 0;
7626         memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7627
7628         ret = 0;
7629         if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7630                             sizeof(struct kvm_clock_pairing)))
7631                 ret = -KVM_EFAULT;
7632
7633         return ret;
7634 }
7635 #endif
7636
7637 /*
7638  * kvm_pv_kick_cpu_op:  Kick a vcpu.
7639  *
7640  * @apicid - apicid of vcpu to be kicked.
7641  */
7642 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7643 {
7644         struct kvm_lapic_irq lapic_irq;
7645
7646         lapic_irq.shorthand = APIC_DEST_NOSHORT;
7647         lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
7648         lapic_irq.level = 0;
7649         lapic_irq.dest_id = apicid;
7650         lapic_irq.msi_redir_hint = false;
7651
7652         lapic_irq.delivery_mode = APIC_DM_REMRD;
7653         kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
7654 }
7655
7656 bool kvm_apicv_activated(struct kvm *kvm)
7657 {
7658         return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7659 }
7660 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7661
7662 void kvm_apicv_init(struct kvm *kvm, bool enable)
7663 {
7664         if (enable)
7665                 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7666                           &kvm->arch.apicv_inhibit_reasons);
7667         else
7668                 set_bit(APICV_INHIBIT_REASON_DISABLE,
7669                         &kvm->arch.apicv_inhibit_reasons);
7670 }
7671 EXPORT_SYMBOL_GPL(kvm_apicv_init);
7672
7673 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7674 {
7675         struct kvm_vcpu *target = NULL;
7676         struct kvm_apic_map *map;
7677
7678         rcu_read_lock();
7679         map = rcu_dereference(kvm->arch.apic_map);
7680
7681         if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7682                 target = map->phys_map[dest_id]->vcpu;
7683
7684         rcu_read_unlock();
7685
7686         if (target && READ_ONCE(target->ready))
7687                 kvm_vcpu_yield_to(target);
7688 }
7689
7690 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7691 {
7692         unsigned long nr, a0, a1, a2, a3, ret;
7693         int op_64_bit;
7694
7695         if (kvm_hv_hypercall_enabled(vcpu->kvm))
7696                 return kvm_hv_hypercall(vcpu);
7697
7698         nr = kvm_rax_read(vcpu);
7699         a0 = kvm_rbx_read(vcpu);
7700         a1 = kvm_rcx_read(vcpu);
7701         a2 = kvm_rdx_read(vcpu);
7702         a3 = kvm_rsi_read(vcpu);
7703
7704         trace_kvm_hypercall(nr, a0, a1, a2, a3);
7705
7706         op_64_bit = is_64_bit_mode(vcpu);
7707         if (!op_64_bit) {
7708                 nr &= 0xFFFFFFFF;
7709                 a0 &= 0xFFFFFFFF;
7710                 a1 &= 0xFFFFFFFF;
7711                 a2 &= 0xFFFFFFFF;
7712                 a3 &= 0xFFFFFFFF;
7713         }
7714
7715         if (kvm_x86_ops.get_cpl(vcpu) != 0) {
7716                 ret = -KVM_EPERM;
7717                 goto out;
7718         }
7719
7720         switch (nr) {
7721         case KVM_HC_VAPIC_POLL_IRQ:
7722                 ret = 0;
7723                 break;
7724         case KVM_HC_KICK_CPU:
7725                 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7726                 kvm_sched_yield(vcpu->kvm, a1);
7727                 ret = 0;
7728                 break;
7729 #ifdef CONFIG_X86_64
7730         case KVM_HC_CLOCK_PAIRING:
7731                 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7732                 break;
7733 #endif
7734         case KVM_HC_SEND_IPI:
7735                 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7736                 break;
7737         case KVM_HC_SCHED_YIELD:
7738                 kvm_sched_yield(vcpu->kvm, a0);
7739                 ret = 0;
7740                 break;
7741         default:
7742                 ret = -KVM_ENOSYS;
7743                 break;
7744         }
7745 out:
7746         if (!op_64_bit)
7747                 ret = (u32)ret;
7748         kvm_rax_write(vcpu, ret);
7749
7750         ++vcpu->stat.hypercalls;
7751         return kvm_skip_emulated_instruction(vcpu);
7752 }
7753 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7754
7755 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
7756 {
7757         struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7758         char instruction[3];
7759         unsigned long rip = kvm_rip_read(vcpu);
7760
7761         kvm_x86_ops.patch_hypercall(vcpu, instruction);
7762
7763         return emulator_write_emulated(ctxt, rip, instruction, 3,
7764                 &ctxt->exception);
7765 }
7766
7767 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
7768 {
7769         return vcpu->run->request_interrupt_window &&
7770                 likely(!pic_in_kernel(vcpu->kvm));
7771 }
7772
7773 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
7774 {
7775         struct kvm_run *kvm_run = vcpu->run;
7776
7777         kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
7778         kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
7779         kvm_run->cr8 = kvm_get_cr8(vcpu);
7780         kvm_run->apic_base = kvm_get_apic_base(vcpu);
7781         kvm_run->ready_for_interrupt_injection =
7782                 pic_in_kernel(vcpu->kvm) ||
7783                 kvm_vcpu_ready_for_interrupt_injection(vcpu);
7784 }
7785
7786 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7787 {
7788         int max_irr, tpr;
7789
7790         if (!kvm_x86_ops.update_cr8_intercept)
7791                 return;
7792
7793         if (!lapic_in_kernel(vcpu))
7794                 return;
7795
7796         if (vcpu->arch.apicv_active)
7797                 return;
7798
7799         if (!vcpu->arch.apic->vapic_addr)
7800                 max_irr = kvm_lapic_find_highest_irr(vcpu);
7801         else
7802                 max_irr = -1;
7803
7804         if (max_irr != -1)
7805                 max_irr >>= 4;
7806
7807         tpr = kvm_lapic_get_cr8(vcpu);
7808
7809         kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
7810 }
7811
7812 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
7813 {
7814         int r;
7815         bool can_inject = true;
7816
7817         /* try to reinject previous events if any */
7818
7819         if (vcpu->arch.exception.injected) {
7820                 kvm_x86_ops.queue_exception(vcpu);
7821                 can_inject = false;
7822         }
7823         /*
7824          * Do not inject an NMI or interrupt if there is a pending
7825          * exception.  Exceptions and interrupts are recognized at
7826          * instruction boundaries, i.e. the start of an instruction.
7827          * Trap-like exceptions, e.g. #DB, have higher priority than
7828          * NMIs and interrupts, i.e. traps are recognized before an
7829          * NMI/interrupt that's pending on the same instruction.
7830          * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7831          * priority, but are only generated (pended) during instruction
7832          * execution, i.e. a pending fault-like exception means the
7833          * fault occurred on the *previous* instruction and must be
7834          * serviced prior to recognizing any new events in order to
7835          * fully complete the previous instruction.
7836          */
7837         else if (!vcpu->arch.exception.pending) {
7838                 if (vcpu->arch.nmi_injected) {
7839                         kvm_x86_ops.set_nmi(vcpu);
7840                         can_inject = false;
7841                 } else if (vcpu->arch.interrupt.injected) {
7842                         kvm_x86_ops.set_irq(vcpu);
7843                         can_inject = false;
7844                 }
7845         }
7846
7847         WARN_ON_ONCE(vcpu->arch.exception.injected &&
7848                      vcpu->arch.exception.pending);
7849
7850         /*
7851          * Call check_nested_events() even if we reinjected a previous event
7852          * in order for caller to determine if it should require immediate-exit
7853          * from L2 to L1 due to pending L1 events which require exit
7854          * from L2 to L1.
7855          */
7856         if (is_guest_mode(vcpu)) {
7857                 r = kvm_x86_ops.nested_ops->check_events(vcpu);
7858                 if (r < 0)
7859                         goto busy;
7860         }
7861
7862         /* try to inject new event if pending */
7863         if (vcpu->arch.exception.pending) {
7864                 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7865                                         vcpu->arch.exception.has_error_code,
7866                                         vcpu->arch.exception.error_code);
7867
7868                 vcpu->arch.exception.pending = false;
7869                 vcpu->arch.exception.injected = true;
7870
7871                 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7872                         __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7873                                              X86_EFLAGS_RF);
7874
7875                 if (vcpu->arch.exception.nr == DB_VECTOR) {
7876                         kvm_deliver_exception_payload(vcpu);
7877                         if (vcpu->arch.dr7 & DR7_GD) {
7878                                 vcpu->arch.dr7 &= ~DR7_GD;
7879                                 kvm_update_dr7(vcpu);
7880                         }
7881                 }
7882
7883                 kvm_x86_ops.queue_exception(vcpu);
7884                 can_inject = false;
7885         }
7886
7887         /*
7888          * Finally, inject interrupt events.  If an event cannot be injected
7889          * due to architectural conditions (e.g. IF=0) a window-open exit
7890          * will re-request KVM_REQ_EVENT.  Sometimes however an event is pending
7891          * and can architecturally be injected, but we cannot do it right now:
7892          * an interrupt could have arrived just now and we have to inject it
7893          * as a vmexit, or there could already an event in the queue, which is
7894          * indicated by can_inject.  In that case we request an immediate exit
7895          * in order to make progress and get back here for another iteration.
7896          * The kvm_x86_ops hooks communicate this by returning -EBUSY.
7897          */
7898         if (vcpu->arch.smi_pending) {
7899                 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
7900                 if (r < 0)
7901                         goto busy;
7902                 if (r) {
7903                         vcpu->arch.smi_pending = false;
7904                         ++vcpu->arch.smi_count;
7905                         enter_smm(vcpu);
7906                         can_inject = false;
7907                 } else
7908                         kvm_x86_ops.enable_smi_window(vcpu);
7909         }
7910
7911         if (vcpu->arch.nmi_pending) {
7912                 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
7913                 if (r < 0)
7914                         goto busy;
7915                 if (r) {
7916                         --vcpu->arch.nmi_pending;
7917                         vcpu->arch.nmi_injected = true;
7918                         kvm_x86_ops.set_nmi(vcpu);
7919                         can_inject = false;
7920                         WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
7921                 }
7922                 if (vcpu->arch.nmi_pending)
7923                         kvm_x86_ops.enable_nmi_window(vcpu);
7924         }
7925
7926         if (kvm_cpu_has_injectable_intr(vcpu)) {
7927                 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
7928                 if (r < 0)
7929                         goto busy;
7930                 if (r) {
7931                         kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
7932                         kvm_x86_ops.set_irq(vcpu);
7933                         WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
7934                 }
7935                 if (kvm_cpu_has_injectable_intr(vcpu))
7936                         kvm_x86_ops.enable_irq_window(vcpu);
7937         }
7938
7939         if (is_guest_mode(vcpu) &&
7940             kvm_x86_ops.nested_ops->hv_timer_pending &&
7941             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
7942                 *req_immediate_exit = true;
7943
7944         WARN_ON(vcpu->arch.exception.pending);
7945         return;
7946
7947 busy:
7948         *req_immediate_exit = true;
7949         return;
7950 }
7951
7952 static void process_nmi(struct kvm_vcpu *vcpu)
7953 {
7954         unsigned limit = 2;
7955
7956         /*
7957          * x86 is limited to one NMI running, and one NMI pending after it.
7958          * If an NMI is already in progress, limit further NMIs to just one.
7959          * Otherwise, allow two (and we'll inject the first one immediately).
7960          */
7961         if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7962                 limit = 1;
7963
7964         vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7965         vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7966         kvm_make_request(KVM_REQ_EVENT, vcpu);
7967 }
7968
7969 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
7970 {
7971         u32 flags = 0;
7972         flags |= seg->g       << 23;
7973         flags |= seg->db      << 22;
7974         flags |= seg->l       << 21;
7975         flags |= seg->avl     << 20;
7976         flags |= seg->present << 15;
7977         flags |= seg->dpl     << 13;
7978         flags |= seg->s       << 12;
7979         flags |= seg->type    << 8;
7980         return flags;
7981 }
7982
7983 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
7984 {
7985         struct kvm_segment seg;
7986         int offset;
7987
7988         kvm_get_segment(vcpu, &seg, n);
7989         put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7990
7991         if (n < 3)
7992                 offset = 0x7f84 + n * 12;
7993         else
7994                 offset = 0x7f2c + (n - 3) * 12;
7995
7996         put_smstate(u32, buf, offset + 8, seg.base);
7997         put_smstate(u32, buf, offset + 4, seg.limit);
7998         put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
7999 }
8000
8001 #ifdef CONFIG_X86_64
8002 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8003 {
8004         struct kvm_segment seg;
8005         int offset;
8006         u16 flags;
8007
8008         kvm_get_segment(vcpu, &seg, n);
8009         offset = 0x7e00 + n * 16;
8010
8011         flags = enter_smm_get_segment_flags(&seg) >> 8;
8012         put_smstate(u16, buf, offset, seg.selector);
8013         put_smstate(u16, buf, offset + 2, flags);
8014         put_smstate(u32, buf, offset + 4, seg.limit);
8015         put_smstate(u64, buf, offset + 8, seg.base);
8016 }
8017 #endif
8018
8019 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8020 {
8021         struct desc_ptr dt;
8022         struct kvm_segment seg;
8023         unsigned long val;
8024         int i;
8025
8026         put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8027         put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8028         put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8029         put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8030
8031         for (i = 0; i < 8; i++)
8032                 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8033
8034         kvm_get_dr(vcpu, 6, &val);
8035         put_smstate(u32, buf, 0x7fcc, (u32)val);
8036         kvm_get_dr(vcpu, 7, &val);
8037         put_smstate(u32, buf, 0x7fc8, (u32)val);
8038
8039         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8040         put_smstate(u32, buf, 0x7fc4, seg.selector);
8041         put_smstate(u32, buf, 0x7f64, seg.base);
8042         put_smstate(u32, buf, 0x7f60, seg.limit);
8043         put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8044
8045         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8046         put_smstate(u32, buf, 0x7fc0, seg.selector);
8047         put_smstate(u32, buf, 0x7f80, seg.base);
8048         put_smstate(u32, buf, 0x7f7c, seg.limit);
8049         put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8050
8051         kvm_x86_ops.get_gdt(vcpu, &dt);
8052         put_smstate(u32, buf, 0x7f74, dt.address);
8053         put_smstate(u32, buf, 0x7f70, dt.size);
8054
8055         kvm_x86_ops.get_idt(vcpu, &dt);
8056         put_smstate(u32, buf, 0x7f58, dt.address);
8057         put_smstate(u32, buf, 0x7f54, dt.size);
8058
8059         for (i = 0; i < 6; i++)
8060                 enter_smm_save_seg_32(vcpu, buf, i);
8061
8062         put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8063
8064         /* revision id */
8065         put_smstate(u32, buf, 0x7efc, 0x00020000);
8066         put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8067 }
8068
8069 #ifdef CONFIG_X86_64
8070 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8071 {
8072         struct desc_ptr dt;
8073         struct kvm_segment seg;
8074         unsigned long val;
8075         int i;
8076
8077         for (i = 0; i < 16; i++)
8078                 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8079
8080         put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8081         put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8082
8083         kvm_get_dr(vcpu, 6, &val);
8084         put_smstate(u64, buf, 0x7f68, val);
8085         kvm_get_dr(vcpu, 7, &val);
8086         put_smstate(u64, buf, 0x7f60, val);
8087
8088         put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8089         put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8090         put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8091
8092         put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8093
8094         /* revision id */
8095         put_smstate(u32, buf, 0x7efc, 0x00020064);
8096
8097         put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8098
8099         kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8100         put_smstate(u16, buf, 0x7e90, seg.selector);
8101         put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8102         put_smstate(u32, buf, 0x7e94, seg.limit);
8103         put_smstate(u64, buf, 0x7e98, seg.base);
8104
8105         kvm_x86_ops.get_idt(vcpu, &dt);
8106         put_smstate(u32, buf, 0x7e84, dt.size);
8107         put_smstate(u64, buf, 0x7e88, dt.address);
8108
8109         kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8110         put_smstate(u16, buf, 0x7e70, seg.selector);
8111         put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8112         put_smstate(u32, buf, 0x7e74, seg.limit);
8113         put_smstate(u64, buf, 0x7e78, seg.base);
8114
8115         kvm_x86_ops.get_gdt(vcpu, &dt);
8116         put_smstate(u32, buf, 0x7e64, dt.size);
8117         put_smstate(u64, buf, 0x7e68, dt.address);
8118
8119         for (i = 0; i < 6; i++)
8120                 enter_smm_save_seg_64(vcpu, buf, i);
8121 }
8122 #endif
8123
8124 static void enter_smm(struct kvm_vcpu *vcpu)
8125 {
8126         struct kvm_segment cs, ds;
8127         struct desc_ptr dt;
8128         char buf[512];
8129         u32 cr0;
8130
8131         trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8132         memset(buf, 0, 512);
8133 #ifdef CONFIG_X86_64
8134         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8135                 enter_smm_save_state_64(vcpu, buf);
8136         else
8137 #endif
8138                 enter_smm_save_state_32(vcpu, buf);
8139
8140         /*
8141          * Give pre_enter_smm() a chance to make ISA-specific changes to the
8142          * vCPU state (e.g. leave guest mode) after we've saved the state into
8143          * the SMM state-save area.
8144          */
8145         kvm_x86_ops.pre_enter_smm(vcpu, buf);
8146
8147         vcpu->arch.hflags |= HF_SMM_MASK;
8148         kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8149
8150         if (kvm_x86_ops.get_nmi_mask(vcpu))
8151                 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8152         else
8153                 kvm_x86_ops.set_nmi_mask(vcpu, true);
8154
8155         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8156         kvm_rip_write(vcpu, 0x8000);
8157
8158         cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8159         kvm_x86_ops.set_cr0(vcpu, cr0);
8160         vcpu->arch.cr0 = cr0;
8161
8162         kvm_x86_ops.set_cr4(vcpu, 0);
8163
8164         /* Undocumented: IDT limit is set to zero on entry to SMM.  */
8165         dt.address = dt.size = 0;
8166         kvm_x86_ops.set_idt(vcpu, &dt);
8167
8168         __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8169
8170         cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8171         cs.base = vcpu->arch.smbase;
8172
8173         ds.selector = 0;
8174         ds.base = 0;
8175
8176         cs.limit    = ds.limit = 0xffffffff;
8177         cs.type     = ds.type = 0x3;
8178         cs.dpl      = ds.dpl = 0;
8179         cs.db       = ds.db = 0;
8180         cs.s        = ds.s = 1;
8181         cs.l        = ds.l = 0;
8182         cs.g        = ds.g = 1;
8183         cs.avl      = ds.avl = 0;
8184         cs.present  = ds.present = 1;
8185         cs.unusable = ds.unusable = 0;
8186         cs.padding  = ds.padding = 0;
8187
8188         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8189         kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8190         kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8191         kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8192         kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8193         kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8194
8195 #ifdef CONFIG_X86_64
8196         if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8197                 kvm_x86_ops.set_efer(vcpu, 0);
8198 #endif
8199
8200         kvm_update_cpuid_runtime(vcpu);
8201         kvm_mmu_reset_context(vcpu);
8202 }
8203
8204 static void process_smi(struct kvm_vcpu *vcpu)
8205 {
8206         vcpu->arch.smi_pending = true;
8207         kvm_make_request(KVM_REQ_EVENT, vcpu);
8208 }
8209
8210 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8211                                        unsigned long *vcpu_bitmap)
8212 {
8213         cpumask_var_t cpus;
8214
8215         zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8216
8217         kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8218                                     NULL, vcpu_bitmap, cpus);
8219
8220         free_cpumask_var(cpus);
8221 }
8222
8223 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8224 {
8225         kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8226 }
8227
8228 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8229 {
8230         if (!lapic_in_kernel(vcpu))
8231                 return;
8232
8233         vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8234         kvm_apic_update_apicv(vcpu);
8235         kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8236 }
8237 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8238
8239 /*
8240  * NOTE: Do not hold any lock prior to calling this.
8241  *
8242  * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8243  * locked, because it calls __x86_set_memory_region() which does
8244  * synchronize_srcu(&kvm->srcu).
8245  */
8246 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8247 {
8248         struct kvm_vcpu *except;
8249         unsigned long old, new, expected;
8250
8251         if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8252             !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8253                 return;
8254
8255         old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8256         do {
8257                 expected = new = old;
8258                 if (activate)
8259                         __clear_bit(bit, &new);
8260                 else
8261                         __set_bit(bit, &new);
8262                 if (new == old)
8263                         break;
8264                 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8265         } while (old != expected);
8266
8267         if (!!old == !!new)
8268                 return;
8269
8270         trace_kvm_apicv_update_request(activate, bit);
8271         if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8272                 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8273
8274         /*
8275          * Sending request to update APICV for all other vcpus,
8276          * while update the calling vcpu immediately instead of
8277          * waiting for another #VMEXIT to handle the request.
8278          */
8279         except = kvm_get_running_vcpu();
8280         kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8281                                          except);
8282         if (except)
8283                 kvm_vcpu_update_apicv(except);
8284 }
8285 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8286
8287 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8288 {
8289         if (!kvm_apic_present(vcpu))
8290                 return;
8291
8292         bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8293
8294         if (irqchip_split(vcpu->kvm))
8295                 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8296         else {
8297                 if (vcpu->arch.apicv_active)
8298                         kvm_x86_ops.sync_pir_to_irr(vcpu);
8299                 if (ioapic_in_kernel(vcpu->kvm))
8300                         kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8301         }
8302
8303         if (is_guest_mode(vcpu))
8304                 vcpu->arch.load_eoi_exitmap_pending = true;
8305         else
8306                 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8307 }
8308
8309 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8310 {
8311         u64 eoi_exit_bitmap[4];
8312
8313         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8314                 return;
8315
8316         bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8317                   vcpu_to_synic(vcpu)->vec_bitmap, 256);
8318         kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8319 }
8320
8321 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8322                                             unsigned long start, unsigned long end)
8323 {
8324         unsigned long apic_address;
8325
8326         /*
8327          * The physical address of apic access page is stored in the VMCS.
8328          * Update it when it becomes invalid.
8329          */
8330         apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8331         if (start <= apic_address && apic_address < end)
8332                 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8333 }
8334
8335 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8336 {
8337         if (!lapic_in_kernel(vcpu))
8338                 return;
8339
8340         if (!kvm_x86_ops.set_apic_access_page_addr)
8341                 return;
8342
8343         kvm_x86_ops.set_apic_access_page_addr(vcpu);
8344 }
8345
8346 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8347 {
8348         smp_send_reschedule(vcpu->cpu);
8349 }
8350 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8351
8352 /*
8353  * Returns 1 to let vcpu_run() continue the guest execution loop without
8354  * exiting to the userspace.  Otherwise, the value will be returned to the
8355  * userspace.
8356  */
8357 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8358 {
8359         int r;
8360         bool req_int_win =
8361                 dm_request_for_irq_injection(vcpu) &&
8362                 kvm_cpu_accept_dm_intr(vcpu);
8363         fastpath_t exit_fastpath;
8364
8365         bool req_immediate_exit = false;
8366
8367         if (kvm_request_pending(vcpu)) {
8368                 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8369                         if (unlikely(!kvm_x86_ops.nested_ops->get_vmcs12_pages(vcpu))) {
8370                                 r = 0;
8371                                 goto out;
8372                         }
8373                 }
8374                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8375                         kvm_mmu_unload(vcpu);
8376                 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8377                         __kvm_migrate_timers(vcpu);
8378                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8379                         kvm_gen_update_masterclock(vcpu->kvm);
8380                 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8381                         kvm_gen_kvmclock_update(vcpu);
8382                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8383                         r = kvm_guest_time_update(vcpu);
8384                         if (unlikely(r))
8385                                 goto out;
8386                 }
8387                 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8388                         kvm_mmu_sync_roots(vcpu);
8389                 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8390                         kvm_mmu_load_pgd(vcpu);
8391                 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8392                         kvm_vcpu_flush_tlb_all(vcpu);
8393
8394                         /* Flushing all ASIDs flushes the current ASID... */
8395                         kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8396                 }
8397                 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8398                         kvm_vcpu_flush_tlb_current(vcpu);
8399                 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8400                         kvm_vcpu_flush_tlb_guest(vcpu);
8401
8402                 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8403                         vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8404                         r = 0;
8405                         goto out;
8406                 }
8407                 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8408                         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8409                         vcpu->mmio_needed = 0;
8410                         r = 0;
8411                         goto out;
8412                 }
8413                 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8414                         /* Page is swapped out. Do synthetic halt */
8415                         vcpu->arch.apf.halted = true;
8416                         r = 1;
8417                         goto out;
8418                 }
8419                 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8420                         record_steal_time(vcpu);
8421                 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8422                         process_smi(vcpu);
8423                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8424                         process_nmi(vcpu);
8425                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8426                         kvm_pmu_handle_event(vcpu);
8427                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8428                         kvm_pmu_deliver_pmi(vcpu);
8429                 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8430                         BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8431                         if (test_bit(vcpu->arch.pending_ioapic_eoi,
8432                                      vcpu->arch.ioapic_handled_vectors)) {
8433                                 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8434                                 vcpu->run->eoi.vector =
8435                                                 vcpu->arch.pending_ioapic_eoi;
8436                                 r = 0;
8437                                 goto out;
8438                         }
8439                 }
8440                 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8441                         vcpu_scan_ioapic(vcpu);
8442                 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8443                         vcpu_load_eoi_exitmap(vcpu);
8444                 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8445                         kvm_vcpu_reload_apic_access_page(vcpu);
8446                 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8447                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8448                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8449                         r = 0;
8450                         goto out;
8451                 }
8452                 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8453                         vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8454                         vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8455                         r = 0;
8456                         goto out;
8457                 }
8458                 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8459                         vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8460                         vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8461                         r = 0;
8462                         goto out;
8463                 }
8464
8465                 /*
8466                  * KVM_REQ_HV_STIMER has to be processed after
8467                  * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8468                  * depend on the guest clock being up-to-date
8469                  */
8470                 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8471                         kvm_hv_process_stimers(vcpu);
8472                 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8473                         kvm_vcpu_update_apicv(vcpu);
8474                 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8475                         kvm_check_async_pf_completion(vcpu);
8476         }
8477
8478         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8479                 ++vcpu->stat.req_event;
8480                 kvm_apic_accept_events(vcpu);
8481                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8482                         r = 1;
8483                         goto out;
8484                 }
8485
8486                 inject_pending_event(vcpu, &req_immediate_exit);
8487                 if (req_int_win)
8488                         kvm_x86_ops.enable_irq_window(vcpu);
8489
8490                 if (kvm_lapic_enabled(vcpu)) {
8491                         update_cr8_intercept(vcpu);
8492                         kvm_lapic_sync_to_vapic(vcpu);
8493                 }
8494         }
8495
8496         r = kvm_mmu_reload(vcpu);
8497         if (unlikely(r)) {
8498                 goto cancel_injection;
8499         }
8500
8501         preempt_disable();
8502
8503         kvm_x86_ops.prepare_guest_switch(vcpu);
8504
8505         /*
8506          * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
8507          * IPI are then delayed after guest entry, which ensures that they
8508          * result in virtual interrupt delivery.
8509          */
8510         local_irq_disable();
8511         vcpu->mode = IN_GUEST_MODE;
8512
8513         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8514
8515         /*
8516          * 1) We should set ->mode before checking ->requests.  Please see
8517          * the comment in kvm_vcpu_exiting_guest_mode().
8518          *
8519          * 2) For APICv, we should set ->mode before checking PID.ON. This
8520          * pairs with the memory barrier implicit in pi_test_and_set_on
8521          * (see vmx_deliver_posted_interrupt).
8522          *
8523          * 3) This also orders the write to mode from any reads to the page
8524          * tables done while the VCPU is running.  Please see the comment
8525          * in kvm_flush_remote_tlbs.
8526          */
8527         smp_mb__after_srcu_read_unlock();
8528
8529         /*
8530          * This handles the case where a posted interrupt was
8531          * notified with kvm_vcpu_kick.
8532          */
8533         if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8534                 kvm_x86_ops.sync_pir_to_irr(vcpu);
8535
8536         if (kvm_vcpu_exit_request(vcpu)) {
8537                 vcpu->mode = OUTSIDE_GUEST_MODE;
8538                 smp_wmb();
8539                 local_irq_enable();
8540                 preempt_enable();
8541                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8542                 r = 1;
8543                 goto cancel_injection;
8544         }
8545
8546         if (req_immediate_exit) {
8547                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8548                 kvm_x86_ops.request_immediate_exit(vcpu);
8549         }
8550
8551         trace_kvm_entry(vcpu->vcpu_id);
8552
8553         fpregs_assert_state_consistent();
8554         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8555                 switch_fpu_return();
8556
8557         if (unlikely(vcpu->arch.switch_db_regs)) {
8558                 set_debugreg(0, 7);
8559                 set_debugreg(vcpu->arch.eff_db[0], 0);
8560                 set_debugreg(vcpu->arch.eff_db[1], 1);
8561                 set_debugreg(vcpu->arch.eff_db[2], 2);
8562                 set_debugreg(vcpu->arch.eff_db[3], 3);
8563                 set_debugreg(vcpu->arch.dr6, 6);
8564                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8565         }
8566
8567         exit_fastpath = kvm_x86_ops.run(vcpu);
8568
8569         /*
8570          * Do this here before restoring debug registers on the host.  And
8571          * since we do this before handling the vmexit, a DR access vmexit
8572          * can (a) read the correct value of the debug registers, (b) set
8573          * KVM_DEBUGREG_WONT_EXIT again.
8574          */
8575         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8576                 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8577                 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8578                 kvm_update_dr0123(vcpu);
8579                 kvm_update_dr7(vcpu);
8580                 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8581         }
8582
8583         /*
8584          * If the guest has used debug registers, at least dr7
8585          * will be disabled while returning to the host.
8586          * If we don't have active breakpoints in the host, we don't
8587          * care about the messed up debug address registers. But if
8588          * we have some of them active, restore the old state.
8589          */
8590         if (hw_breakpoint_active())
8591                 hw_breakpoint_restore();
8592
8593         vcpu->arch.last_vmentry_cpu = vcpu->cpu;
8594         vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8595
8596         vcpu->mode = OUTSIDE_GUEST_MODE;
8597         smp_wmb();
8598
8599         kvm_x86_ops.handle_exit_irqoff(vcpu);
8600
8601         /*
8602          * Consume any pending interrupts, including the possible source of
8603          * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8604          * An instruction is required after local_irq_enable() to fully unblock
8605          * interrupts on processors that implement an interrupt shadow, the
8606          * stat.exits increment will do nicely.
8607          */
8608         kvm_before_interrupt(vcpu);
8609         local_irq_enable();
8610         ++vcpu->stat.exits;
8611         local_irq_disable();
8612         kvm_after_interrupt(vcpu);
8613
8614         if (lapic_in_kernel(vcpu)) {
8615                 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8616                 if (delta != S64_MIN) {
8617                         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8618                         vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8619                 }
8620         }
8621
8622         local_irq_enable();
8623         preempt_enable();
8624
8625         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8626
8627         /*
8628          * Profile KVM exit RIPs:
8629          */
8630         if (unlikely(prof_on == KVM_PROFILING)) {
8631                 unsigned long rip = kvm_rip_read(vcpu);
8632                 profile_hit(KVM_PROFILING, (void *)rip);
8633         }
8634
8635         if (unlikely(vcpu->arch.tsc_always_catchup))
8636                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8637
8638         if (vcpu->arch.apic_attention)
8639                 kvm_lapic_sync_from_vapic(vcpu);
8640
8641         r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
8642         return r;
8643
8644 cancel_injection:
8645         if (req_immediate_exit)
8646                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8647         kvm_x86_ops.cancel_injection(vcpu);
8648         if (unlikely(vcpu->arch.apic_attention))
8649                 kvm_lapic_sync_from_vapic(vcpu);
8650 out:
8651         return r;
8652 }
8653
8654 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8655 {
8656         if (!kvm_arch_vcpu_runnable(vcpu) &&
8657             (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
8658                 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8659                 kvm_vcpu_block(vcpu);
8660                 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8661
8662                 if (kvm_x86_ops.post_block)
8663                         kvm_x86_ops.post_block(vcpu);
8664
8665                 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8666                         return 1;
8667         }
8668
8669         kvm_apic_accept_events(vcpu);
8670         switch(vcpu->arch.mp_state) {
8671         case KVM_MP_STATE_HALTED:
8672                 vcpu->arch.pv.pv_unhalted = false;
8673                 vcpu->arch.mp_state =
8674                         KVM_MP_STATE_RUNNABLE;
8675                 fallthrough;
8676         case KVM_MP_STATE_RUNNABLE:
8677                 vcpu->arch.apf.halted = false;
8678                 break;
8679         case KVM_MP_STATE_INIT_RECEIVED:
8680                 break;
8681         default:
8682                 return -EINTR;
8683         }
8684         return 1;
8685 }
8686
8687 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8688 {
8689         if (is_guest_mode(vcpu))
8690                 kvm_x86_ops.nested_ops->check_events(vcpu);
8691
8692         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8693                 !vcpu->arch.apf.halted);
8694 }
8695
8696 static int vcpu_run(struct kvm_vcpu *vcpu)
8697 {
8698         int r;
8699         struct kvm *kvm = vcpu->kvm;
8700
8701         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8702         vcpu->arch.l1tf_flush_l1d = true;
8703
8704         for (;;) {
8705                 if (kvm_vcpu_running(vcpu)) {
8706                         r = vcpu_enter_guest(vcpu);
8707                 } else {
8708                         r = vcpu_block(kvm, vcpu);
8709                 }
8710
8711                 if (r <= 0)
8712                         break;
8713
8714                 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
8715                 if (kvm_cpu_has_pending_timer(vcpu))
8716                         kvm_inject_pending_timer_irqs(vcpu);
8717
8718                 if (dm_request_for_irq_injection(vcpu) &&
8719                         kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
8720                         r = 0;
8721                         vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
8722                         ++vcpu->stat.request_irq_exits;
8723                         break;
8724                 }
8725
8726                 if (__xfer_to_guest_mode_work_pending()) {
8727                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8728                         r = xfer_to_guest_mode_handle_work(vcpu);
8729                         if (r)
8730                                 return r;
8731                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
8732                 }
8733         }
8734
8735         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8736
8737         return r;
8738 }
8739
8740 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8741 {
8742         int r;
8743
8744         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8745         r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
8746         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8747         return r;
8748 }
8749
8750 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8751 {
8752         BUG_ON(!vcpu->arch.pio.count);
8753
8754         return complete_emulated_io(vcpu);
8755 }
8756
8757 /*
8758  * Implements the following, as a state machine:
8759  *
8760  * read:
8761  *   for each fragment
8762  *     for each mmio piece in the fragment
8763  *       write gpa, len
8764  *       exit
8765  *       copy data
8766  *   execute insn
8767  *
8768  * write:
8769  *   for each fragment
8770  *     for each mmio piece in the fragment
8771  *       write gpa, len
8772  *       copy data
8773  *       exit
8774  */
8775 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
8776 {
8777         struct kvm_run *run = vcpu->run;
8778         struct kvm_mmio_fragment *frag;
8779         unsigned len;
8780
8781         BUG_ON(!vcpu->mmio_needed);
8782
8783         /* Complete previous fragment */
8784         frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8785         len = min(8u, frag->len);
8786         if (!vcpu->mmio_is_write)
8787                 memcpy(frag->data, run->mmio.data, len);
8788
8789         if (frag->len <= 8) {
8790                 /* Switch to the next fragment. */
8791                 frag++;
8792                 vcpu->mmio_cur_fragment++;
8793         } else {
8794                 /* Go forward to the next mmio piece. */
8795                 frag->data += len;
8796                 frag->gpa += len;
8797                 frag->len -= len;
8798         }
8799
8800         if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
8801                 vcpu->mmio_needed = 0;
8802
8803                 /* FIXME: return into emulator if single-stepping.  */
8804                 if (vcpu->mmio_is_write)
8805                         return 1;
8806                 vcpu->mmio_read_completed = 1;
8807                 return complete_emulated_io(vcpu);
8808         }
8809
8810         run->exit_reason = KVM_EXIT_MMIO;
8811         run->mmio.phys_addr = frag->gpa;
8812         if (vcpu->mmio_is_write)
8813                 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8814         run->mmio.len = min(8u, frag->len);
8815         run->mmio.is_write = vcpu->mmio_is_write;
8816         vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8817         return 0;
8818 }
8819
8820 static void kvm_save_current_fpu(struct fpu *fpu)
8821 {
8822         /*
8823          * If the target FPU state is not resident in the CPU registers, just
8824          * memcpy() from current, else save CPU state directly to the target.
8825          */
8826         if (test_thread_flag(TIF_NEED_FPU_LOAD))
8827                 memcpy(&fpu->state, &current->thread.fpu.state,
8828                        fpu_kernel_xstate_size);
8829         else
8830                 copy_fpregs_to_fpstate(fpu);
8831 }
8832
8833 /* Swap (qemu) user FPU context for the guest FPU context. */
8834 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8835 {
8836         fpregs_lock();
8837
8838         kvm_save_current_fpu(vcpu->arch.user_fpu);
8839
8840         /* PKRU is separately restored in kvm_x86_ops.run.  */
8841         __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
8842                                 ~XFEATURE_MASK_PKRU);
8843
8844         fpregs_mark_activate();
8845         fpregs_unlock();
8846
8847         trace_kvm_fpu(1);
8848 }
8849
8850 /* When vcpu_run ends, restore user space FPU context. */
8851 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8852 {
8853         fpregs_lock();
8854
8855         kvm_save_current_fpu(vcpu->arch.guest_fpu);
8856
8857         copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
8858
8859         fpregs_mark_activate();
8860         fpregs_unlock();
8861
8862         ++vcpu->stat.fpu_reload;
8863         trace_kvm_fpu(0);
8864 }
8865
8866 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
8867 {
8868         struct kvm_run *kvm_run = vcpu->run;
8869         int r;
8870
8871         vcpu_load(vcpu);
8872         kvm_sigset_activate(vcpu);
8873         kvm_load_guest_fpu(vcpu);
8874
8875         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
8876                 if (kvm_run->immediate_exit) {
8877                         r = -EINTR;
8878                         goto out;
8879                 }
8880                 kvm_vcpu_block(vcpu);
8881                 kvm_apic_accept_events(vcpu);
8882                 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
8883                 r = -EAGAIN;
8884                 if (signal_pending(current)) {
8885                         r = -EINTR;
8886                         kvm_run->exit_reason = KVM_EXIT_INTR;
8887                         ++vcpu->stat.signal_exits;
8888                 }
8889                 goto out;
8890         }
8891
8892         if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8893                 r = -EINVAL;
8894                 goto out;
8895         }
8896
8897         if (kvm_run->kvm_dirty_regs) {
8898                 r = sync_regs(vcpu);
8899                 if (r != 0)
8900                         goto out;
8901         }
8902
8903         /* re-sync apic's tpr */
8904         if (!lapic_in_kernel(vcpu)) {
8905                 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8906                         r = -EINVAL;
8907                         goto out;
8908                 }
8909         }
8910
8911         if (unlikely(vcpu->arch.complete_userspace_io)) {
8912                 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8913                 vcpu->arch.complete_userspace_io = NULL;
8914                 r = cui(vcpu);
8915                 if (r <= 0)
8916                         goto out;
8917         } else
8918                 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
8919
8920         if (kvm_run->immediate_exit)
8921                 r = -EINTR;
8922         else
8923                 r = vcpu_run(vcpu);
8924
8925 out:
8926         kvm_put_guest_fpu(vcpu);
8927         if (kvm_run->kvm_valid_regs)
8928                 store_regs(vcpu);
8929         post_kvm_run_save(vcpu);
8930         kvm_sigset_deactivate(vcpu);
8931
8932         vcpu_put(vcpu);
8933         return r;
8934 }
8935
8936 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8937 {
8938         if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8939                 /*
8940                  * We are here if userspace calls get_regs() in the middle of
8941                  * instruction emulation. Registers state needs to be copied
8942                  * back from emulation context to vcpu. Userspace shouldn't do
8943                  * that usually, but some bad designed PV devices (vmware
8944                  * backdoor interface) need this to work
8945                  */
8946                 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
8947                 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8948         }
8949         regs->rax = kvm_rax_read(vcpu);
8950         regs->rbx = kvm_rbx_read(vcpu);
8951         regs->rcx = kvm_rcx_read(vcpu);
8952         regs->rdx = kvm_rdx_read(vcpu);
8953         regs->rsi = kvm_rsi_read(vcpu);
8954         regs->rdi = kvm_rdi_read(vcpu);
8955         regs->rsp = kvm_rsp_read(vcpu);
8956         regs->rbp = kvm_rbp_read(vcpu);
8957 #ifdef CONFIG_X86_64
8958         regs->r8 = kvm_r8_read(vcpu);
8959         regs->r9 = kvm_r9_read(vcpu);
8960         regs->r10 = kvm_r10_read(vcpu);
8961         regs->r11 = kvm_r11_read(vcpu);
8962         regs->r12 = kvm_r12_read(vcpu);
8963         regs->r13 = kvm_r13_read(vcpu);
8964         regs->r14 = kvm_r14_read(vcpu);
8965         regs->r15 = kvm_r15_read(vcpu);
8966 #endif
8967
8968         regs->rip = kvm_rip_read(vcpu);
8969         regs->rflags = kvm_get_rflags(vcpu);
8970 }
8971
8972 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8973 {
8974         vcpu_load(vcpu);
8975         __get_regs(vcpu, regs);
8976         vcpu_put(vcpu);
8977         return 0;
8978 }
8979
8980 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8981 {
8982         vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8983         vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8984
8985         kvm_rax_write(vcpu, regs->rax);
8986         kvm_rbx_write(vcpu, regs->rbx);
8987         kvm_rcx_write(vcpu, regs->rcx);
8988         kvm_rdx_write(vcpu, regs->rdx);
8989         kvm_rsi_write(vcpu, regs->rsi);
8990         kvm_rdi_write(vcpu, regs->rdi);
8991         kvm_rsp_write(vcpu, regs->rsp);
8992         kvm_rbp_write(vcpu, regs->rbp);
8993 #ifdef CONFIG_X86_64
8994         kvm_r8_write(vcpu, regs->r8);
8995         kvm_r9_write(vcpu, regs->r9);
8996         kvm_r10_write(vcpu, regs->r10);
8997         kvm_r11_write(vcpu, regs->r11);
8998         kvm_r12_write(vcpu, regs->r12);
8999         kvm_r13_write(vcpu, regs->r13);
9000         kvm_r14_write(vcpu, regs->r14);
9001         kvm_r15_write(vcpu, regs->r15);
9002 #endif
9003
9004         kvm_rip_write(vcpu, regs->rip);
9005         kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9006
9007         vcpu->arch.exception.pending = false;
9008
9009         kvm_make_request(KVM_REQ_EVENT, vcpu);
9010 }
9011
9012 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9013 {
9014         vcpu_load(vcpu);
9015         __set_regs(vcpu, regs);
9016         vcpu_put(vcpu);
9017         return 0;
9018 }
9019
9020 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9021 {
9022         struct kvm_segment cs;
9023
9024         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9025         *db = cs.db;
9026         *l = cs.l;
9027 }
9028 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9029
9030 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9031 {
9032         struct desc_ptr dt;
9033
9034         kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9035         kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9036         kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9037         kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9038         kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9039         kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9040
9041         kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9042         kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9043
9044         kvm_x86_ops.get_idt(vcpu, &dt);
9045         sregs->idt.limit = dt.size;
9046         sregs->idt.base = dt.address;
9047         kvm_x86_ops.get_gdt(vcpu, &dt);
9048         sregs->gdt.limit = dt.size;
9049         sregs->gdt.base = dt.address;
9050
9051         sregs->cr0 = kvm_read_cr0(vcpu);
9052         sregs->cr2 = vcpu->arch.cr2;
9053         sregs->cr3 = kvm_read_cr3(vcpu);
9054         sregs->cr4 = kvm_read_cr4(vcpu);
9055         sregs->cr8 = kvm_get_cr8(vcpu);
9056         sregs->efer = vcpu->arch.efer;
9057         sregs->apic_base = kvm_get_apic_base(vcpu);
9058
9059         memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9060
9061         if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9062                 set_bit(vcpu->arch.interrupt.nr,
9063                         (unsigned long *)sregs->interrupt_bitmap);
9064 }
9065
9066 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9067                                   struct kvm_sregs *sregs)
9068 {
9069         vcpu_load(vcpu);
9070         __get_sregs(vcpu, sregs);
9071         vcpu_put(vcpu);
9072         return 0;
9073 }
9074
9075 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9076                                     struct kvm_mp_state *mp_state)
9077 {
9078         vcpu_load(vcpu);
9079         if (kvm_mpx_supported())
9080                 kvm_load_guest_fpu(vcpu);
9081
9082         kvm_apic_accept_events(vcpu);
9083         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9084                                         vcpu->arch.pv.pv_unhalted)
9085                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9086         else
9087                 mp_state->mp_state = vcpu->arch.mp_state;
9088
9089         if (kvm_mpx_supported())
9090                 kvm_put_guest_fpu(vcpu);
9091         vcpu_put(vcpu);
9092         return 0;
9093 }
9094
9095 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9096                                     struct kvm_mp_state *mp_state)
9097 {
9098         int ret = -EINVAL;
9099
9100         vcpu_load(vcpu);
9101
9102         if (!lapic_in_kernel(vcpu) &&
9103             mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9104                 goto out;
9105
9106         /*
9107          * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9108          * INIT state; latched init should be reported using
9109          * KVM_SET_VCPU_EVENTS, so reject it here.
9110          */
9111         if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9112             (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9113              mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9114                 goto out;
9115
9116         if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9117                 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9118                 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9119         } else
9120                 vcpu->arch.mp_state = mp_state->mp_state;
9121         kvm_make_request(KVM_REQ_EVENT, vcpu);
9122
9123         ret = 0;
9124 out:
9125         vcpu_put(vcpu);
9126         return ret;
9127 }
9128
9129 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9130                     int reason, bool has_error_code, u32 error_code)
9131 {
9132         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9133         int ret;
9134
9135         init_emulate_ctxt(vcpu);
9136
9137         ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9138                                    has_error_code, error_code);
9139         if (ret) {
9140                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9141                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9142                 vcpu->run->internal.ndata = 0;
9143                 return 0;
9144         }
9145
9146         kvm_rip_write(vcpu, ctxt->eip);
9147         kvm_set_rflags(vcpu, ctxt->eflags);
9148         return 1;
9149 }
9150 EXPORT_SYMBOL_GPL(kvm_task_switch);
9151
9152 static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9153 {
9154         if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9155                 /*
9156                  * When EFER.LME and CR0.PG are set, the processor is in
9157                  * 64-bit mode (though maybe in a 32-bit code segment).
9158                  * CR4.PAE and EFER.LMA must be set.
9159                  */
9160                 if (!(sregs->cr4 & X86_CR4_PAE)
9161                     || !(sregs->efer & EFER_LMA))
9162                         return -EINVAL;
9163         } else {
9164                 /*
9165                  * Not in 64-bit mode: EFER.LMA is clear and the code
9166                  * segment cannot be 64-bit.
9167                  */
9168                 if (sregs->efer & EFER_LMA || sregs->cs.l)
9169                         return -EINVAL;
9170         }
9171
9172         return kvm_valid_cr4(vcpu, sregs->cr4);
9173 }
9174
9175 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9176 {
9177         struct msr_data apic_base_msr;
9178         int mmu_reset_needed = 0;
9179         int cpuid_update_needed = 0;
9180         int pending_vec, max_bits, idx;
9181         struct desc_ptr dt;
9182         int ret = -EINVAL;
9183
9184         if (kvm_valid_sregs(vcpu, sregs))
9185                 goto out;
9186
9187         apic_base_msr.data = sregs->apic_base;
9188         apic_base_msr.host_initiated = true;
9189         if (kvm_set_apic_base(vcpu, &apic_base_msr))
9190                 goto out;
9191
9192         dt.size = sregs->idt.limit;
9193         dt.address = sregs->idt.base;
9194         kvm_x86_ops.set_idt(vcpu, &dt);
9195         dt.size = sregs->gdt.limit;
9196         dt.address = sregs->gdt.base;
9197         kvm_x86_ops.set_gdt(vcpu, &dt);
9198
9199         vcpu->arch.cr2 = sregs->cr2;
9200         mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9201         vcpu->arch.cr3 = sregs->cr3;
9202         kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9203
9204         kvm_set_cr8(vcpu, sregs->cr8);
9205
9206         mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9207         kvm_x86_ops.set_efer(vcpu, sregs->efer);
9208
9209         mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9210         kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9211         vcpu->arch.cr0 = sregs->cr0;
9212
9213         mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9214         cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
9215                                 (X86_CR4_OSXSAVE | X86_CR4_PKE));
9216         kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9217         if (cpuid_update_needed)
9218                 kvm_update_cpuid_runtime(vcpu);
9219
9220         idx = srcu_read_lock(&vcpu->kvm->srcu);
9221         if (is_pae_paging(vcpu)) {
9222                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9223                 mmu_reset_needed = 1;
9224         }
9225         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9226
9227         if (mmu_reset_needed)
9228                 kvm_mmu_reset_context(vcpu);
9229
9230         max_bits = KVM_NR_INTERRUPTS;
9231         pending_vec = find_first_bit(
9232                 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9233         if (pending_vec < max_bits) {
9234                 kvm_queue_interrupt(vcpu, pending_vec, false);
9235                 pr_debug("Set back pending irq %d\n", pending_vec);
9236         }
9237
9238         kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9239         kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9240         kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9241         kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9242         kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9243         kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9244
9245         kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9246         kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9247
9248         update_cr8_intercept(vcpu);
9249
9250         /* Older userspace won't unhalt the vcpu on reset. */
9251         if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9252             sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9253             !is_protmode(vcpu))
9254                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9255
9256         kvm_make_request(KVM_REQ_EVENT, vcpu);
9257
9258         ret = 0;
9259 out:
9260         return ret;
9261 }
9262
9263 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9264                                   struct kvm_sregs *sregs)
9265 {
9266         int ret;
9267
9268         vcpu_load(vcpu);
9269         ret = __set_sregs(vcpu, sregs);
9270         vcpu_put(vcpu);
9271         return ret;
9272 }
9273
9274 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9275                                         struct kvm_guest_debug *dbg)
9276 {
9277         unsigned long rflags;
9278         int i, r;
9279
9280         vcpu_load(vcpu);
9281
9282         if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9283                 r = -EBUSY;
9284                 if (vcpu->arch.exception.pending)
9285                         goto out;
9286                 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9287                         kvm_queue_exception(vcpu, DB_VECTOR);
9288                 else
9289                         kvm_queue_exception(vcpu, BP_VECTOR);
9290         }
9291
9292         /*
9293          * Read rflags as long as potentially injected trace flags are still
9294          * filtered out.
9295          */
9296         rflags = kvm_get_rflags(vcpu);
9297
9298         vcpu->guest_debug = dbg->control;
9299         if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9300                 vcpu->guest_debug = 0;
9301
9302         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9303                 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9304                         vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9305                 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9306         } else {
9307                 for (i = 0; i < KVM_NR_DB_REGS; i++)
9308                         vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9309         }
9310         kvm_update_dr7(vcpu);
9311
9312         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9313                 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9314                         get_segment_base(vcpu, VCPU_SREG_CS);
9315
9316         /*
9317          * Trigger an rflags update that will inject or remove the trace
9318          * flags.
9319          */
9320         kvm_set_rflags(vcpu, rflags);
9321
9322         kvm_x86_ops.update_exception_bitmap(vcpu);
9323
9324         r = 0;
9325
9326 out:
9327         vcpu_put(vcpu);
9328         return r;
9329 }
9330
9331 /*
9332  * Translate a guest virtual address to a guest physical address.
9333  */
9334 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9335                                     struct kvm_translation *tr)
9336 {
9337         unsigned long vaddr = tr->linear_address;
9338         gpa_t gpa;
9339         int idx;
9340
9341         vcpu_load(vcpu);
9342
9343         idx = srcu_read_lock(&vcpu->kvm->srcu);
9344         gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9345         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9346         tr->physical_address = gpa;
9347         tr->valid = gpa != UNMAPPED_GVA;
9348         tr->writeable = 1;
9349         tr->usermode = 0;
9350
9351         vcpu_put(vcpu);
9352         return 0;
9353 }
9354
9355 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9356 {
9357         struct fxregs_state *fxsave;
9358
9359         vcpu_load(vcpu);
9360
9361         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9362         memcpy(fpu->fpr, fxsave->st_space, 128);
9363         fpu->fcw = fxsave->cwd;
9364         fpu->fsw = fxsave->swd;
9365         fpu->ftwx = fxsave->twd;
9366         fpu->last_opcode = fxsave->fop;
9367         fpu->last_ip = fxsave->rip;
9368         fpu->last_dp = fxsave->rdp;
9369         memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9370
9371         vcpu_put(vcpu);
9372         return 0;
9373 }
9374
9375 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9376 {
9377         struct fxregs_state *fxsave;
9378
9379         vcpu_load(vcpu);
9380
9381         fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9382
9383         memcpy(fxsave->st_space, fpu->fpr, 128);
9384         fxsave->cwd = fpu->fcw;
9385         fxsave->swd = fpu->fsw;
9386         fxsave->twd = fpu->ftwx;
9387         fxsave->fop = fpu->last_opcode;
9388         fxsave->rip = fpu->last_ip;
9389         fxsave->rdp = fpu->last_dp;
9390         memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9391
9392         vcpu_put(vcpu);
9393         return 0;
9394 }
9395
9396 static void store_regs(struct kvm_vcpu *vcpu)
9397 {
9398         BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9399
9400         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9401                 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9402
9403         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9404                 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9405
9406         if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9407                 kvm_vcpu_ioctl_x86_get_vcpu_events(
9408                                 vcpu, &vcpu->run->s.regs.events);
9409 }
9410
9411 static int sync_regs(struct kvm_vcpu *vcpu)
9412 {
9413         if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9414                 return -EINVAL;
9415
9416         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9417                 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9418                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9419         }
9420         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9421                 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9422                         return -EINVAL;
9423                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9424         }
9425         if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9426                 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9427                                 vcpu, &vcpu->run->s.regs.events))
9428                         return -EINVAL;
9429                 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9430         }
9431
9432         return 0;
9433 }
9434
9435 static void fx_init(struct kvm_vcpu *vcpu)
9436 {
9437         fpstate_init(&vcpu->arch.guest_fpu->state);
9438         if (boot_cpu_has(X86_FEATURE_XSAVES))
9439                 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9440                         host_xcr0 | XSTATE_COMPACTION_ENABLED;
9441
9442         /*
9443          * Ensure guest xcr0 is valid for loading
9444          */
9445         vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9446
9447         vcpu->arch.cr0 |= X86_CR0_ET;
9448 }
9449
9450 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9451 {
9452         if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9453                 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9454                              "guest TSC will not be reliable\n");
9455
9456         return 0;
9457 }
9458
9459 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9460 {
9461         struct page *page;
9462         int r;
9463
9464         if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9465                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9466         else
9467                 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9468
9469         kvm_set_tsc_khz(vcpu, max_tsc_khz);
9470
9471         r = kvm_mmu_create(vcpu);
9472         if (r < 0)
9473                 return r;
9474
9475         if (irqchip_in_kernel(vcpu->kvm)) {
9476                 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9477                 if (r < 0)
9478                         goto fail_mmu_destroy;
9479                 if (kvm_apicv_activated(vcpu->kvm))
9480                         vcpu->arch.apicv_active = true;
9481         } else
9482                 static_key_slow_inc(&kvm_no_apic_vcpu);
9483
9484         r = -ENOMEM;
9485
9486         page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9487         if (!page)
9488                 goto fail_free_lapic;
9489         vcpu->arch.pio_data = page_address(page);
9490
9491         vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9492                                        GFP_KERNEL_ACCOUNT);
9493         if (!vcpu->arch.mce_banks)
9494                 goto fail_free_pio_data;
9495         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9496
9497         if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9498                                 GFP_KERNEL_ACCOUNT))
9499                 goto fail_free_mce_banks;
9500
9501         if (!alloc_emulate_ctxt(vcpu))
9502                 goto free_wbinvd_dirty_mask;
9503
9504         vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9505                                                 GFP_KERNEL_ACCOUNT);
9506         if (!vcpu->arch.user_fpu) {
9507                 pr_err("kvm: failed to allocate userspace's fpu\n");
9508                 goto free_emulate_ctxt;
9509         }
9510
9511         vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9512                                                  GFP_KERNEL_ACCOUNT);
9513         if (!vcpu->arch.guest_fpu) {
9514                 pr_err("kvm: failed to allocate vcpu's fpu\n");
9515                 goto free_user_fpu;
9516         }
9517         fx_init(vcpu);
9518
9519         vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9520
9521         vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9522
9523         kvm_async_pf_hash_reset(vcpu);
9524         kvm_pmu_init(vcpu);
9525
9526         vcpu->arch.pending_external_vector = -1;
9527         vcpu->arch.preempted_in_kernel = false;
9528
9529         kvm_hv_vcpu_init(vcpu);
9530
9531         r = kvm_x86_ops.vcpu_create(vcpu);
9532         if (r)
9533                 goto free_guest_fpu;
9534
9535         vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9536         vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9537         kvm_vcpu_mtrr_init(vcpu);
9538         vcpu_load(vcpu);
9539         kvm_vcpu_reset(vcpu, false);
9540         kvm_init_mmu(vcpu, false);
9541         vcpu_put(vcpu);
9542         return 0;
9543
9544 free_guest_fpu:
9545         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9546 free_user_fpu:
9547         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9548 free_emulate_ctxt:
9549         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9550 free_wbinvd_dirty_mask:
9551         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9552 fail_free_mce_banks:
9553         kfree(vcpu->arch.mce_banks);
9554 fail_free_pio_data:
9555         free_page((unsigned long)vcpu->arch.pio_data);
9556 fail_free_lapic:
9557         kvm_free_lapic(vcpu);
9558 fail_mmu_destroy:
9559         kvm_mmu_destroy(vcpu);
9560         return r;
9561 }
9562
9563 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9564 {
9565         struct msr_data msr;
9566         struct kvm *kvm = vcpu->kvm;
9567
9568         kvm_hv_vcpu_postcreate(vcpu);
9569
9570         if (mutex_lock_killable(&vcpu->mutex))
9571                 return;
9572         vcpu_load(vcpu);
9573         msr.data = 0x0;
9574         msr.index = MSR_IA32_TSC;
9575         msr.host_initiated = true;
9576         kvm_write_tsc(vcpu, &msr);
9577         vcpu_put(vcpu);
9578
9579         /* poll control enabled by default */
9580         vcpu->arch.msr_kvm_poll_control = 1;
9581
9582         mutex_unlock(&vcpu->mutex);
9583
9584         if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9585                 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9586                                                 KVMCLOCK_SYNC_PERIOD);
9587 }
9588
9589 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9590 {
9591         struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9592         int idx;
9593
9594         kvm_release_pfn(cache->pfn, cache->dirty, cache);
9595
9596         kvmclock_reset(vcpu);
9597
9598         kvm_x86_ops.vcpu_free(vcpu);
9599
9600         kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9601         free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9602         kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9603         kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9604
9605         kvm_hv_vcpu_uninit(vcpu);
9606         kvm_pmu_destroy(vcpu);
9607         kfree(vcpu->arch.mce_banks);
9608         kvm_free_lapic(vcpu);
9609         idx = srcu_read_lock(&vcpu->kvm->srcu);
9610         kvm_mmu_destroy(vcpu);
9611         srcu_read_unlock(&vcpu->kvm->srcu, idx);
9612         free_page((unsigned long)vcpu->arch.pio_data);
9613         if (!lapic_in_kernel(vcpu))
9614                 static_key_slow_dec(&kvm_no_apic_vcpu);
9615 }
9616
9617 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
9618 {
9619         kvm_lapic_reset(vcpu, init_event);
9620
9621         vcpu->arch.hflags = 0;
9622
9623         vcpu->arch.smi_pending = 0;
9624         vcpu->arch.smi_count = 0;
9625         atomic_set(&vcpu->arch.nmi_queued, 0);
9626         vcpu->arch.nmi_pending = 0;
9627         vcpu->arch.nmi_injected = false;
9628         kvm_clear_interrupt_queue(vcpu);
9629         kvm_clear_exception_queue(vcpu);
9630
9631         memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
9632         kvm_update_dr0123(vcpu);
9633         vcpu->arch.dr6 = DR6_INIT;
9634         vcpu->arch.dr7 = DR7_FIXED_1;
9635         kvm_update_dr7(vcpu);
9636
9637         vcpu->arch.cr2 = 0;
9638
9639         kvm_make_request(KVM_REQ_EVENT, vcpu);
9640         vcpu->arch.apf.msr_en_val = 0;
9641         vcpu->arch.apf.msr_int_val = 0;
9642         vcpu->arch.st.msr_val = 0;
9643
9644         kvmclock_reset(vcpu);
9645
9646         kvm_clear_async_pf_completion_queue(vcpu);
9647         kvm_async_pf_hash_reset(vcpu);
9648         vcpu->arch.apf.halted = false;
9649
9650         if (kvm_mpx_supported()) {
9651                 void *mpx_state_buffer;
9652
9653                 /*
9654                  * To avoid have the INIT path from kvm_apic_has_events() that be
9655                  * called with loaded FPU and does not let userspace fix the state.
9656                  */
9657                 if (init_event)
9658                         kvm_put_guest_fpu(vcpu);
9659                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9660                                         XFEATURE_BNDREGS);
9661                 if (mpx_state_buffer)
9662                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
9663                 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
9664                                         XFEATURE_BNDCSR);
9665                 if (mpx_state_buffer)
9666                         memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
9667                 if (init_event)
9668                         kvm_load_guest_fpu(vcpu);
9669         }
9670
9671         if (!init_event) {
9672                 kvm_pmu_reset(vcpu);
9673                 vcpu->arch.smbase = 0x30000;
9674
9675                 vcpu->arch.msr_misc_features_enables = 0;
9676
9677                 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9678         }
9679
9680         memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9681         vcpu->arch.regs_avail = ~0;
9682         vcpu->arch.regs_dirty = ~0;
9683
9684         vcpu->arch.ia32_xss = 0;
9685
9686         kvm_x86_ops.vcpu_reset(vcpu, init_event);
9687 }
9688
9689 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
9690 {
9691         struct kvm_segment cs;
9692
9693         kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9694         cs.selector = vector << 8;
9695         cs.base = vector << 12;
9696         kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9697         kvm_rip_write(vcpu, 0);
9698 }
9699
9700 int kvm_arch_hardware_enable(void)
9701 {
9702         struct kvm *kvm;
9703         struct kvm_vcpu *vcpu;
9704         int i;
9705         int ret;
9706         u64 local_tsc;
9707         u64 max_tsc = 0;
9708         bool stable, backwards_tsc = false;
9709
9710         kvm_shared_msr_cpu_online();
9711         ret = kvm_x86_ops.hardware_enable();
9712         if (ret != 0)
9713                 return ret;
9714
9715         local_tsc = rdtsc();
9716         stable = !kvm_check_tsc_unstable();
9717         list_for_each_entry(kvm, &vm_list, vm_list) {
9718                 kvm_for_each_vcpu(i, vcpu, kvm) {
9719                         if (!stable && vcpu->cpu == smp_processor_id())
9720                                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9721                         if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9722                                 backwards_tsc = true;
9723                                 if (vcpu->arch.last_host_tsc > max_tsc)
9724                                         max_tsc = vcpu->arch.last_host_tsc;
9725                         }
9726                 }
9727         }
9728
9729         /*
9730          * Sometimes, even reliable TSCs go backwards.  This happens on
9731          * platforms that reset TSC during suspend or hibernate actions, but
9732          * maintain synchronization.  We must compensate.  Fortunately, we can
9733          * detect that condition here, which happens early in CPU bringup,
9734          * before any KVM threads can be running.  Unfortunately, we can't
9735          * bring the TSCs fully up to date with real time, as we aren't yet far
9736          * enough into CPU bringup that we know how much real time has actually
9737          * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
9738          * variables that haven't been updated yet.
9739          *
9740          * So we simply find the maximum observed TSC above, then record the
9741          * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
9742          * the adjustment will be applied.  Note that we accumulate
9743          * adjustments, in case multiple suspend cycles happen before some VCPU
9744          * gets a chance to run again.  In the event that no KVM threads get a
9745          * chance to run, we will miss the entire elapsed period, as we'll have
9746          * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9747          * loose cycle time.  This isn't too big a deal, since the loss will be
9748          * uniform across all VCPUs (not to mention the scenario is extremely
9749          * unlikely). It is possible that a second hibernate recovery happens
9750          * much faster than a first, causing the observed TSC here to be
9751          * smaller; this would require additional padding adjustment, which is
9752          * why we set last_host_tsc to the local tsc observed here.
9753          *
9754          * N.B. - this code below runs only on platforms with reliable TSC,
9755          * as that is the only way backwards_tsc is set above.  Also note
9756          * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9757          * have the same delta_cyc adjustment applied if backwards_tsc
9758          * is detected.  Note further, this adjustment is only done once,
9759          * as we reset last_host_tsc on all VCPUs to stop this from being
9760          * called multiple times (one for each physical CPU bringup).
9761          *
9762          * Platforms with unreliable TSCs don't have to deal with this, they
9763          * will be compensated by the logic in vcpu_load, which sets the TSC to
9764          * catchup mode.  This will catchup all VCPUs to real time, but cannot
9765          * guarantee that they stay in perfect synchronization.
9766          */
9767         if (backwards_tsc) {
9768                 u64 delta_cyc = max_tsc - local_tsc;
9769                 list_for_each_entry(kvm, &vm_list, vm_list) {
9770                         kvm->arch.backwards_tsc_observed = true;
9771                         kvm_for_each_vcpu(i, vcpu, kvm) {
9772                                 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9773                                 vcpu->arch.last_host_tsc = local_tsc;
9774                                 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9775                         }
9776
9777                         /*
9778                          * We have to disable TSC offset matching.. if you were
9779                          * booting a VM while issuing an S4 host suspend....
9780                          * you may have some problem.  Solving this issue is
9781                          * left as an exercise to the reader.
9782                          */
9783                         kvm->arch.last_tsc_nsec = 0;
9784                         kvm->arch.last_tsc_write = 0;
9785                 }
9786
9787         }
9788         return 0;
9789 }
9790
9791 void kvm_arch_hardware_disable(void)
9792 {
9793         kvm_x86_ops.hardware_disable();
9794         drop_user_return_notifiers();
9795 }
9796
9797 int kvm_arch_hardware_setup(void *opaque)
9798 {
9799         struct kvm_x86_init_ops *ops = opaque;
9800         int r;
9801
9802         rdmsrl_safe(MSR_EFER, &host_efer);
9803
9804         if (boot_cpu_has(X86_FEATURE_XSAVES))
9805                 rdmsrl(MSR_IA32_XSS, host_xss);
9806
9807         r = ops->hardware_setup();
9808         if (r != 0)
9809                 return r;
9810
9811         memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9812
9813         if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9814                 supported_xss = 0;
9815
9816 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9817         cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9818 #undef __kvm_cpu_cap_has
9819
9820         if (kvm_has_tsc_control) {
9821                 /*
9822                  * Make sure the user can only configure tsc_khz values that
9823                  * fit into a signed integer.
9824                  * A min value is not calculated because it will always
9825                  * be 1 on all machines.
9826                  */
9827                 u64 max = min(0x7fffffffULL,
9828                               __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9829                 kvm_max_guest_tsc_khz = max;
9830
9831                 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
9832         }
9833
9834         kvm_init_msr_list();
9835         return 0;
9836 }
9837
9838 void kvm_arch_hardware_unsetup(void)
9839 {
9840         kvm_x86_ops.hardware_unsetup();
9841 }
9842
9843 int kvm_arch_check_processor_compat(void *opaque)
9844 {
9845         struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9846         struct kvm_x86_init_ops *ops = opaque;
9847
9848         WARN_ON(!irqs_disabled());
9849
9850         if (__cr4_reserved_bits(cpu_has, c) !=
9851             __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9852                 return -EIO;
9853
9854         return ops->check_processor_compatibility();
9855 }
9856
9857 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9858 {
9859         return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9860 }
9861 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9862
9863 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9864 {
9865         return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
9866 }
9867
9868 struct static_key kvm_no_apic_vcpu __read_mostly;
9869 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
9870
9871 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9872 {
9873         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9874
9875         vcpu->arch.l1tf_flush_l1d = true;
9876         if (pmu->version && unlikely(pmu->event_count)) {
9877                 pmu->need_cleanup = true;
9878                 kvm_make_request(KVM_REQ_PMU, vcpu);
9879         }
9880         kvm_x86_ops.sched_in(vcpu, cpu);
9881 }
9882
9883 void kvm_arch_free_vm(struct kvm *kvm)
9884 {
9885         kfree(kvm->arch.hyperv.hv_pa_pg);
9886         vfree(kvm);
9887 }
9888
9889
9890 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
9891 {
9892         if (type)
9893                 return -EINVAL;
9894
9895         INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
9896         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
9897         INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
9898         INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
9899         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
9900         atomic_set(&kvm->arch.noncoherent_dma_count, 0);
9901
9902         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9903         set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
9904         /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9905         set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9906                 &kvm->arch.irq_sources_bitmap);
9907
9908         raw_spin_lock_init(&kvm->arch.tsc_write_lock);
9909         mutex_init(&kvm->arch.apic_map_lock);
9910         spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9911
9912         kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
9913         pvclock_update_vm_gtod_copy(kvm);
9914
9915         kvm->arch.guest_can_read_msr_platform_info = true;
9916
9917         INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
9918         INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
9919
9920         kvm_hv_init_vm(kvm);
9921         kvm_page_track_init(kvm);
9922         kvm_mmu_init_vm(kvm);
9923
9924         return kvm_x86_ops.vm_init(kvm);
9925 }
9926
9927 int kvm_arch_post_init_vm(struct kvm *kvm)
9928 {
9929         return kvm_mmu_post_init_vm(kvm);
9930 }
9931
9932 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9933 {
9934         vcpu_load(vcpu);
9935         kvm_mmu_unload(vcpu);
9936         vcpu_put(vcpu);
9937 }
9938
9939 static void kvm_free_vcpus(struct kvm *kvm)
9940 {
9941         unsigned int i;
9942         struct kvm_vcpu *vcpu;
9943
9944         /*
9945          * Unpin any mmu pages first.
9946          */
9947         kvm_for_each_vcpu(i, vcpu, kvm) {
9948                 kvm_clear_async_pf_completion_queue(vcpu);
9949                 kvm_unload_vcpu_mmu(vcpu);
9950         }
9951         kvm_for_each_vcpu(i, vcpu, kvm)
9952                 kvm_vcpu_destroy(vcpu);
9953
9954         mutex_lock(&kvm->lock);
9955         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9956                 kvm->vcpus[i] = NULL;
9957
9958         atomic_set(&kvm->online_vcpus, 0);
9959         mutex_unlock(&kvm->lock);
9960 }
9961
9962 void kvm_arch_sync_events(struct kvm *kvm)
9963 {
9964         cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
9965         cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
9966         kvm_free_pit(kvm);
9967 }
9968
9969 int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9970 {
9971         int i, r;
9972         unsigned long hva, old_npages;
9973         struct kvm_memslots *slots = kvm_memslots(kvm);
9974         struct kvm_memory_slot *slot;
9975
9976         /* Called with kvm->slots_lock held.  */
9977         if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9978                 return -EINVAL;
9979
9980         slot = id_to_memslot(slots, id);
9981         if (size) {
9982                 if (slot && slot->npages)
9983                         return -EEXIST;
9984
9985                 /*
9986                  * MAP_SHARED to prevent internal slot pages from being moved
9987                  * by fork()/COW.
9988                  */
9989                 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9990                               MAP_SHARED | MAP_ANONYMOUS, 0);
9991                 if (IS_ERR((void *)hva))
9992                         return PTR_ERR((void *)hva);
9993         } else {
9994                 if (!slot || !slot->npages)
9995                         return 0;
9996
9997                 old_npages = slot->npages;
9998                 hva = 0;
9999         }
10000
10001         for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10002                 struct kvm_userspace_memory_region m;
10003
10004                 m.slot = id | (i << 16);
10005                 m.flags = 0;
10006                 m.guest_phys_addr = gpa;
10007                 m.userspace_addr = hva;
10008                 m.memory_size = size;
10009                 r = __kvm_set_memory_region(kvm, &m);
10010                 if (r < 0)
10011                         return r;
10012         }
10013
10014         if (!size)
10015                 vm_munmap(hva, old_npages * PAGE_SIZE);
10016
10017         return 0;
10018 }
10019 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10020
10021 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10022 {
10023         kvm_mmu_pre_destroy_vm(kvm);
10024 }
10025
10026 void kvm_arch_destroy_vm(struct kvm *kvm)
10027 {
10028         if (current->mm == kvm->mm) {
10029                 /*
10030                  * Free memory regions allocated on behalf of userspace,
10031                  * unless the the memory map has changed due to process exit
10032                  * or fd copying.
10033                  */
10034                 mutex_lock(&kvm->slots_lock);
10035                 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10036                                         0, 0);
10037                 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10038                                         0, 0);
10039                 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10040                 mutex_unlock(&kvm->slots_lock);
10041         }
10042         if (kvm_x86_ops.vm_destroy)
10043                 kvm_x86_ops.vm_destroy(kvm);
10044         kvm_pic_destroy(kvm);
10045         kvm_ioapic_destroy(kvm);
10046         kvm_free_vcpus(kvm);
10047         kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10048         kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10049         kvm_mmu_uninit_vm(kvm);
10050         kvm_page_track_cleanup(kvm);
10051         kvm_hv_destroy_vm(kvm);
10052 }
10053
10054 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10055 {
10056         int i;
10057
10058         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10059                 kvfree(slot->arch.rmap[i]);
10060                 slot->arch.rmap[i] = NULL;
10061
10062                 if (i == 0)
10063                         continue;
10064
10065                 kvfree(slot->arch.lpage_info[i - 1]);
10066                 slot->arch.lpage_info[i - 1] = NULL;
10067         }
10068
10069         kvm_page_track_free_memslot(slot);
10070 }
10071
10072 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10073                                       unsigned long npages)
10074 {
10075         int i;
10076
10077         /*
10078          * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
10079          * old arrays will be freed by __kvm_set_memory_region() if installing
10080          * the new memslot is successful.
10081          */
10082         memset(&slot->arch, 0, sizeof(slot->arch));
10083
10084         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10085                 struct kvm_lpage_info *linfo;
10086                 unsigned long ugfn;
10087                 int lpages;
10088                 int level = i + 1;
10089
10090                 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10091                                       slot->base_gfn, level) + 1;
10092
10093                 slot->arch.rmap[i] =
10094                         kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10095                                  GFP_KERNEL_ACCOUNT);
10096                 if (!slot->arch.rmap[i])
10097                         goto out_free;
10098                 if (i == 0)
10099                         continue;
10100
10101                 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10102                 if (!linfo)
10103                         goto out_free;
10104
10105                 slot->arch.lpage_info[i - 1] = linfo;
10106
10107                 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10108                         linfo[0].disallow_lpage = 1;
10109                 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10110                         linfo[lpages - 1].disallow_lpage = 1;
10111                 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10112                 /*
10113                  * If the gfn and userspace address are not aligned wrt each
10114                  * other, disable large page support for this slot.
10115                  */
10116                 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10117                         unsigned long j;
10118
10119                         for (j = 0; j < lpages; ++j)
10120                                 linfo[j].disallow_lpage = 1;
10121                 }
10122         }
10123
10124         if (kvm_page_track_create_memslot(slot, npages))
10125                 goto out_free;
10126
10127         return 0;
10128
10129 out_free:
10130         for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10131                 kvfree(slot->arch.rmap[i]);
10132                 slot->arch.rmap[i] = NULL;
10133                 if (i == 0)
10134                         continue;
10135
10136                 kvfree(slot->arch.lpage_info[i - 1]);
10137                 slot->arch.lpage_info[i - 1] = NULL;
10138         }
10139         return -ENOMEM;
10140 }
10141
10142 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10143 {
10144         struct kvm_vcpu *vcpu;
10145         int i;
10146
10147         /*
10148          * memslots->generation has been incremented.
10149          * mmio generation may have reached its maximum value.
10150          */
10151         kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10152
10153         /* Force re-initialization of steal_time cache */
10154         kvm_for_each_vcpu(i, vcpu, kvm)
10155                 kvm_vcpu_kick(vcpu);
10156 }
10157
10158 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10159                                 struct kvm_memory_slot *memslot,
10160                                 const struct kvm_userspace_memory_region *mem,
10161                                 enum kvm_mr_change change)
10162 {
10163         if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10164                 return kvm_alloc_memslot_metadata(memslot,
10165                                                   mem->memory_size >> PAGE_SHIFT);
10166         return 0;
10167 }
10168
10169 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10170                                      struct kvm_memory_slot *old,
10171                                      struct kvm_memory_slot *new,
10172                                      enum kvm_mr_change change)
10173 {
10174         /*
10175          * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10176          * See comments below.
10177          */
10178         if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10179                 return;
10180
10181         /*
10182          * Dirty logging tracks sptes in 4k granularity, meaning that large
10183          * sptes have to be split.  If live migration is successful, the guest
10184          * in the source machine will be destroyed and large sptes will be
10185          * created in the destination. However, if the guest continues to run
10186          * in the source machine (for example if live migration fails), small
10187          * sptes will remain around and cause bad performance.
10188          *
10189          * Scan sptes if dirty logging has been stopped, dropping those
10190          * which can be collapsed into a single large-page spte.  Later
10191          * page faults will create the large-page sptes.
10192          *
10193          * There is no need to do this in any of the following cases:
10194          * CREATE:      No dirty mappings will already exist.
10195          * MOVE/DELETE: The old mappings will already have been cleaned up by
10196          *              kvm_arch_flush_shadow_memslot()
10197          */
10198         if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10199             !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10200                 kvm_mmu_zap_collapsible_sptes(kvm, new);
10201
10202         /*
10203          * Enable or disable dirty logging for the slot.
10204          *
10205          * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10206          * slot have been zapped so no dirty logging updates are needed for
10207          * the old slot.
10208          * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10209          * any mappings that might be created in it will consume the
10210          * properties of the new slot and do not need to be updated here.
10211          *
10212          * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10213          * called to enable/disable dirty logging.
10214          *
10215          * When disabling dirty logging with PML enabled, the D-bit is set
10216          * for sptes in the slot in order to prevent unnecessary GPA
10217          * logging in the PML buffer (and potential PML buffer full VMEXIT).
10218          * This guarantees leaving PML enabled for the guest's lifetime
10219          * won't have any additional overhead from PML when the guest is
10220          * running with dirty logging disabled.
10221          *
10222          * When enabling dirty logging, large sptes are write-protected
10223          * so they can be split on first write.  New large sptes cannot
10224          * be created for this slot until the end of the logging.
10225          * See the comments in fast_page_fault().
10226          * For small sptes, nothing is done if the dirty log is in the
10227          * initial-all-set state.  Otherwise, depending on whether pml
10228          * is enabled the D-bit or the W-bit will be cleared.
10229          */
10230         if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10231                 if (kvm_x86_ops.slot_enable_log_dirty) {
10232                         kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10233                 } else {
10234                         int level =
10235                                 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10236                                 PG_LEVEL_2M : PG_LEVEL_4K;
10237
10238                         /*
10239                          * If we're with initial-all-set, we don't need
10240                          * to write protect any small page because
10241                          * they're reported as dirty already.  However
10242                          * we still need to write-protect huge pages
10243                          * so that the page split can happen lazily on
10244                          * the first write to the huge page.
10245                          */
10246                         kvm_mmu_slot_remove_write_access(kvm, new, level);
10247                 }
10248         } else {
10249                 if (kvm_x86_ops.slot_disable_log_dirty)
10250                         kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10251         }
10252 }
10253
10254 void kvm_arch_commit_memory_region(struct kvm *kvm,
10255                                 const struct kvm_userspace_memory_region *mem,
10256                                 struct kvm_memory_slot *old,
10257                                 const struct kvm_memory_slot *new,
10258                                 enum kvm_mr_change change)
10259 {
10260         if (!kvm->arch.n_requested_mmu_pages)
10261                 kvm_mmu_change_mmu_pages(kvm,
10262                                 kvm_mmu_calculate_default_mmu_pages(kvm));
10263
10264         /*
10265          * FIXME: const-ify all uses of struct kvm_memory_slot.
10266          */
10267         kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10268
10269         /* Free the arrays associated with the old memslot. */
10270         if (change == KVM_MR_MOVE)
10271                 kvm_arch_free_memslot(kvm, old);
10272 }
10273
10274 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10275 {
10276         kvm_mmu_zap_all(kvm);
10277 }
10278
10279 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10280                                    struct kvm_memory_slot *slot)
10281 {
10282         kvm_page_track_flush_slot(kvm, slot);
10283 }
10284
10285 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10286 {
10287         return (is_guest_mode(vcpu) &&
10288                         kvm_x86_ops.guest_apic_has_interrupt &&
10289                         kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10290 }
10291
10292 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10293 {
10294         if (!list_empty_careful(&vcpu->async_pf.done))
10295                 return true;
10296
10297         if (kvm_apic_has_events(vcpu))
10298                 return true;
10299
10300         if (vcpu->arch.pv.pv_unhalted)
10301                 return true;
10302
10303         if (vcpu->arch.exception.pending)
10304                 return true;
10305
10306         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10307             (vcpu->arch.nmi_pending &&
10308              kvm_x86_ops.nmi_allowed(vcpu, false)))
10309                 return true;
10310
10311         if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10312             (vcpu->arch.smi_pending &&
10313              kvm_x86_ops.smi_allowed(vcpu, false)))
10314                 return true;
10315
10316         if (kvm_arch_interrupt_allowed(vcpu) &&
10317             (kvm_cpu_has_interrupt(vcpu) ||
10318             kvm_guest_apic_has_interrupt(vcpu)))
10319                 return true;
10320
10321         if (kvm_hv_has_stimer_pending(vcpu))
10322                 return true;
10323
10324         if (is_guest_mode(vcpu) &&
10325             kvm_x86_ops.nested_ops->hv_timer_pending &&
10326             kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10327                 return true;
10328
10329         return false;
10330 }
10331
10332 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10333 {
10334         return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10335 }
10336
10337 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10338 {
10339         if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10340                 return true;
10341
10342         if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10343                 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10344                  kvm_test_request(KVM_REQ_EVENT, vcpu))
10345                 return true;
10346
10347         if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10348                 return true;
10349
10350         return false;
10351 }
10352
10353 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10354 {
10355         return vcpu->arch.preempted_in_kernel;
10356 }
10357
10358 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10359 {
10360         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10361 }
10362
10363 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10364 {
10365         return kvm_x86_ops.interrupt_allowed(vcpu, false);
10366 }
10367
10368 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10369 {
10370         if (is_64_bit_mode(vcpu))
10371                 return kvm_rip_read(vcpu);
10372         return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10373                      kvm_rip_read(vcpu));
10374 }
10375 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10376
10377 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10378 {
10379         return kvm_get_linear_rip(vcpu) == linear_rip;
10380 }
10381 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10382
10383 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10384 {
10385         unsigned long rflags;
10386
10387         rflags = kvm_x86_ops.get_rflags(vcpu);
10388         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10389                 rflags &= ~X86_EFLAGS_TF;
10390         return rflags;
10391 }
10392 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10393
10394 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10395 {
10396         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10397             kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10398                 rflags |= X86_EFLAGS_TF;
10399         kvm_x86_ops.set_rflags(vcpu, rflags);
10400 }
10401
10402 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10403 {
10404         __kvm_set_rflags(vcpu, rflags);
10405         kvm_make_request(KVM_REQ_EVENT, vcpu);
10406 }
10407 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10408
10409 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10410 {
10411         int r;
10412
10413         if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10414               work->wakeup_all)
10415                 return;
10416
10417         r = kvm_mmu_reload(vcpu);
10418         if (unlikely(r))
10419                 return;
10420
10421         if (!vcpu->arch.mmu->direct_map &&
10422               work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10423                 return;
10424
10425         kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10426 }
10427
10428 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10429 {
10430         BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10431
10432         return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10433 }
10434
10435 static inline u32 kvm_async_pf_next_probe(u32 key)
10436 {
10437         return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10438 }
10439
10440 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10441 {
10442         u32 key = kvm_async_pf_hash_fn(gfn);
10443
10444         while (vcpu->arch.apf.gfns[key] != ~0)
10445                 key = kvm_async_pf_next_probe(key);
10446
10447         vcpu->arch.apf.gfns[key] = gfn;
10448 }
10449
10450 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10451 {
10452         int i;
10453         u32 key = kvm_async_pf_hash_fn(gfn);
10454
10455         for (i = 0; i < ASYNC_PF_PER_VCPU &&
10456                      (vcpu->arch.apf.gfns[key] != gfn &&
10457                       vcpu->arch.apf.gfns[key] != ~0); i++)
10458                 key = kvm_async_pf_next_probe(key);
10459
10460         return key;
10461 }
10462
10463 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10464 {
10465         return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10466 }
10467
10468 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10469 {
10470         u32 i, j, k;
10471
10472         i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10473
10474         if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10475                 return;
10476
10477         while (true) {
10478                 vcpu->arch.apf.gfns[i] = ~0;
10479                 do {
10480                         j = kvm_async_pf_next_probe(j);
10481                         if (vcpu->arch.apf.gfns[j] == ~0)
10482                                 return;
10483                         k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10484                         /*
10485                          * k lies cyclically in ]i,j]
10486                          * |    i.k.j |
10487                          * |....j i.k.| or  |.k..j i...|
10488                          */
10489                 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10490                 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10491                 i = j;
10492         }
10493 }
10494
10495 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10496 {
10497         u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10498
10499         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10500                                       sizeof(reason));
10501 }
10502
10503 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10504 {
10505         unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10506
10507         return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10508                                              &token, offset, sizeof(token));
10509 }
10510
10511 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10512 {
10513         unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10514         u32 val;
10515
10516         if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10517                                          &val, offset, sizeof(val)))
10518                 return false;
10519
10520         return !val;
10521 }
10522
10523 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10524 {
10525         if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10526                 return false;
10527
10528         if (!kvm_pv_async_pf_enabled(vcpu) ||
10529             (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10530                 return false;
10531
10532         return true;
10533 }
10534
10535 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10536 {
10537         if (unlikely(!lapic_in_kernel(vcpu) ||
10538                      kvm_event_needs_reinjection(vcpu) ||
10539                      vcpu->arch.exception.pending))
10540                 return false;
10541
10542         if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10543                 return false;
10544
10545         /*
10546          * If interrupts are off we cannot even use an artificial
10547          * halt state.
10548          */
10549         return kvm_arch_interrupt_allowed(vcpu);
10550 }
10551
10552 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10553                                      struct kvm_async_pf *work)
10554 {
10555         struct x86_exception fault;
10556
10557         trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10558         kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10559
10560         if (kvm_can_deliver_async_pf(vcpu) &&
10561             !apf_put_user_notpresent(vcpu)) {
10562                 fault.vector = PF_VECTOR;
10563                 fault.error_code_valid = true;
10564                 fault.error_code = 0;
10565                 fault.nested_page_fault = false;
10566                 fault.address = work->arch.token;
10567                 fault.async_page_fault = true;
10568                 kvm_inject_page_fault(vcpu, &fault);
10569                 return true;
10570         } else {
10571                 /*
10572                  * It is not possible to deliver a paravirtualized asynchronous
10573                  * page fault, but putting the guest in an artificial halt state
10574                  * can be beneficial nevertheless: if an interrupt arrives, we
10575                  * can deliver it timely and perhaps the guest will schedule
10576                  * another process.  When the instruction that triggered a page
10577                  * fault is retried, hopefully the page will be ready in the host.
10578                  */
10579                 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
10580                 return false;
10581         }
10582 }
10583
10584 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10585                                  struct kvm_async_pf *work)
10586 {
10587         struct kvm_lapic_irq irq = {
10588                 .delivery_mode = APIC_DM_FIXED,
10589                 .vector = vcpu->arch.apf.vec
10590         };
10591
10592         if (work->wakeup_all)
10593                 work->arch.token = ~0; /* broadcast wakeup */
10594         else
10595                 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
10596         trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
10597
10598         if ((work->wakeup_all || work->notpresent_injected) &&
10599             kvm_pv_async_pf_enabled(vcpu) &&
10600             !apf_put_user_ready(vcpu, work->arch.token)) {
10601                 vcpu->arch.apf.pageready_pending = true;
10602                 kvm_apic_set_irq(vcpu, &irq, NULL);
10603         }
10604
10605         vcpu->arch.apf.halted = false;
10606         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10607 }
10608
10609 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
10610 {
10611         kvm_make_request(KVM_REQ_APF_READY, vcpu);
10612         if (!vcpu->arch.apf.pageready_pending)
10613                 kvm_vcpu_kick(vcpu);
10614 }
10615
10616 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
10617 {
10618         if (!kvm_pv_async_pf_enabled(vcpu))
10619                 return true;
10620         else
10621                 return apf_pageready_slot_free(vcpu);
10622 }
10623
10624 void kvm_arch_start_assignment(struct kvm *kvm)
10625 {
10626         atomic_inc(&kvm->arch.assigned_device_count);
10627 }
10628 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10629
10630 void kvm_arch_end_assignment(struct kvm *kvm)
10631 {
10632         atomic_dec(&kvm->arch.assigned_device_count);
10633 }
10634 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10635
10636 bool kvm_arch_has_assigned_device(struct kvm *kvm)
10637 {
10638         return atomic_read(&kvm->arch.assigned_device_count);
10639 }
10640 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10641
10642 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10643 {
10644         atomic_inc(&kvm->arch.noncoherent_dma_count);
10645 }
10646 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10647
10648 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10649 {
10650         atomic_dec(&kvm->arch.noncoherent_dma_count);
10651 }
10652 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10653
10654 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10655 {
10656         return atomic_read(&kvm->arch.noncoherent_dma_count);
10657 }
10658 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10659
10660 bool kvm_arch_has_irq_bypass(void)
10661 {
10662         return true;
10663 }
10664
10665 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10666                                       struct irq_bypass_producer *prod)
10667 {
10668         struct kvm_kernel_irqfd *irqfd =
10669                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10670         int ret;
10671
10672         irqfd->producer = prod;
10673         kvm_arch_start_assignment(irqfd->kvm);
10674         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
10675                                          prod->irq, irqfd->gsi, 1);
10676
10677         if (ret)
10678                 kvm_arch_end_assignment(irqfd->kvm);
10679
10680         return ret;
10681 }
10682
10683 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10684                                       struct irq_bypass_producer *prod)
10685 {
10686         int ret;
10687         struct kvm_kernel_irqfd *irqfd =
10688                 container_of(cons, struct kvm_kernel_irqfd, consumer);
10689
10690         WARN_ON(irqfd->producer != prod);
10691         irqfd->producer = NULL;
10692
10693         /*
10694          * When producer of consumer is unregistered, we change back to
10695          * remapped mode, so we can re-use the current implementation
10696          * when the irq is masked/disabled or the consumer side (KVM
10697          * int this case doesn't want to receive the interrupts.
10698         */
10699         ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10700         if (ret)
10701                 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10702                        " fails: %d\n", irqfd->consumer.token, ret);
10703
10704         kvm_arch_end_assignment(irqfd->kvm);
10705 }
10706
10707 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10708                                    uint32_t guest_irq, bool set)
10709 {
10710         return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
10711 }
10712
10713 bool kvm_vector_hashing_enabled(void)
10714 {
10715         return vector_hashing;
10716 }
10717
10718 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10719 {
10720         return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10721 }
10722 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10723
10724
10725 int kvm_spec_ctrl_test_value(u64 value)
10726 {
10727         /*
10728          * test that setting IA32_SPEC_CTRL to given value
10729          * is allowed by the host processor
10730          */
10731
10732         u64 saved_value;
10733         unsigned long flags;
10734         int ret = 0;
10735
10736         local_irq_save(flags);
10737
10738         if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
10739                 ret = 1;
10740         else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
10741                 ret = 1;
10742         else
10743                 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
10744
10745         local_irq_restore(flags);
10746
10747         return ret;
10748 }
10749 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
10750
10751 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
10752 {
10753         struct x86_exception fault;
10754         u32 access = error_code &
10755                 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
10756
10757         if (!(error_code & PFERR_PRESENT_MASK) ||
10758             vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
10759                 /*
10760                  * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
10761                  * tables probably do not match the TLB.  Just proceed
10762                  * with the error code that the processor gave.
10763                  */
10764                 fault.vector = PF_VECTOR;
10765                 fault.error_code_valid = true;
10766                 fault.error_code = error_code;
10767                 fault.nested_page_fault = false;
10768                 fault.address = gva;
10769         }
10770         vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
10771 }
10772 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
10773
10774 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
10775 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
10776 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10777 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10778 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10779 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
10780 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
10781 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
10782 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
10783 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
10784 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
10785 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
10786 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
10787 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
10788 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
10789 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
10790 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
10791 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
10792 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10793 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
10794 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
10795 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);