1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
33 #include <linux/clocksource.h>
34 #include <linux/interrupt.h>
35 #include <linux/kvm.h>
37 #include <linux/vmalloc.h>
38 #include <linux/export.h>
39 #include <linux/moduleparam.h>
40 #include <linux/mman.h>
41 #include <linux/highmem.h>
42 #include <linux/iommu.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/cpufreq.h>
45 #include <linux/user-return-notifier.h>
46 #include <linux/srcu.h>
47 #include <linux/slab.h>
48 #include <linux/perf_event.h>
49 #include <linux/uaccess.h>
50 #include <linux/hash.h>
51 #include <linux/pci.h>
52 #include <linux/timekeeper_internal.h>
53 #include <linux/pvclock_gtod.h>
54 #include <linux/kvm_irqfd.h>
55 #include <linux/irqbypass.h>
56 #include <linux/sched/stat.h>
57 #include <linux/sched/isolation.h>
58 #include <linux/mem_encrypt.h>
59 #include <linux/entry-kvm.h>
61 #include <trace/events/kvm.h>
63 #include <asm/debugreg.h>
67 #include <linux/kernel_stat.h>
68 #include <asm/fpu/internal.h> /* Ugh! */
69 #include <asm/pvclock.h>
70 #include <asm/div64.h>
71 #include <asm/irq_remapping.h>
72 #include <asm/mshyperv.h>
73 #include <asm/hypervisor.h>
74 #include <asm/tlbflush.h>
75 #include <asm/intel_pt.h>
76 #include <asm/emulate_prefix.h>
77 #include <clocksource/hyperv_timer.h>
79 #define CREATE_TRACE_POINTS
82 #define MAX_IO_MSRS 256
83 #define KVM_MAX_MCE_BANKS 32
84 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
85 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
87 #define emul_to_vcpu(ctxt) \
88 ((struct kvm_vcpu *)(ctxt)->vcpu)
91 * - enable syscall per default because its emulated by KVM
92 * - enable LME and LMA per default on 64 bit KVM
96 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
98 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
101 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
103 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
104 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
106 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
107 static void process_nmi(struct kvm_vcpu *vcpu);
108 static void enter_smm(struct kvm_vcpu *vcpu);
109 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
110 static void store_regs(struct kvm_vcpu *vcpu);
111 static int sync_regs(struct kvm_vcpu *vcpu);
113 struct kvm_x86_ops kvm_x86_ops __read_mostly;
114 EXPORT_SYMBOL_GPL(kvm_x86_ops);
116 static bool __read_mostly ignore_msrs = 0;
117 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
119 static bool __read_mostly report_ignored_msrs = true;
120 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
122 unsigned int min_timer_period_us = 200;
123 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
125 static bool __read_mostly kvmclock_periodic_sync = true;
126 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
128 bool __read_mostly kvm_has_tsc_control;
129 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
130 u32 __read_mostly kvm_max_guest_tsc_khz;
131 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
132 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
133 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
134 u64 __read_mostly kvm_max_tsc_scaling_ratio;
135 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
136 u64 __read_mostly kvm_default_tsc_scaling_ratio;
137 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
139 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
140 static u32 __read_mostly tsc_tolerance_ppm = 250;
141 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
144 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
145 * adaptive tuning starting from default advancment of 1000ns. '0' disables
146 * advancement entirely. Any other value is used as-is and disables adaptive
147 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
149 static int __read_mostly lapic_timer_advance_ns = -1;
150 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
152 static bool __read_mostly vector_hashing = true;
153 module_param(vector_hashing, bool, S_IRUGO);
155 bool __read_mostly enable_vmware_backdoor = false;
156 module_param(enable_vmware_backdoor, bool, S_IRUGO);
157 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
159 static bool __read_mostly force_emulation_prefix = false;
160 module_param(force_emulation_prefix, bool, S_IRUGO);
162 int __read_mostly pi_inject_timer = -1;
163 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
166 * Restoring the host value for MSRs that are only consumed when running in
167 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
168 * returns to userspace, i.e. the kernel can run with the guest's value.
170 #define KVM_MAX_NR_USER_RETURN_MSRS 16
172 struct kvm_user_return_msrs_global {
174 u32 msrs[KVM_MAX_NR_USER_RETURN_MSRS];
177 struct kvm_user_return_msrs {
178 struct user_return_notifier urn;
180 struct kvm_user_return_msr_values {
183 } values[KVM_MAX_NR_USER_RETURN_MSRS];
186 static struct kvm_user_return_msrs_global __read_mostly user_return_msrs_global;
187 static struct kvm_user_return_msrs __percpu *user_return_msrs;
189 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
190 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
191 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
192 | XFEATURE_MASK_PKRU)
194 u64 __read_mostly host_efer;
195 EXPORT_SYMBOL_GPL(host_efer);
197 bool __read_mostly allow_smaller_maxphyaddr = 0;
198 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
200 static u64 __read_mostly host_xss;
201 u64 __read_mostly supported_xss;
202 EXPORT_SYMBOL_GPL(supported_xss);
204 struct kvm_stats_debugfs_item debugfs_entries[] = {
205 VCPU_STAT("pf_fixed", pf_fixed),
206 VCPU_STAT("pf_guest", pf_guest),
207 VCPU_STAT("tlb_flush", tlb_flush),
208 VCPU_STAT("invlpg", invlpg),
209 VCPU_STAT("exits", exits),
210 VCPU_STAT("io_exits", io_exits),
211 VCPU_STAT("mmio_exits", mmio_exits),
212 VCPU_STAT("signal_exits", signal_exits),
213 VCPU_STAT("irq_window", irq_window_exits),
214 VCPU_STAT("nmi_window", nmi_window_exits),
215 VCPU_STAT("halt_exits", halt_exits),
216 VCPU_STAT("halt_successful_poll", halt_successful_poll),
217 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
218 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
219 VCPU_STAT("halt_wakeup", halt_wakeup),
220 VCPU_STAT("hypercalls", hypercalls),
221 VCPU_STAT("request_irq", request_irq_exits),
222 VCPU_STAT("irq_exits", irq_exits),
223 VCPU_STAT("host_state_reload", host_state_reload),
224 VCPU_STAT("fpu_reload", fpu_reload),
225 VCPU_STAT("insn_emulation", insn_emulation),
226 VCPU_STAT("insn_emulation_fail", insn_emulation_fail),
227 VCPU_STAT("irq_injections", irq_injections),
228 VCPU_STAT("nmi_injections", nmi_injections),
229 VCPU_STAT("req_event", req_event),
230 VCPU_STAT("l1d_flush", l1d_flush),
231 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
232 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
233 VM_STAT("mmu_shadow_zapped", mmu_shadow_zapped),
234 VM_STAT("mmu_pte_write", mmu_pte_write),
235 VM_STAT("mmu_pte_updated", mmu_pte_updated),
236 VM_STAT("mmu_pde_zapped", mmu_pde_zapped),
237 VM_STAT("mmu_flooded", mmu_flooded),
238 VM_STAT("mmu_recycled", mmu_recycled),
239 VM_STAT("mmu_cache_miss", mmu_cache_miss),
240 VM_STAT("mmu_unsync", mmu_unsync),
241 VM_STAT("remote_tlb_flush", remote_tlb_flush),
242 VM_STAT("largepages", lpages, .mode = 0444),
243 VM_STAT("nx_largepages_splitted", nx_lpage_splits, .mode = 0444),
244 VM_STAT("max_mmu_page_hash_collisions", max_mmu_page_hash_collisions),
248 u64 __read_mostly host_xcr0;
249 u64 __read_mostly supported_xcr0;
250 EXPORT_SYMBOL_GPL(supported_xcr0);
252 static struct kmem_cache *x86_fpu_cache;
254 static struct kmem_cache *x86_emulator_cache;
257 * When called, it means the previous get/set msr reached an invalid msr.
258 * Return true if we want to ignore/silent this failed msr access.
260 static bool kvm_msr_ignored_check(struct kvm_vcpu *vcpu, u32 msr,
261 u64 data, bool write)
263 const char *op = write ? "wrmsr" : "rdmsr";
266 if (report_ignored_msrs)
267 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
272 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
278 static struct kmem_cache *kvm_alloc_emulator_cache(void)
280 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
281 unsigned int size = sizeof(struct x86_emulate_ctxt);
283 return kmem_cache_create_usercopy("x86_emulator", size,
284 __alignof__(struct x86_emulate_ctxt),
285 SLAB_ACCOUNT, useroffset,
286 size - useroffset, NULL);
289 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
291 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
294 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
295 vcpu->arch.apf.gfns[i] = ~0;
298 static void kvm_on_user_return(struct user_return_notifier *urn)
301 struct kvm_user_return_msrs *msrs
302 = container_of(urn, struct kvm_user_return_msrs, urn);
303 struct kvm_user_return_msr_values *values;
307 * Disabling irqs at this point since the following code could be
308 * interrupted and executed through kvm_arch_hardware_disable()
310 local_irq_save(flags);
311 if (msrs->registered) {
312 msrs->registered = false;
313 user_return_notifier_unregister(urn);
315 local_irq_restore(flags);
316 for (slot = 0; slot < user_return_msrs_global.nr; ++slot) {
317 values = &msrs->values[slot];
318 if (values->host != values->curr) {
319 wrmsrl(user_return_msrs_global.msrs[slot], values->host);
320 values->curr = values->host;
325 void kvm_define_user_return_msr(unsigned slot, u32 msr)
327 BUG_ON(slot >= KVM_MAX_NR_USER_RETURN_MSRS);
328 user_return_msrs_global.msrs[slot] = msr;
329 if (slot >= user_return_msrs_global.nr)
330 user_return_msrs_global.nr = slot + 1;
332 EXPORT_SYMBOL_GPL(kvm_define_user_return_msr);
334 static void kvm_user_return_msr_cpu_online(void)
336 unsigned int cpu = smp_processor_id();
337 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
341 for (i = 0; i < user_return_msrs_global.nr; ++i) {
342 rdmsrl_safe(user_return_msrs_global.msrs[i], &value);
343 msrs->values[i].host = value;
344 msrs->values[i].curr = value;
348 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
350 unsigned int cpu = smp_processor_id();
351 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
354 value = (value & mask) | (msrs->values[slot].host & ~mask);
355 if (value == msrs->values[slot].curr)
357 err = wrmsrl_safe(user_return_msrs_global.msrs[slot], value);
361 msrs->values[slot].curr = value;
362 if (!msrs->registered) {
363 msrs->urn.on_user_return = kvm_on_user_return;
364 user_return_notifier_register(&msrs->urn);
365 msrs->registered = true;
369 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
371 static void drop_user_return_notifiers(void)
373 unsigned int cpu = smp_processor_id();
374 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
376 if (msrs->registered)
377 kvm_on_user_return(&msrs->urn);
380 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
382 return vcpu->arch.apic_base;
384 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
386 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
388 return kvm_apic_mode(kvm_get_apic_base(vcpu));
390 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
392 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
394 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
395 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
396 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
397 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
399 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
401 if (!msr_info->host_initiated) {
402 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
404 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
408 kvm_lapic_set_base(vcpu, msr_info->data);
409 kvm_recalculate_apic_map(vcpu->kvm);
412 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
414 asmlinkage __visible noinstr void kvm_spurious_fault(void)
416 /* Fault while not rebooting. We want the trace. */
417 BUG_ON(!kvm_rebooting);
419 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
421 #define EXCPT_BENIGN 0
422 #define EXCPT_CONTRIBUTORY 1
425 static int exception_class(int vector)
435 return EXCPT_CONTRIBUTORY;
442 #define EXCPT_FAULT 0
444 #define EXCPT_ABORT 2
445 #define EXCPT_INTERRUPT 3
447 static int exception_type(int vector)
451 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
452 return EXCPT_INTERRUPT;
456 /* #DB is trap, as instruction watchpoints are handled elsewhere */
457 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
460 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
463 /* Reserved exceptions will result in fault */
467 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
469 unsigned nr = vcpu->arch.exception.nr;
470 bool has_payload = vcpu->arch.exception.has_payload;
471 unsigned long payload = vcpu->arch.exception.payload;
479 * "Certain debug exceptions may clear bit 0-3. The
480 * remaining contents of the DR6 register are never
481 * cleared by the processor".
483 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
485 * DR6.RTM is set by all #DB exceptions that don't clear it.
487 vcpu->arch.dr6 |= DR6_RTM;
488 vcpu->arch.dr6 |= payload;
490 * Bit 16 should be set in the payload whenever the #DB
491 * exception should clear DR6.RTM. This makes the payload
492 * compatible with the pending debug exceptions under VMX.
493 * Though not currently documented in the SDM, this also
494 * makes the payload compatible with the exit qualification
495 * for #DB exceptions under VMX.
497 vcpu->arch.dr6 ^= payload & DR6_RTM;
500 * The #DB payload is defined as compatible with the 'pending
501 * debug exceptions' field under VMX, not DR6. While bit 12 is
502 * defined in the 'pending debug exceptions' field (enabled
503 * breakpoint), it is reserved and must be zero in DR6.
505 vcpu->arch.dr6 &= ~BIT(12);
508 vcpu->arch.cr2 = payload;
512 vcpu->arch.exception.has_payload = false;
513 vcpu->arch.exception.payload = 0;
515 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
517 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
518 unsigned nr, bool has_error, u32 error_code,
519 bool has_payload, unsigned long payload, bool reinject)
524 kvm_make_request(KVM_REQ_EVENT, vcpu);
526 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
528 if (has_error && !is_protmode(vcpu))
532 * On vmentry, vcpu->arch.exception.pending is only
533 * true if an event injection was blocked by
534 * nested_run_pending. In that case, however,
535 * vcpu_enter_guest requests an immediate exit,
536 * and the guest shouldn't proceed far enough to
539 WARN_ON_ONCE(vcpu->arch.exception.pending);
540 vcpu->arch.exception.injected = true;
541 if (WARN_ON_ONCE(has_payload)) {
543 * A reinjected event has already
544 * delivered its payload.
550 vcpu->arch.exception.pending = true;
551 vcpu->arch.exception.injected = false;
553 vcpu->arch.exception.has_error_code = has_error;
554 vcpu->arch.exception.nr = nr;
555 vcpu->arch.exception.error_code = error_code;
556 vcpu->arch.exception.has_payload = has_payload;
557 vcpu->arch.exception.payload = payload;
558 if (!is_guest_mode(vcpu))
559 kvm_deliver_exception_payload(vcpu);
563 /* to check exception */
564 prev_nr = vcpu->arch.exception.nr;
565 if (prev_nr == DF_VECTOR) {
566 /* triple fault -> shutdown */
567 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
570 class1 = exception_class(prev_nr);
571 class2 = exception_class(nr);
572 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
573 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
575 * Generate double fault per SDM Table 5-5. Set
576 * exception.pending = true so that the double fault
577 * can trigger a nested vmexit.
579 vcpu->arch.exception.pending = true;
580 vcpu->arch.exception.injected = false;
581 vcpu->arch.exception.has_error_code = true;
582 vcpu->arch.exception.nr = DF_VECTOR;
583 vcpu->arch.exception.error_code = 0;
584 vcpu->arch.exception.has_payload = false;
585 vcpu->arch.exception.payload = 0;
587 /* replace previous exception with a new one in a hope
588 that instruction re-execution will regenerate lost
593 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
595 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
597 EXPORT_SYMBOL_GPL(kvm_queue_exception);
599 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
601 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
603 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
605 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
606 unsigned long payload)
608 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
610 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
612 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
613 u32 error_code, unsigned long payload)
615 kvm_multiple_exception(vcpu, nr, true, error_code,
616 true, payload, false);
619 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
622 kvm_inject_gp(vcpu, 0);
624 return kvm_skip_emulated_instruction(vcpu);
628 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
630 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
632 ++vcpu->stat.pf_guest;
633 vcpu->arch.exception.nested_apf =
634 is_guest_mode(vcpu) && fault->async_page_fault;
635 if (vcpu->arch.exception.nested_apf) {
636 vcpu->arch.apf.nested_apf_token = fault->address;
637 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
639 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
643 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
645 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
646 struct x86_exception *fault)
648 struct kvm_mmu *fault_mmu;
649 WARN_ON_ONCE(fault->vector != PF_VECTOR);
651 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
655 * Invalidate the TLB entry for the faulting address, if it exists,
656 * else the access will fault indefinitely (and to emulate hardware).
658 if ((fault->error_code & PFERR_PRESENT_MASK) &&
659 !(fault->error_code & PFERR_RSVD_MASK))
660 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
661 fault_mmu->root_hpa);
663 fault_mmu->inject_page_fault(vcpu, fault);
664 return fault->nested_page_fault;
666 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
668 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
670 atomic_inc(&vcpu->arch.nmi_queued);
671 kvm_make_request(KVM_REQ_NMI, vcpu);
673 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
675 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
677 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
679 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
681 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
683 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
685 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
688 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
689 * a #GP and return false.
691 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
693 if (kvm_x86_ops.get_cpl(vcpu) <= required_cpl)
695 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
698 EXPORT_SYMBOL_GPL(kvm_require_cpl);
700 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
702 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 kvm_queue_exception(vcpu, UD_VECTOR);
708 EXPORT_SYMBOL_GPL(kvm_require_dr);
711 * This function will be used to read from the physical memory of the currently
712 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
713 * can read from guest physical or from the guest's guest physical memory.
715 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
716 gfn_t ngfn, void *data, int offset, int len,
719 struct x86_exception exception;
723 ngpa = gfn_to_gpa(ngfn);
724 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
725 if (real_gfn == UNMAPPED_GVA)
728 real_gfn = gpa_to_gfn(real_gfn);
730 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
732 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
734 static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
735 void *data, int offset, int len, u32 access)
737 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
738 data, offset, len, access);
741 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
743 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
748 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
750 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
752 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
753 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
756 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
758 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
759 offset * sizeof(u64), sizeof(pdpte),
760 PFERR_USER_MASK|PFERR_WRITE_MASK);
765 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
766 if ((pdpte[i] & PT_PRESENT_MASK) &&
767 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
774 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
775 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
781 EXPORT_SYMBOL_GPL(load_pdptrs);
783 bool pdptrs_changed(struct kvm_vcpu *vcpu)
785 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
790 if (!is_pae_paging(vcpu))
793 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
796 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
797 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
798 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
799 PFERR_USER_MASK | PFERR_WRITE_MASK);
803 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
805 EXPORT_SYMBOL_GPL(pdptrs_changed);
807 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
809 unsigned long old_cr0 = kvm_read_cr0(vcpu);
810 unsigned long pdptr_bits = X86_CR0_CD | X86_CR0_NW | X86_CR0_PG;
811 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
816 if (cr0 & 0xffffffff00000000UL)
820 cr0 &= ~CR0_RESERVED_BITS;
822 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
825 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
829 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
830 (cr0 & X86_CR0_PG)) {
835 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
840 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
841 is_pae(vcpu) && ((cr0 ^ old_cr0) & pdptr_bits) &&
842 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu)))
845 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
848 kvm_x86_ops.set_cr0(vcpu, cr0);
850 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
851 kvm_clear_async_pf_completion_queue(vcpu);
852 kvm_async_pf_hash_reset(vcpu);
855 if ((cr0 ^ old_cr0) & update_bits)
856 kvm_mmu_reset_context(vcpu);
858 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
859 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
860 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
861 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
865 EXPORT_SYMBOL_GPL(kvm_set_cr0);
867 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
869 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
871 EXPORT_SYMBOL_GPL(kvm_lmsw);
873 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
875 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
877 if (vcpu->arch.xcr0 != host_xcr0)
878 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
880 if (vcpu->arch.xsaves_enabled &&
881 vcpu->arch.ia32_xss != host_xss)
882 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
885 if (static_cpu_has(X86_FEATURE_PKU) &&
886 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
887 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
888 vcpu->arch.pkru != vcpu->arch.host_pkru)
889 __write_pkru(vcpu->arch.pkru);
891 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
893 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
895 if (static_cpu_has(X86_FEATURE_PKU) &&
896 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
897 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
898 vcpu->arch.pkru = rdpkru();
899 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
900 __write_pkru(vcpu->arch.host_pkru);
903 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
905 if (vcpu->arch.xcr0 != host_xcr0)
906 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
908 if (vcpu->arch.xsaves_enabled &&
909 vcpu->arch.ia32_xss != host_xss)
910 wrmsrl(MSR_IA32_XSS, host_xss);
914 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
916 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
919 u64 old_xcr0 = vcpu->arch.xcr0;
922 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
923 if (index != XCR_XFEATURE_ENABLED_MASK)
925 if (!(xcr0 & XFEATURE_MASK_FP))
927 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
931 * Do not allow the guest to set bits that we do not support
932 * saving. However, xcr0 bit 0 is always set, even if the
933 * emulated CPU does not support XSAVE (see fx_init).
935 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
936 if (xcr0 & ~valid_bits)
939 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
940 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
943 if (xcr0 & XFEATURE_MASK_AVX512) {
944 if (!(xcr0 & XFEATURE_MASK_YMM))
946 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
949 vcpu->arch.xcr0 = xcr0;
951 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
952 kvm_update_cpuid_runtime(vcpu);
956 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
958 if (kvm_x86_ops.get_cpl(vcpu) != 0 ||
959 __kvm_set_xcr(vcpu, index, xcr)) {
960 kvm_inject_gp(vcpu, 0);
965 EXPORT_SYMBOL_GPL(kvm_set_xcr);
967 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
969 if (cr4 & cr4_reserved_bits)
972 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
975 return kvm_x86_ops.is_valid_cr4(vcpu, cr4);
977 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
979 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
981 unsigned long old_cr4 = kvm_read_cr4(vcpu);
982 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
984 unsigned long mmu_role_bits = pdptr_bits | X86_CR4_SMAP | X86_CR4_PKE;
986 if (!kvm_is_valid_cr4(vcpu, cr4))
989 if (is_long_mode(vcpu)) {
990 if (!(cr4 & X86_CR4_PAE))
992 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
994 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
995 && ((cr4 ^ old_cr4) & pdptr_bits)
996 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
1000 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1001 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1004 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1005 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1009 kvm_x86_ops.set_cr4(vcpu, cr4);
1011 if (((cr4 ^ old_cr4) & mmu_role_bits) ||
1012 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1013 kvm_mmu_reset_context(vcpu);
1017 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1019 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1021 bool skip_tlb_flush = false;
1022 #ifdef CONFIG_X86_64
1023 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1026 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1027 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1031 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
1032 if (!skip_tlb_flush) {
1033 kvm_mmu_sync_roots(vcpu);
1034 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1039 if (is_long_mode(vcpu) &&
1040 (cr3 & vcpu->arch.cr3_lm_rsvd_bits))
1042 else if (is_pae_paging(vcpu) &&
1043 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
1046 kvm_mmu_new_pgd(vcpu, cr3, skip_tlb_flush, skip_tlb_flush);
1047 vcpu->arch.cr3 = cr3;
1048 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
1052 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1054 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1056 if (cr8 & CR8_RESERVED_BITS)
1058 if (lapic_in_kernel(vcpu))
1059 kvm_lapic_set_tpr(vcpu, cr8);
1061 vcpu->arch.cr8 = cr8;
1064 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1066 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1068 if (lapic_in_kernel(vcpu))
1069 return kvm_lapic_get_cr8(vcpu);
1071 return vcpu->arch.cr8;
1073 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1075 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1079 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1080 for (i = 0; i < KVM_NR_DB_REGS; i++)
1081 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1082 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1086 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1090 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1091 dr7 = vcpu->arch.guest_debug_dr7;
1093 dr7 = vcpu->arch.dr7;
1094 kvm_x86_ops.set_dr7(vcpu, dr7);
1095 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1096 if (dr7 & DR7_BP_EN_MASK)
1097 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1099 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1101 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1103 u64 fixed = DR6_FIXED_1;
1105 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1110 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1112 size_t size = ARRAY_SIZE(vcpu->arch.db);
1116 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1117 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1118 vcpu->arch.eff_db[dr] = val;
1122 if (!kvm_dr6_valid(val))
1123 return -1; /* #GP */
1124 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1128 if (!kvm_dr7_valid(val))
1129 return -1; /* #GP */
1130 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1131 kvm_update_dr7(vcpu);
1138 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1140 if (__kvm_set_dr(vcpu, dr, val)) {
1141 kvm_inject_gp(vcpu, 0);
1146 EXPORT_SYMBOL_GPL(kvm_set_dr);
1148 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1150 size_t size = ARRAY_SIZE(vcpu->arch.db);
1154 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1158 *val = vcpu->arch.dr6;
1162 *val = vcpu->arch.dr7;
1167 EXPORT_SYMBOL_GPL(kvm_get_dr);
1169 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1171 u32 ecx = kvm_rcx_read(vcpu);
1175 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
1178 kvm_rax_write(vcpu, (u32)data);
1179 kvm_rdx_write(vcpu, data >> 32);
1182 EXPORT_SYMBOL_GPL(kvm_rdpmc);
1185 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1186 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1188 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1189 * extract the supported MSRs from the related const lists.
1190 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1191 * capabilities of the host cpu. This capabilities test skips MSRs that are
1192 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1193 * may depend on host virtualization features rather than host cpu features.
1196 static const u32 msrs_to_save_all[] = {
1197 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1199 #ifdef CONFIG_X86_64
1200 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1202 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1203 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1205 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1206 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1207 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1208 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1209 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1210 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1211 MSR_IA32_UMWAIT_CONTROL,
1213 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1214 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1215 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1216 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1217 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1218 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1219 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1220 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1221 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1222 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1223 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1224 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1225 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1226 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1227 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1228 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1229 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1230 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1231 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1232 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1233 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1234 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1237 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1238 static unsigned num_msrs_to_save;
1240 static const u32 emulated_msrs_all[] = {
1241 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1242 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1243 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1244 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1245 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1246 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1247 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1249 HV_X64_MSR_VP_INDEX,
1250 HV_X64_MSR_VP_RUNTIME,
1251 HV_X64_MSR_SCONTROL,
1252 HV_X64_MSR_STIMER0_CONFIG,
1253 HV_X64_MSR_VP_ASSIST_PAGE,
1254 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1255 HV_X64_MSR_TSC_EMULATION_STATUS,
1256 HV_X64_MSR_SYNDBG_OPTIONS,
1257 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1258 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1259 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1261 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1262 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1264 MSR_IA32_TSC_ADJUST,
1265 MSR_IA32_TSCDEADLINE,
1266 MSR_IA32_ARCH_CAPABILITIES,
1267 MSR_IA32_PERF_CAPABILITIES,
1268 MSR_IA32_MISC_ENABLE,
1269 MSR_IA32_MCG_STATUS,
1271 MSR_IA32_MCG_EXT_CTL,
1275 MSR_MISC_FEATURES_ENABLES,
1276 MSR_AMD64_VIRT_SPEC_CTRL,
1281 * The following list leaves out MSRs whose values are determined
1282 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1283 * We always support the "true" VMX control MSRs, even if the host
1284 * processor does not, so I am putting these registers here rather
1285 * than in msrs_to_save_all.
1288 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1289 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1290 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1291 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1293 MSR_IA32_VMX_CR0_FIXED0,
1294 MSR_IA32_VMX_CR4_FIXED0,
1295 MSR_IA32_VMX_VMCS_ENUM,
1296 MSR_IA32_VMX_PROCBASED_CTLS2,
1297 MSR_IA32_VMX_EPT_VPID_CAP,
1298 MSR_IA32_VMX_VMFUNC,
1301 MSR_KVM_POLL_CONTROL,
1304 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1305 static unsigned num_emulated_msrs;
1308 * List of msr numbers which are used to expose MSR-based features that
1309 * can be used by a hypervisor to validate requested CPU features.
1311 static const u32 msr_based_features_all[] = {
1313 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1314 MSR_IA32_VMX_PINBASED_CTLS,
1315 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1316 MSR_IA32_VMX_PROCBASED_CTLS,
1317 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1318 MSR_IA32_VMX_EXIT_CTLS,
1319 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1320 MSR_IA32_VMX_ENTRY_CTLS,
1322 MSR_IA32_VMX_CR0_FIXED0,
1323 MSR_IA32_VMX_CR0_FIXED1,
1324 MSR_IA32_VMX_CR4_FIXED0,
1325 MSR_IA32_VMX_CR4_FIXED1,
1326 MSR_IA32_VMX_VMCS_ENUM,
1327 MSR_IA32_VMX_PROCBASED_CTLS2,
1328 MSR_IA32_VMX_EPT_VPID_CAP,
1329 MSR_IA32_VMX_VMFUNC,
1333 MSR_IA32_ARCH_CAPABILITIES,
1334 MSR_IA32_PERF_CAPABILITIES,
1337 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1338 static unsigned int num_msr_based_features;
1340 static u64 kvm_get_arch_capabilities(void)
1344 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1345 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1348 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1349 * the nested hypervisor runs with NX huge pages. If it is not,
1350 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1351 * L1 guests, so it need not worry about its own (L2) guests.
1353 data |= ARCH_CAP_PSCHANGE_MC_NO;
1356 * If we're doing cache flushes (either "always" or "cond")
1357 * we will do one whenever the guest does a vmlaunch/vmresume.
1358 * If an outer hypervisor is doing the cache flush for us
1359 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1360 * capability to the guest too, and if EPT is disabled we're not
1361 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1362 * require a nested hypervisor to do a flush of its own.
1364 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1365 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1367 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1368 data |= ARCH_CAP_RDCL_NO;
1369 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1370 data |= ARCH_CAP_SSB_NO;
1371 if (!boot_cpu_has_bug(X86_BUG_MDS))
1372 data |= ARCH_CAP_MDS_NO;
1375 * On TAA affected systems:
1376 * - nothing to do if TSX is disabled on the host.
1377 * - we emulate TSX_CTRL if present on the host.
1378 * This lets the guest use VERW to clear CPU buffers.
1380 if (!boot_cpu_has(X86_FEATURE_RTM))
1381 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
1382 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1383 data |= ARCH_CAP_TAA_NO;
1388 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1390 switch (msr->index) {
1391 case MSR_IA32_ARCH_CAPABILITIES:
1392 msr->data = kvm_get_arch_capabilities();
1394 case MSR_IA32_UCODE_REV:
1395 rdmsrl_safe(msr->index, &msr->data);
1398 return kvm_x86_ops.get_msr_feature(msr);
1403 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1405 struct kvm_msr_entry msr;
1409 r = kvm_get_msr_feature(&msr);
1411 if (r == KVM_MSR_RET_INVALID) {
1412 /* Unconditionally clear the output for simplicity */
1414 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1426 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1428 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1431 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1434 if (efer & (EFER_LME | EFER_LMA) &&
1435 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1438 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1444 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1446 if (efer & efer_reserved_bits)
1449 return __kvm_valid_efer(vcpu, efer);
1451 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1453 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1455 u64 old_efer = vcpu->arch.efer;
1456 u64 efer = msr_info->data;
1459 if (efer & efer_reserved_bits)
1462 if (!msr_info->host_initiated) {
1463 if (!__kvm_valid_efer(vcpu, efer))
1466 if (is_paging(vcpu) &&
1467 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1472 efer |= vcpu->arch.efer & EFER_LMA;
1474 r = kvm_x86_ops.set_efer(vcpu, efer);
1480 /* Update reserved bits */
1481 if ((efer ^ old_efer) & EFER_NX)
1482 kvm_mmu_reset_context(vcpu);
1487 void kvm_enable_efer_bits(u64 mask)
1489 efer_reserved_bits &= ~mask;
1491 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1493 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1495 struct kvm *kvm = vcpu->kvm;
1496 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
1497 u32 count = kvm->arch.msr_filter.count;
1499 bool r = kvm->arch.msr_filter.default_allow;
1502 /* MSR filtering not set up or x2APIC enabled, allow everything */
1503 if (!count || (index >= 0x800 && index <= 0x8ff))
1506 /* Prevent collision with set_msr_filter */
1507 idx = srcu_read_lock(&kvm->srcu);
1509 for (i = 0; i < count; i++) {
1510 u32 start = ranges[i].base;
1511 u32 end = start + ranges[i].nmsrs;
1512 u32 flags = ranges[i].flags;
1513 unsigned long *bitmap = ranges[i].bitmap;
1515 if ((index >= start) && (index < end) && (flags & type)) {
1516 r = !!test_bit(index - start, bitmap);
1521 srcu_read_unlock(&kvm->srcu, idx);
1525 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1528 * Write @data into the MSR specified by @index. Select MSR specific fault
1529 * checks are bypassed if @host_initiated is %true.
1530 * Returns 0 on success, non-0 otherwise.
1531 * Assumes vcpu_load() was already called.
1533 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1534 bool host_initiated)
1536 struct msr_data msr;
1538 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1539 return KVM_MSR_RET_FILTERED;
1544 case MSR_KERNEL_GS_BASE:
1547 if (is_noncanonical_address(data, vcpu))
1550 case MSR_IA32_SYSENTER_EIP:
1551 case MSR_IA32_SYSENTER_ESP:
1553 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1554 * non-canonical address is written on Intel but not on
1555 * AMD (which ignores the top 32-bits, because it does
1556 * not implement 64-bit SYSENTER).
1558 * 64-bit code should hence be able to write a non-canonical
1559 * value on AMD. Making the address canonical ensures that
1560 * vmentry does not fail on Intel after writing a non-canonical
1561 * value, and that something deterministic happens if the guest
1562 * invokes 64-bit SYSENTER.
1564 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1569 msr.host_initiated = host_initiated;
1571 return kvm_x86_ops.set_msr(vcpu, &msr);
1574 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1575 u32 index, u64 data, bool host_initiated)
1577 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1579 if (ret == KVM_MSR_RET_INVALID)
1580 if (kvm_msr_ignored_check(vcpu, index, data, true))
1587 * Read the MSR specified by @index into @data. Select MSR specific fault
1588 * checks are bypassed if @host_initiated is %true.
1589 * Returns 0 on success, non-0 otherwise.
1590 * Assumes vcpu_load() was already called.
1592 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1593 bool host_initiated)
1595 struct msr_data msr;
1598 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1599 return KVM_MSR_RET_FILTERED;
1602 msr.host_initiated = host_initiated;
1604 ret = kvm_x86_ops.get_msr(vcpu, &msr);
1610 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1611 u32 index, u64 *data, bool host_initiated)
1613 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1615 if (ret == KVM_MSR_RET_INVALID) {
1616 /* Unconditionally clear *data for simplicity */
1618 if (kvm_msr_ignored_check(vcpu, index, 0, false))
1625 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1627 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1629 EXPORT_SYMBOL_GPL(kvm_get_msr);
1631 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1633 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1635 EXPORT_SYMBOL_GPL(kvm_set_msr);
1637 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1639 int err = vcpu->run->msr.error;
1641 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1642 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1645 return kvm_x86_ops.complete_emulated_msr(vcpu, err);
1648 static int complete_emulated_wrmsr(struct kvm_vcpu *vcpu)
1650 return kvm_x86_ops.complete_emulated_msr(vcpu, vcpu->run->msr.error);
1653 static u64 kvm_msr_reason(int r)
1656 case KVM_MSR_RET_INVALID:
1657 return KVM_MSR_EXIT_REASON_UNKNOWN;
1658 case KVM_MSR_RET_FILTERED:
1659 return KVM_MSR_EXIT_REASON_FILTER;
1661 return KVM_MSR_EXIT_REASON_INVAL;
1665 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1666 u32 exit_reason, u64 data,
1667 int (*completion)(struct kvm_vcpu *vcpu),
1670 u64 msr_reason = kvm_msr_reason(r);
1672 /* Check if the user wanted to know about this MSR fault */
1673 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1676 vcpu->run->exit_reason = exit_reason;
1677 vcpu->run->msr.error = 0;
1678 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1679 vcpu->run->msr.reason = msr_reason;
1680 vcpu->run->msr.index = index;
1681 vcpu->run->msr.data = data;
1682 vcpu->arch.complete_userspace_io = completion;
1687 static int kvm_get_msr_user_space(struct kvm_vcpu *vcpu, u32 index, int r)
1689 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_RDMSR, 0,
1690 complete_emulated_rdmsr, r);
1693 static int kvm_set_msr_user_space(struct kvm_vcpu *vcpu, u32 index, u64 data, int r)
1695 return kvm_msr_user_space(vcpu, index, KVM_EXIT_X86_WRMSR, data,
1696 complete_emulated_wrmsr, r);
1699 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1701 u32 ecx = kvm_rcx_read(vcpu);
1705 r = kvm_get_msr(vcpu, ecx, &data);
1707 /* MSR read failed? See if we should ask user space */
1708 if (r && kvm_get_msr_user_space(vcpu, ecx, r)) {
1709 /* Bounce to user space */
1714 trace_kvm_msr_read(ecx, data);
1716 kvm_rax_write(vcpu, data & -1u);
1717 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1719 trace_kvm_msr_read_ex(ecx);
1722 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1724 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1726 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1728 u32 ecx = kvm_rcx_read(vcpu);
1729 u64 data = kvm_read_edx_eax(vcpu);
1732 r = kvm_set_msr(vcpu, ecx, data);
1734 /* MSR write failed? See if we should ask user space */
1735 if (r && kvm_set_msr_user_space(vcpu, ecx, data, r))
1736 /* Bounce to user space */
1739 /* Signal all other negative errors to userspace */
1744 trace_kvm_msr_write(ecx, data);
1746 trace_kvm_msr_write_ex(ecx, data);
1748 return kvm_x86_ops.complete_emulated_msr(vcpu, r);
1750 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1752 bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
1754 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
1755 xfer_to_guest_mode_work_pending();
1757 EXPORT_SYMBOL_GPL(kvm_vcpu_exit_request);
1760 * The fast path for frequent and performance sensitive wrmsr emulation,
1761 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1762 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1763 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1764 * other cases which must be called after interrupts are enabled on the host.
1766 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1768 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
1771 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
1772 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1773 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
1774 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
1777 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
1778 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1779 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
1780 trace_kvm_apic_write(APIC_ICR, (u32)data);
1787 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
1789 if (!kvm_can_use_hv_timer(vcpu))
1792 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1796 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1798 u32 msr = kvm_rcx_read(vcpu);
1800 fastpath_t ret = EXIT_FASTPATH_NONE;
1803 case APIC_BASE_MSR + (APIC_ICR >> 4):
1804 data = kvm_read_edx_eax(vcpu);
1805 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
1806 kvm_skip_emulated_instruction(vcpu);
1807 ret = EXIT_FASTPATH_EXIT_HANDLED;
1810 case MSR_IA32_TSCDEADLINE:
1811 data = kvm_read_edx_eax(vcpu);
1812 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
1813 kvm_skip_emulated_instruction(vcpu);
1814 ret = EXIT_FASTPATH_REENTER_GUEST;
1821 if (ret != EXIT_FASTPATH_NONE)
1822 trace_kvm_msr_write(msr, data);
1826 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1829 * Adapt set_msr() to msr_io()'s calling convention
1831 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1833 return kvm_get_msr_ignored_check(vcpu, index, data, true);
1836 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1838 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
1841 #ifdef CONFIG_X86_64
1842 struct pvclock_clock {
1852 struct pvclock_gtod_data {
1855 struct pvclock_clock clock; /* extract of a clocksource struct */
1856 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
1862 static struct pvclock_gtod_data pvclock_gtod_data;
1864 static void update_pvclock_gtod(struct timekeeper *tk)
1866 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1868 write_seqcount_begin(&vdata->seq);
1870 /* copy pvclock gtod data */
1871 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
1872 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1873 vdata->clock.mask = tk->tkr_mono.mask;
1874 vdata->clock.mult = tk->tkr_mono.mult;
1875 vdata->clock.shift = tk->tkr_mono.shift;
1876 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
1877 vdata->clock.offset = tk->tkr_mono.base;
1879 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
1880 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1881 vdata->raw_clock.mask = tk->tkr_raw.mask;
1882 vdata->raw_clock.mult = tk->tkr_raw.mult;
1883 vdata->raw_clock.shift = tk->tkr_raw.shift;
1884 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
1885 vdata->raw_clock.offset = tk->tkr_raw.base;
1887 vdata->wall_time_sec = tk->xtime_sec;
1889 vdata->offs_boot = tk->offs_boot;
1891 write_seqcount_end(&vdata->seq);
1894 static s64 get_kvmclock_base_ns(void)
1896 /* Count up from boot time, but with the frequency of the raw clock. */
1897 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
1900 static s64 get_kvmclock_base_ns(void)
1902 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
1903 return ktime_get_boottime_ns();
1907 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1911 struct pvclock_wall_clock wc;
1914 kvm->arch.wall_clock = wall_clock;
1919 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1924 ++version; /* first time write, random junk */
1928 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1932 * The guest calculates current wall clock time by adding
1933 * system time (updated by kvm_guest_time_update below) to the
1934 * wall clock specified here. We do the reverse here.
1936 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
1938 wc.nsec = do_div(wall_nsec, 1000000000);
1939 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
1940 wc.version = version;
1942 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1945 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1948 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
1949 bool old_msr, bool host_initiated)
1951 struct kvm_arch *ka = &vcpu->kvm->arch;
1953 if (vcpu->vcpu_id == 0 && !host_initiated) {
1954 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
1955 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1957 ka->boot_vcpu_runs_old_kvmclock = old_msr;
1960 vcpu->arch.time = system_time;
1961 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
1963 /* we verify if the enable bit is set... */
1964 vcpu->arch.pv_time_enabled = false;
1965 if (!(system_time & 1))
1968 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
1969 &vcpu->arch.pv_time, system_time & ~1ULL,
1970 sizeof(struct pvclock_vcpu_time_info)))
1971 vcpu->arch.pv_time_enabled = true;
1976 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1978 do_shl32_div32(dividend, divisor);
1982 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
1983 s8 *pshift, u32 *pmultiplier)
1991 scaled64 = scaled_hz;
1992 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1997 tps32 = (uint32_t)tps64;
1998 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1999 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2007 *pmultiplier = div_frac(scaled64, tps32);
2010 #ifdef CONFIG_X86_64
2011 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2014 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2015 static unsigned long max_tsc_khz;
2017 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2019 u64 v = (u64)khz * (1000000 + ppm);
2024 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2028 /* Guest TSC same frequency as host TSC? */
2030 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2034 /* TSC scaling supported? */
2035 if (!kvm_has_tsc_control) {
2036 if (user_tsc_khz > tsc_khz) {
2037 vcpu->arch.tsc_catchup = 1;
2038 vcpu->arch.tsc_always_catchup = 1;
2041 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2046 /* TSC scaling required - calculate ratio */
2047 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2048 user_tsc_khz, tsc_khz);
2050 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2051 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2056 vcpu->arch.tsc_scaling_ratio = ratio;
2060 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2062 u32 thresh_lo, thresh_hi;
2063 int use_scaling = 0;
2065 /* tsc_khz can be zero if TSC calibration fails */
2066 if (user_tsc_khz == 0) {
2067 /* set tsc_scaling_ratio to a safe value */
2068 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
2072 /* Compute a scale to convert nanoseconds in TSC cycles */
2073 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2074 &vcpu->arch.virtual_tsc_shift,
2075 &vcpu->arch.virtual_tsc_mult);
2076 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2079 * Compute the variation in TSC rate which is acceptable
2080 * within the range of tolerance and decide if the
2081 * rate being applied is within that bounds of the hardware
2082 * rate. If so, no scaling or compensation need be done.
2084 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2085 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2086 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2087 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2090 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2093 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2095 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2096 vcpu->arch.virtual_tsc_mult,
2097 vcpu->arch.virtual_tsc_shift);
2098 tsc += vcpu->arch.this_tsc_write;
2102 static inline int gtod_is_based_on_tsc(int mode)
2104 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2107 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2109 #ifdef CONFIG_X86_64
2111 struct kvm_arch *ka = &vcpu->kvm->arch;
2112 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2114 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2115 atomic_read(&vcpu->kvm->online_vcpus));
2118 * Once the masterclock is enabled, always perform request in
2119 * order to update it.
2121 * In order to enable masterclock, the host clocksource must be TSC
2122 * and the vcpus need to have matched TSCs. When that happens,
2123 * perform request to enable masterclock.
2125 if (ka->use_master_clock ||
2126 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2127 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2129 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2130 atomic_read(&vcpu->kvm->online_vcpus),
2131 ka->use_master_clock, gtod->clock.vclock_mode);
2136 * Multiply tsc by a fixed point number represented by ratio.
2138 * The most significant 64-N bits (mult) of ratio represent the
2139 * integral part of the fixed point number; the remaining N bits
2140 * (frac) represent the fractional part, ie. ratio represents a fixed
2141 * point number (mult + frac * 2^(-N)).
2143 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2145 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2147 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2150 u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
2153 u64 ratio = vcpu->arch.tsc_scaling_ratio;
2155 if (ratio != kvm_default_tsc_scaling_ratio)
2156 _tsc = __scale_tsc(ratio, tsc);
2160 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2162 static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2166 tsc = kvm_scale_tsc(vcpu, rdtsc());
2168 return target_tsc - tsc;
2171 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2173 return vcpu->arch.l1_tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
2175 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2177 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2179 vcpu->arch.l1_tsc_offset = offset;
2180 vcpu->arch.tsc_offset = kvm_x86_ops.write_l1_tsc_offset(vcpu, offset);
2183 static inline bool kvm_check_tsc_unstable(void)
2185 #ifdef CONFIG_X86_64
2187 * TSC is marked unstable when we're running on Hyper-V,
2188 * 'TSC page' clocksource is good.
2190 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2193 return check_tsc_unstable();
2196 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2198 struct kvm *kvm = vcpu->kvm;
2199 u64 offset, ns, elapsed;
2200 unsigned long flags;
2202 bool already_matched;
2203 bool synchronizing = false;
2205 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2206 offset = kvm_compute_tsc_offset(vcpu, data);
2207 ns = get_kvmclock_base_ns();
2208 elapsed = ns - kvm->arch.last_tsc_nsec;
2210 if (vcpu->arch.virtual_tsc_khz) {
2213 * detection of vcpu initialization -- need to sync
2214 * with other vCPUs. This particularly helps to keep
2215 * kvm_clock stable after CPU hotplug
2217 synchronizing = true;
2219 u64 tsc_exp = kvm->arch.last_tsc_write +
2220 nsec_to_cycles(vcpu, elapsed);
2221 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2223 * Special case: TSC write with a small delta (1 second)
2224 * of virtual cycle time against real time is
2225 * interpreted as an attempt to synchronize the CPU.
2227 synchronizing = data < tsc_exp + tsc_hz &&
2228 data + tsc_hz > tsc_exp;
2233 * For a reliable TSC, we can match TSC offsets, and for an unstable
2234 * TSC, we add elapsed time in this computation. We could let the
2235 * compensation code attempt to catch up if we fall behind, but
2236 * it's better to try to match offsets from the beginning.
2238 if (synchronizing &&
2239 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2240 if (!kvm_check_tsc_unstable()) {
2241 offset = kvm->arch.cur_tsc_offset;
2243 u64 delta = nsec_to_cycles(vcpu, elapsed);
2245 offset = kvm_compute_tsc_offset(vcpu, data);
2248 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
2251 * We split periods of matched TSC writes into generations.
2252 * For each generation, we track the original measured
2253 * nanosecond time, offset, and write, so if TSCs are in
2254 * sync, we can match exact offset, and if not, we can match
2255 * exact software computation in compute_guest_tsc()
2257 * These values are tracked in kvm->arch.cur_xxx variables.
2259 kvm->arch.cur_tsc_generation++;
2260 kvm->arch.cur_tsc_nsec = ns;
2261 kvm->arch.cur_tsc_write = data;
2262 kvm->arch.cur_tsc_offset = offset;
2267 * We also track th most recent recorded KHZ, write and time to
2268 * allow the matching interval to be extended at each write.
2270 kvm->arch.last_tsc_nsec = ns;
2271 kvm->arch.last_tsc_write = data;
2272 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2274 vcpu->arch.last_guest_tsc = data;
2276 /* Keep track of which generation this VCPU has synchronized to */
2277 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2278 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2279 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2281 kvm_vcpu_write_tsc_offset(vcpu, offset);
2282 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2284 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
2286 kvm->arch.nr_vcpus_matched_tsc = 0;
2287 } else if (!already_matched) {
2288 kvm->arch.nr_vcpus_matched_tsc++;
2291 kvm_track_tsc_matching(vcpu);
2292 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
2295 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2298 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2299 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2302 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2304 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2305 WARN_ON(adjustment < 0);
2306 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
2307 adjust_tsc_offset_guest(vcpu, adjustment);
2310 #ifdef CONFIG_X86_64
2312 static u64 read_tsc(void)
2314 u64 ret = (u64)rdtsc_ordered();
2315 u64 last = pvclock_gtod_data.clock.cycle_last;
2317 if (likely(ret >= last))
2321 * GCC likes to generate cmov here, but this branch is extremely
2322 * predictable (it's just a function of time and the likely is
2323 * very likely) and there's a data dependence, so force GCC
2324 * to generate a branch instead. I don't barrier() because
2325 * we don't actually need a barrier, and if this function
2326 * ever gets inlined it will generate worse code.
2332 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2338 switch (clock->vclock_mode) {
2339 case VDSO_CLOCKMODE_HVCLOCK:
2340 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2342 if (tsc_pg_val != U64_MAX) {
2343 /* TSC page valid */
2344 *mode = VDSO_CLOCKMODE_HVCLOCK;
2345 v = (tsc_pg_val - clock->cycle_last) &
2348 /* TSC page invalid */
2349 *mode = VDSO_CLOCKMODE_NONE;
2352 case VDSO_CLOCKMODE_TSC:
2353 *mode = VDSO_CLOCKMODE_TSC;
2354 *tsc_timestamp = read_tsc();
2355 v = (*tsc_timestamp - clock->cycle_last) &
2359 *mode = VDSO_CLOCKMODE_NONE;
2362 if (*mode == VDSO_CLOCKMODE_NONE)
2363 *tsc_timestamp = v = 0;
2365 return v * clock->mult;
2368 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2370 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2376 seq = read_seqcount_begin(>od->seq);
2377 ns = gtod->raw_clock.base_cycles;
2378 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2379 ns >>= gtod->raw_clock.shift;
2380 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2381 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2387 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2389 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2395 seq = read_seqcount_begin(>od->seq);
2396 ts->tv_sec = gtod->wall_time_sec;
2397 ns = gtod->clock.base_cycles;
2398 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2399 ns >>= gtod->clock.shift;
2400 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2402 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2408 /* returns true if host is using TSC based clocksource */
2409 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2411 /* checked again under seqlock below */
2412 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2415 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2419 /* returns true if host is using TSC based clocksource */
2420 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2423 /* checked again under seqlock below */
2424 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2427 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2433 * Assuming a stable TSC across physical CPUS, and a stable TSC
2434 * across virtual CPUs, the following condition is possible.
2435 * Each numbered line represents an event visible to both
2436 * CPUs at the next numbered event.
2438 * "timespecX" represents host monotonic time. "tscX" represents
2441 * VCPU0 on CPU0 | VCPU1 on CPU1
2443 * 1. read timespec0,tsc0
2444 * 2. | timespec1 = timespec0 + N
2446 * 3. transition to guest | transition to guest
2447 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2448 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2449 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2451 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2454 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2456 * - 0 < N - M => M < N
2458 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2459 * always the case (the difference between two distinct xtime instances
2460 * might be smaller then the difference between corresponding TSC reads,
2461 * when updating guest vcpus pvclock areas).
2463 * To avoid that problem, do not allow visibility of distinct
2464 * system_timestamp/tsc_timestamp values simultaneously: use a master
2465 * copy of host monotonic time values. Update that master copy
2468 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2472 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2474 #ifdef CONFIG_X86_64
2475 struct kvm_arch *ka = &kvm->arch;
2477 bool host_tsc_clocksource, vcpus_matched;
2479 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2480 atomic_read(&kvm->online_vcpus));
2483 * If the host uses TSC clock, then passthrough TSC as stable
2486 host_tsc_clocksource = kvm_get_time_and_clockread(
2487 &ka->master_kernel_ns,
2488 &ka->master_cycle_now);
2490 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2491 && !ka->backwards_tsc_observed
2492 && !ka->boot_vcpu_runs_old_kvmclock;
2494 if (ka->use_master_clock)
2495 atomic_set(&kvm_guest_has_master_clock, 1);
2497 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2498 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2503 void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2505 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2508 static void kvm_gen_update_masterclock(struct kvm *kvm)
2510 #ifdef CONFIG_X86_64
2512 struct kvm_vcpu *vcpu;
2513 struct kvm_arch *ka = &kvm->arch;
2515 spin_lock(&ka->pvclock_gtod_sync_lock);
2516 kvm_make_mclock_inprogress_request(kvm);
2517 /* no guest entries from this point */
2518 pvclock_update_vm_gtod_copy(kvm);
2520 kvm_for_each_vcpu(i, vcpu, kvm)
2521 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2523 /* guest entries allowed */
2524 kvm_for_each_vcpu(i, vcpu, kvm)
2525 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2527 spin_unlock(&ka->pvclock_gtod_sync_lock);
2531 u64 get_kvmclock_ns(struct kvm *kvm)
2533 struct kvm_arch *ka = &kvm->arch;
2534 struct pvclock_vcpu_time_info hv_clock;
2537 spin_lock(&ka->pvclock_gtod_sync_lock);
2538 if (!ka->use_master_clock) {
2539 spin_unlock(&ka->pvclock_gtod_sync_lock);
2540 return get_kvmclock_base_ns() + ka->kvmclock_offset;
2543 hv_clock.tsc_timestamp = ka->master_cycle_now;
2544 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2545 spin_unlock(&ka->pvclock_gtod_sync_lock);
2547 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2550 if (__this_cpu_read(cpu_tsc_khz)) {
2551 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2552 &hv_clock.tsc_shift,
2553 &hv_clock.tsc_to_system_mul);
2554 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2556 ret = get_kvmclock_base_ns() + ka->kvmclock_offset;
2563 static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2565 struct kvm_vcpu_arch *vcpu = &v->arch;
2566 struct pvclock_vcpu_time_info guest_hv_clock;
2568 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
2569 &guest_hv_clock, sizeof(guest_hv_clock))))
2572 /* This VCPU is paused, but it's legal for a guest to read another
2573 * VCPU's kvmclock, so we really have to follow the specification where
2574 * it says that version is odd if data is being modified, and even after
2577 * Version field updates must be kept separate. This is because
2578 * kvm_write_guest_cached might use a "rep movs" instruction, and
2579 * writes within a string instruction are weakly ordered. So there
2580 * are three writes overall.
2582 * As a small optimization, only write the version field in the first
2583 * and third write. The vcpu->pv_time cache is still valid, because the
2584 * version field is the first in the struct.
2586 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2588 if (guest_hv_clock.version & 1)
2589 ++guest_hv_clock.version; /* first time write, random junk */
2591 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2592 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2594 sizeof(vcpu->hv_clock.version));
2598 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2599 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2601 if (vcpu->pvclock_set_guest_stopped_request) {
2602 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2603 vcpu->pvclock_set_guest_stopped_request = false;
2606 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2608 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2610 sizeof(vcpu->hv_clock));
2614 vcpu->hv_clock.version++;
2615 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2617 sizeof(vcpu->hv_clock.version));
2620 static int kvm_guest_time_update(struct kvm_vcpu *v)
2622 unsigned long flags, tgt_tsc_khz;
2623 struct kvm_vcpu_arch *vcpu = &v->arch;
2624 struct kvm_arch *ka = &v->kvm->arch;
2626 u64 tsc_timestamp, host_tsc;
2628 bool use_master_clock;
2634 * If the host uses TSC clock, then passthrough TSC as stable
2637 spin_lock(&ka->pvclock_gtod_sync_lock);
2638 use_master_clock = ka->use_master_clock;
2639 if (use_master_clock) {
2640 host_tsc = ka->master_cycle_now;
2641 kernel_ns = ka->master_kernel_ns;
2643 spin_unlock(&ka->pvclock_gtod_sync_lock);
2645 /* Keep irq disabled to prevent changes to the clock */
2646 local_irq_save(flags);
2647 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2648 if (unlikely(tgt_tsc_khz == 0)) {
2649 local_irq_restore(flags);
2650 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2653 if (!use_master_clock) {
2655 kernel_ns = get_kvmclock_base_ns();
2658 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
2661 * We may have to catch up the TSC to match elapsed wall clock
2662 * time for two reasons, even if kvmclock is used.
2663 * 1) CPU could have been running below the maximum TSC rate
2664 * 2) Broken TSC compensation resets the base at each VCPU
2665 * entry to avoid unknown leaps of TSC even when running
2666 * again on the same CPU. This may cause apparent elapsed
2667 * time to disappear, and the guest to stand still or run
2670 if (vcpu->tsc_catchup) {
2671 u64 tsc = compute_guest_tsc(v, kernel_ns);
2672 if (tsc > tsc_timestamp) {
2673 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
2674 tsc_timestamp = tsc;
2678 local_irq_restore(flags);
2680 /* With all the info we got, fill in the values */
2682 if (kvm_has_tsc_control)
2683 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2685 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
2686 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
2687 &vcpu->hv_clock.tsc_shift,
2688 &vcpu->hv_clock.tsc_to_system_mul);
2689 vcpu->hw_tsc_khz = tgt_tsc_khz;
2692 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
2693 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
2694 vcpu->last_guest_tsc = tsc_timestamp;
2696 /* If the host uses TSC clocksource, then it is stable */
2698 if (use_master_clock)
2699 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2701 vcpu->hv_clock.flags = pvclock_flags;
2703 if (vcpu->pv_time_enabled)
2704 kvm_setup_pvclock_page(v);
2705 if (v == kvm_get_vcpu(v->kvm, 0))
2706 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
2711 * kvmclock updates which are isolated to a given vcpu, such as
2712 * vcpu->cpu migration, should not allow system_timestamp from
2713 * the rest of the vcpus to remain static. Otherwise ntp frequency
2714 * correction applies to one vcpu's system_timestamp but not
2717 * So in those cases, request a kvmclock update for all vcpus.
2718 * We need to rate-limit these requests though, as they can
2719 * considerably slow guests that have a large number of vcpus.
2720 * The time for a remote vcpu to update its kvmclock is bound
2721 * by the delay we use to rate-limit the updates.
2724 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2726 static void kvmclock_update_fn(struct work_struct *work)
2729 struct delayed_work *dwork = to_delayed_work(work);
2730 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2731 kvmclock_update_work);
2732 struct kvm *kvm = container_of(ka, struct kvm, arch);
2733 struct kvm_vcpu *vcpu;
2735 kvm_for_each_vcpu(i, vcpu, kvm) {
2736 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2737 kvm_vcpu_kick(vcpu);
2741 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2743 struct kvm *kvm = v->kvm;
2745 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2746 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2747 KVMCLOCK_UPDATE_DELAY);
2750 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2752 static void kvmclock_sync_fn(struct work_struct *work)
2754 struct delayed_work *dwork = to_delayed_work(work);
2755 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2756 kvmclock_sync_work);
2757 struct kvm *kvm = container_of(ka, struct kvm, arch);
2759 if (!kvmclock_periodic_sync)
2762 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2763 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2764 KVMCLOCK_SYNC_PERIOD);
2768 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2770 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2772 /* McStatusWrEn enabled? */
2773 if (guest_cpuid_is_amd_or_hygon(vcpu))
2774 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2779 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2781 u64 mcg_cap = vcpu->arch.mcg_cap;
2782 unsigned bank_num = mcg_cap & 0xff;
2783 u32 msr = msr_info->index;
2784 u64 data = msr_info->data;
2787 case MSR_IA32_MCG_STATUS:
2788 vcpu->arch.mcg_status = data;
2790 case MSR_IA32_MCG_CTL:
2791 if (!(mcg_cap & MCG_CTL_P) &&
2792 (data || !msr_info->host_initiated))
2794 if (data != 0 && data != ~(u64)0)
2796 vcpu->arch.mcg_ctl = data;
2799 if (msr >= MSR_IA32_MC0_CTL &&
2800 msr < MSR_IA32_MCx_CTL(bank_num)) {
2801 u32 offset = array_index_nospec(
2802 msr - MSR_IA32_MC0_CTL,
2803 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2805 /* only 0 or all 1s can be written to IA32_MCi_CTL
2806 * some Linux kernels though clear bit 10 in bank 4 to
2807 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2808 * this to avoid an uncatched #GP in the guest
2810 if ((offset & 0x3) == 0 &&
2811 data != 0 && (data | (1 << 10)) != ~(u64)0)
2815 if (!msr_info->host_initiated &&
2816 (offset & 0x3) == 1 && data != 0) {
2817 if (!can_set_mci_status(vcpu))
2821 vcpu->arch.mce_banks[offset] = data;
2829 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2831 struct kvm *kvm = vcpu->kvm;
2832 int lm = is_long_mode(vcpu);
2833 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2834 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2835 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2836 : kvm->arch.xen_hvm_config.blob_size_32;
2837 u32 page_num = data & ~PAGE_MASK;
2838 u64 page_addr = data & PAGE_MASK;
2841 if (page_num >= blob_size)
2844 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2846 return PTR_ERR(page);
2848 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE)) {
2855 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
2857 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
2859 return (vcpu->arch.apf.msr_en_val & mask) == mask;
2862 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2864 gpa_t gpa = data & ~0x3f;
2866 /* Bits 4:5 are reserved, Should be zero */
2870 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
2871 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
2874 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
2875 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
2878 if (!lapic_in_kernel(vcpu))
2879 return data ? 1 : 0;
2881 vcpu->arch.apf.msr_en_val = data;
2883 if (!kvm_pv_async_pf_enabled(vcpu)) {
2884 kvm_clear_async_pf_completion_queue(vcpu);
2885 kvm_async_pf_hash_reset(vcpu);
2889 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2893 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
2894 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
2896 kvm_async_pf_wakeup_all(vcpu);
2901 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
2903 /* Bits 8-63 are reserved */
2907 if (!lapic_in_kernel(vcpu))
2910 vcpu->arch.apf.msr_int_val = data;
2912 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
2917 static void kvmclock_reset(struct kvm_vcpu *vcpu)
2919 vcpu->arch.pv_time_enabled = false;
2920 vcpu->arch.time = 0;
2923 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
2925 ++vcpu->stat.tlb_flush;
2926 kvm_x86_ops.tlb_flush_all(vcpu);
2929 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
2931 ++vcpu->stat.tlb_flush;
2932 kvm_x86_ops.tlb_flush_guest(vcpu);
2935 static void record_steal_time(struct kvm_vcpu *vcpu)
2937 struct kvm_host_map map;
2938 struct kvm_steal_time *st;
2940 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2943 /* -EAGAIN is returned in atomic context so we can just return. */
2944 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2945 &map, &vcpu->arch.st.cache, false))
2949 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2952 * Doing a TLB flush here, on the guest's behalf, can avoid
2955 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
2956 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2957 st->preempted & KVM_VCPU_FLUSH_TLB);
2958 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
2959 kvm_vcpu_flush_tlb_guest(vcpu);
2962 vcpu->arch.st.preempted = 0;
2964 if (st->version & 1)
2965 st->version += 1; /* first time write, random junk */
2971 st->steal += current->sched_info.run_delay -
2972 vcpu->arch.st.last_steal;
2973 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2979 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
2982 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2985 u32 msr = msr_info->index;
2986 u64 data = msr_info->data;
2989 case MSR_AMD64_NB_CFG:
2990 case MSR_IA32_UCODE_WRITE:
2991 case MSR_VM_HSAVE_PA:
2992 case MSR_AMD64_PATCH_LOADER:
2993 case MSR_AMD64_BU_CFG2:
2994 case MSR_AMD64_DC_CFG:
2995 case MSR_F15H_EX_CFG:
2998 case MSR_IA32_UCODE_REV:
2999 if (msr_info->host_initiated)
3000 vcpu->arch.microcode_version = data;
3002 case MSR_IA32_ARCH_CAPABILITIES:
3003 if (!msr_info->host_initiated)
3005 vcpu->arch.arch_capabilities = data;
3007 case MSR_IA32_PERF_CAPABILITIES: {
3008 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3010 if (!msr_info->host_initiated)
3012 if (guest_cpuid_has(vcpu, X86_FEATURE_PDCM) && kvm_get_msr_feature(&msr_ent))
3014 if (data & ~msr_ent.data)
3017 vcpu->arch.perf_capabilities = data;
3022 return set_efer(vcpu, msr_info);
3024 data &= ~(u64)0x40; /* ignore flush filter disable */
3025 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3026 data &= ~(u64)0x8; /* ignore TLB cache disable */
3028 /* Handle McStatusWrEn */
3029 if (data == BIT_ULL(18)) {
3030 vcpu->arch.msr_hwcr = data;
3031 } else if (data != 0) {
3032 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3037 case MSR_FAM10H_MMIO_CONF_BASE:
3039 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3044 case MSR_IA32_DEBUGCTLMSR:
3046 /* We support the non-activated case already */
3048 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
3049 /* Values other than LBR and BTF are vendor-specific,
3050 thus reserved and should throw a #GP */
3052 } else if (report_ignored_msrs)
3053 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
3056 case 0x200 ... 0x2ff:
3057 return kvm_mtrr_set_msr(vcpu, msr, data);
3058 case MSR_IA32_APICBASE:
3059 return kvm_set_apic_base(vcpu, msr_info);
3060 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3061 return kvm_x2apic_msr_write(vcpu, msr, data);
3062 case MSR_IA32_TSCDEADLINE:
3063 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3065 case MSR_IA32_TSC_ADJUST:
3066 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3067 if (!msr_info->host_initiated) {
3068 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3069 adjust_tsc_offset_guest(vcpu, adj);
3071 vcpu->arch.ia32_tsc_adjust_msr = data;
3074 case MSR_IA32_MISC_ENABLE:
3075 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3076 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3077 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3079 vcpu->arch.ia32_misc_enable_msr = data;
3080 kvm_update_cpuid_runtime(vcpu);
3082 vcpu->arch.ia32_misc_enable_msr = data;
3085 case MSR_IA32_SMBASE:
3086 if (!msr_info->host_initiated)
3088 vcpu->arch.smbase = data;
3090 case MSR_IA32_POWER_CTL:
3091 vcpu->arch.msr_ia32_power_ctl = data;
3094 if (msr_info->host_initiated) {
3095 kvm_synchronize_tsc(vcpu, data);
3097 u64 adj = kvm_compute_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3098 adjust_tsc_offset_guest(vcpu, adj);
3099 vcpu->arch.ia32_tsc_adjust_msr += adj;
3103 if (!msr_info->host_initiated &&
3104 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3107 * KVM supports exposing PT to the guest, but does not support
3108 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3109 * XSAVES/XRSTORS to save/restore PT MSRs.
3111 if (data & ~supported_xss)
3113 vcpu->arch.ia32_xss = data;
3116 if (!msr_info->host_initiated)
3118 vcpu->arch.smi_count = data;
3120 case MSR_KVM_WALL_CLOCK_NEW:
3121 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3124 kvm_write_wall_clock(vcpu->kvm, data);
3126 case MSR_KVM_WALL_CLOCK:
3127 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3130 kvm_write_wall_clock(vcpu->kvm, data);
3132 case MSR_KVM_SYSTEM_TIME_NEW:
3133 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3136 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3138 case MSR_KVM_SYSTEM_TIME:
3139 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3142 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3144 case MSR_KVM_ASYNC_PF_EN:
3145 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3148 if (kvm_pv_enable_async_pf(vcpu, data))
3151 case MSR_KVM_ASYNC_PF_INT:
3152 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3155 if (kvm_pv_enable_async_pf_int(vcpu, data))
3158 case MSR_KVM_ASYNC_PF_ACK:
3159 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3162 vcpu->arch.apf.pageready_pending = false;
3163 kvm_check_async_pf_completion(vcpu);
3166 case MSR_KVM_STEAL_TIME:
3167 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3170 if (unlikely(!sched_info_on()))
3173 if (data & KVM_STEAL_RESERVED_MASK)
3176 vcpu->arch.st.msr_val = data;
3178 if (!(data & KVM_MSR_ENABLED))
3181 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3184 case MSR_KVM_PV_EOI_EN:
3185 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3188 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
3192 case MSR_KVM_POLL_CONTROL:
3193 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3196 /* only enable bit supported */
3197 if (data & (-1ULL << 1))
3200 vcpu->arch.msr_kvm_poll_control = data;
3203 case MSR_IA32_MCG_CTL:
3204 case MSR_IA32_MCG_STATUS:
3205 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3206 return set_msr_mce(vcpu, msr_info);
3208 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3209 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3212 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3213 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3214 if (kvm_pmu_is_valid_msr(vcpu, msr))
3215 return kvm_pmu_set_msr(vcpu, msr_info);
3217 if (pr || data != 0)
3218 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3219 "0x%x data 0x%llx\n", msr, data);
3221 case MSR_K7_CLK_CTL:
3223 * Ignore all writes to this no longer documented MSR.
3224 * Writes are only relevant for old K7 processors,
3225 * all pre-dating SVM, but a recommended workaround from
3226 * AMD for these chips. It is possible to specify the
3227 * affected processor models on the command line, hence
3228 * the need to ignore the workaround.
3231 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3232 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3233 case HV_X64_MSR_SYNDBG_OPTIONS:
3234 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3235 case HV_X64_MSR_CRASH_CTL:
3236 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3237 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3238 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3239 case HV_X64_MSR_TSC_EMULATION_STATUS:
3240 return kvm_hv_set_msr_common(vcpu, msr, data,
3241 msr_info->host_initiated);
3242 case MSR_IA32_BBL_CR_CTL3:
3243 /* Drop writes to this legacy MSR -- see rdmsr
3244 * counterpart for further detail.
3246 if (report_ignored_msrs)
3247 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3250 case MSR_AMD64_OSVW_ID_LENGTH:
3251 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3253 vcpu->arch.osvw.length = data;
3255 case MSR_AMD64_OSVW_STATUS:
3256 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3258 vcpu->arch.osvw.status = data;
3260 case MSR_PLATFORM_INFO:
3261 if (!msr_info->host_initiated ||
3262 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3263 cpuid_fault_enabled(vcpu)))
3265 vcpu->arch.msr_platform_info = data;
3267 case MSR_MISC_FEATURES_ENABLES:
3268 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3269 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3270 !supports_cpuid_fault(vcpu)))
3272 vcpu->arch.msr_misc_features_enables = data;
3275 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
3276 return xen_hvm_config(vcpu, data);
3277 if (kvm_pmu_is_valid_msr(vcpu, msr))
3278 return kvm_pmu_set_msr(vcpu, msr_info);
3279 return KVM_MSR_RET_INVALID;
3283 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3285 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3288 u64 mcg_cap = vcpu->arch.mcg_cap;
3289 unsigned bank_num = mcg_cap & 0xff;
3292 case MSR_IA32_P5_MC_ADDR:
3293 case MSR_IA32_P5_MC_TYPE:
3296 case MSR_IA32_MCG_CAP:
3297 data = vcpu->arch.mcg_cap;
3299 case MSR_IA32_MCG_CTL:
3300 if (!(mcg_cap & MCG_CTL_P) && !host)
3302 data = vcpu->arch.mcg_ctl;
3304 case MSR_IA32_MCG_STATUS:
3305 data = vcpu->arch.mcg_status;
3308 if (msr >= MSR_IA32_MC0_CTL &&
3309 msr < MSR_IA32_MCx_CTL(bank_num)) {
3310 u32 offset = array_index_nospec(
3311 msr - MSR_IA32_MC0_CTL,
3312 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3314 data = vcpu->arch.mce_banks[offset];
3323 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3325 switch (msr_info->index) {
3326 case MSR_IA32_PLATFORM_ID:
3327 case MSR_IA32_EBL_CR_POWERON:
3328 case MSR_IA32_DEBUGCTLMSR:
3329 case MSR_IA32_LASTBRANCHFROMIP:
3330 case MSR_IA32_LASTBRANCHTOIP:
3331 case MSR_IA32_LASTINTFROMIP:
3332 case MSR_IA32_LASTINTTOIP:
3334 case MSR_K8_TSEG_ADDR:
3335 case MSR_K8_TSEG_MASK:
3336 case MSR_VM_HSAVE_PA:
3337 case MSR_K8_INT_PENDING_MSG:
3338 case MSR_AMD64_NB_CFG:
3339 case MSR_FAM10H_MMIO_CONF_BASE:
3340 case MSR_AMD64_BU_CFG2:
3341 case MSR_IA32_PERF_CTL:
3342 case MSR_AMD64_DC_CFG:
3343 case MSR_F15H_EX_CFG:
3345 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3346 * limit) MSRs. Just return 0, as we do not want to expose the host
3347 * data here. Do not conditionalize this on CPUID, as KVM does not do
3348 * so for existing CPU-specific MSRs.
3350 case MSR_RAPL_POWER_UNIT:
3351 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3352 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3353 case MSR_PKG_ENERGY_STATUS: /* Total package */
3354 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3357 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3358 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3359 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3360 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3361 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3362 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3363 return kvm_pmu_get_msr(vcpu, msr_info);
3366 case MSR_IA32_UCODE_REV:
3367 msr_info->data = vcpu->arch.microcode_version;
3369 case MSR_IA32_ARCH_CAPABILITIES:
3370 if (!msr_info->host_initiated &&
3371 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3373 msr_info->data = vcpu->arch.arch_capabilities;
3375 case MSR_IA32_PERF_CAPABILITIES:
3376 if (!msr_info->host_initiated &&
3377 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3379 msr_info->data = vcpu->arch.perf_capabilities;
3381 case MSR_IA32_POWER_CTL:
3382 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3384 case MSR_IA32_TSC: {
3386 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3387 * even when not intercepted. AMD manual doesn't explicitly
3388 * state this but appears to behave the same.
3390 * On userspace reads and writes, however, we unconditionally
3391 * return L1's TSC value to ensure backwards-compatible
3392 * behavior for migration.
3394 u64 tsc_offset = msr_info->host_initiated ? vcpu->arch.l1_tsc_offset :
3395 vcpu->arch.tsc_offset;
3397 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + tsc_offset;
3401 case 0x200 ... 0x2ff:
3402 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3403 case 0xcd: /* fsb frequency */
3407 * MSR_EBC_FREQUENCY_ID
3408 * Conservative value valid for even the basic CPU models.
3409 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3410 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3411 * and 266MHz for model 3, or 4. Set Core Clock
3412 * Frequency to System Bus Frequency Ratio to 1 (bits
3413 * 31:24) even though these are only valid for CPU
3414 * models > 2, however guests may end up dividing or
3415 * multiplying by zero otherwise.
3417 case MSR_EBC_FREQUENCY_ID:
3418 msr_info->data = 1 << 24;
3420 case MSR_IA32_APICBASE:
3421 msr_info->data = kvm_get_apic_base(vcpu);
3423 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3424 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3425 case MSR_IA32_TSCDEADLINE:
3426 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3428 case MSR_IA32_TSC_ADJUST:
3429 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3431 case MSR_IA32_MISC_ENABLE:
3432 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3434 case MSR_IA32_SMBASE:
3435 if (!msr_info->host_initiated)
3437 msr_info->data = vcpu->arch.smbase;
3440 msr_info->data = vcpu->arch.smi_count;
3442 case MSR_IA32_PERF_STATUS:
3443 /* TSC increment by tick */
3444 msr_info->data = 1000ULL;
3445 /* CPU multiplier */
3446 msr_info->data |= (((uint64_t)4ULL) << 40);
3449 msr_info->data = vcpu->arch.efer;
3451 case MSR_KVM_WALL_CLOCK:
3452 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3455 msr_info->data = vcpu->kvm->arch.wall_clock;
3457 case MSR_KVM_WALL_CLOCK_NEW:
3458 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3461 msr_info->data = vcpu->kvm->arch.wall_clock;
3463 case MSR_KVM_SYSTEM_TIME:
3464 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3467 msr_info->data = vcpu->arch.time;
3469 case MSR_KVM_SYSTEM_TIME_NEW:
3470 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3473 msr_info->data = vcpu->arch.time;
3475 case MSR_KVM_ASYNC_PF_EN:
3476 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3479 msr_info->data = vcpu->arch.apf.msr_en_val;
3481 case MSR_KVM_ASYNC_PF_INT:
3482 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3485 msr_info->data = vcpu->arch.apf.msr_int_val;
3487 case MSR_KVM_ASYNC_PF_ACK:
3488 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3493 case MSR_KVM_STEAL_TIME:
3494 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3497 msr_info->data = vcpu->arch.st.msr_val;
3499 case MSR_KVM_PV_EOI_EN:
3500 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3503 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3505 case MSR_KVM_POLL_CONTROL:
3506 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3509 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3511 case MSR_IA32_P5_MC_ADDR:
3512 case MSR_IA32_P5_MC_TYPE:
3513 case MSR_IA32_MCG_CAP:
3514 case MSR_IA32_MCG_CTL:
3515 case MSR_IA32_MCG_STATUS:
3516 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3517 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3518 msr_info->host_initiated);
3520 if (!msr_info->host_initiated &&
3521 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3523 msr_info->data = vcpu->arch.ia32_xss;
3525 case MSR_K7_CLK_CTL:
3527 * Provide expected ramp-up count for K7. All other
3528 * are set to zero, indicating minimum divisors for
3531 * This prevents guest kernels on AMD host with CPU
3532 * type 6, model 8 and higher from exploding due to
3533 * the rdmsr failing.
3535 msr_info->data = 0x20000000;
3537 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3538 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3539 case HV_X64_MSR_SYNDBG_OPTIONS:
3540 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3541 case HV_X64_MSR_CRASH_CTL:
3542 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3543 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3544 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3545 case HV_X64_MSR_TSC_EMULATION_STATUS:
3546 return kvm_hv_get_msr_common(vcpu,
3547 msr_info->index, &msr_info->data,
3548 msr_info->host_initiated);
3549 case MSR_IA32_BBL_CR_CTL3:
3550 /* This legacy MSR exists but isn't fully documented in current
3551 * silicon. It is however accessed by winxp in very narrow
3552 * scenarios where it sets bit #19, itself documented as
3553 * a "reserved" bit. Best effort attempt to source coherent
3554 * read data here should the balance of the register be
3555 * interpreted by the guest:
3557 * L2 cache control register 3: 64GB range, 256KB size,
3558 * enabled, latency 0x1, configured
3560 msr_info->data = 0xbe702111;
3562 case MSR_AMD64_OSVW_ID_LENGTH:
3563 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3565 msr_info->data = vcpu->arch.osvw.length;
3567 case MSR_AMD64_OSVW_STATUS:
3568 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3570 msr_info->data = vcpu->arch.osvw.status;
3572 case MSR_PLATFORM_INFO:
3573 if (!msr_info->host_initiated &&
3574 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3576 msr_info->data = vcpu->arch.msr_platform_info;
3578 case MSR_MISC_FEATURES_ENABLES:
3579 msr_info->data = vcpu->arch.msr_misc_features_enables;
3582 msr_info->data = vcpu->arch.msr_hwcr;
3585 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3586 return kvm_pmu_get_msr(vcpu, msr_info);
3587 return KVM_MSR_RET_INVALID;
3591 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3594 * Read or write a bunch of msrs. All parameters are kernel addresses.
3596 * @return number of msrs set successfully.
3598 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3599 struct kvm_msr_entry *entries,
3600 int (*do_msr)(struct kvm_vcpu *vcpu,
3601 unsigned index, u64 *data))
3605 for (i = 0; i < msrs->nmsrs; ++i)
3606 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3613 * Read or write a bunch of msrs. Parameters are user addresses.
3615 * @return number of msrs set successfully.
3617 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3618 int (*do_msr)(struct kvm_vcpu *vcpu,
3619 unsigned index, u64 *data),
3622 struct kvm_msrs msrs;
3623 struct kvm_msr_entry *entries;
3628 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
3632 if (msrs.nmsrs >= MAX_IO_MSRS)
3635 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
3636 entries = memdup_user(user_msrs->entries, size);
3637 if (IS_ERR(entries)) {
3638 r = PTR_ERR(entries);
3642 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3647 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3658 static inline bool kvm_can_mwait_in_guest(void)
3660 return boot_cpu_has(X86_FEATURE_MWAIT) &&
3661 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3662 boot_cpu_has(X86_FEATURE_ARAT);
3665 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
3666 struct kvm_cpuid2 __user *cpuid_arg)
3668 struct kvm_cpuid2 cpuid;
3672 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3675 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3680 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3686 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
3691 case KVM_CAP_IRQCHIP:
3693 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
3694 case KVM_CAP_SET_TSS_ADDR:
3695 case KVM_CAP_EXT_CPUID:
3696 case KVM_CAP_EXT_EMUL_CPUID:
3697 case KVM_CAP_CLOCKSOURCE:
3699 case KVM_CAP_NOP_IO_DELAY:
3700 case KVM_CAP_MP_STATE:
3701 case KVM_CAP_SYNC_MMU:
3702 case KVM_CAP_USER_NMI:
3703 case KVM_CAP_REINJECT_CONTROL:
3704 case KVM_CAP_IRQ_INJECT_STATUS:
3705 case KVM_CAP_IOEVENTFD:
3706 case KVM_CAP_IOEVENTFD_NO_LENGTH:
3708 case KVM_CAP_PIT_STATE2:
3709 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
3710 case KVM_CAP_XEN_HVM:
3711 case KVM_CAP_VCPU_EVENTS:
3712 case KVM_CAP_HYPERV:
3713 case KVM_CAP_HYPERV_VAPIC:
3714 case KVM_CAP_HYPERV_SPIN:
3715 case KVM_CAP_HYPERV_SYNIC:
3716 case KVM_CAP_HYPERV_SYNIC2:
3717 case KVM_CAP_HYPERV_VP_INDEX:
3718 case KVM_CAP_HYPERV_EVENTFD:
3719 case KVM_CAP_HYPERV_TLBFLUSH:
3720 case KVM_CAP_HYPERV_SEND_IPI:
3721 case KVM_CAP_HYPERV_CPUID:
3722 case KVM_CAP_SYS_HYPERV_CPUID:
3723 case KVM_CAP_PCI_SEGMENT:
3724 case KVM_CAP_DEBUGREGS:
3725 case KVM_CAP_X86_ROBUST_SINGLESTEP:
3727 case KVM_CAP_ASYNC_PF:
3728 case KVM_CAP_ASYNC_PF_INT:
3729 case KVM_CAP_GET_TSC_KHZ:
3730 case KVM_CAP_KVMCLOCK_CTRL:
3731 case KVM_CAP_READONLY_MEM:
3732 case KVM_CAP_HYPERV_TIME:
3733 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
3734 case KVM_CAP_TSC_DEADLINE_TIMER:
3735 case KVM_CAP_DISABLE_QUIRKS:
3736 case KVM_CAP_SET_BOOT_CPU_ID:
3737 case KVM_CAP_SPLIT_IRQCHIP:
3738 case KVM_CAP_IMMEDIATE_EXIT:
3739 case KVM_CAP_PMU_EVENT_FILTER:
3740 case KVM_CAP_GET_MSR_FEATURES:
3741 case KVM_CAP_MSR_PLATFORM_INFO:
3742 case KVM_CAP_EXCEPTION_PAYLOAD:
3743 case KVM_CAP_SET_GUEST_DEBUG:
3744 case KVM_CAP_LAST_CPU:
3745 case KVM_CAP_X86_USER_SPACE_MSR:
3746 case KVM_CAP_X86_MSR_FILTER:
3747 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
3750 case KVM_CAP_SYNC_REGS:
3751 r = KVM_SYNC_X86_VALID_FIELDS;
3753 case KVM_CAP_ADJUST_CLOCK:
3754 r = KVM_CLOCK_TSC_STABLE;
3756 case KVM_CAP_X86_DISABLE_EXITS:
3757 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3758 KVM_X86_DISABLE_EXITS_CSTATE;
3759 if(kvm_can_mwait_in_guest())
3760 r |= KVM_X86_DISABLE_EXITS_MWAIT;
3762 case KVM_CAP_X86_SMM:
3763 /* SMBASE is usually relocated above 1M on modern chipsets,
3764 * and SMM handlers might indeed rely on 4G segment limits,
3765 * so do not report SMM to be available if real mode is
3766 * emulated via vm86 mode. Still, do not go to great lengths
3767 * to avoid userspace's usage of the feature, because it is a
3768 * fringe case that is not enabled except via specific settings
3769 * of the module parameters.
3771 r = kvm_x86_ops.has_emulated_msr(MSR_IA32_SMBASE);
3774 r = !kvm_x86_ops.cpu_has_accelerated_tpr();
3776 case KVM_CAP_NR_VCPUS:
3777 r = KVM_SOFT_MAX_VCPUS;
3779 case KVM_CAP_MAX_VCPUS:
3782 case KVM_CAP_MAX_VCPU_ID:
3783 r = KVM_MAX_VCPU_ID;
3785 case KVM_CAP_PV_MMU: /* obsolete */
3789 r = KVM_MAX_MCE_BANKS;
3792 r = boot_cpu_has(X86_FEATURE_XSAVE);
3794 case KVM_CAP_TSC_CONTROL:
3795 r = kvm_has_tsc_control;
3797 case KVM_CAP_X2APIC_API:
3798 r = KVM_X2APIC_API_VALID_FLAGS;
3800 case KVM_CAP_NESTED_STATE:
3801 r = kvm_x86_ops.nested_ops->get_state ?
3802 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
3804 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3805 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
3807 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3808 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
3810 case KVM_CAP_SMALLER_MAXPHYADDR:
3811 r = (int) allow_smaller_maxphyaddr;
3813 case KVM_CAP_STEAL_TIME:
3814 r = sched_info_on();
3823 long kvm_arch_dev_ioctl(struct file *filp,
3824 unsigned int ioctl, unsigned long arg)
3826 void __user *argp = (void __user *)arg;
3830 case KVM_GET_MSR_INDEX_LIST: {
3831 struct kvm_msr_list __user *user_msr_list = argp;
3832 struct kvm_msr_list msr_list;
3836 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3839 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
3840 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3843 if (n < msr_list.nmsrs)
3846 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3847 num_msrs_to_save * sizeof(u32)))
3849 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
3851 num_emulated_msrs * sizeof(u32)))
3856 case KVM_GET_SUPPORTED_CPUID:
3857 case KVM_GET_EMULATED_CPUID: {
3858 struct kvm_cpuid2 __user *cpuid_arg = argp;
3859 struct kvm_cpuid2 cpuid;
3862 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
3865 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3871 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
3876 case KVM_X86_GET_MCE_CAP_SUPPORTED:
3878 if (copy_to_user(argp, &kvm_mce_cap_supported,
3879 sizeof(kvm_mce_cap_supported)))
3883 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3884 struct kvm_msr_list __user *user_msr_list = argp;
3885 struct kvm_msr_list msr_list;
3889 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3892 msr_list.nmsrs = num_msr_based_features;
3893 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3896 if (n < msr_list.nmsrs)
3899 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3900 num_msr_based_features * sizeof(u32)))
3906 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3908 case KVM_GET_SUPPORTED_HV_CPUID:
3909 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
3919 static void wbinvd_ipi(void *garbage)
3924 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3926 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
3929 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3931 /* Address WBINVD may be executed by guest */
3932 if (need_emulate_wbinvd(vcpu)) {
3933 if (kvm_x86_ops.has_wbinvd_exit())
3934 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3935 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3936 smp_call_function_single(vcpu->cpu,
3937 wbinvd_ipi, NULL, 1);
3940 kvm_x86_ops.vcpu_load(vcpu, cpu);
3942 /* Save host pkru register if supported */
3943 vcpu->arch.host_pkru = read_pkru();
3945 /* Apply any externally detected TSC adjustments (due to suspend) */
3946 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3947 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3948 vcpu->arch.tsc_offset_adjustment = 0;
3949 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3952 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
3953 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
3954 rdtsc() - vcpu->arch.last_host_tsc;
3956 mark_tsc_unstable("KVM discovered backwards TSC");
3958 if (kvm_check_tsc_unstable()) {
3959 u64 offset = kvm_compute_tsc_offset(vcpu,
3960 vcpu->arch.last_guest_tsc);
3961 kvm_vcpu_write_tsc_offset(vcpu, offset);
3962 vcpu->arch.tsc_catchup = 1;
3965 if (kvm_lapic_hv_timer_in_use(vcpu))
3966 kvm_lapic_restart_hv_timer(vcpu);
3969 * On a host with synchronized TSC, there is no need to update
3970 * kvmclock on vcpu->cpu migration
3972 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
3973 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
3974 if (vcpu->cpu != cpu)
3975 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
3979 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3982 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3984 struct kvm_host_map map;
3985 struct kvm_steal_time *st;
3987 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3990 if (vcpu->arch.st.preempted)
3993 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3994 &vcpu->arch.st.cache, true))
3998 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
4000 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4002 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
4005 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4009 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4010 vcpu->arch.preempted_in_kernel = !kvm_x86_ops.get_cpl(vcpu);
4013 * Disable page faults because we're in atomic context here.
4014 * kvm_write_guest_offset_cached() would call might_fault()
4015 * that relies on pagefault_disable() to tell if there's a
4016 * bug. NOTE: the write to guest memory may not go through if
4017 * during postcopy live migration or if there's heavy guest
4020 pagefault_disable();
4022 * kvm_memslots() will be called by
4023 * kvm_write_guest_offset_cached() so take the srcu lock.
4025 idx = srcu_read_lock(&vcpu->kvm->srcu);
4026 kvm_steal_time_set_preempted(vcpu);
4027 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4029 kvm_x86_ops.vcpu_put(vcpu);
4030 vcpu->arch.last_host_tsc = rdtsc();
4032 * If userspace has set any breakpoints or watchpoints, dr6 is restored
4033 * on every vmexit, but if not, we might have a stale dr6 from the
4034 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
4039 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4040 struct kvm_lapic_state *s)
4042 if (vcpu->arch.apicv_active)
4043 kvm_x86_ops.sync_pir_to_irr(vcpu);
4045 return kvm_apic_get_state(vcpu, s);
4048 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4049 struct kvm_lapic_state *s)
4053 r = kvm_apic_set_state(vcpu, s);
4056 update_cr8_intercept(vcpu);
4061 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4063 return (!lapic_in_kernel(vcpu) ||
4064 kvm_apic_accept_pic_intr(vcpu));
4068 * if userspace requested an interrupt window, check that the
4069 * interrupt window is open.
4071 * No need to exit to userspace if we already have an interrupt queued.
4073 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4075 return kvm_arch_interrupt_allowed(vcpu) &&
4076 !kvm_cpu_has_interrupt(vcpu) &&
4077 !kvm_event_needs_reinjection(vcpu) &&
4078 kvm_cpu_accept_dm_intr(vcpu);
4081 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4082 struct kvm_interrupt *irq)
4084 if (irq->irq >= KVM_NR_INTERRUPTS)
4087 if (!irqchip_in_kernel(vcpu->kvm)) {
4088 kvm_queue_interrupt(vcpu, irq->irq, false);
4089 kvm_make_request(KVM_REQ_EVENT, vcpu);
4094 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4095 * fail for in-kernel 8259.
4097 if (pic_in_kernel(vcpu->kvm))
4100 if (vcpu->arch.pending_external_vector != -1)
4103 vcpu->arch.pending_external_vector = irq->irq;
4104 kvm_make_request(KVM_REQ_EVENT, vcpu);
4108 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4110 kvm_inject_nmi(vcpu);
4115 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4117 kvm_make_request(KVM_REQ_SMI, vcpu);
4122 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4123 struct kvm_tpr_access_ctl *tac)
4127 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4131 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4135 unsigned bank_num = mcg_cap & 0xff, bank;
4138 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4140 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4143 vcpu->arch.mcg_cap = mcg_cap;
4144 /* Init IA32_MCG_CTL to all 1s */
4145 if (mcg_cap & MCG_CTL_P)
4146 vcpu->arch.mcg_ctl = ~(u64)0;
4147 /* Init IA32_MCi_CTL to all 1s */
4148 for (bank = 0; bank < bank_num; bank++)
4149 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4151 kvm_x86_ops.setup_mce(vcpu);
4156 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4157 struct kvm_x86_mce *mce)
4159 u64 mcg_cap = vcpu->arch.mcg_cap;
4160 unsigned bank_num = mcg_cap & 0xff;
4161 u64 *banks = vcpu->arch.mce_banks;
4163 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4166 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4167 * reporting is disabled
4169 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4170 vcpu->arch.mcg_ctl != ~(u64)0)
4172 banks += 4 * mce->bank;
4174 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4175 * reporting is disabled for the bank
4177 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4179 if (mce->status & MCI_STATUS_UC) {
4180 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4181 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4182 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4185 if (banks[1] & MCI_STATUS_VAL)
4186 mce->status |= MCI_STATUS_OVER;
4187 banks[2] = mce->addr;
4188 banks[3] = mce->misc;
4189 vcpu->arch.mcg_status = mce->mcg_status;
4190 banks[1] = mce->status;
4191 kvm_queue_exception(vcpu, MC_VECTOR);
4192 } else if (!(banks[1] & MCI_STATUS_VAL)
4193 || !(banks[1] & MCI_STATUS_UC)) {
4194 if (banks[1] & MCI_STATUS_VAL)
4195 mce->status |= MCI_STATUS_OVER;
4196 banks[2] = mce->addr;
4197 banks[3] = mce->misc;
4198 banks[1] = mce->status;
4200 banks[1] |= MCI_STATUS_OVER;
4204 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4205 struct kvm_vcpu_events *events)
4210 * In guest mode, payload delivery should be deferred,
4211 * so that the L1 hypervisor can intercept #PF before
4212 * CR2 is modified (or intercept #DB before DR6 is
4213 * modified under nVMX). Unless the per-VM capability,
4214 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4215 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4216 * opportunistically defer the exception payload, deliver it if the
4217 * capability hasn't been requested before processing a
4218 * KVM_GET_VCPU_EVENTS.
4220 if (!vcpu->kvm->arch.exception_payload_enabled &&
4221 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4222 kvm_deliver_exception_payload(vcpu);
4225 * The API doesn't provide the instruction length for software
4226 * exceptions, so don't report them. As long as the guest RIP
4227 * isn't advanced, we should expect to encounter the exception
4230 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4231 events->exception.injected = 0;
4232 events->exception.pending = 0;
4234 events->exception.injected = vcpu->arch.exception.injected;
4235 events->exception.pending = vcpu->arch.exception.pending;
4237 * For ABI compatibility, deliberately conflate
4238 * pending and injected exceptions when
4239 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4241 if (!vcpu->kvm->arch.exception_payload_enabled)
4242 events->exception.injected |=
4243 vcpu->arch.exception.pending;
4245 events->exception.nr = vcpu->arch.exception.nr;
4246 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4247 events->exception.error_code = vcpu->arch.exception.error_code;
4248 events->exception_has_payload = vcpu->arch.exception.has_payload;
4249 events->exception_payload = vcpu->arch.exception.payload;
4251 events->interrupt.injected =
4252 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4253 events->interrupt.nr = vcpu->arch.interrupt.nr;
4254 events->interrupt.soft = 0;
4255 events->interrupt.shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
4257 events->nmi.injected = vcpu->arch.nmi_injected;
4258 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4259 events->nmi.masked = kvm_x86_ops.get_nmi_mask(vcpu);
4260 events->nmi.pad = 0;
4262 events->sipi_vector = 0; /* never valid when reporting to user space */
4264 events->smi.smm = is_smm(vcpu);
4265 events->smi.pending = vcpu->arch.smi_pending;
4266 events->smi.smm_inside_nmi =
4267 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4268 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4270 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4271 | KVM_VCPUEVENT_VALID_SHADOW
4272 | KVM_VCPUEVENT_VALID_SMM);
4273 if (vcpu->kvm->arch.exception_payload_enabled)
4274 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4276 memset(&events->reserved, 0, sizeof(events->reserved));
4279 static void kvm_smm_changed(struct kvm_vcpu *vcpu);
4281 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4282 struct kvm_vcpu_events *events)
4284 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4285 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4286 | KVM_VCPUEVENT_VALID_SHADOW
4287 | KVM_VCPUEVENT_VALID_SMM
4288 | KVM_VCPUEVENT_VALID_PAYLOAD))
4291 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4292 if (!vcpu->kvm->arch.exception_payload_enabled)
4294 if (events->exception.pending)
4295 events->exception.injected = 0;
4297 events->exception_has_payload = 0;
4299 events->exception.pending = 0;
4300 events->exception_has_payload = 0;
4303 if ((events->exception.injected || events->exception.pending) &&
4304 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4307 /* INITs are latched while in SMM */
4308 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4309 (events->smi.smm || events->smi.pending) &&
4310 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4314 vcpu->arch.exception.injected = events->exception.injected;
4315 vcpu->arch.exception.pending = events->exception.pending;
4316 vcpu->arch.exception.nr = events->exception.nr;
4317 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4318 vcpu->arch.exception.error_code = events->exception.error_code;
4319 vcpu->arch.exception.has_payload = events->exception_has_payload;
4320 vcpu->arch.exception.payload = events->exception_payload;
4322 vcpu->arch.interrupt.injected = events->interrupt.injected;
4323 vcpu->arch.interrupt.nr = events->interrupt.nr;
4324 vcpu->arch.interrupt.soft = events->interrupt.soft;
4325 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4326 kvm_x86_ops.set_interrupt_shadow(vcpu,
4327 events->interrupt.shadow);
4329 vcpu->arch.nmi_injected = events->nmi.injected;
4330 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4331 vcpu->arch.nmi_pending = events->nmi.pending;
4332 kvm_x86_ops.set_nmi_mask(vcpu, events->nmi.masked);
4334 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4335 lapic_in_kernel(vcpu))
4336 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4338 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4339 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4340 if (events->smi.smm)
4341 vcpu->arch.hflags |= HF_SMM_MASK;
4343 vcpu->arch.hflags &= ~HF_SMM_MASK;
4344 kvm_smm_changed(vcpu);
4347 vcpu->arch.smi_pending = events->smi.pending;
4349 if (events->smi.smm) {
4350 if (events->smi.smm_inside_nmi)
4351 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4353 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4356 if (lapic_in_kernel(vcpu)) {
4357 if (events->smi.latched_init)
4358 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4360 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4364 kvm_make_request(KVM_REQ_EVENT, vcpu);
4369 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4370 struct kvm_debugregs *dbgregs)
4374 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4375 kvm_get_dr(vcpu, 6, &val);
4377 dbgregs->dr7 = vcpu->arch.dr7;
4379 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4382 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4383 struct kvm_debugregs *dbgregs)
4388 if (dbgregs->dr6 & ~0xffffffffull)
4390 if (dbgregs->dr7 & ~0xffffffffull)
4393 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
4394 kvm_update_dr0123(vcpu);
4395 vcpu->arch.dr6 = dbgregs->dr6;
4396 vcpu->arch.dr7 = dbgregs->dr7;
4397 kvm_update_dr7(vcpu);
4402 #define XSTATE_COMPACTION_ENABLED (1ULL << 63)
4404 static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
4406 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4407 u64 xstate_bv = xsave->header.xfeatures;
4411 * Copy legacy XSAVE area, to avoid complications with CPUID
4412 * leaves 0 and 1 in the loop below.
4414 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
4417 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
4418 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
4421 * Copy each region from the possibly compacted offset to the
4422 * non-compacted offset.
4424 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4426 u64 xfeature_mask = valid & -valid;
4427 int xfeature_nr = fls64(xfeature_mask) - 1;
4428 void *src = get_xsave_addr(xsave, xfeature_nr);
4431 u32 size, offset, ecx, edx;
4432 cpuid_count(XSTATE_CPUID, xfeature_nr,
4433 &size, &offset, &ecx, &edx);
4434 if (xfeature_nr == XFEATURE_PKRU)
4435 memcpy(dest + offset, &vcpu->arch.pkru,
4436 sizeof(vcpu->arch.pkru));
4438 memcpy(dest + offset, src, size);
4442 valid -= xfeature_mask;
4446 static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4448 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
4449 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4453 * Copy legacy XSAVE area, to avoid complications with CPUID
4454 * leaves 0 and 1 in the loop below.
4456 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4458 /* Set XSTATE_BV and possibly XCOMP_BV. */
4459 xsave->header.xfeatures = xstate_bv;
4460 if (boot_cpu_has(X86_FEATURE_XSAVES))
4461 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
4464 * Copy each region from the non-compacted offset to the
4465 * possibly compacted offset.
4467 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
4469 u64 xfeature_mask = valid & -valid;
4470 int xfeature_nr = fls64(xfeature_mask) - 1;
4471 void *dest = get_xsave_addr(xsave, xfeature_nr);
4474 u32 size, offset, ecx, edx;
4475 cpuid_count(XSTATE_CPUID, xfeature_nr,
4476 &size, &offset, &ecx, &edx);
4477 if (xfeature_nr == XFEATURE_PKRU)
4478 memcpy(&vcpu->arch.pkru, src + offset,
4479 sizeof(vcpu->arch.pkru));
4481 memcpy(dest, src + offset, size);
4484 valid -= xfeature_mask;
4488 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4489 struct kvm_xsave *guest_xsave)
4491 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4492 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4493 fill_xsave((u8 *) guest_xsave->region, vcpu);
4495 memcpy(guest_xsave->region,
4496 &vcpu->arch.guest_fpu->state.fxsave,
4497 sizeof(struct fxregs_state));
4498 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
4499 XFEATURE_MASK_FPSSE;
4503 #define XSAVE_MXCSR_OFFSET 24
4505 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4506 struct kvm_xsave *guest_xsave)
4509 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
4510 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
4512 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
4514 * Here we allow setting states that are not present in
4515 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4516 * with old userspace.
4518 if (xstate_bv & ~supported_xcr0 || mxcsr & ~mxcsr_feature_mask)
4520 load_xsave(vcpu, (u8 *)guest_xsave->region);
4522 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4523 mxcsr & ~mxcsr_feature_mask)
4525 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
4526 guest_xsave->region, sizeof(struct fxregs_state));
4531 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4532 struct kvm_xcrs *guest_xcrs)
4534 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
4535 guest_xcrs->nr_xcrs = 0;
4539 guest_xcrs->nr_xcrs = 1;
4540 guest_xcrs->flags = 0;
4541 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4542 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4545 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4546 struct kvm_xcrs *guest_xcrs)
4550 if (!boot_cpu_has(X86_FEATURE_XSAVE))
4553 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4556 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4557 /* Only support XCR0 currently */
4558 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
4559 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
4560 guest_xcrs->xcrs[i].value);
4569 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4570 * stopped by the hypervisor. This function will be called from the host only.
4571 * EINVAL is returned when the host attempts to set the flag for a guest that
4572 * does not support pv clocks.
4574 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4576 if (!vcpu->arch.pv_time_enabled)
4578 vcpu->arch.pvclock_set_guest_stopped_request = true;
4579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4583 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4584 struct kvm_enable_cap *cap)
4587 uint16_t vmcs_version;
4588 void __user *user_ptr;
4594 case KVM_CAP_HYPERV_SYNIC2:
4599 case KVM_CAP_HYPERV_SYNIC:
4600 if (!irqchip_in_kernel(vcpu->kvm))
4602 return kvm_hv_activate_synic(vcpu, cap->cap ==
4603 KVM_CAP_HYPERV_SYNIC2);
4604 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4605 if (!kvm_x86_ops.nested_ops->enable_evmcs)
4607 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
4609 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4610 if (copy_to_user(user_ptr, &vmcs_version,
4611 sizeof(vmcs_version)))
4615 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4616 if (!kvm_x86_ops.enable_direct_tlbflush)
4619 return kvm_x86_ops.enable_direct_tlbflush(vcpu);
4621 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4622 vcpu->arch.pv_cpuid.enforce = cap->args[0];
4623 if (vcpu->arch.pv_cpuid.enforce)
4624 kvm_update_pv_runtime(vcpu);
4633 long kvm_arch_vcpu_ioctl(struct file *filp,
4634 unsigned int ioctl, unsigned long arg)
4636 struct kvm_vcpu *vcpu = filp->private_data;
4637 void __user *argp = (void __user *)arg;
4640 struct kvm_lapic_state *lapic;
4641 struct kvm_xsave *xsave;
4642 struct kvm_xcrs *xcrs;
4650 case KVM_GET_LAPIC: {
4652 if (!lapic_in_kernel(vcpu))
4654 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4655 GFP_KERNEL_ACCOUNT);
4660 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
4664 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
4669 case KVM_SET_LAPIC: {
4671 if (!lapic_in_kernel(vcpu))
4673 u.lapic = memdup_user(argp, sizeof(*u.lapic));
4674 if (IS_ERR(u.lapic)) {
4675 r = PTR_ERR(u.lapic);
4679 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
4682 case KVM_INTERRUPT: {
4683 struct kvm_interrupt irq;
4686 if (copy_from_user(&irq, argp, sizeof(irq)))
4688 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
4692 r = kvm_vcpu_ioctl_nmi(vcpu);
4696 r = kvm_vcpu_ioctl_smi(vcpu);
4699 case KVM_SET_CPUID: {
4700 struct kvm_cpuid __user *cpuid_arg = argp;
4701 struct kvm_cpuid cpuid;
4704 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4706 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4709 case KVM_SET_CPUID2: {
4710 struct kvm_cpuid2 __user *cpuid_arg = argp;
4711 struct kvm_cpuid2 cpuid;
4714 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4716 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
4717 cpuid_arg->entries);
4720 case KVM_GET_CPUID2: {
4721 struct kvm_cpuid2 __user *cpuid_arg = argp;
4722 struct kvm_cpuid2 cpuid;
4725 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4727 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
4728 cpuid_arg->entries);
4732 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4737 case KVM_GET_MSRS: {
4738 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4739 r = msr_io(vcpu, argp, do_get_msr, 1);
4740 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4743 case KVM_SET_MSRS: {
4744 int idx = srcu_read_lock(&vcpu->kvm->srcu);
4745 r = msr_io(vcpu, argp, do_set_msr, 0);
4746 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4749 case KVM_TPR_ACCESS_REPORTING: {
4750 struct kvm_tpr_access_ctl tac;
4753 if (copy_from_user(&tac, argp, sizeof(tac)))
4755 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4759 if (copy_to_user(argp, &tac, sizeof(tac)))
4764 case KVM_SET_VAPIC_ADDR: {
4765 struct kvm_vapic_addr va;
4769 if (!lapic_in_kernel(vcpu))
4772 if (copy_from_user(&va, argp, sizeof(va)))
4774 idx = srcu_read_lock(&vcpu->kvm->srcu);
4775 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
4776 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4779 case KVM_X86_SETUP_MCE: {
4783 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
4785 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4788 case KVM_X86_SET_MCE: {
4789 struct kvm_x86_mce mce;
4792 if (copy_from_user(&mce, argp, sizeof(mce)))
4794 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4797 case KVM_GET_VCPU_EVENTS: {
4798 struct kvm_vcpu_events events;
4800 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4803 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4808 case KVM_SET_VCPU_EVENTS: {
4809 struct kvm_vcpu_events events;
4812 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4815 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4818 case KVM_GET_DEBUGREGS: {
4819 struct kvm_debugregs dbgregs;
4821 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4824 if (copy_to_user(argp, &dbgregs,
4825 sizeof(struct kvm_debugregs)))
4830 case KVM_SET_DEBUGREGS: {
4831 struct kvm_debugregs dbgregs;
4834 if (copy_from_user(&dbgregs, argp,
4835 sizeof(struct kvm_debugregs)))
4838 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4841 case KVM_GET_XSAVE: {
4842 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
4847 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
4850 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
4855 case KVM_SET_XSAVE: {
4856 u.xsave = memdup_user(argp, sizeof(*u.xsave));
4857 if (IS_ERR(u.xsave)) {
4858 r = PTR_ERR(u.xsave);
4862 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
4865 case KVM_GET_XCRS: {
4866 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
4871 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
4874 if (copy_to_user(argp, u.xcrs,
4875 sizeof(struct kvm_xcrs)))
4880 case KVM_SET_XCRS: {
4881 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
4882 if (IS_ERR(u.xcrs)) {
4883 r = PTR_ERR(u.xcrs);
4887 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
4890 case KVM_SET_TSC_KHZ: {
4894 user_tsc_khz = (u32)arg;
4896 if (kvm_has_tsc_control &&
4897 user_tsc_khz >= kvm_max_guest_tsc_khz)
4900 if (user_tsc_khz == 0)
4901 user_tsc_khz = tsc_khz;
4903 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4908 case KVM_GET_TSC_KHZ: {
4909 r = vcpu->arch.virtual_tsc_khz;
4912 case KVM_KVMCLOCK_CTRL: {
4913 r = kvm_set_guest_paused(vcpu);
4916 case KVM_ENABLE_CAP: {
4917 struct kvm_enable_cap cap;
4920 if (copy_from_user(&cap, argp, sizeof(cap)))
4922 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4925 case KVM_GET_NESTED_STATE: {
4926 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4930 if (!kvm_x86_ops.nested_ops->get_state)
4933 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4935 if (get_user(user_data_size, &user_kvm_nested_state->size))
4938 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
4943 if (r > user_data_size) {
4944 if (put_user(r, &user_kvm_nested_state->size))
4954 case KVM_SET_NESTED_STATE: {
4955 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4956 struct kvm_nested_state kvm_state;
4960 if (!kvm_x86_ops.nested_ops->set_state)
4964 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4968 if (kvm_state.size < sizeof(kvm_state))
4971 if (kvm_state.flags &
4972 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4973 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
4974 | KVM_STATE_NESTED_GIF_SET))
4977 /* nested_run_pending implies guest_mode. */
4978 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4979 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
4982 idx = srcu_read_lock(&vcpu->kvm->srcu);
4983 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
4984 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4987 case KVM_GET_SUPPORTED_HV_CPUID:
4988 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5000 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5002 return VM_FAULT_SIGBUS;
5005 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5009 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5011 ret = kvm_x86_ops.set_tss_addr(kvm, addr);
5015 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5018 return kvm_x86_ops.set_identity_map_addr(kvm, ident_addr);
5021 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5022 unsigned long kvm_nr_mmu_pages)
5024 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5027 mutex_lock(&kvm->slots_lock);
5029 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5030 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5032 mutex_unlock(&kvm->slots_lock);
5036 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5038 return kvm->arch.n_max_mmu_pages;
5041 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5043 struct kvm_pic *pic = kvm->arch.vpic;
5047 switch (chip->chip_id) {
5048 case KVM_IRQCHIP_PIC_MASTER:
5049 memcpy(&chip->chip.pic, &pic->pics[0],
5050 sizeof(struct kvm_pic_state));
5052 case KVM_IRQCHIP_PIC_SLAVE:
5053 memcpy(&chip->chip.pic, &pic->pics[1],
5054 sizeof(struct kvm_pic_state));
5056 case KVM_IRQCHIP_IOAPIC:
5057 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5066 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5068 struct kvm_pic *pic = kvm->arch.vpic;
5072 switch (chip->chip_id) {
5073 case KVM_IRQCHIP_PIC_MASTER:
5074 spin_lock(&pic->lock);
5075 memcpy(&pic->pics[0], &chip->chip.pic,
5076 sizeof(struct kvm_pic_state));
5077 spin_unlock(&pic->lock);
5079 case KVM_IRQCHIP_PIC_SLAVE:
5080 spin_lock(&pic->lock);
5081 memcpy(&pic->pics[1], &chip->chip.pic,
5082 sizeof(struct kvm_pic_state));
5083 spin_unlock(&pic->lock);
5085 case KVM_IRQCHIP_IOAPIC:
5086 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5092 kvm_pic_update_irq(pic);
5096 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5098 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5100 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5102 mutex_lock(&kps->lock);
5103 memcpy(ps, &kps->channels, sizeof(*ps));
5104 mutex_unlock(&kps->lock);
5108 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5111 struct kvm_pit *pit = kvm->arch.vpit;
5113 mutex_lock(&pit->pit_state.lock);
5114 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5115 for (i = 0; i < 3; i++)
5116 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5117 mutex_unlock(&pit->pit_state.lock);
5121 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5123 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5124 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5125 sizeof(ps->channels));
5126 ps->flags = kvm->arch.vpit->pit_state.flags;
5127 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5128 memset(&ps->reserved, 0, sizeof(ps->reserved));
5132 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5136 u32 prev_legacy, cur_legacy;
5137 struct kvm_pit *pit = kvm->arch.vpit;
5139 mutex_lock(&pit->pit_state.lock);
5140 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5141 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5142 if (!prev_legacy && cur_legacy)
5144 memcpy(&pit->pit_state.channels, &ps->channels,
5145 sizeof(pit->pit_state.channels));
5146 pit->pit_state.flags = ps->flags;
5147 for (i = 0; i < 3; i++)
5148 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5150 mutex_unlock(&pit->pit_state.lock);
5154 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5155 struct kvm_reinject_control *control)
5157 struct kvm_pit *pit = kvm->arch.vpit;
5159 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5160 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5161 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5163 mutex_lock(&pit->pit_state.lock);
5164 kvm_pit_set_reinject(pit, control->pit_reinject);
5165 mutex_unlock(&pit->pit_state.lock);
5170 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5173 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
5175 if (kvm_x86_ops.flush_log_dirty)
5176 kvm_x86_ops.flush_log_dirty(kvm);
5179 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5182 if (!irqchip_in_kernel(kvm))
5185 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5186 irq_event->irq, irq_event->level,
5191 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5192 struct kvm_enable_cap *cap)
5200 case KVM_CAP_DISABLE_QUIRKS:
5201 kvm->arch.disabled_quirks = cap->args[0];
5204 case KVM_CAP_SPLIT_IRQCHIP: {
5205 mutex_lock(&kvm->lock);
5207 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5208 goto split_irqchip_unlock;
5210 if (irqchip_in_kernel(kvm))
5211 goto split_irqchip_unlock;
5212 if (kvm->created_vcpus)
5213 goto split_irqchip_unlock;
5214 r = kvm_setup_empty_irq_routing(kvm);
5216 goto split_irqchip_unlock;
5217 /* Pairs with irqchip_in_kernel. */
5219 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5220 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5222 split_irqchip_unlock:
5223 mutex_unlock(&kvm->lock);
5226 case KVM_CAP_X2APIC_API:
5228 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5231 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5232 kvm->arch.x2apic_format = true;
5233 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5234 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5238 case KVM_CAP_X86_DISABLE_EXITS:
5240 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5243 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5244 kvm_can_mwait_in_guest())
5245 kvm->arch.mwait_in_guest = true;
5246 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5247 kvm->arch.hlt_in_guest = true;
5248 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5249 kvm->arch.pause_in_guest = true;
5250 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5251 kvm->arch.cstate_in_guest = true;
5254 case KVM_CAP_MSR_PLATFORM_INFO:
5255 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5258 case KVM_CAP_EXCEPTION_PAYLOAD:
5259 kvm->arch.exception_payload_enabled = cap->args[0];
5262 case KVM_CAP_X86_USER_SPACE_MSR:
5263 kvm->arch.user_space_msr_mask = cap->args[0];
5273 static void kvm_clear_msr_filter(struct kvm *kvm)
5276 u32 count = kvm->arch.msr_filter.count;
5277 struct msr_bitmap_range ranges[16];
5279 mutex_lock(&kvm->lock);
5280 kvm->arch.msr_filter.count = 0;
5281 memcpy(ranges, kvm->arch.msr_filter.ranges, count * sizeof(ranges[0]));
5282 mutex_unlock(&kvm->lock);
5283 synchronize_srcu(&kvm->srcu);
5285 for (i = 0; i < count; i++)
5286 kfree(ranges[i].bitmap);
5289 static int kvm_add_msr_filter(struct kvm *kvm, struct kvm_msr_filter_range *user_range)
5291 struct msr_bitmap_range *ranges = kvm->arch.msr_filter.ranges;
5292 struct msr_bitmap_range range;
5293 unsigned long *bitmap = NULL;
5297 if (!user_range->nmsrs)
5300 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
5301 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
5304 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
5306 return PTR_ERR(bitmap);
5308 range = (struct msr_bitmap_range) {
5309 .flags = user_range->flags,
5310 .base = user_range->base,
5311 .nmsrs = user_range->nmsrs,
5315 if (range.flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) {
5325 /* Everything ok, add this range identifier to our global pool */
5326 ranges[kvm->arch.msr_filter.count] = range;
5327 /* Make sure we filled the array before we tell anyone to walk it */
5329 kvm->arch.msr_filter.count++;
5337 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
5339 struct kvm_msr_filter __user *user_msr_filter = argp;
5340 struct kvm_msr_filter filter;
5346 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
5349 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
5350 empty &= !filter.ranges[i].nmsrs;
5352 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
5353 if (empty && !default_allow)
5356 kvm_clear_msr_filter(kvm);
5358 kvm->arch.msr_filter.default_allow = default_allow;
5361 * Protect from concurrent calls to this function that could trigger
5362 * a TOCTOU violation on kvm->arch.msr_filter.count.
5364 mutex_lock(&kvm->lock);
5365 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
5366 r = kvm_add_msr_filter(kvm, &filter.ranges[i]);
5371 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
5372 mutex_unlock(&kvm->lock);
5377 long kvm_arch_vm_ioctl(struct file *filp,
5378 unsigned int ioctl, unsigned long arg)
5380 struct kvm *kvm = filp->private_data;
5381 void __user *argp = (void __user *)arg;
5384 * This union makes it completely explicit to gcc-3.x
5385 * that these two variables' stack usage should be
5386 * combined, not added together.
5389 struct kvm_pit_state ps;
5390 struct kvm_pit_state2 ps2;
5391 struct kvm_pit_config pit_config;
5395 case KVM_SET_TSS_ADDR:
5396 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
5398 case KVM_SET_IDENTITY_MAP_ADDR: {
5401 mutex_lock(&kvm->lock);
5403 if (kvm->created_vcpus)
5404 goto set_identity_unlock;
5406 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
5407 goto set_identity_unlock;
5408 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
5409 set_identity_unlock:
5410 mutex_unlock(&kvm->lock);
5413 case KVM_SET_NR_MMU_PAGES:
5414 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
5416 case KVM_GET_NR_MMU_PAGES:
5417 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
5419 case KVM_CREATE_IRQCHIP: {
5420 mutex_lock(&kvm->lock);
5423 if (irqchip_in_kernel(kvm))
5424 goto create_irqchip_unlock;
5427 if (kvm->created_vcpus)
5428 goto create_irqchip_unlock;
5430 r = kvm_pic_init(kvm);
5432 goto create_irqchip_unlock;
5434 r = kvm_ioapic_init(kvm);
5436 kvm_pic_destroy(kvm);
5437 goto create_irqchip_unlock;
5440 r = kvm_setup_default_irq_routing(kvm);
5442 kvm_ioapic_destroy(kvm);
5443 kvm_pic_destroy(kvm);
5444 goto create_irqchip_unlock;
5446 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
5448 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
5449 create_irqchip_unlock:
5450 mutex_unlock(&kvm->lock);
5453 case KVM_CREATE_PIT:
5454 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
5456 case KVM_CREATE_PIT2:
5458 if (copy_from_user(&u.pit_config, argp,
5459 sizeof(struct kvm_pit_config)))
5462 mutex_lock(&kvm->lock);
5465 goto create_pit_unlock;
5467 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
5471 mutex_unlock(&kvm->lock);
5473 case KVM_GET_IRQCHIP: {
5474 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5475 struct kvm_irqchip *chip;
5477 chip = memdup_user(argp, sizeof(*chip));
5484 if (!irqchip_kernel(kvm))
5485 goto get_irqchip_out;
5486 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
5488 goto get_irqchip_out;
5490 if (copy_to_user(argp, chip, sizeof(*chip)))
5491 goto get_irqchip_out;
5497 case KVM_SET_IRQCHIP: {
5498 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
5499 struct kvm_irqchip *chip;
5501 chip = memdup_user(argp, sizeof(*chip));
5508 if (!irqchip_kernel(kvm))
5509 goto set_irqchip_out;
5510 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
5517 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
5520 if (!kvm->arch.vpit)
5522 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
5526 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
5533 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
5535 mutex_lock(&kvm->lock);
5537 if (!kvm->arch.vpit)
5539 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
5541 mutex_unlock(&kvm->lock);
5544 case KVM_GET_PIT2: {
5546 if (!kvm->arch.vpit)
5548 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5552 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5557 case KVM_SET_PIT2: {
5559 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5561 mutex_lock(&kvm->lock);
5563 if (!kvm->arch.vpit)
5565 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
5567 mutex_unlock(&kvm->lock);
5570 case KVM_REINJECT_CONTROL: {
5571 struct kvm_reinject_control control;
5573 if (copy_from_user(&control, argp, sizeof(control)))
5576 if (!kvm->arch.vpit)
5578 r = kvm_vm_ioctl_reinject(kvm, &control);
5581 case KVM_SET_BOOT_CPU_ID:
5583 mutex_lock(&kvm->lock);
5584 if (kvm->created_vcpus)
5587 kvm->arch.bsp_vcpu_id = arg;
5588 mutex_unlock(&kvm->lock);
5590 case KVM_XEN_HVM_CONFIG: {
5591 struct kvm_xen_hvm_config xhc;
5593 if (copy_from_user(&xhc, argp, sizeof(xhc)))
5598 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
5602 case KVM_SET_CLOCK: {
5603 struct kvm_clock_data user_ns;
5607 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5616 * TODO: userspace has to take care of races with VCPU_RUN, so
5617 * kvm_gen_update_masterclock() can be cut down to locked
5618 * pvclock_update_vm_gtod_copy().
5620 kvm_gen_update_masterclock(kvm);
5621 now_ns = get_kvmclock_ns(kvm);
5622 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
5623 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
5626 case KVM_GET_CLOCK: {
5627 struct kvm_clock_data user_ns;
5630 now_ns = get_kvmclock_ns(kvm);
5631 user_ns.clock = now_ns;
5632 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
5633 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
5636 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5641 case KVM_MEMORY_ENCRYPT_OP: {
5643 if (kvm_x86_ops.mem_enc_op)
5644 r = kvm_x86_ops.mem_enc_op(kvm, argp);
5647 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5648 struct kvm_enc_region region;
5651 if (copy_from_user(®ion, argp, sizeof(region)))
5655 if (kvm_x86_ops.mem_enc_reg_region)
5656 r = kvm_x86_ops.mem_enc_reg_region(kvm, ®ion);
5659 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5660 struct kvm_enc_region region;
5663 if (copy_from_user(®ion, argp, sizeof(region)))
5667 if (kvm_x86_ops.mem_enc_unreg_region)
5668 r = kvm_x86_ops.mem_enc_unreg_region(kvm, ®ion);
5671 case KVM_HYPERV_EVENTFD: {
5672 struct kvm_hyperv_eventfd hvevfd;
5675 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5677 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5680 case KVM_SET_PMU_EVENT_FILTER:
5681 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5683 case KVM_X86_SET_MSR_FILTER:
5684 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
5693 static void kvm_init_msr_list(void)
5695 struct x86_pmu_capability x86_pmu;
5699 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5700 "Please update the fixed PMCs in msrs_to_saved_all[]");
5702 perf_get_x86_pmu_capability(&x86_pmu);
5704 num_msrs_to_save = 0;
5705 num_emulated_msrs = 0;
5706 num_msr_based_features = 0;
5708 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5709 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
5713 * Even MSRs that are valid in the host may not be exposed
5714 * to the guests in some cases.
5716 switch (msrs_to_save_all[i]) {
5717 case MSR_IA32_BNDCFGS:
5718 if (!kvm_mpx_supported())
5722 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP))
5725 case MSR_IA32_UMWAIT_CONTROL:
5726 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
5729 case MSR_IA32_RTIT_CTL:
5730 case MSR_IA32_RTIT_STATUS:
5731 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
5734 case MSR_IA32_RTIT_CR3_MATCH:
5735 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5736 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5739 case MSR_IA32_RTIT_OUTPUT_BASE:
5740 case MSR_IA32_RTIT_OUTPUT_MASK:
5741 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5742 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5743 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5746 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
5747 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
5748 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
5749 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5752 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
5753 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
5754 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5757 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
5758 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
5759 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5766 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
5769 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5770 if (!kvm_x86_ops.has_emulated_msr(emulated_msrs_all[i]))
5773 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
5776 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
5777 struct kvm_msr_entry msr;
5779 msr.index = msr_based_features_all[i];
5780 if (kvm_get_msr_feature(&msr))
5783 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
5787 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5795 if (!(lapic_in_kernel(vcpu) &&
5796 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5797 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
5808 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
5815 if (!(lapic_in_kernel(vcpu) &&
5816 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5818 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
5820 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
5830 static void kvm_set_segment(struct kvm_vcpu *vcpu,
5831 struct kvm_segment *var, int seg)
5833 kvm_x86_ops.set_segment(vcpu, var, seg);
5836 void kvm_get_segment(struct kvm_vcpu *vcpu,
5837 struct kvm_segment *var, int seg)
5839 kvm_x86_ops.get_segment(vcpu, var, seg);
5842 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5843 struct x86_exception *exception)
5847 BUG_ON(!mmu_is_nested(vcpu));
5849 /* NPT walks are always user-walks */
5850 access |= PFERR_USER_MASK;
5851 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
5856 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5857 struct x86_exception *exception)
5859 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5860 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5863 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5864 struct x86_exception *exception)
5866 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5867 access |= PFERR_FETCH_MASK;
5868 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5871 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5872 struct x86_exception *exception)
5874 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5875 access |= PFERR_WRITE_MASK;
5876 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5879 /* uses this to access any guest's mapped memory without checking CPL */
5880 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5881 struct x86_exception *exception)
5883 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
5886 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5887 struct kvm_vcpu *vcpu, u32 access,
5888 struct x86_exception *exception)
5891 int r = X86EMUL_CONTINUE;
5894 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
5896 unsigned offset = addr & (PAGE_SIZE-1);
5897 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
5900 if (gpa == UNMAPPED_GVA)
5901 return X86EMUL_PROPAGATE_FAULT;
5902 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5905 r = X86EMUL_IO_NEEDED;
5917 /* used for instruction fetching */
5918 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5919 gva_t addr, void *val, unsigned int bytes,
5920 struct x86_exception *exception)
5922 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5923 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5927 /* Inline kvm_read_guest_virt_helper for speed. */
5928 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5930 if (unlikely(gpa == UNMAPPED_GVA))
5931 return X86EMUL_PROPAGATE_FAULT;
5933 offset = addr & (PAGE_SIZE-1);
5934 if (WARN_ON(offset + bytes > PAGE_SIZE))
5935 bytes = (unsigned)PAGE_SIZE - offset;
5936 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5938 if (unlikely(ret < 0))
5939 return X86EMUL_IO_NEEDED;
5941 return X86EMUL_CONTINUE;
5944 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
5945 gva_t addr, void *val, unsigned int bytes,
5946 struct x86_exception *exception)
5948 u32 access = (kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5951 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5952 * is returned, but our callers are not ready for that and they blindly
5953 * call kvm_inject_page_fault. Ensure that they at least do not leak
5954 * uninitialized kernel stack memory into cr2 and error code.
5956 memset(exception, 0, sizeof(*exception));
5957 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
5960 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
5962 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5963 gva_t addr, void *val, unsigned int bytes,
5964 struct x86_exception *exception, bool system)
5966 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5969 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
5970 access |= PFERR_USER_MASK;
5972 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
5975 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5976 unsigned long addr, void *val, unsigned int bytes)
5978 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5979 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5981 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5984 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5985 struct kvm_vcpu *vcpu, u32 access,
5986 struct x86_exception *exception)
5989 int r = X86EMUL_CONTINUE;
5992 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
5995 unsigned offset = addr & (PAGE_SIZE-1);
5996 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5999 if (gpa == UNMAPPED_GVA)
6000 return X86EMUL_PROPAGATE_FAULT;
6001 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6003 r = X86EMUL_IO_NEEDED;
6015 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6016 unsigned int bytes, struct x86_exception *exception,
6019 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6020 u32 access = PFERR_WRITE_MASK;
6022 if (!system && kvm_x86_ops.get_cpl(vcpu) == 3)
6023 access |= PFERR_USER_MASK;
6025 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6029 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6030 unsigned int bytes, struct x86_exception *exception)
6032 /* kvm_write_guest_virt_system can pull in tons of pages. */
6033 vcpu->arch.l1tf_flush_l1d = true;
6035 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6036 PFERR_WRITE_MASK, exception);
6038 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6040 int handle_ud(struct kvm_vcpu *vcpu)
6042 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6043 int emul_type = EMULTYPE_TRAP_UD;
6044 char sig[5]; /* ud2; .ascii "kvm" */
6045 struct x86_exception e;
6047 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, NULL, 0)))
6050 if (force_emulation_prefix &&
6051 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6052 sig, sizeof(sig), &e) == 0 &&
6053 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6054 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6055 emul_type = EMULTYPE_TRAP_UD_FORCED;
6058 return kvm_emulate_instruction(vcpu, emul_type);
6060 EXPORT_SYMBOL_GPL(handle_ud);
6062 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6063 gpa_t gpa, bool write)
6065 /* For APIC access vmexit */
6066 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6069 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6070 trace_vcpu_match_mmio(gva, gpa, write, true);
6077 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6078 gpa_t *gpa, struct x86_exception *exception,
6081 u32 access = ((kvm_x86_ops.get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
6082 | (write ? PFERR_WRITE_MASK : 0);
6085 * currently PKRU is only applied to ept enabled guest so
6086 * there is no pkey in EPT page table for L1 guest or EPT
6087 * shadow page table for L2 guest.
6089 if (vcpu_match_mmio_gva(vcpu, gva)
6090 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
6091 vcpu->arch.mmio_access, 0, access)) {
6092 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6093 (gva & (PAGE_SIZE - 1));
6094 trace_vcpu_match_mmio(gva, *gpa, write, false);
6098 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
6100 if (*gpa == UNMAPPED_GVA)
6103 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6106 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6107 const void *val, int bytes)
6111 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
6114 kvm_page_track_write(vcpu, gpa, val, bytes);
6118 struct read_write_emulator_ops {
6119 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
6121 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
6122 void *val, int bytes);
6123 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6124 int bytes, void *val);
6125 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
6126 void *val, int bytes);
6130 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
6132 if (vcpu->mmio_read_completed) {
6133 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
6134 vcpu->mmio_fragments[0].gpa, val);
6135 vcpu->mmio_read_completed = 0;
6142 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6143 void *val, int bytes)
6145 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
6148 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
6149 void *val, int bytes)
6151 return emulator_write_phys(vcpu, gpa, val, bytes);
6154 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
6156 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
6157 return vcpu_mmio_write(vcpu, gpa, bytes, val);
6160 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6161 void *val, int bytes)
6163 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
6164 return X86EMUL_IO_NEEDED;
6167 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
6168 void *val, int bytes)
6170 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
6172 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
6173 return X86EMUL_CONTINUE;
6176 static const struct read_write_emulator_ops read_emultor = {
6177 .read_write_prepare = read_prepare,
6178 .read_write_emulate = read_emulate,
6179 .read_write_mmio = vcpu_mmio_read,
6180 .read_write_exit_mmio = read_exit_mmio,
6183 static const struct read_write_emulator_ops write_emultor = {
6184 .read_write_emulate = write_emulate,
6185 .read_write_mmio = write_mmio,
6186 .read_write_exit_mmio = write_exit_mmio,
6190 static int emulator_read_write_onepage(unsigned long addr, void *val,
6192 struct x86_exception *exception,
6193 struct kvm_vcpu *vcpu,
6194 const struct read_write_emulator_ops *ops)
6198 bool write = ops->write;
6199 struct kvm_mmio_fragment *frag;
6200 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6203 * If the exit was due to a NPF we may already have a GPA.
6204 * If the GPA is present, use it to avoid the GVA to GPA table walk.
6205 * Note, this cannot be used on string operations since string
6206 * operation using rep will only have the initial GPA from the NPF
6209 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
6210 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
6211 gpa = ctxt->gpa_val;
6212 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
6214 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
6216 return X86EMUL_PROPAGATE_FAULT;
6219 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
6220 return X86EMUL_CONTINUE;
6223 * Is this MMIO handled locally?
6225 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
6226 if (handled == bytes)
6227 return X86EMUL_CONTINUE;
6233 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
6234 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
6238 return X86EMUL_CONTINUE;
6241 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
6243 void *val, unsigned int bytes,
6244 struct x86_exception *exception,
6245 const struct read_write_emulator_ops *ops)
6247 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6251 if (ops->read_write_prepare &&
6252 ops->read_write_prepare(vcpu, val, bytes))
6253 return X86EMUL_CONTINUE;
6255 vcpu->mmio_nr_fragments = 0;
6257 /* Crossing a page boundary? */
6258 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
6261 now = -addr & ~PAGE_MASK;
6262 rc = emulator_read_write_onepage(addr, val, now, exception,
6265 if (rc != X86EMUL_CONTINUE)
6268 if (ctxt->mode != X86EMUL_MODE_PROT64)
6274 rc = emulator_read_write_onepage(addr, val, bytes, exception,
6276 if (rc != X86EMUL_CONTINUE)
6279 if (!vcpu->mmio_nr_fragments)
6282 gpa = vcpu->mmio_fragments[0].gpa;
6284 vcpu->mmio_needed = 1;
6285 vcpu->mmio_cur_fragment = 0;
6287 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
6288 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
6289 vcpu->run->exit_reason = KVM_EXIT_MMIO;
6290 vcpu->run->mmio.phys_addr = gpa;
6292 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
6295 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
6299 struct x86_exception *exception)
6301 return emulator_read_write(ctxt, addr, val, bytes,
6302 exception, &read_emultor);
6305 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
6309 struct x86_exception *exception)
6311 return emulator_read_write(ctxt, addr, (void *)val, bytes,
6312 exception, &write_emultor);
6315 #define CMPXCHG_TYPE(t, ptr, old, new) \
6316 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
6318 #ifdef CONFIG_X86_64
6319 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
6321 # define CMPXCHG64(ptr, old, new) \
6322 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
6325 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
6330 struct x86_exception *exception)
6332 struct kvm_host_map map;
6333 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6339 /* guests cmpxchg8b have to be emulated atomically */
6340 if (bytes > 8 || (bytes & (bytes - 1)))
6343 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
6345 if (gpa == UNMAPPED_GVA ||
6346 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6350 * Emulate the atomic as a straight write to avoid #AC if SLD is
6351 * enabled in the host and the access splits a cache line.
6353 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
6354 page_line_mask = ~(cache_line_size() - 1);
6356 page_line_mask = PAGE_MASK;
6358 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
6361 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
6364 kaddr = map.hva + offset_in_page(gpa);
6368 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
6371 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
6374 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
6377 exchanged = CMPXCHG64(kaddr, old, new);
6383 kvm_vcpu_unmap(vcpu, &map, true);
6386 return X86EMUL_CMPXCHG_FAILED;
6388 kvm_page_track_write(vcpu, gpa, new, bytes);
6390 return X86EMUL_CONTINUE;
6393 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
6395 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
6398 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
6402 for (i = 0; i < vcpu->arch.pio.count; i++) {
6403 if (vcpu->arch.pio.in)
6404 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
6405 vcpu->arch.pio.size, pd);
6407 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
6408 vcpu->arch.pio.port, vcpu->arch.pio.size,
6412 pd += vcpu->arch.pio.size;
6417 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
6418 unsigned short port, void *val,
6419 unsigned int count, bool in)
6421 vcpu->arch.pio.port = port;
6422 vcpu->arch.pio.in = in;
6423 vcpu->arch.pio.count = count;
6424 vcpu->arch.pio.size = size;
6426 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
6427 vcpu->arch.pio.count = 0;
6431 vcpu->run->exit_reason = KVM_EXIT_IO;
6432 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
6433 vcpu->run->io.size = size;
6434 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
6435 vcpu->run->io.count = count;
6436 vcpu->run->io.port = port;
6441 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
6442 unsigned short port, void *val, unsigned int count)
6446 if (vcpu->arch.pio.count)
6449 memset(vcpu->arch.pio_data, 0, size * count);
6451 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
6454 memcpy(val, vcpu->arch.pio_data, size * count);
6455 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
6456 vcpu->arch.pio.count = 0;
6463 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
6464 int size, unsigned short port, void *val,
6467 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
6471 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
6472 unsigned short port, const void *val,
6475 memcpy(vcpu->arch.pio_data, val, size * count);
6476 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6477 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
6480 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
6481 int size, unsigned short port,
6482 const void *val, unsigned int count)
6484 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
6487 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
6489 return kvm_x86_ops.get_segment_base(vcpu, seg);
6492 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
6494 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
6497 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
6499 if (!need_emulate_wbinvd(vcpu))
6500 return X86EMUL_CONTINUE;
6502 if (kvm_x86_ops.has_wbinvd_exit()) {
6503 int cpu = get_cpu();
6505 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
6506 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6507 wbinvd_ipi, NULL, 1);
6509 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
6512 return X86EMUL_CONTINUE;
6515 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6517 kvm_emulate_wbinvd_noskip(vcpu);
6518 return kvm_skip_emulated_instruction(vcpu);
6520 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6524 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6526 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
6529 static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6530 unsigned long *dest)
6532 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
6535 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6536 unsigned long value)
6539 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
6542 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
6544 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
6547 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
6549 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6550 unsigned long value;
6554 value = kvm_read_cr0(vcpu);
6557 value = vcpu->arch.cr2;
6560 value = kvm_read_cr3(vcpu);
6563 value = kvm_read_cr4(vcpu);
6566 value = kvm_get_cr8(vcpu);
6569 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6576 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
6578 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6583 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
6586 vcpu->arch.cr2 = val;
6589 res = kvm_set_cr3(vcpu, val);
6592 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
6595 res = kvm_set_cr8(vcpu, val);
6598 kvm_err("%s: unexpected cr %u\n", __func__, cr);
6605 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
6607 return kvm_x86_ops.get_cpl(emul_to_vcpu(ctxt));
6610 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6612 kvm_x86_ops.get_gdt(emul_to_vcpu(ctxt), dt);
6615 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6617 kvm_x86_ops.get_idt(emul_to_vcpu(ctxt), dt);
6620 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6622 kvm_x86_ops.set_gdt(emul_to_vcpu(ctxt), dt);
6625 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6627 kvm_x86_ops.set_idt(emul_to_vcpu(ctxt), dt);
6630 static unsigned long emulator_get_cached_segment_base(
6631 struct x86_emulate_ctxt *ctxt, int seg)
6633 return get_segment_base(emul_to_vcpu(ctxt), seg);
6636 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6637 struct desc_struct *desc, u32 *base3,
6640 struct kvm_segment var;
6642 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
6643 *selector = var.selector;
6646 memset(desc, 0, sizeof(*desc));
6654 set_desc_limit(desc, var.limit);
6655 set_desc_base(desc, (unsigned long)var.base);
6656 #ifdef CONFIG_X86_64
6658 *base3 = var.base >> 32;
6660 desc->type = var.type;
6662 desc->dpl = var.dpl;
6663 desc->p = var.present;
6664 desc->avl = var.avl;
6672 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6673 struct desc_struct *desc, u32 base3,
6676 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6677 struct kvm_segment var;
6679 var.selector = selector;
6680 var.base = get_desc_base(desc);
6681 #ifdef CONFIG_X86_64
6682 var.base |= ((u64)base3) << 32;
6684 var.limit = get_desc_limit(desc);
6686 var.limit = (var.limit << 12) | 0xfff;
6687 var.type = desc->type;
6688 var.dpl = desc->dpl;
6693 var.avl = desc->avl;
6694 var.present = desc->p;
6695 var.unusable = !var.present;
6698 kvm_set_segment(vcpu, &var, seg);
6702 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6703 u32 msr_index, u64 *pdata)
6705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6708 r = kvm_get_msr(vcpu, msr_index, pdata);
6710 if (r && kvm_get_msr_user_space(vcpu, msr_index, r)) {
6711 /* Bounce to user space */
6712 return X86EMUL_IO_NEEDED;
6718 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6719 u32 msr_index, u64 data)
6721 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6724 r = kvm_set_msr(vcpu, msr_index, data);
6726 if (r && kvm_set_msr_user_space(vcpu, msr_index, data, r)) {
6727 /* Bounce to user space */
6728 return X86EMUL_IO_NEEDED;
6734 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6736 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6738 return vcpu->arch.smbase;
6741 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6743 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6745 vcpu->arch.smbase = smbase;
6748 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6751 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
6754 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6755 u32 pmc, u64 *pdata)
6757 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
6760 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6762 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6765 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
6766 struct x86_instruction_info *info,
6767 enum x86_intercept_stage stage)
6769 return kvm_x86_ops.check_intercept(emul_to_vcpu(ctxt), info, stage,
6773 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6774 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
6777 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
6780 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6782 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6785 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6787 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6790 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6792 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6795 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6797 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6800 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6802 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6805 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6807 kvm_x86_ops.set_nmi_mask(emul_to_vcpu(ctxt), masked);
6810 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6812 return emul_to_vcpu(ctxt)->arch.hflags;
6815 static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6817 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6820 static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6821 const char *smstate)
6823 return kvm_x86_ops.pre_leave_smm(emul_to_vcpu(ctxt), smstate);
6826 static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6828 kvm_smm_changed(emul_to_vcpu(ctxt));
6831 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6833 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6836 static const struct x86_emulate_ops emulate_ops = {
6837 .read_gpr = emulator_read_gpr,
6838 .write_gpr = emulator_write_gpr,
6839 .read_std = emulator_read_std,
6840 .write_std = emulator_write_std,
6841 .read_phys = kvm_read_guest_phys_system,
6842 .fetch = kvm_fetch_guest_virt,
6843 .read_emulated = emulator_read_emulated,
6844 .write_emulated = emulator_write_emulated,
6845 .cmpxchg_emulated = emulator_cmpxchg_emulated,
6846 .invlpg = emulator_invlpg,
6847 .pio_in_emulated = emulator_pio_in_emulated,
6848 .pio_out_emulated = emulator_pio_out_emulated,
6849 .get_segment = emulator_get_segment,
6850 .set_segment = emulator_set_segment,
6851 .get_cached_segment_base = emulator_get_cached_segment_base,
6852 .get_gdt = emulator_get_gdt,
6853 .get_idt = emulator_get_idt,
6854 .set_gdt = emulator_set_gdt,
6855 .set_idt = emulator_set_idt,
6856 .get_cr = emulator_get_cr,
6857 .set_cr = emulator_set_cr,
6858 .cpl = emulator_get_cpl,
6859 .get_dr = emulator_get_dr,
6860 .set_dr = emulator_set_dr,
6861 .get_smbase = emulator_get_smbase,
6862 .set_smbase = emulator_set_smbase,
6863 .set_msr = emulator_set_msr,
6864 .get_msr = emulator_get_msr,
6865 .check_pmc = emulator_check_pmc,
6866 .read_pmc = emulator_read_pmc,
6867 .halt = emulator_halt,
6868 .wbinvd = emulator_wbinvd,
6869 .fix_hypercall = emulator_fix_hypercall,
6870 .intercept = emulator_intercept,
6871 .get_cpuid = emulator_get_cpuid,
6872 .guest_has_long_mode = emulator_guest_has_long_mode,
6873 .guest_has_movbe = emulator_guest_has_movbe,
6874 .guest_has_fxsr = emulator_guest_has_fxsr,
6875 .set_nmi_mask = emulator_set_nmi_mask,
6876 .get_hflags = emulator_get_hflags,
6877 .set_hflags = emulator_set_hflags,
6878 .pre_leave_smm = emulator_pre_leave_smm,
6879 .post_leave_smm = emulator_post_leave_smm,
6880 .set_xcr = emulator_set_xcr,
6883 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6885 u32 int_shadow = kvm_x86_ops.get_interrupt_shadow(vcpu);
6887 * an sti; sti; sequence only disable interrupts for the first
6888 * instruction. So, if the last instruction, be it emulated or
6889 * not, left the system with the INT_STI flag enabled, it
6890 * means that the last instruction is an sti. We should not
6891 * leave the flag on in this case. The same goes for mov ss
6893 if (int_shadow & mask)
6895 if (unlikely(int_shadow || mask)) {
6896 kvm_x86_ops.set_interrupt_shadow(vcpu, mask);
6898 kvm_make_request(KVM_REQ_EVENT, vcpu);
6902 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
6904 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6905 if (ctxt->exception.vector == PF_VECTOR)
6906 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
6908 if (ctxt->exception.error_code_valid)
6909 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6910 ctxt->exception.error_code);
6912 kvm_queue_exception(vcpu, ctxt->exception.vector);
6916 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
6918 struct x86_emulate_ctxt *ctxt;
6920 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
6922 pr_err("kvm: failed to allocate vcpu's emulator\n");
6927 ctxt->ops = &emulate_ops;
6928 vcpu->arch.emulate_ctxt = ctxt;
6933 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6935 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6938 kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6940 ctxt->gpa_available = false;
6941 ctxt->eflags = kvm_get_rflags(vcpu);
6942 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6944 ctxt->eip = kvm_rip_read(vcpu);
6945 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6946 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
6947 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
6948 cs_db ? X86EMUL_MODE_PROT32 :
6949 X86EMUL_MODE_PROT16;
6950 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
6951 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6952 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
6954 init_decode_cache(ctxt);
6955 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
6958 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
6960 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
6963 init_emulate_ctxt(vcpu);
6967 ctxt->_eip = ctxt->eip + inc_eip;
6968 ret = emulate_int_real(ctxt, irq);
6970 if (ret != X86EMUL_CONTINUE) {
6971 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6973 ctxt->eip = ctxt->_eip;
6974 kvm_rip_write(vcpu, ctxt->eip);
6975 kvm_set_rflags(vcpu, ctxt->eflags);
6978 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6980 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6982 ++vcpu->stat.insn_emulation_fail;
6983 trace_kvm_emulate_insn_failed(vcpu);
6985 if (emulation_type & EMULTYPE_VMWARE_GP) {
6986 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6990 if (emulation_type & EMULTYPE_SKIP) {
6991 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6992 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6993 vcpu->run->internal.ndata = 0;
6997 kvm_queue_exception(vcpu, UD_VECTOR);
6999 if (!is_guest_mode(vcpu) && kvm_x86_ops.get_cpl(vcpu) == 0) {
7000 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7001 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
7002 vcpu->run->internal.ndata = 0;
7009 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7010 bool write_fault_to_shadow_pgtable,
7013 gpa_t gpa = cr2_or_gpa;
7016 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7019 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7020 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7023 if (!vcpu->arch.mmu->direct_map) {
7025 * Write permission should be allowed since only
7026 * write access need to be emulated.
7028 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7031 * If the mapping is invalid in guest, let cpu retry
7032 * it to generate fault.
7034 if (gpa == UNMAPPED_GVA)
7039 * Do not retry the unhandleable instruction if it faults on the
7040 * readonly host memory, otherwise it will goto a infinite loop:
7041 * retry instruction -> write #PF -> emulation fail -> retry
7042 * instruction -> ...
7044 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
7047 * If the instruction failed on the error pfn, it can not be fixed,
7048 * report the error to userspace.
7050 if (is_error_noslot_pfn(pfn))
7053 kvm_release_pfn_clean(pfn);
7055 /* The instructions are well-emulated on direct mmu. */
7056 if (vcpu->arch.mmu->direct_map) {
7057 unsigned int indirect_shadow_pages;
7059 spin_lock(&vcpu->kvm->mmu_lock);
7060 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
7061 spin_unlock(&vcpu->kvm->mmu_lock);
7063 if (indirect_shadow_pages)
7064 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7070 * if emulation was due to access to shadowed page table
7071 * and it failed try to unshadow page and re-enter the
7072 * guest to let CPU execute the instruction.
7074 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7077 * If the access faults on its page table, it can not
7078 * be fixed by unprotecting shadow page and it should
7079 * be reported to userspace.
7081 return !write_fault_to_shadow_pgtable;
7084 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
7085 gpa_t cr2_or_gpa, int emulation_type)
7087 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7088 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
7090 last_retry_eip = vcpu->arch.last_retry_eip;
7091 last_retry_addr = vcpu->arch.last_retry_addr;
7094 * If the emulation is caused by #PF and it is non-page_table
7095 * writing instruction, it means the VM-EXIT is caused by shadow
7096 * page protected, we can zap the shadow page and retry this
7097 * instruction directly.
7099 * Note: if the guest uses a non-page-table modifying instruction
7100 * on the PDE that points to the instruction, then we will unmap
7101 * the instruction and go to an infinite loop. So, we cache the
7102 * last retried eip and the last fault address, if we meet the eip
7103 * and the address again, we can break out of the potential infinite
7106 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
7108 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
7111 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
7112 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
7115 if (x86_page_table_writing_insn(ctxt))
7118 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
7121 vcpu->arch.last_retry_eip = ctxt->eip;
7122 vcpu->arch.last_retry_addr = cr2_or_gpa;
7124 if (!vcpu->arch.mmu->direct_map)
7125 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
7127 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
7132 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
7133 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
7135 static void kvm_smm_changed(struct kvm_vcpu *vcpu)
7137 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
7138 /* This is a good place to trace that we are exiting SMM. */
7139 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
7141 /* Process a latched INIT or SMI, if any. */
7142 kvm_make_request(KVM_REQ_EVENT, vcpu);
7145 kvm_mmu_reset_context(vcpu);
7148 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
7157 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
7158 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
7163 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
7165 struct kvm_run *kvm_run = vcpu->run;
7167 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
7168 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
7169 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
7170 kvm_run->debug.arch.exception = DB_VECTOR;
7171 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7174 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
7178 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
7180 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7183 r = kvm_x86_ops.skip_emulated_instruction(vcpu);
7188 * rflags is the old, "raw" value of the flags. The new value has
7189 * not been saved yet.
7191 * This is correct even for TF set by the guest, because "the
7192 * processor will not generate this exception after the instruction
7193 * that sets the TF flag".
7195 if (unlikely(rflags & X86_EFLAGS_TF))
7196 r = kvm_vcpu_do_singlestep(vcpu);
7199 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
7201 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
7203 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
7204 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
7205 struct kvm_run *kvm_run = vcpu->run;
7206 unsigned long eip = kvm_get_linear_rip(vcpu);
7207 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7208 vcpu->arch.guest_debug_dr7,
7212 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
7213 kvm_run->debug.arch.pc = eip;
7214 kvm_run->debug.arch.exception = DB_VECTOR;
7215 kvm_run->exit_reason = KVM_EXIT_DEBUG;
7221 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
7222 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
7223 unsigned long eip = kvm_get_linear_rip(vcpu);
7224 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
7229 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
7238 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
7240 switch (ctxt->opcode_len) {
7247 case 0xe6: /* OUT */
7251 case 0x6c: /* INS */
7253 case 0x6e: /* OUTS */
7260 case 0x33: /* RDPMC */
7269 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
7270 int emulation_type, void *insn, int insn_len)
7273 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7274 bool writeback = true;
7275 bool write_fault_to_spt;
7277 if (unlikely(!kvm_x86_ops.can_emulate_instruction(vcpu, insn, insn_len)))
7280 vcpu->arch.l1tf_flush_l1d = true;
7283 * Clear write_fault_to_shadow_pgtable here to ensure it is
7286 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
7287 vcpu->arch.write_fault_to_shadow_pgtable = false;
7288 kvm_clear_exception_queue(vcpu);
7290 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
7291 init_emulate_ctxt(vcpu);
7294 * We will reenter on the same instruction since
7295 * we do not set complete_userspace_io. This does not
7296 * handle watchpoints yet, those would be handled in
7299 if (!(emulation_type & EMULTYPE_SKIP) &&
7300 kvm_vcpu_check_breakpoint(vcpu, &r))
7303 ctxt->interruptibility = 0;
7304 ctxt->have_exception = false;
7305 ctxt->exception.vector = -1;
7306 ctxt->perm_ok = false;
7308 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
7310 r = x86_decode_insn(ctxt, insn, insn_len);
7312 trace_kvm_emulate_insn_start(vcpu);
7313 ++vcpu->stat.insn_emulation;
7314 if (r != EMULATION_OK) {
7315 if ((emulation_type & EMULTYPE_TRAP_UD) ||
7316 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
7317 kvm_queue_exception(vcpu, UD_VECTOR);
7320 if (reexecute_instruction(vcpu, cr2_or_gpa,
7324 if (ctxt->have_exception) {
7326 * #UD should result in just EMULATION_FAILED, and trap-like
7327 * exception should not be encountered during decode.
7329 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
7330 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
7331 inject_emulated_exception(vcpu);
7334 return handle_emulation_failure(vcpu, emulation_type);
7338 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
7339 !is_vmware_backdoor_opcode(ctxt)) {
7340 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7345 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
7346 * for kvm_skip_emulated_instruction(). The caller is responsible for
7347 * updating interruptibility state and injecting single-step #DBs.
7349 if (emulation_type & EMULTYPE_SKIP) {
7350 kvm_rip_write(vcpu, ctxt->_eip);
7351 if (ctxt->eflags & X86_EFLAGS_RF)
7352 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
7356 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
7359 /* this is needed for vmware backdoor interface to work since it
7360 changes registers values during IO operation */
7361 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
7362 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7363 emulator_invalidate_register_cache(ctxt);
7367 if (emulation_type & EMULTYPE_PF) {
7368 /* Save the faulting GPA (cr2) in the address field */
7369 ctxt->exception.address = cr2_or_gpa;
7371 /* With shadow page tables, cr2 contains a GVA or nGPA. */
7372 if (vcpu->arch.mmu->direct_map) {
7373 ctxt->gpa_available = true;
7374 ctxt->gpa_val = cr2_or_gpa;
7377 /* Sanitize the address out of an abundance of paranoia. */
7378 ctxt->exception.address = 0;
7381 r = x86_emulate_insn(ctxt);
7383 if (r == EMULATION_INTERCEPTED)
7386 if (r == EMULATION_FAILED) {
7387 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
7391 return handle_emulation_failure(vcpu, emulation_type);
7394 if (ctxt->have_exception) {
7396 if (inject_emulated_exception(vcpu))
7398 } else if (vcpu->arch.pio.count) {
7399 if (!vcpu->arch.pio.in) {
7400 /* FIXME: return into emulator if single-stepping. */
7401 vcpu->arch.pio.count = 0;
7404 vcpu->arch.complete_userspace_io = complete_emulated_pio;
7407 } else if (vcpu->mmio_needed) {
7408 ++vcpu->stat.mmio_exits;
7410 if (!vcpu->mmio_is_write)
7413 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7414 } else if (r == EMULATION_RESTART)
7420 unsigned long rflags = kvm_x86_ops.get_rflags(vcpu);
7421 toggle_interruptibility(vcpu, ctxt->interruptibility);
7422 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7423 if (!ctxt->have_exception ||
7424 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
7425 kvm_rip_write(vcpu, ctxt->eip);
7426 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
7427 r = kvm_vcpu_do_singlestep(vcpu);
7428 if (kvm_x86_ops.update_emulated_instruction)
7429 kvm_x86_ops.update_emulated_instruction(vcpu);
7430 __kvm_set_rflags(vcpu, ctxt->eflags);
7434 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
7435 * do nothing, and it will be requested again as soon as
7436 * the shadow expires. But we still need to check here,
7437 * because POPF has no interrupt shadow.
7439 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
7440 kvm_make_request(KVM_REQ_EVENT, vcpu);
7442 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
7447 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
7449 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
7451 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
7453 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
7454 void *insn, int insn_len)
7456 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
7458 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
7460 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
7462 vcpu->arch.pio.count = 0;
7466 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
7468 vcpu->arch.pio.count = 0;
7470 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
7473 return kvm_skip_emulated_instruction(vcpu);
7476 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
7477 unsigned short port)
7479 unsigned long val = kvm_rax_read(vcpu);
7480 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
7486 * Workaround userspace that relies on old KVM behavior of %rip being
7487 * incremented prior to exiting to userspace to handle "OUT 0x7e".
7490 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
7491 vcpu->arch.complete_userspace_io =
7492 complete_fast_pio_out_port_0x7e;
7493 kvm_skip_emulated_instruction(vcpu);
7495 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7496 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
7501 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
7505 /* We should only ever be called with arch.pio.count equal to 1 */
7506 BUG_ON(vcpu->arch.pio.count != 1);
7508 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
7509 vcpu->arch.pio.count = 0;
7513 /* For size less than 4 we merge, else we zero extend */
7514 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
7517 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
7518 * the copy and tracing
7520 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
7521 kvm_rax_write(vcpu, val);
7523 return kvm_skip_emulated_instruction(vcpu);
7526 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
7527 unsigned short port)
7532 /* For size less than 4 we merge, else we zero extend */
7533 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
7535 ret = emulator_pio_in(vcpu, size, port, &val, 1);
7537 kvm_rax_write(vcpu, val);
7541 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
7542 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
7547 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
7552 ret = kvm_fast_pio_in(vcpu, size, port);
7554 ret = kvm_fast_pio_out(vcpu, size, port);
7555 return ret && kvm_skip_emulated_instruction(vcpu);
7557 EXPORT_SYMBOL_GPL(kvm_fast_pio);
7559 static int kvmclock_cpu_down_prep(unsigned int cpu)
7561 __this_cpu_write(cpu_tsc_khz, 0);
7565 static void tsc_khz_changed(void *data)
7567 struct cpufreq_freqs *freq = data;
7568 unsigned long khz = 0;
7572 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7573 khz = cpufreq_quick_get(raw_smp_processor_id());
7576 __this_cpu_write(cpu_tsc_khz, khz);
7579 #ifdef CONFIG_X86_64
7580 static void kvm_hyperv_tsc_notifier(void)
7583 struct kvm_vcpu *vcpu;
7586 mutex_lock(&kvm_lock);
7587 list_for_each_entry(kvm, &vm_list, vm_list)
7588 kvm_make_mclock_inprogress_request(kvm);
7590 hyperv_stop_tsc_emulation();
7592 /* TSC frequency always matches when on Hyper-V */
7593 for_each_present_cpu(cpu)
7594 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7595 kvm_max_guest_tsc_khz = tsc_khz;
7597 list_for_each_entry(kvm, &vm_list, vm_list) {
7598 struct kvm_arch *ka = &kvm->arch;
7600 spin_lock(&ka->pvclock_gtod_sync_lock);
7602 pvclock_update_vm_gtod_copy(kvm);
7604 kvm_for_each_vcpu(cpu, vcpu, kvm)
7605 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7607 kvm_for_each_vcpu(cpu, vcpu, kvm)
7608 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7610 spin_unlock(&ka->pvclock_gtod_sync_lock);
7612 mutex_unlock(&kvm_lock);
7616 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
7619 struct kvm_vcpu *vcpu;
7620 int i, send_ipi = 0;
7623 * We allow guests to temporarily run on slowing clocks,
7624 * provided we notify them after, or to run on accelerating
7625 * clocks, provided we notify them before. Thus time never
7628 * However, we have a problem. We can't atomically update
7629 * the frequency of a given CPU from this function; it is
7630 * merely a notifier, which can be called from any CPU.
7631 * Changing the TSC frequency at arbitrary points in time
7632 * requires a recomputation of local variables related to
7633 * the TSC for each VCPU. We must flag these local variables
7634 * to be updated and be sure the update takes place with the
7635 * new frequency before any guests proceed.
7637 * Unfortunately, the combination of hotplug CPU and frequency
7638 * change creates an intractable locking scenario; the order
7639 * of when these callouts happen is undefined with respect to
7640 * CPU hotplug, and they can race with each other. As such,
7641 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7642 * undefined; you can actually have a CPU frequency change take
7643 * place in between the computation of X and the setting of the
7644 * variable. To protect against this problem, all updates of
7645 * the per_cpu tsc_khz variable are done in an interrupt
7646 * protected IPI, and all callers wishing to update the value
7647 * must wait for a synchronous IPI to complete (which is trivial
7648 * if the caller is on the CPU already). This establishes the
7649 * necessary total order on variable updates.
7651 * Note that because a guest time update may take place
7652 * anytime after the setting of the VCPU's request bit, the
7653 * correct TSC value must be set before the request. However,
7654 * to ensure the update actually makes it to any guest which
7655 * starts running in hardware virtualization between the set
7656 * and the acquisition of the spinlock, we must also ping the
7657 * CPU after setting the request bit.
7661 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7663 mutex_lock(&kvm_lock);
7664 list_for_each_entry(kvm, &vm_list, vm_list) {
7665 kvm_for_each_vcpu(i, vcpu, kvm) {
7666 if (vcpu->cpu != cpu)
7668 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7669 if (vcpu->cpu != raw_smp_processor_id())
7673 mutex_unlock(&kvm_lock);
7675 if (freq->old < freq->new && send_ipi) {
7677 * We upscale the frequency. Must make the guest
7678 * doesn't see old kvmclock values while running with
7679 * the new frequency, otherwise we risk the guest sees
7680 * time go backwards.
7682 * In case we update the frequency for another cpu
7683 * (which might be in guest context) send an interrupt
7684 * to kick the cpu out of guest context. Next time
7685 * guest context is entered kvmclock will be updated,
7686 * so the guest will not see stale values.
7688 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
7692 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7695 struct cpufreq_freqs *freq = data;
7698 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7700 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7703 for_each_cpu(cpu, freq->policy->cpus)
7704 __kvmclock_cpufreq_notifier(freq, cpu);
7709 static struct notifier_block kvmclock_cpufreq_notifier_block = {
7710 .notifier_call = kvmclock_cpufreq_notifier
7713 static int kvmclock_cpu_online(unsigned int cpu)
7715 tsc_khz_changed(NULL);
7719 static void kvm_timer_init(void)
7721 max_tsc_khz = tsc_khz;
7723 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
7724 #ifdef CONFIG_CPU_FREQ
7725 struct cpufreq_policy *policy;
7729 policy = cpufreq_cpu_get(cpu);
7731 if (policy->cpuinfo.max_freq)
7732 max_tsc_khz = policy->cpuinfo.max_freq;
7733 cpufreq_cpu_put(policy);
7737 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7738 CPUFREQ_TRANSITION_NOTIFIER);
7741 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
7742 kvmclock_cpu_online, kvmclock_cpu_down_prep);
7745 DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7746 EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
7748 int kvm_is_in_guest(void)
7750 return __this_cpu_read(current_vcpu) != NULL;
7753 static int kvm_is_user_mode(void)
7757 if (__this_cpu_read(current_vcpu))
7758 user_mode = kvm_x86_ops.get_cpl(__this_cpu_read(current_vcpu));
7760 return user_mode != 0;
7763 static unsigned long kvm_get_guest_ip(void)
7765 unsigned long ip = 0;
7767 if (__this_cpu_read(current_vcpu))
7768 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
7773 static void kvm_handle_intel_pt_intr(void)
7775 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7777 kvm_make_request(KVM_REQ_PMI, vcpu);
7778 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7779 (unsigned long *)&vcpu->arch.pmu.global_status);
7782 static struct perf_guest_info_callbacks kvm_guest_cbs = {
7783 .is_in_guest = kvm_is_in_guest,
7784 .is_user_mode = kvm_is_user_mode,
7785 .get_guest_ip = kvm_get_guest_ip,
7786 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
7789 #ifdef CONFIG_X86_64
7790 static void pvclock_gtod_update_fn(struct work_struct *work)
7794 struct kvm_vcpu *vcpu;
7797 mutex_lock(&kvm_lock);
7798 list_for_each_entry(kvm, &vm_list, vm_list)
7799 kvm_for_each_vcpu(i, vcpu, kvm)
7800 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
7801 atomic_set(&kvm_guest_has_master_clock, 0);
7802 mutex_unlock(&kvm_lock);
7805 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7808 * Notification about pvclock gtod data update.
7810 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7813 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7814 struct timekeeper *tk = priv;
7816 update_pvclock_gtod(tk);
7818 /* disable master clock if host does not trust, or does not
7819 * use, TSC based clocksource.
7821 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
7822 atomic_read(&kvm_guest_has_master_clock) != 0)
7823 queue_work(system_long_wq, &pvclock_gtod_work);
7828 static struct notifier_block pvclock_gtod_notifier = {
7829 .notifier_call = pvclock_gtod_notify,
7833 int kvm_arch_init(void *opaque)
7835 struct kvm_x86_init_ops *ops = opaque;
7838 if (kvm_x86_ops.hardware_enable) {
7839 printk(KERN_ERR "kvm: already loaded the other module\n");
7844 if (!ops->cpu_has_kvm_support()) {
7845 pr_err_ratelimited("kvm: no hardware support\n");
7849 if (ops->disabled_by_bios()) {
7850 pr_err_ratelimited("kvm: disabled by bios\n");
7856 * KVM explicitly assumes that the guest has an FPU and
7857 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7858 * vCPU's FPU state as a fxregs_state struct.
7860 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7861 printk(KERN_ERR "kvm: inadequate fpu\n");
7867 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
7868 __alignof__(struct fpu), SLAB_ACCOUNT,
7870 if (!x86_fpu_cache) {
7871 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7875 x86_emulator_cache = kvm_alloc_emulator_cache();
7876 if (!x86_emulator_cache) {
7877 pr_err("kvm: failed to allocate cache for x86 emulator\n");
7878 goto out_free_x86_fpu_cache;
7881 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
7882 if (!user_return_msrs) {
7883 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
7884 goto out_free_x86_emulator_cache;
7887 r = kvm_mmu_module_init();
7889 goto out_free_percpu;
7891 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
7892 PT_DIRTY_MASK, PT64_NX_MASK, 0,
7893 PT_PRESENT_MASK, 0, sme_me_mask);
7896 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7898 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
7899 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7900 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
7904 if (pi_inject_timer == -1)
7905 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
7906 #ifdef CONFIG_X86_64
7907 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
7909 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7910 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
7916 free_percpu(user_return_msrs);
7917 out_free_x86_emulator_cache:
7918 kmem_cache_destroy(x86_emulator_cache);
7919 out_free_x86_fpu_cache:
7920 kmem_cache_destroy(x86_fpu_cache);
7925 void kvm_arch_exit(void)
7927 #ifdef CONFIG_X86_64
7928 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
7929 clear_hv_tscchange_cb();
7932 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7934 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7935 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7936 CPUFREQ_TRANSITION_NOTIFIER);
7937 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
7938 #ifdef CONFIG_X86_64
7939 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7941 kvm_x86_ops.hardware_enable = NULL;
7942 kvm_mmu_module_exit();
7943 free_percpu(user_return_msrs);
7944 kmem_cache_destroy(x86_fpu_cache);
7947 int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
7949 ++vcpu->stat.halt_exits;
7950 if (lapic_in_kernel(vcpu)) {
7951 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
7954 vcpu->run->exit_reason = KVM_EXIT_HLT;
7958 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7960 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7962 int ret = kvm_skip_emulated_instruction(vcpu);
7964 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7965 * KVM_EXIT_DEBUG here.
7967 return kvm_vcpu_halt(vcpu) && ret;
7969 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7971 #ifdef CONFIG_X86_64
7972 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7973 unsigned long clock_type)
7975 struct kvm_clock_pairing clock_pairing;
7976 struct timespec64 ts;
7980 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7981 return -KVM_EOPNOTSUPP;
7983 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7984 return -KVM_EOPNOTSUPP;
7986 clock_pairing.sec = ts.tv_sec;
7987 clock_pairing.nsec = ts.tv_nsec;
7988 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7989 clock_pairing.flags = 0;
7990 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
7993 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7994 sizeof(struct kvm_clock_pairing)))
8002 * kvm_pv_kick_cpu_op: Kick a vcpu.
8004 * @apicid - apicid of vcpu to be kicked.
8006 static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
8008 struct kvm_lapic_irq lapic_irq;
8010 lapic_irq.shorthand = APIC_DEST_NOSHORT;
8011 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
8012 lapic_irq.level = 0;
8013 lapic_irq.dest_id = apicid;
8014 lapic_irq.msi_redir_hint = false;
8016 lapic_irq.delivery_mode = APIC_DM_REMRD;
8017 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
8020 bool kvm_apicv_activated(struct kvm *kvm)
8022 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
8024 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
8026 void kvm_apicv_init(struct kvm *kvm, bool enable)
8029 clear_bit(APICV_INHIBIT_REASON_DISABLE,
8030 &kvm->arch.apicv_inhibit_reasons);
8032 set_bit(APICV_INHIBIT_REASON_DISABLE,
8033 &kvm->arch.apicv_inhibit_reasons);
8035 EXPORT_SYMBOL_GPL(kvm_apicv_init);
8037 static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
8039 struct kvm_vcpu *target = NULL;
8040 struct kvm_apic_map *map;
8043 map = rcu_dereference(kvm->arch.apic_map);
8045 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
8046 target = map->phys_map[dest_id]->vcpu;
8050 if (target && READ_ONCE(target->ready))
8051 kvm_vcpu_yield_to(target);
8054 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
8056 unsigned long nr, a0, a1, a2, a3, ret;
8059 if (kvm_hv_hypercall_enabled(vcpu->kvm))
8060 return kvm_hv_hypercall(vcpu);
8062 nr = kvm_rax_read(vcpu);
8063 a0 = kvm_rbx_read(vcpu);
8064 a1 = kvm_rcx_read(vcpu);
8065 a2 = kvm_rdx_read(vcpu);
8066 a3 = kvm_rsi_read(vcpu);
8068 trace_kvm_hypercall(nr, a0, a1, a2, a3);
8070 op_64_bit = is_64_bit_mode(vcpu);
8079 if (kvm_x86_ops.get_cpl(vcpu) != 0) {
8087 case KVM_HC_VAPIC_POLL_IRQ:
8090 case KVM_HC_KICK_CPU:
8091 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
8094 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
8095 kvm_sched_yield(vcpu->kvm, a1);
8098 #ifdef CONFIG_X86_64
8099 case KVM_HC_CLOCK_PAIRING:
8100 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
8103 case KVM_HC_SEND_IPI:
8104 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
8107 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
8109 case KVM_HC_SCHED_YIELD:
8110 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
8113 kvm_sched_yield(vcpu->kvm, a0);
8123 kvm_rax_write(vcpu, ret);
8125 ++vcpu->stat.hypercalls;
8126 return kvm_skip_emulated_instruction(vcpu);
8128 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
8130 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8133 char instruction[3];
8134 unsigned long rip = kvm_rip_read(vcpu);
8136 kvm_x86_ops.patch_hypercall(vcpu, instruction);
8138 return emulator_write_emulated(ctxt, rip, instruction, 3,
8142 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
8144 return vcpu->run->request_interrupt_window &&
8145 likely(!pic_in_kernel(vcpu->kvm));
8148 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
8150 struct kvm_run *kvm_run = vcpu->run;
8153 * if_flag is obsolete and useless, so do not bother
8154 * setting it for SEV-ES guests. Userspace can just
8155 * use kvm_run->ready_for_interrupt_injection.
8157 kvm_run->if_flag = !vcpu->arch.guest_state_protected
8158 && (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
8160 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
8161 kvm_run->cr8 = kvm_get_cr8(vcpu);
8162 kvm_run->apic_base = kvm_get_apic_base(vcpu);
8163 kvm_run->ready_for_interrupt_injection =
8164 pic_in_kernel(vcpu->kvm) ||
8165 kvm_vcpu_ready_for_interrupt_injection(vcpu);
8168 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
8172 if (!kvm_x86_ops.update_cr8_intercept)
8175 if (!lapic_in_kernel(vcpu))
8178 if (vcpu->arch.apicv_active)
8181 if (!vcpu->arch.apic->vapic_addr)
8182 max_irr = kvm_lapic_find_highest_irr(vcpu);
8189 tpr = kvm_lapic_get_cr8(vcpu);
8191 kvm_x86_ops.update_cr8_intercept(vcpu, tpr, max_irr);
8194 static void inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
8197 bool can_inject = true;
8199 /* try to reinject previous events if any */
8201 if (vcpu->arch.exception.injected) {
8202 kvm_x86_ops.queue_exception(vcpu);
8206 * Do not inject an NMI or interrupt if there is a pending
8207 * exception. Exceptions and interrupts are recognized at
8208 * instruction boundaries, i.e. the start of an instruction.
8209 * Trap-like exceptions, e.g. #DB, have higher priority than
8210 * NMIs and interrupts, i.e. traps are recognized before an
8211 * NMI/interrupt that's pending on the same instruction.
8212 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
8213 * priority, but are only generated (pended) during instruction
8214 * execution, i.e. a pending fault-like exception means the
8215 * fault occurred on the *previous* instruction and must be
8216 * serviced prior to recognizing any new events in order to
8217 * fully complete the previous instruction.
8219 else if (!vcpu->arch.exception.pending) {
8220 if (vcpu->arch.nmi_injected) {
8221 kvm_x86_ops.set_nmi(vcpu);
8223 } else if (vcpu->arch.interrupt.injected) {
8224 kvm_x86_ops.set_irq(vcpu);
8229 WARN_ON_ONCE(vcpu->arch.exception.injected &&
8230 vcpu->arch.exception.pending);
8233 * Call check_nested_events() even if we reinjected a previous event
8234 * in order for caller to determine if it should require immediate-exit
8235 * from L2 to L1 due to pending L1 events which require exit
8238 if (is_guest_mode(vcpu)) {
8239 r = kvm_x86_ops.nested_ops->check_events(vcpu);
8244 /* try to inject new event if pending */
8245 if (vcpu->arch.exception.pending) {
8246 trace_kvm_inj_exception(vcpu->arch.exception.nr,
8247 vcpu->arch.exception.has_error_code,
8248 vcpu->arch.exception.error_code);
8250 vcpu->arch.exception.pending = false;
8251 vcpu->arch.exception.injected = true;
8253 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
8254 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
8257 if (vcpu->arch.exception.nr == DB_VECTOR) {
8258 kvm_deliver_exception_payload(vcpu);
8259 if (vcpu->arch.dr7 & DR7_GD) {
8260 vcpu->arch.dr7 &= ~DR7_GD;
8261 kvm_update_dr7(vcpu);
8265 kvm_x86_ops.queue_exception(vcpu);
8270 * Finally, inject interrupt events. If an event cannot be injected
8271 * due to architectural conditions (e.g. IF=0) a window-open exit
8272 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
8273 * and can architecturally be injected, but we cannot do it right now:
8274 * an interrupt could have arrived just now and we have to inject it
8275 * as a vmexit, or there could already an event in the queue, which is
8276 * indicated by can_inject. In that case we request an immediate exit
8277 * in order to make progress and get back here for another iteration.
8278 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
8280 if (vcpu->arch.smi_pending) {
8281 r = can_inject ? kvm_x86_ops.smi_allowed(vcpu, true) : -EBUSY;
8285 vcpu->arch.smi_pending = false;
8286 ++vcpu->arch.smi_count;
8290 kvm_x86_ops.enable_smi_window(vcpu);
8293 if (vcpu->arch.nmi_pending) {
8294 r = can_inject ? kvm_x86_ops.nmi_allowed(vcpu, true) : -EBUSY;
8298 --vcpu->arch.nmi_pending;
8299 vcpu->arch.nmi_injected = true;
8300 kvm_x86_ops.set_nmi(vcpu);
8302 WARN_ON(kvm_x86_ops.nmi_allowed(vcpu, true) < 0);
8304 if (vcpu->arch.nmi_pending)
8305 kvm_x86_ops.enable_nmi_window(vcpu);
8308 if (kvm_cpu_has_injectable_intr(vcpu)) {
8309 r = can_inject ? kvm_x86_ops.interrupt_allowed(vcpu, true) : -EBUSY;
8313 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
8314 kvm_x86_ops.set_irq(vcpu);
8315 WARN_ON(kvm_x86_ops.interrupt_allowed(vcpu, true) < 0);
8317 if (kvm_cpu_has_injectable_intr(vcpu))
8318 kvm_x86_ops.enable_irq_window(vcpu);
8321 if (is_guest_mode(vcpu) &&
8322 kvm_x86_ops.nested_ops->hv_timer_pending &&
8323 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
8324 *req_immediate_exit = true;
8326 WARN_ON(vcpu->arch.exception.pending);
8330 *req_immediate_exit = true;
8334 static void process_nmi(struct kvm_vcpu *vcpu)
8339 * x86 is limited to one NMI running, and one NMI pending after it.
8340 * If an NMI is already in progress, limit further NMIs to just one.
8341 * Otherwise, allow two (and we'll inject the first one immediately).
8343 if (kvm_x86_ops.get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
8346 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
8347 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
8348 kvm_make_request(KVM_REQ_EVENT, vcpu);
8351 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
8354 flags |= seg->g << 23;
8355 flags |= seg->db << 22;
8356 flags |= seg->l << 21;
8357 flags |= seg->avl << 20;
8358 flags |= seg->present << 15;
8359 flags |= seg->dpl << 13;
8360 flags |= seg->s << 12;
8361 flags |= seg->type << 8;
8365 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
8367 struct kvm_segment seg;
8370 kvm_get_segment(vcpu, &seg, n);
8371 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
8374 offset = 0x7f84 + n * 12;
8376 offset = 0x7f2c + (n - 3) * 12;
8378 put_smstate(u32, buf, offset + 8, seg.base);
8379 put_smstate(u32, buf, offset + 4, seg.limit);
8380 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
8383 #ifdef CONFIG_X86_64
8384 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
8386 struct kvm_segment seg;
8390 kvm_get_segment(vcpu, &seg, n);
8391 offset = 0x7e00 + n * 16;
8393 flags = enter_smm_get_segment_flags(&seg) >> 8;
8394 put_smstate(u16, buf, offset, seg.selector);
8395 put_smstate(u16, buf, offset + 2, flags);
8396 put_smstate(u32, buf, offset + 4, seg.limit);
8397 put_smstate(u64, buf, offset + 8, seg.base);
8401 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
8404 struct kvm_segment seg;
8408 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
8409 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
8410 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
8411 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
8413 for (i = 0; i < 8; i++)
8414 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
8416 kvm_get_dr(vcpu, 6, &val);
8417 put_smstate(u32, buf, 0x7fcc, (u32)val);
8418 kvm_get_dr(vcpu, 7, &val);
8419 put_smstate(u32, buf, 0x7fc8, (u32)val);
8421 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8422 put_smstate(u32, buf, 0x7fc4, seg.selector);
8423 put_smstate(u32, buf, 0x7f64, seg.base);
8424 put_smstate(u32, buf, 0x7f60, seg.limit);
8425 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
8427 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8428 put_smstate(u32, buf, 0x7fc0, seg.selector);
8429 put_smstate(u32, buf, 0x7f80, seg.base);
8430 put_smstate(u32, buf, 0x7f7c, seg.limit);
8431 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
8433 kvm_x86_ops.get_gdt(vcpu, &dt);
8434 put_smstate(u32, buf, 0x7f74, dt.address);
8435 put_smstate(u32, buf, 0x7f70, dt.size);
8437 kvm_x86_ops.get_idt(vcpu, &dt);
8438 put_smstate(u32, buf, 0x7f58, dt.address);
8439 put_smstate(u32, buf, 0x7f54, dt.size);
8441 for (i = 0; i < 6; i++)
8442 enter_smm_save_seg_32(vcpu, buf, i);
8444 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
8447 put_smstate(u32, buf, 0x7efc, 0x00020000);
8448 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
8451 #ifdef CONFIG_X86_64
8452 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
8455 struct kvm_segment seg;
8459 for (i = 0; i < 16; i++)
8460 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
8462 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
8463 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
8465 kvm_get_dr(vcpu, 6, &val);
8466 put_smstate(u64, buf, 0x7f68, val);
8467 kvm_get_dr(vcpu, 7, &val);
8468 put_smstate(u64, buf, 0x7f60, val);
8470 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
8471 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
8472 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
8474 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
8477 put_smstate(u32, buf, 0x7efc, 0x00020064);
8479 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
8481 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
8482 put_smstate(u16, buf, 0x7e90, seg.selector);
8483 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
8484 put_smstate(u32, buf, 0x7e94, seg.limit);
8485 put_smstate(u64, buf, 0x7e98, seg.base);
8487 kvm_x86_ops.get_idt(vcpu, &dt);
8488 put_smstate(u32, buf, 0x7e84, dt.size);
8489 put_smstate(u64, buf, 0x7e88, dt.address);
8491 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
8492 put_smstate(u16, buf, 0x7e70, seg.selector);
8493 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
8494 put_smstate(u32, buf, 0x7e74, seg.limit);
8495 put_smstate(u64, buf, 0x7e78, seg.base);
8497 kvm_x86_ops.get_gdt(vcpu, &dt);
8498 put_smstate(u32, buf, 0x7e64, dt.size);
8499 put_smstate(u64, buf, 0x7e68, dt.address);
8501 for (i = 0; i < 6; i++)
8502 enter_smm_save_seg_64(vcpu, buf, i);
8506 static void enter_smm(struct kvm_vcpu *vcpu)
8508 struct kvm_segment cs, ds;
8513 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
8514 memset(buf, 0, 512);
8515 #ifdef CONFIG_X86_64
8516 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8517 enter_smm_save_state_64(vcpu, buf);
8520 enter_smm_save_state_32(vcpu, buf);
8523 * Give pre_enter_smm() a chance to make ISA-specific changes to the
8524 * vCPU state (e.g. leave guest mode) after we've saved the state into
8525 * the SMM state-save area.
8527 kvm_x86_ops.pre_enter_smm(vcpu, buf);
8529 vcpu->arch.hflags |= HF_SMM_MASK;
8530 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
8532 if (kvm_x86_ops.get_nmi_mask(vcpu))
8533 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
8535 kvm_x86_ops.set_nmi_mask(vcpu, true);
8537 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
8538 kvm_rip_write(vcpu, 0x8000);
8540 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
8541 kvm_x86_ops.set_cr0(vcpu, cr0);
8542 vcpu->arch.cr0 = cr0;
8544 kvm_x86_ops.set_cr4(vcpu, 0);
8546 /* Undocumented: IDT limit is set to zero on entry to SMM. */
8547 dt.address = dt.size = 0;
8548 kvm_x86_ops.set_idt(vcpu, &dt);
8550 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
8552 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
8553 cs.base = vcpu->arch.smbase;
8558 cs.limit = ds.limit = 0xffffffff;
8559 cs.type = ds.type = 0x3;
8560 cs.dpl = ds.dpl = 0;
8565 cs.avl = ds.avl = 0;
8566 cs.present = ds.present = 1;
8567 cs.unusable = ds.unusable = 0;
8568 cs.padding = ds.padding = 0;
8570 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8571 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
8572 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
8573 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
8574 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
8575 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
8577 #ifdef CONFIG_X86_64
8578 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
8579 kvm_x86_ops.set_efer(vcpu, 0);
8582 kvm_update_cpuid_runtime(vcpu);
8583 kvm_mmu_reset_context(vcpu);
8586 static void process_smi(struct kvm_vcpu *vcpu)
8588 vcpu->arch.smi_pending = true;
8589 kvm_make_request(KVM_REQ_EVENT, vcpu);
8592 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
8593 unsigned long *vcpu_bitmap)
8597 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8599 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8600 NULL, vcpu_bitmap, cpus);
8602 free_cpumask_var(cpus);
8605 void kvm_make_scan_ioapic_request(struct kvm *kvm)
8607 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8610 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
8612 if (!lapic_in_kernel(vcpu))
8615 vcpu->arch.apicv_active = kvm_apicv_activated(vcpu->kvm);
8616 kvm_apic_update_apicv(vcpu);
8617 kvm_x86_ops.refresh_apicv_exec_ctrl(vcpu);
8619 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
8622 * NOTE: Do not hold any lock prior to calling this.
8624 * In particular, kvm_request_apicv_update() expects kvm->srcu not to be
8625 * locked, because it calls __x86_set_memory_region() which does
8626 * synchronize_srcu(&kvm->srcu).
8628 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
8630 struct kvm_vcpu *except;
8631 unsigned long old, new, expected;
8633 if (!kvm_x86_ops.check_apicv_inhibit_reasons ||
8634 !kvm_x86_ops.check_apicv_inhibit_reasons(bit))
8637 old = READ_ONCE(kvm->arch.apicv_inhibit_reasons);
8639 expected = new = old;
8641 __clear_bit(bit, &new);
8643 __set_bit(bit, &new);
8646 old = cmpxchg(&kvm->arch.apicv_inhibit_reasons, expected, new);
8647 } while (old != expected);
8652 trace_kvm_apicv_update_request(activate, bit);
8653 if (kvm_x86_ops.pre_update_apicv_exec_ctrl)
8654 kvm_x86_ops.pre_update_apicv_exec_ctrl(kvm, activate);
8657 * Sending request to update APICV for all other vcpus,
8658 * while update the calling vcpu immediately instead of
8659 * waiting for another #VMEXIT to handle the request.
8661 except = kvm_get_running_vcpu();
8662 kvm_make_all_cpus_request_except(kvm, KVM_REQ_APICV_UPDATE,
8665 kvm_vcpu_update_apicv(except);
8667 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
8669 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
8671 if (!kvm_apic_present(vcpu))
8674 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
8676 if (irqchip_split(vcpu->kvm))
8677 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
8679 if (vcpu->arch.apicv_active)
8680 kvm_x86_ops.sync_pir_to_irr(vcpu);
8681 if (ioapic_in_kernel(vcpu->kvm))
8682 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
8685 if (is_guest_mode(vcpu))
8686 vcpu->arch.load_eoi_exitmap_pending = true;
8688 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8691 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8693 u64 eoi_exit_bitmap[4];
8695 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8698 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8699 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8700 kvm_x86_ops.load_eoi_exitmap(vcpu, eoi_exit_bitmap);
8703 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8704 unsigned long start, unsigned long end)
8706 unsigned long apic_address;
8709 * The physical address of apic access page is stored in the VMCS.
8710 * Update it when it becomes invalid.
8712 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8713 if (start <= apic_address && apic_address < end)
8714 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
8717 void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8719 if (!lapic_in_kernel(vcpu))
8722 if (!kvm_x86_ops.set_apic_access_page_addr)
8725 kvm_x86_ops.set_apic_access_page_addr(vcpu);
8728 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8730 smp_send_reschedule(vcpu->cpu);
8732 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8735 * Returns 1 to let vcpu_run() continue the guest execution loop without
8736 * exiting to the userspace. Otherwise, the value will be returned to the
8739 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
8743 dm_request_for_irq_injection(vcpu) &&
8744 kvm_cpu_accept_dm_intr(vcpu);
8745 fastpath_t exit_fastpath;
8747 bool req_immediate_exit = false;
8749 /* Forbid vmenter if vcpu dirty ring is soft-full */
8750 if (unlikely(vcpu->kvm->dirty_ring_size &&
8751 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
8752 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
8753 trace_kvm_dirty_ring_exit(vcpu);
8758 if (kvm_request_pending(vcpu)) {
8759 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
8760 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
8765 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
8766 kvm_mmu_unload(vcpu);
8767 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
8768 __kvm_migrate_timers(vcpu);
8769 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8770 kvm_gen_update_masterclock(vcpu->kvm);
8771 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8772 kvm_gen_kvmclock_update(vcpu);
8773 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8774 r = kvm_guest_time_update(vcpu);
8778 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
8779 kvm_mmu_sync_roots(vcpu);
8780 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
8781 kvm_mmu_load_pgd(vcpu);
8782 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
8783 kvm_vcpu_flush_tlb_all(vcpu);
8785 /* Flushing all ASIDs flushes the current ASID... */
8786 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
8788 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
8789 kvm_vcpu_flush_tlb_current(vcpu);
8790 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu))
8791 kvm_vcpu_flush_tlb_guest(vcpu);
8793 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
8794 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
8798 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
8799 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
8800 vcpu->mmio_needed = 0;
8804 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8805 /* Page is swapped out. Do synthetic halt */
8806 vcpu->arch.apf.halted = true;
8810 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8811 record_steal_time(vcpu);
8812 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8814 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8816 if (kvm_check_request(KVM_REQ_PMU, vcpu))
8817 kvm_pmu_handle_event(vcpu);
8818 if (kvm_check_request(KVM_REQ_PMI, vcpu))
8819 kvm_pmu_deliver_pmi(vcpu);
8820 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8821 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8822 if (test_bit(vcpu->arch.pending_ioapic_eoi,
8823 vcpu->arch.ioapic_handled_vectors)) {
8824 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8825 vcpu->run->eoi.vector =
8826 vcpu->arch.pending_ioapic_eoi;
8831 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8832 vcpu_scan_ioapic(vcpu);
8833 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8834 vcpu_load_eoi_exitmap(vcpu);
8835 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8836 kvm_vcpu_reload_apic_access_page(vcpu);
8837 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8838 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8839 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8843 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8844 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8845 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8849 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8850 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8851 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8857 * KVM_REQ_HV_STIMER has to be processed after
8858 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8859 * depend on the guest clock being up-to-date
8861 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8862 kvm_hv_process_stimers(vcpu);
8863 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
8864 kvm_vcpu_update_apicv(vcpu);
8865 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
8866 kvm_check_async_pf_completion(vcpu);
8867 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
8868 kvm_x86_ops.msr_filter_changed(vcpu);
8871 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
8872 ++vcpu->stat.req_event;
8873 kvm_apic_accept_events(vcpu);
8874 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8879 inject_pending_event(vcpu, &req_immediate_exit);
8881 kvm_x86_ops.enable_irq_window(vcpu);
8883 if (kvm_lapic_enabled(vcpu)) {
8884 update_cr8_intercept(vcpu);
8885 kvm_lapic_sync_to_vapic(vcpu);
8889 r = kvm_mmu_reload(vcpu);
8891 goto cancel_injection;
8896 kvm_x86_ops.prepare_guest_switch(vcpu);
8899 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8900 * IPI are then delayed after guest entry, which ensures that they
8901 * result in virtual interrupt delivery.
8903 local_irq_disable();
8904 vcpu->mode = IN_GUEST_MODE;
8906 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8909 * 1) We should set ->mode before checking ->requests. Please see
8910 * the comment in kvm_vcpu_exiting_guest_mode().
8912 * 2) For APICv, we should set ->mode before checking PID.ON. This
8913 * pairs with the memory barrier implicit in pi_test_and_set_on
8914 * (see vmx_deliver_posted_interrupt).
8916 * 3) This also orders the write to mode from any reads to the page
8917 * tables done while the VCPU is running. Please see the comment
8918 * in kvm_flush_remote_tlbs.
8920 smp_mb__after_srcu_read_unlock();
8923 * This handles the case where a posted interrupt was
8924 * notified with kvm_vcpu_kick.
8926 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8927 kvm_x86_ops.sync_pir_to_irr(vcpu);
8929 if (kvm_vcpu_exit_request(vcpu)) {
8930 vcpu->mode = OUTSIDE_GUEST_MODE;
8934 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
8936 goto cancel_injection;
8939 if (req_immediate_exit) {
8940 kvm_make_request(KVM_REQ_EVENT, vcpu);
8941 kvm_x86_ops.request_immediate_exit(vcpu);
8944 trace_kvm_entry(vcpu);
8946 fpregs_assert_state_consistent();
8947 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8948 switch_fpu_return();
8950 if (unlikely(vcpu->arch.switch_db_regs)) {
8952 set_debugreg(vcpu->arch.eff_db[0], 0);
8953 set_debugreg(vcpu->arch.eff_db[1], 1);
8954 set_debugreg(vcpu->arch.eff_db[2], 2);
8955 set_debugreg(vcpu->arch.eff_db[3], 3);
8956 set_debugreg(vcpu->arch.dr6, 6);
8957 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8960 exit_fastpath = kvm_x86_ops.run(vcpu);
8963 * Do this here before restoring debug registers on the host. And
8964 * since we do this before handling the vmexit, a DR access vmexit
8965 * can (a) read the correct value of the debug registers, (b) set
8966 * KVM_DEBUGREG_WONT_EXIT again.
8968 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
8969 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8970 kvm_x86_ops.sync_dirty_debug_regs(vcpu);
8971 kvm_update_dr0123(vcpu);
8972 kvm_update_dr7(vcpu);
8973 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
8977 * If the guest has used debug registers, at least dr7
8978 * will be disabled while returning to the host.
8979 * If we don't have active breakpoints in the host, we don't
8980 * care about the messed up debug address registers. But if
8981 * we have some of them active, restore the old state.
8983 if (hw_breakpoint_active())
8984 hw_breakpoint_restore();
8986 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
8987 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
8989 vcpu->mode = OUTSIDE_GUEST_MODE;
8992 kvm_x86_ops.handle_exit_irqoff(vcpu);
8995 * Consume any pending interrupts, including the possible source of
8996 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8997 * An instruction is required after local_irq_enable() to fully unblock
8998 * interrupts on processors that implement an interrupt shadow, the
8999 * stat.exits increment will do nicely.
9001 kvm_before_interrupt(vcpu);
9004 local_irq_disable();
9005 kvm_after_interrupt(vcpu);
9007 if (lapic_in_kernel(vcpu)) {
9008 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
9009 if (delta != S64_MIN) {
9010 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
9011 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
9018 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9021 * Profile KVM exit RIPs:
9023 if (unlikely(prof_on == KVM_PROFILING)) {
9024 unsigned long rip = kvm_rip_read(vcpu);
9025 profile_hit(KVM_PROFILING, (void *)rip);
9028 if (unlikely(vcpu->arch.tsc_always_catchup))
9029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9031 if (vcpu->arch.apic_attention)
9032 kvm_lapic_sync_from_vapic(vcpu);
9034 r = kvm_x86_ops.handle_exit(vcpu, exit_fastpath);
9038 if (req_immediate_exit)
9039 kvm_make_request(KVM_REQ_EVENT, vcpu);
9040 kvm_x86_ops.cancel_injection(vcpu);
9041 if (unlikely(vcpu->arch.apic_attention))
9042 kvm_lapic_sync_from_vapic(vcpu);
9047 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
9049 if (!kvm_arch_vcpu_runnable(vcpu) &&
9050 (!kvm_x86_ops.pre_block || kvm_x86_ops.pre_block(vcpu) == 0)) {
9051 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9052 kvm_vcpu_block(vcpu);
9053 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9055 if (kvm_x86_ops.post_block)
9056 kvm_x86_ops.post_block(vcpu);
9058 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
9062 kvm_apic_accept_events(vcpu);
9063 switch(vcpu->arch.mp_state) {
9064 case KVM_MP_STATE_HALTED:
9065 vcpu->arch.pv.pv_unhalted = false;
9066 vcpu->arch.mp_state =
9067 KVM_MP_STATE_RUNNABLE;
9069 case KVM_MP_STATE_RUNNABLE:
9070 vcpu->arch.apf.halted = false;
9072 case KVM_MP_STATE_INIT_RECEIVED:
9080 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
9082 if (is_guest_mode(vcpu))
9083 kvm_x86_ops.nested_ops->check_events(vcpu);
9085 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
9086 !vcpu->arch.apf.halted);
9089 static int vcpu_run(struct kvm_vcpu *vcpu)
9092 struct kvm *kvm = vcpu->kvm;
9094 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9095 vcpu->arch.l1tf_flush_l1d = true;
9098 if (kvm_vcpu_running(vcpu)) {
9099 r = vcpu_enter_guest(vcpu);
9101 r = vcpu_block(kvm, vcpu);
9107 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
9108 if (kvm_cpu_has_pending_timer(vcpu))
9109 kvm_inject_pending_timer_irqs(vcpu);
9111 if (dm_request_for_irq_injection(vcpu) &&
9112 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
9114 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
9115 ++vcpu->stat.request_irq_exits;
9119 if (__xfer_to_guest_mode_work_pending()) {
9120 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9121 r = xfer_to_guest_mode_handle_work(vcpu);
9124 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
9128 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
9133 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
9137 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9138 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
9139 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9143 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
9145 BUG_ON(!vcpu->arch.pio.count);
9147 return complete_emulated_io(vcpu);
9151 * Implements the following, as a state machine:
9155 * for each mmio piece in the fragment
9163 * for each mmio piece in the fragment
9168 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
9170 struct kvm_run *run = vcpu->run;
9171 struct kvm_mmio_fragment *frag;
9174 BUG_ON(!vcpu->mmio_needed);
9176 /* Complete previous fragment */
9177 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
9178 len = min(8u, frag->len);
9179 if (!vcpu->mmio_is_write)
9180 memcpy(frag->data, run->mmio.data, len);
9182 if (frag->len <= 8) {
9183 /* Switch to the next fragment. */
9185 vcpu->mmio_cur_fragment++;
9187 /* Go forward to the next mmio piece. */
9193 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
9194 vcpu->mmio_needed = 0;
9196 /* FIXME: return into emulator if single-stepping. */
9197 if (vcpu->mmio_is_write)
9199 vcpu->mmio_read_completed = 1;
9200 return complete_emulated_io(vcpu);
9203 run->exit_reason = KVM_EXIT_MMIO;
9204 run->mmio.phys_addr = frag->gpa;
9205 if (vcpu->mmio_is_write)
9206 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
9207 run->mmio.len = min(8u, frag->len);
9208 run->mmio.is_write = vcpu->mmio_is_write;
9209 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9213 static void kvm_save_current_fpu(struct fpu *fpu)
9216 * If the target FPU state is not resident in the CPU registers, just
9217 * memcpy() from current, else save CPU state directly to the target.
9219 if (test_thread_flag(TIF_NEED_FPU_LOAD))
9220 memcpy(&fpu->state, ¤t->thread.fpu.state,
9221 fpu_kernel_xstate_size);
9223 copy_fpregs_to_fpstate(fpu);
9226 /* Swap (qemu) user FPU context for the guest FPU context. */
9227 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
9231 kvm_save_current_fpu(vcpu->arch.user_fpu);
9233 /* PKRU is separately restored in kvm_x86_ops.run. */
9234 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
9235 ~XFEATURE_MASK_PKRU);
9237 fpregs_mark_activate();
9243 /* When vcpu_run ends, restore user space FPU context. */
9244 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
9248 kvm_save_current_fpu(vcpu->arch.guest_fpu);
9250 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
9252 fpregs_mark_activate();
9255 ++vcpu->stat.fpu_reload;
9259 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
9261 struct kvm_run *kvm_run = vcpu->run;
9265 kvm_sigset_activate(vcpu);
9266 kvm_load_guest_fpu(vcpu);
9268 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
9269 if (kvm_run->immediate_exit) {
9273 kvm_vcpu_block(vcpu);
9274 kvm_apic_accept_events(vcpu);
9275 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
9277 if (signal_pending(current)) {
9279 kvm_run->exit_reason = KVM_EXIT_INTR;
9280 ++vcpu->stat.signal_exits;
9285 if (kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
9290 if (kvm_run->kvm_dirty_regs) {
9291 r = sync_regs(vcpu);
9296 /* re-sync apic's tpr */
9297 if (!lapic_in_kernel(vcpu)) {
9298 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
9304 if (unlikely(vcpu->arch.complete_userspace_io)) {
9305 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
9306 vcpu->arch.complete_userspace_io = NULL;
9311 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
9313 if (kvm_run->immediate_exit)
9319 kvm_put_guest_fpu(vcpu);
9320 if (kvm_run->kvm_valid_regs)
9322 post_kvm_run_save(vcpu);
9323 kvm_sigset_deactivate(vcpu);
9329 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9331 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
9333 * We are here if userspace calls get_regs() in the middle of
9334 * instruction emulation. Registers state needs to be copied
9335 * back from emulation context to vcpu. Userspace shouldn't do
9336 * that usually, but some bad designed PV devices (vmware
9337 * backdoor interface) need this to work
9339 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
9340 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9342 regs->rax = kvm_rax_read(vcpu);
9343 regs->rbx = kvm_rbx_read(vcpu);
9344 regs->rcx = kvm_rcx_read(vcpu);
9345 regs->rdx = kvm_rdx_read(vcpu);
9346 regs->rsi = kvm_rsi_read(vcpu);
9347 regs->rdi = kvm_rdi_read(vcpu);
9348 regs->rsp = kvm_rsp_read(vcpu);
9349 regs->rbp = kvm_rbp_read(vcpu);
9350 #ifdef CONFIG_X86_64
9351 regs->r8 = kvm_r8_read(vcpu);
9352 regs->r9 = kvm_r9_read(vcpu);
9353 regs->r10 = kvm_r10_read(vcpu);
9354 regs->r11 = kvm_r11_read(vcpu);
9355 regs->r12 = kvm_r12_read(vcpu);
9356 regs->r13 = kvm_r13_read(vcpu);
9357 regs->r14 = kvm_r14_read(vcpu);
9358 regs->r15 = kvm_r15_read(vcpu);
9361 regs->rip = kvm_rip_read(vcpu);
9362 regs->rflags = kvm_get_rflags(vcpu);
9365 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9368 __get_regs(vcpu, regs);
9373 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9375 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
9376 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9378 kvm_rax_write(vcpu, regs->rax);
9379 kvm_rbx_write(vcpu, regs->rbx);
9380 kvm_rcx_write(vcpu, regs->rcx);
9381 kvm_rdx_write(vcpu, regs->rdx);
9382 kvm_rsi_write(vcpu, regs->rsi);
9383 kvm_rdi_write(vcpu, regs->rdi);
9384 kvm_rsp_write(vcpu, regs->rsp);
9385 kvm_rbp_write(vcpu, regs->rbp);
9386 #ifdef CONFIG_X86_64
9387 kvm_r8_write(vcpu, regs->r8);
9388 kvm_r9_write(vcpu, regs->r9);
9389 kvm_r10_write(vcpu, regs->r10);
9390 kvm_r11_write(vcpu, regs->r11);
9391 kvm_r12_write(vcpu, regs->r12);
9392 kvm_r13_write(vcpu, regs->r13);
9393 kvm_r14_write(vcpu, regs->r14);
9394 kvm_r15_write(vcpu, regs->r15);
9397 kvm_rip_write(vcpu, regs->rip);
9398 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
9400 vcpu->arch.exception.pending = false;
9402 kvm_make_request(KVM_REQ_EVENT, vcpu);
9405 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
9408 __set_regs(vcpu, regs);
9413 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
9415 struct kvm_segment cs;
9417 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9421 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
9423 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9427 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9428 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9429 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9430 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9431 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9432 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9434 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9435 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9437 kvm_x86_ops.get_idt(vcpu, &dt);
9438 sregs->idt.limit = dt.size;
9439 sregs->idt.base = dt.address;
9440 kvm_x86_ops.get_gdt(vcpu, &dt);
9441 sregs->gdt.limit = dt.size;
9442 sregs->gdt.base = dt.address;
9444 sregs->cr0 = kvm_read_cr0(vcpu);
9445 sregs->cr2 = vcpu->arch.cr2;
9446 sregs->cr3 = kvm_read_cr3(vcpu);
9447 sregs->cr4 = kvm_read_cr4(vcpu);
9448 sregs->cr8 = kvm_get_cr8(vcpu);
9449 sregs->efer = vcpu->arch.efer;
9450 sregs->apic_base = kvm_get_apic_base(vcpu);
9452 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
9454 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
9455 set_bit(vcpu->arch.interrupt.nr,
9456 (unsigned long *)sregs->interrupt_bitmap);
9459 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
9460 struct kvm_sregs *sregs)
9463 __get_sregs(vcpu, sregs);
9468 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
9469 struct kvm_mp_state *mp_state)
9472 if (kvm_mpx_supported())
9473 kvm_load_guest_fpu(vcpu);
9475 kvm_apic_accept_events(vcpu);
9476 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
9477 vcpu->arch.pv.pv_unhalted)
9478 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
9480 mp_state->mp_state = vcpu->arch.mp_state;
9482 if (kvm_mpx_supported())
9483 kvm_put_guest_fpu(vcpu);
9488 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
9489 struct kvm_mp_state *mp_state)
9495 if (!lapic_in_kernel(vcpu) &&
9496 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
9500 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
9501 * INIT state; latched init should be reported using
9502 * KVM_SET_VCPU_EVENTS, so reject it here.
9504 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
9505 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
9506 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
9509 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
9510 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
9511 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
9513 vcpu->arch.mp_state = mp_state->mp_state;
9514 kvm_make_request(KVM_REQ_EVENT, vcpu);
9522 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
9523 int reason, bool has_error_code, u32 error_code)
9525 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9528 init_emulate_ctxt(vcpu);
9530 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9531 has_error_code, error_code);
9533 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
9534 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
9535 vcpu->run->internal.ndata = 0;
9539 kvm_rip_write(vcpu, ctxt->eip);
9540 kvm_set_rflags(vcpu, ctxt->eflags);
9543 EXPORT_SYMBOL_GPL(kvm_task_switch);
9545 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9547 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
9549 * When EFER.LME and CR0.PG are set, the processor is in
9550 * 64-bit mode (though maybe in a 32-bit code segment).
9551 * CR4.PAE and EFER.LMA must be set.
9553 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
9557 * Not in 64-bit mode: EFER.LMA is clear and the code
9558 * segment cannot be 64-bit.
9560 if (sregs->efer & EFER_LMA || sregs->cs.l)
9564 return kvm_is_valid_cr4(vcpu, sregs->cr4);
9567 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
9569 struct msr_data apic_base_msr;
9570 int mmu_reset_needed = 0;
9571 int pending_vec, max_bits, idx;
9575 if (!kvm_is_valid_sregs(vcpu, sregs))
9578 apic_base_msr.data = sregs->apic_base;
9579 apic_base_msr.host_initiated = true;
9580 if (kvm_set_apic_base(vcpu, &apic_base_msr))
9583 dt.size = sregs->idt.limit;
9584 dt.address = sregs->idt.base;
9585 kvm_x86_ops.set_idt(vcpu, &dt);
9586 dt.size = sregs->gdt.limit;
9587 dt.address = sregs->gdt.base;
9588 kvm_x86_ops.set_gdt(vcpu, &dt);
9590 vcpu->arch.cr2 = sregs->cr2;
9591 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
9592 vcpu->arch.cr3 = sregs->cr3;
9593 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
9595 kvm_set_cr8(vcpu, sregs->cr8);
9597 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
9598 kvm_x86_ops.set_efer(vcpu, sregs->efer);
9600 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
9601 kvm_x86_ops.set_cr0(vcpu, sregs->cr0);
9602 vcpu->arch.cr0 = sregs->cr0;
9604 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
9605 kvm_x86_ops.set_cr4(vcpu, sregs->cr4);
9607 idx = srcu_read_lock(&vcpu->kvm->srcu);
9608 if (is_pae_paging(vcpu)) {
9609 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
9610 mmu_reset_needed = 1;
9612 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9614 if (mmu_reset_needed)
9615 kvm_mmu_reset_context(vcpu);
9617 max_bits = KVM_NR_INTERRUPTS;
9618 pending_vec = find_first_bit(
9619 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
9620 if (pending_vec < max_bits) {
9621 kvm_queue_interrupt(vcpu, pending_vec, false);
9622 pr_debug("Set back pending irq %d\n", pending_vec);
9625 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9626 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9627 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9628 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9629 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9630 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
9632 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9633 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
9635 update_cr8_intercept(vcpu);
9637 /* Older userspace won't unhalt the vcpu on reset. */
9638 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9639 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
9641 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9643 kvm_make_request(KVM_REQ_EVENT, vcpu);
9650 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9651 struct kvm_sregs *sregs)
9656 ret = __set_sregs(vcpu, sregs);
9661 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9662 struct kvm_guest_debug *dbg)
9664 unsigned long rflags;
9667 if (vcpu->arch.guest_state_protected)
9672 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9674 if (vcpu->arch.exception.pending)
9676 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9677 kvm_queue_exception(vcpu, DB_VECTOR);
9679 kvm_queue_exception(vcpu, BP_VECTOR);
9683 * Read rflags as long as potentially injected trace flags are still
9686 rflags = kvm_get_rflags(vcpu);
9688 vcpu->guest_debug = dbg->control;
9689 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9690 vcpu->guest_debug = 0;
9692 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
9693 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9694 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
9695 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
9697 for (i = 0; i < KVM_NR_DB_REGS; i++)
9698 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
9700 kvm_update_dr7(vcpu);
9702 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9703 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9704 get_segment_base(vcpu, VCPU_SREG_CS);
9707 * Trigger an rflags update that will inject or remove the trace
9710 kvm_set_rflags(vcpu, rflags);
9712 kvm_x86_ops.update_exception_bitmap(vcpu);
9722 * Translate a guest virtual address to a guest physical address.
9724 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9725 struct kvm_translation *tr)
9727 unsigned long vaddr = tr->linear_address;
9733 idx = srcu_read_lock(&vcpu->kvm->srcu);
9734 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
9735 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9736 tr->physical_address = gpa;
9737 tr->valid = gpa != UNMAPPED_GVA;
9745 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9747 struct fxregs_state *fxsave;
9751 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9752 memcpy(fpu->fpr, fxsave->st_space, 128);
9753 fpu->fcw = fxsave->cwd;
9754 fpu->fsw = fxsave->swd;
9755 fpu->ftwx = fxsave->twd;
9756 fpu->last_opcode = fxsave->fop;
9757 fpu->last_ip = fxsave->rip;
9758 fpu->last_dp = fxsave->rdp;
9759 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
9765 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9767 struct fxregs_state *fxsave;
9771 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
9773 memcpy(fxsave->st_space, fpu->fpr, 128);
9774 fxsave->cwd = fpu->fcw;
9775 fxsave->swd = fpu->fsw;
9776 fxsave->twd = fpu->ftwx;
9777 fxsave->fop = fpu->last_opcode;
9778 fxsave->rip = fpu->last_ip;
9779 fxsave->rdp = fpu->last_dp;
9780 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
9786 static void store_regs(struct kvm_vcpu *vcpu)
9788 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9790 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9791 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9793 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9794 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9796 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9797 kvm_vcpu_ioctl_x86_get_vcpu_events(
9798 vcpu, &vcpu->run->s.regs.events);
9801 static int sync_regs(struct kvm_vcpu *vcpu)
9803 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9806 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9807 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9808 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9810 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9811 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9813 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9815 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9816 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9817 vcpu, &vcpu->run->s.regs.events))
9819 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9825 static void fx_init(struct kvm_vcpu *vcpu)
9827 fpstate_init(&vcpu->arch.guest_fpu->state);
9828 if (boot_cpu_has(X86_FEATURE_XSAVES))
9829 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
9830 host_xcr0 | XSTATE_COMPACTION_ENABLED;
9833 * Ensure guest xcr0 is valid for loading
9835 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
9837 vcpu->arch.cr0 |= X86_CR0_ET;
9840 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
9842 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9843 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9844 "guest TSC will not be reliable\n");
9849 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9854 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9855 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9857 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
9859 kvm_set_tsc_khz(vcpu, max_tsc_khz);
9861 r = kvm_mmu_create(vcpu);
9865 if (irqchip_in_kernel(vcpu->kvm)) {
9866 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9868 goto fail_mmu_destroy;
9869 if (kvm_apicv_activated(vcpu->kvm))
9870 vcpu->arch.apicv_active = true;
9872 static_key_slow_inc(&kvm_no_apic_vcpu);
9876 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9878 goto fail_free_lapic;
9879 vcpu->arch.pio_data = page_address(page);
9881 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9882 GFP_KERNEL_ACCOUNT);
9883 if (!vcpu->arch.mce_banks)
9884 goto fail_free_pio_data;
9885 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9887 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9888 GFP_KERNEL_ACCOUNT))
9889 goto fail_free_mce_banks;
9891 if (!alloc_emulate_ctxt(vcpu))
9892 goto free_wbinvd_dirty_mask;
9894 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9895 GFP_KERNEL_ACCOUNT);
9896 if (!vcpu->arch.user_fpu) {
9897 pr_err("kvm: failed to allocate userspace's fpu\n");
9898 goto free_emulate_ctxt;
9901 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9902 GFP_KERNEL_ACCOUNT);
9903 if (!vcpu->arch.guest_fpu) {
9904 pr_err("kvm: failed to allocate vcpu's fpu\n");
9909 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9911 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9913 kvm_async_pf_hash_reset(vcpu);
9916 vcpu->arch.pending_external_vector = -1;
9917 vcpu->arch.preempted_in_kernel = false;
9919 kvm_hv_vcpu_init(vcpu);
9921 r = kvm_x86_ops.vcpu_create(vcpu);
9923 goto free_guest_fpu;
9925 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
9926 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
9927 kvm_vcpu_mtrr_init(vcpu);
9929 kvm_vcpu_reset(vcpu, false);
9930 kvm_init_mmu(vcpu, false);
9935 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9937 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9939 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9940 free_wbinvd_dirty_mask:
9941 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9942 fail_free_mce_banks:
9943 kfree(vcpu->arch.mce_banks);
9945 free_page((unsigned long)vcpu->arch.pio_data);
9947 kvm_free_lapic(vcpu);
9949 kvm_mmu_destroy(vcpu);
9953 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
9955 struct kvm *kvm = vcpu->kvm;
9957 kvm_hv_vcpu_postcreate(vcpu);
9959 if (mutex_lock_killable(&vcpu->mutex))
9962 kvm_synchronize_tsc(vcpu, 0);
9965 /* poll control enabled by default */
9966 vcpu->arch.msr_kvm_poll_control = 1;
9968 mutex_unlock(&vcpu->mutex);
9970 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
9971 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9972 KVMCLOCK_SYNC_PERIOD);
9975 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
9977 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
9980 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9982 kvmclock_reset(vcpu);
9984 kvm_x86_ops.vcpu_free(vcpu);
9986 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
9987 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9988 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9989 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9991 kvm_hv_vcpu_uninit(vcpu);
9992 kvm_pmu_destroy(vcpu);
9993 kfree(vcpu->arch.mce_banks);
9994 kvm_free_lapic(vcpu);
9995 idx = srcu_read_lock(&vcpu->kvm->srcu);
9996 kvm_mmu_destroy(vcpu);
9997 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9998 free_page((unsigned long)vcpu->arch.pio_data);
9999 kvfree(vcpu->arch.cpuid_entries);
10000 if (!lapic_in_kernel(vcpu))
10001 static_key_slow_dec(&kvm_no_apic_vcpu);
10004 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
10006 kvm_lapic_reset(vcpu, init_event);
10008 vcpu->arch.hflags = 0;
10010 vcpu->arch.smi_pending = 0;
10011 vcpu->arch.smi_count = 0;
10012 atomic_set(&vcpu->arch.nmi_queued, 0);
10013 vcpu->arch.nmi_pending = 0;
10014 vcpu->arch.nmi_injected = false;
10015 kvm_clear_interrupt_queue(vcpu);
10016 kvm_clear_exception_queue(vcpu);
10018 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
10019 kvm_update_dr0123(vcpu);
10020 vcpu->arch.dr6 = DR6_INIT;
10021 vcpu->arch.dr7 = DR7_FIXED_1;
10022 kvm_update_dr7(vcpu);
10024 vcpu->arch.cr2 = 0;
10026 kvm_make_request(KVM_REQ_EVENT, vcpu);
10027 vcpu->arch.apf.msr_en_val = 0;
10028 vcpu->arch.apf.msr_int_val = 0;
10029 vcpu->arch.st.msr_val = 0;
10031 kvmclock_reset(vcpu);
10033 kvm_clear_async_pf_completion_queue(vcpu);
10034 kvm_async_pf_hash_reset(vcpu);
10035 vcpu->arch.apf.halted = false;
10037 if (kvm_mpx_supported()) {
10038 void *mpx_state_buffer;
10041 * To avoid have the INIT path from kvm_apic_has_events() that be
10042 * called with loaded FPU and does not let userspace fix the state.
10045 kvm_put_guest_fpu(vcpu);
10046 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10048 if (mpx_state_buffer)
10049 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
10050 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
10052 if (mpx_state_buffer)
10053 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
10055 kvm_load_guest_fpu(vcpu);
10059 kvm_pmu_reset(vcpu);
10060 vcpu->arch.smbase = 0x30000;
10062 vcpu->arch.msr_misc_features_enables = 0;
10064 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
10067 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
10068 vcpu->arch.regs_avail = ~0;
10069 vcpu->arch.regs_dirty = ~0;
10071 vcpu->arch.ia32_xss = 0;
10073 kvm_x86_ops.vcpu_reset(vcpu, init_event);
10076 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
10078 struct kvm_segment cs;
10080 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
10081 cs.selector = vector << 8;
10082 cs.base = vector << 12;
10083 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10084 kvm_rip_write(vcpu, 0);
10087 int kvm_arch_hardware_enable(void)
10090 struct kvm_vcpu *vcpu;
10095 bool stable, backwards_tsc = false;
10097 kvm_user_return_msr_cpu_online();
10098 ret = kvm_x86_ops.hardware_enable();
10102 local_tsc = rdtsc();
10103 stable = !kvm_check_tsc_unstable();
10104 list_for_each_entry(kvm, &vm_list, vm_list) {
10105 kvm_for_each_vcpu(i, vcpu, kvm) {
10106 if (!stable && vcpu->cpu == smp_processor_id())
10107 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10108 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
10109 backwards_tsc = true;
10110 if (vcpu->arch.last_host_tsc > max_tsc)
10111 max_tsc = vcpu->arch.last_host_tsc;
10117 * Sometimes, even reliable TSCs go backwards. This happens on
10118 * platforms that reset TSC during suspend or hibernate actions, but
10119 * maintain synchronization. We must compensate. Fortunately, we can
10120 * detect that condition here, which happens early in CPU bringup,
10121 * before any KVM threads can be running. Unfortunately, we can't
10122 * bring the TSCs fully up to date with real time, as we aren't yet far
10123 * enough into CPU bringup that we know how much real time has actually
10124 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
10125 * variables that haven't been updated yet.
10127 * So we simply find the maximum observed TSC above, then record the
10128 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
10129 * the adjustment will be applied. Note that we accumulate
10130 * adjustments, in case multiple suspend cycles happen before some VCPU
10131 * gets a chance to run again. In the event that no KVM threads get a
10132 * chance to run, we will miss the entire elapsed period, as we'll have
10133 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
10134 * loose cycle time. This isn't too big a deal, since the loss will be
10135 * uniform across all VCPUs (not to mention the scenario is extremely
10136 * unlikely). It is possible that a second hibernate recovery happens
10137 * much faster than a first, causing the observed TSC here to be
10138 * smaller; this would require additional padding adjustment, which is
10139 * why we set last_host_tsc to the local tsc observed here.
10141 * N.B. - this code below runs only on platforms with reliable TSC,
10142 * as that is the only way backwards_tsc is set above. Also note
10143 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
10144 * have the same delta_cyc adjustment applied if backwards_tsc
10145 * is detected. Note further, this adjustment is only done once,
10146 * as we reset last_host_tsc on all VCPUs to stop this from being
10147 * called multiple times (one for each physical CPU bringup).
10149 * Platforms with unreliable TSCs don't have to deal with this, they
10150 * will be compensated by the logic in vcpu_load, which sets the TSC to
10151 * catchup mode. This will catchup all VCPUs to real time, but cannot
10152 * guarantee that they stay in perfect synchronization.
10154 if (backwards_tsc) {
10155 u64 delta_cyc = max_tsc - local_tsc;
10156 list_for_each_entry(kvm, &vm_list, vm_list) {
10157 kvm->arch.backwards_tsc_observed = true;
10158 kvm_for_each_vcpu(i, vcpu, kvm) {
10159 vcpu->arch.tsc_offset_adjustment += delta_cyc;
10160 vcpu->arch.last_host_tsc = local_tsc;
10161 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
10165 * We have to disable TSC offset matching.. if you were
10166 * booting a VM while issuing an S4 host suspend....
10167 * you may have some problem. Solving this issue is
10168 * left as an exercise to the reader.
10170 kvm->arch.last_tsc_nsec = 0;
10171 kvm->arch.last_tsc_write = 0;
10178 void kvm_arch_hardware_disable(void)
10180 kvm_x86_ops.hardware_disable();
10181 drop_user_return_notifiers();
10184 int kvm_arch_hardware_setup(void *opaque)
10186 struct kvm_x86_init_ops *ops = opaque;
10189 rdmsrl_safe(MSR_EFER, &host_efer);
10191 if (boot_cpu_has(X86_FEATURE_XSAVES))
10192 rdmsrl(MSR_IA32_XSS, host_xss);
10194 r = ops->hardware_setup();
10198 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
10200 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
10203 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
10204 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
10205 #undef __kvm_cpu_cap_has
10207 if (kvm_has_tsc_control) {
10209 * Make sure the user can only configure tsc_khz values that
10210 * fit into a signed integer.
10211 * A min value is not calculated because it will always
10212 * be 1 on all machines.
10214 u64 max = min(0x7fffffffULL,
10215 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
10216 kvm_max_guest_tsc_khz = max;
10218 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
10221 kvm_init_msr_list();
10225 void kvm_arch_hardware_unsetup(void)
10227 kvm_x86_ops.hardware_unsetup();
10230 int kvm_arch_check_processor_compat(void *opaque)
10232 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
10233 struct kvm_x86_init_ops *ops = opaque;
10235 WARN_ON(!irqs_disabled());
10237 if (__cr4_reserved_bits(cpu_has, c) !=
10238 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
10241 return ops->check_processor_compatibility();
10244 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
10246 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
10248 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
10250 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
10252 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
10255 struct static_key kvm_no_apic_vcpu __read_mostly;
10256 EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
10258 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
10260 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
10262 vcpu->arch.l1tf_flush_l1d = true;
10263 if (pmu->version && unlikely(pmu->event_count)) {
10264 pmu->need_cleanup = true;
10265 kvm_make_request(KVM_REQ_PMU, vcpu);
10267 kvm_x86_ops.sched_in(vcpu, cpu);
10270 void kvm_arch_free_vm(struct kvm *kvm)
10272 kfree(kvm->arch.hyperv.hv_pa_pg);
10277 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
10282 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
10283 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10284 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
10285 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
10286 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
10287 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
10289 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
10290 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
10291 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
10292 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
10293 &kvm->arch.irq_sources_bitmap);
10295 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
10296 mutex_init(&kvm->arch.apic_map_lock);
10297 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
10299 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
10300 pvclock_update_vm_gtod_copy(kvm);
10302 kvm->arch.guest_can_read_msr_platform_info = true;
10304 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
10305 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
10307 kvm_hv_init_vm(kvm);
10308 kvm_page_track_init(kvm);
10309 kvm_mmu_init_vm(kvm);
10311 return kvm_x86_ops.vm_init(kvm);
10314 int kvm_arch_post_init_vm(struct kvm *kvm)
10316 return kvm_mmu_post_init_vm(kvm);
10319 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
10322 kvm_mmu_unload(vcpu);
10326 static void kvm_free_vcpus(struct kvm *kvm)
10329 struct kvm_vcpu *vcpu;
10332 * Unpin any mmu pages first.
10334 kvm_for_each_vcpu(i, vcpu, kvm) {
10335 kvm_clear_async_pf_completion_queue(vcpu);
10336 kvm_unload_vcpu_mmu(vcpu);
10338 kvm_for_each_vcpu(i, vcpu, kvm)
10339 kvm_vcpu_destroy(vcpu);
10341 mutex_lock(&kvm->lock);
10342 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
10343 kvm->vcpus[i] = NULL;
10345 atomic_set(&kvm->online_vcpus, 0);
10346 mutex_unlock(&kvm->lock);
10349 void kvm_arch_sync_events(struct kvm *kvm)
10351 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
10352 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
10356 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
10359 * __x86_set_memory_region: Setup KVM internal memory slot
10361 * @kvm: the kvm pointer to the VM.
10362 * @id: the slot ID to setup.
10363 * @gpa: the GPA to install the slot (unused when @size == 0).
10364 * @size: the size of the slot. Set to zero to uninstall a slot.
10366 * This function helps to setup a KVM internal memory slot. Specify
10367 * @size > 0 to install a new slot, while @size == 0 to uninstall a
10368 * slot. The return code can be one of the following:
10370 * HVA: on success (uninstall will return a bogus HVA)
10373 * The caller should always use IS_ERR() to check the return value
10374 * before use. Note, the KVM internal memory slots are guaranteed to
10375 * remain valid and unchanged until the VM is destroyed, i.e., the
10376 * GPA->HVA translation will not change. However, the HVA is a user
10377 * address, i.e. its accessibility is not guaranteed, and must be
10378 * accessed via __copy_{to,from}_user().
10380 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
10384 unsigned long hva, old_npages;
10385 struct kvm_memslots *slots = kvm_memslots(kvm);
10386 struct kvm_memory_slot *slot;
10388 /* Called with kvm->slots_lock held. */
10389 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
10390 return ERR_PTR_USR(-EINVAL);
10392 slot = id_to_memslot(slots, id);
10394 if (slot && slot->npages)
10395 return ERR_PTR_USR(-EEXIST);
10398 * MAP_SHARED to prevent internal slot pages from being moved
10401 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
10402 MAP_SHARED | MAP_ANONYMOUS, 0);
10403 if (IS_ERR((void *)hva))
10404 return (void __user *)hva;
10406 if (!slot || !slot->npages)
10409 old_npages = slot->npages;
10413 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
10414 struct kvm_userspace_memory_region m;
10416 m.slot = id | (i << 16);
10418 m.guest_phys_addr = gpa;
10419 m.userspace_addr = hva;
10420 m.memory_size = size;
10421 r = __kvm_set_memory_region(kvm, &m);
10423 return ERR_PTR_USR(r);
10427 vm_munmap(hva, old_npages * PAGE_SIZE);
10429 return (void __user *)hva;
10431 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
10433 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
10435 kvm_mmu_pre_destroy_vm(kvm);
10438 void kvm_arch_destroy_vm(struct kvm *kvm)
10442 if (current->mm == kvm->mm) {
10444 * Free memory regions allocated on behalf of userspace,
10445 * unless the the memory map has changed due to process exit
10448 mutex_lock(&kvm->slots_lock);
10449 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
10451 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
10453 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
10454 mutex_unlock(&kvm->slots_lock);
10456 if (kvm_x86_ops.vm_destroy)
10457 kvm_x86_ops.vm_destroy(kvm);
10458 for (i = 0; i < kvm->arch.msr_filter.count; i++)
10459 kfree(kvm->arch.msr_filter.ranges[i].bitmap);
10460 kvm_pic_destroy(kvm);
10461 kvm_ioapic_destroy(kvm);
10462 kvm_free_vcpus(kvm);
10463 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
10464 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
10465 kvm_mmu_uninit_vm(kvm);
10466 kvm_page_track_cleanup(kvm);
10467 kvm_hv_destroy_vm(kvm);
10470 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
10474 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10475 kvfree(slot->arch.rmap[i]);
10476 slot->arch.rmap[i] = NULL;
10481 kvfree(slot->arch.lpage_info[i - 1]);
10482 slot->arch.lpage_info[i - 1] = NULL;
10485 kvm_page_track_free_memslot(slot);
10488 static int kvm_alloc_memslot_metadata(struct kvm_memory_slot *slot,
10489 unsigned long npages)
10494 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
10495 * old arrays will be freed by __kvm_set_memory_region() if installing
10496 * the new memslot is successful.
10498 memset(&slot->arch, 0, sizeof(slot->arch));
10500 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10501 struct kvm_lpage_info *linfo;
10502 unsigned long ugfn;
10506 lpages = gfn_to_index(slot->base_gfn + npages - 1,
10507 slot->base_gfn, level) + 1;
10509 slot->arch.rmap[i] =
10510 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
10511 GFP_KERNEL_ACCOUNT);
10512 if (!slot->arch.rmap[i])
10517 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
10521 slot->arch.lpage_info[i - 1] = linfo;
10523 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
10524 linfo[0].disallow_lpage = 1;
10525 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
10526 linfo[lpages - 1].disallow_lpage = 1;
10527 ugfn = slot->userspace_addr >> PAGE_SHIFT;
10529 * If the gfn and userspace address are not aligned wrt each
10530 * other, disable large page support for this slot.
10532 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
10535 for (j = 0; j < lpages; ++j)
10536 linfo[j].disallow_lpage = 1;
10540 if (kvm_page_track_create_memslot(slot, npages))
10546 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
10547 kvfree(slot->arch.rmap[i]);
10548 slot->arch.rmap[i] = NULL;
10552 kvfree(slot->arch.lpage_info[i - 1]);
10553 slot->arch.lpage_info[i - 1] = NULL;
10558 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
10560 struct kvm_vcpu *vcpu;
10564 * memslots->generation has been incremented.
10565 * mmio generation may have reached its maximum value.
10567 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
10569 /* Force re-initialization of steal_time cache */
10570 kvm_for_each_vcpu(i, vcpu, kvm)
10571 kvm_vcpu_kick(vcpu);
10574 int kvm_arch_prepare_memory_region(struct kvm *kvm,
10575 struct kvm_memory_slot *memslot,
10576 const struct kvm_userspace_memory_region *mem,
10577 enum kvm_mr_change change)
10579 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
10580 return kvm_alloc_memslot_metadata(memslot,
10581 mem->memory_size >> PAGE_SHIFT);
10585 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
10586 struct kvm_memory_slot *old,
10587 struct kvm_memory_slot *new,
10588 enum kvm_mr_change change)
10591 * Nothing to do for RO slots or CREATE/MOVE/DELETE of a slot.
10592 * See comments below.
10594 if ((change != KVM_MR_FLAGS_ONLY) || (new->flags & KVM_MEM_READONLY))
10598 * Dirty logging tracks sptes in 4k granularity, meaning that large
10599 * sptes have to be split. If live migration is successful, the guest
10600 * in the source machine will be destroyed and large sptes will be
10601 * created in the destination. However, if the guest continues to run
10602 * in the source machine (for example if live migration fails), small
10603 * sptes will remain around and cause bad performance.
10605 * Scan sptes if dirty logging has been stopped, dropping those
10606 * which can be collapsed into a single large-page spte. Later
10607 * page faults will create the large-page sptes.
10609 * There is no need to do this in any of the following cases:
10610 * CREATE: No dirty mappings will already exist.
10611 * MOVE/DELETE: The old mappings will already have been cleaned up by
10612 * kvm_arch_flush_shadow_memslot()
10614 if ((old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
10615 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
10616 kvm_mmu_zap_collapsible_sptes(kvm, new);
10619 * Enable or disable dirty logging for the slot.
10621 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of the old
10622 * slot have been zapped so no dirty logging updates are needed for
10624 * For KVM_MR_CREATE and KVM_MR_MOVE, once the new slot is visible
10625 * any mappings that might be created in it will consume the
10626 * properties of the new slot and do not need to be updated here.
10628 * When PML is enabled, the kvm_x86_ops dirty logging hooks are
10629 * called to enable/disable dirty logging.
10631 * When disabling dirty logging with PML enabled, the D-bit is set
10632 * for sptes in the slot in order to prevent unnecessary GPA
10633 * logging in the PML buffer (and potential PML buffer full VMEXIT).
10634 * This guarantees leaving PML enabled for the guest's lifetime
10635 * won't have any additional overhead from PML when the guest is
10636 * running with dirty logging disabled.
10638 * When enabling dirty logging, large sptes are write-protected
10639 * so they can be split on first write. New large sptes cannot
10640 * be created for this slot until the end of the logging.
10641 * See the comments in fast_page_fault().
10642 * For small sptes, nothing is done if the dirty log is in the
10643 * initial-all-set state. Otherwise, depending on whether pml
10644 * is enabled the D-bit or the W-bit will be cleared.
10646 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
10647 if (kvm_x86_ops.slot_enable_log_dirty) {
10648 kvm_x86_ops.slot_enable_log_dirty(kvm, new);
10651 kvm_dirty_log_manual_protect_and_init_set(kvm) ?
10652 PG_LEVEL_2M : PG_LEVEL_4K;
10655 * If we're with initial-all-set, we don't need
10656 * to write protect any small page because
10657 * they're reported as dirty already. However
10658 * we still need to write-protect huge pages
10659 * so that the page split can happen lazily on
10660 * the first write to the huge page.
10662 kvm_mmu_slot_remove_write_access(kvm, new, level);
10665 if (kvm_x86_ops.slot_disable_log_dirty)
10666 kvm_x86_ops.slot_disable_log_dirty(kvm, new);
10670 void kvm_arch_commit_memory_region(struct kvm *kvm,
10671 const struct kvm_userspace_memory_region *mem,
10672 struct kvm_memory_slot *old,
10673 const struct kvm_memory_slot *new,
10674 enum kvm_mr_change change)
10676 if (!kvm->arch.n_requested_mmu_pages)
10677 kvm_mmu_change_mmu_pages(kvm,
10678 kvm_mmu_calculate_default_mmu_pages(kvm));
10681 * FIXME: const-ify all uses of struct kvm_memory_slot.
10683 kvm_mmu_slot_apply_flags(kvm, old, (struct kvm_memory_slot *) new, change);
10685 /* Free the arrays associated with the old memslot. */
10686 if (change == KVM_MR_MOVE)
10687 kvm_arch_free_memslot(kvm, old);
10690 void kvm_arch_flush_shadow_all(struct kvm *kvm)
10692 kvm_mmu_zap_all(kvm);
10695 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10696 struct kvm_memory_slot *slot)
10698 kvm_page_track_flush_slot(kvm, slot);
10701 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10703 return (is_guest_mode(vcpu) &&
10704 kvm_x86_ops.guest_apic_has_interrupt &&
10705 kvm_x86_ops.guest_apic_has_interrupt(vcpu));
10708 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10710 if (!list_empty_careful(&vcpu->async_pf.done))
10713 if (kvm_apic_has_events(vcpu))
10716 if (vcpu->arch.pv.pv_unhalted)
10719 if (vcpu->arch.exception.pending)
10722 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10723 (vcpu->arch.nmi_pending &&
10724 kvm_x86_ops.nmi_allowed(vcpu, false)))
10727 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10728 (vcpu->arch.smi_pending &&
10729 kvm_x86_ops.smi_allowed(vcpu, false)))
10732 if (kvm_arch_interrupt_allowed(vcpu) &&
10733 (kvm_cpu_has_interrupt(vcpu) ||
10734 kvm_guest_apic_has_interrupt(vcpu)))
10737 if (kvm_hv_has_stimer_pending(vcpu))
10740 if (is_guest_mode(vcpu) &&
10741 kvm_x86_ops.nested_ops->hv_timer_pending &&
10742 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
10748 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10750 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
10753 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10755 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10758 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10759 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10760 kvm_test_request(KVM_REQ_EVENT, vcpu))
10763 if (vcpu->arch.apicv_active && kvm_x86_ops.dy_apicv_has_pending_interrupt(vcpu))
10769 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10771 return vcpu->arch.preempted_in_kernel;
10774 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
10776 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
10779 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10781 return kvm_x86_ops.interrupt_allowed(vcpu, false);
10784 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
10786 /* Can't read the RIP when guest state is protected, just return 0 */
10787 if (vcpu->arch.guest_state_protected)
10790 if (is_64_bit_mode(vcpu))
10791 return kvm_rip_read(vcpu);
10792 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10793 kvm_rip_read(vcpu));
10795 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
10797 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10799 return kvm_get_linear_rip(vcpu) == linear_rip;
10801 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10803 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10805 unsigned long rflags;
10807 rflags = kvm_x86_ops.get_rflags(vcpu);
10808 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10809 rflags &= ~X86_EFLAGS_TF;
10812 EXPORT_SYMBOL_GPL(kvm_get_rflags);
10814 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10816 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
10817 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
10818 rflags |= X86_EFLAGS_TF;
10819 kvm_x86_ops.set_rflags(vcpu, rflags);
10822 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10824 __kvm_set_rflags(vcpu, rflags);
10825 kvm_make_request(KVM_REQ_EVENT, vcpu);
10827 EXPORT_SYMBOL_GPL(kvm_set_rflags);
10829 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10833 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
10837 r = kvm_mmu_reload(vcpu);
10841 if (!vcpu->arch.mmu->direct_map &&
10842 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
10845 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
10848 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10850 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
10852 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10855 static inline u32 kvm_async_pf_next_probe(u32 key)
10857 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
10860 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10862 u32 key = kvm_async_pf_hash_fn(gfn);
10864 while (vcpu->arch.apf.gfns[key] != ~0)
10865 key = kvm_async_pf_next_probe(key);
10867 vcpu->arch.apf.gfns[key] = gfn;
10870 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10873 u32 key = kvm_async_pf_hash_fn(gfn);
10875 for (i = 0; i < ASYNC_PF_PER_VCPU &&
10876 (vcpu->arch.apf.gfns[key] != gfn &&
10877 vcpu->arch.apf.gfns[key] != ~0); i++)
10878 key = kvm_async_pf_next_probe(key);
10883 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10885 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10888 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10892 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10894 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
10898 vcpu->arch.apf.gfns[i] = ~0;
10900 j = kvm_async_pf_next_probe(j);
10901 if (vcpu->arch.apf.gfns[j] == ~0)
10903 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10905 * k lies cyclically in ]i,j]
10907 * |....j i.k.| or |.k..j i...|
10909 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10910 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10915 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
10917 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
10919 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
10923 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
10925 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10927 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10928 &token, offset, sizeof(token));
10931 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
10933 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
10936 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
10937 &val, offset, sizeof(val)))
10943 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10945 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10948 if (!kvm_pv_async_pf_enabled(vcpu) ||
10949 (vcpu->arch.apf.send_user_only && kvm_x86_ops.get_cpl(vcpu) == 0))
10955 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10957 if (unlikely(!lapic_in_kernel(vcpu) ||
10958 kvm_event_needs_reinjection(vcpu) ||
10959 vcpu->arch.exception.pending))
10962 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10966 * If interrupts are off we cannot even use an artificial
10969 return kvm_arch_interrupt_allowed(vcpu);
10972 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10973 struct kvm_async_pf *work)
10975 struct x86_exception fault;
10977 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
10978 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
10980 if (kvm_can_deliver_async_pf(vcpu) &&
10981 !apf_put_user_notpresent(vcpu)) {
10982 fault.vector = PF_VECTOR;
10983 fault.error_code_valid = true;
10984 fault.error_code = 0;
10985 fault.nested_page_fault = false;
10986 fault.address = work->arch.token;
10987 fault.async_page_fault = true;
10988 kvm_inject_page_fault(vcpu, &fault);
10992 * It is not possible to deliver a paravirtualized asynchronous
10993 * page fault, but putting the guest in an artificial halt state
10994 * can be beneficial nevertheless: if an interrupt arrives, we
10995 * can deliver it timely and perhaps the guest will schedule
10996 * another process. When the instruction that triggered a page
10997 * fault is retried, hopefully the page will be ready in the host.
10999 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
11004 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
11005 struct kvm_async_pf *work)
11007 struct kvm_lapic_irq irq = {
11008 .delivery_mode = APIC_DM_FIXED,
11009 .vector = vcpu->arch.apf.vec
11012 if (work->wakeup_all)
11013 work->arch.token = ~0; /* broadcast wakeup */
11015 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
11016 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
11018 if ((work->wakeup_all || work->notpresent_injected) &&
11019 kvm_pv_async_pf_enabled(vcpu) &&
11020 !apf_put_user_ready(vcpu, work->arch.token)) {
11021 vcpu->arch.apf.pageready_pending = true;
11022 kvm_apic_set_irq(vcpu, &irq, NULL);
11025 vcpu->arch.apf.halted = false;
11026 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11029 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
11031 kvm_make_request(KVM_REQ_APF_READY, vcpu);
11032 if (!vcpu->arch.apf.pageready_pending)
11033 kvm_vcpu_kick(vcpu);
11036 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
11038 if (!kvm_pv_async_pf_enabled(vcpu))
11041 return apf_pageready_slot_free(vcpu);
11044 void kvm_arch_start_assignment(struct kvm *kvm)
11046 atomic_inc(&kvm->arch.assigned_device_count);
11048 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
11050 void kvm_arch_end_assignment(struct kvm *kvm)
11052 atomic_dec(&kvm->arch.assigned_device_count);
11054 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
11056 bool kvm_arch_has_assigned_device(struct kvm *kvm)
11058 return atomic_read(&kvm->arch.assigned_device_count);
11060 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
11062 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
11064 atomic_inc(&kvm->arch.noncoherent_dma_count);
11066 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
11068 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
11070 atomic_dec(&kvm->arch.noncoherent_dma_count);
11072 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
11074 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
11076 return atomic_read(&kvm->arch.noncoherent_dma_count);
11078 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
11080 bool kvm_arch_has_irq_bypass(void)
11085 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
11086 struct irq_bypass_producer *prod)
11088 struct kvm_kernel_irqfd *irqfd =
11089 container_of(cons, struct kvm_kernel_irqfd, consumer);
11092 irqfd->producer = prod;
11093 kvm_arch_start_assignment(irqfd->kvm);
11094 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm,
11095 prod->irq, irqfd->gsi, 1);
11098 kvm_arch_end_assignment(irqfd->kvm);
11103 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
11104 struct irq_bypass_producer *prod)
11107 struct kvm_kernel_irqfd *irqfd =
11108 container_of(cons, struct kvm_kernel_irqfd, consumer);
11110 WARN_ON(irqfd->producer != prod);
11111 irqfd->producer = NULL;
11114 * When producer of consumer is unregistered, we change back to
11115 * remapped mode, so we can re-use the current implementation
11116 * when the irq is masked/disabled or the consumer side (KVM
11117 * int this case doesn't want to receive the interrupts.
11119 ret = kvm_x86_ops.update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
11121 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
11122 " fails: %d\n", irqfd->consumer.token, ret);
11124 kvm_arch_end_assignment(irqfd->kvm);
11127 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
11128 uint32_t guest_irq, bool set)
11130 return kvm_x86_ops.update_pi_irte(kvm, host_irq, guest_irq, set);
11133 bool kvm_vector_hashing_enabled(void)
11135 return vector_hashing;
11138 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
11140 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
11142 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
11145 int kvm_spec_ctrl_test_value(u64 value)
11148 * test that setting IA32_SPEC_CTRL to given value
11149 * is allowed by the host processor
11153 unsigned long flags;
11156 local_irq_save(flags);
11158 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
11160 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
11163 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
11165 local_irq_restore(flags);
11169 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
11171 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
11173 struct x86_exception fault;
11174 u32 access = error_code &
11175 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
11177 if (!(error_code & PFERR_PRESENT_MASK) ||
11178 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
11180 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
11181 * tables probably do not match the TLB. Just proceed
11182 * with the error code that the processor gave.
11184 fault.vector = PF_VECTOR;
11185 fault.error_code_valid = true;
11186 fault.error_code = error_code;
11187 fault.nested_page_fault = false;
11188 fault.address = gva;
11190 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
11192 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
11195 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
11196 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
11197 * indicates whether exit to userspace is needed.
11199 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
11200 struct x86_exception *e)
11202 if (r == X86EMUL_PROPAGATE_FAULT) {
11203 kvm_inject_emulated_page_fault(vcpu, e);
11208 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
11209 * while handling a VMX instruction KVM could've handled the request
11210 * correctly by exiting to userspace and performing I/O but there
11211 * doesn't seem to be a real use-case behind such requests, just return
11212 * KVM_EXIT_INTERNAL_ERROR for now.
11214 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11215 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11216 vcpu->run->internal.ndata = 0;
11220 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
11222 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
11225 struct x86_exception e;
11227 unsigned long roots_to_free = 0;
11234 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
11235 if (r != X86EMUL_CONTINUE)
11236 return kvm_handle_memory_failure(vcpu, r, &e);
11238 if (operand.pcid >> 12 != 0) {
11239 kvm_inject_gp(vcpu, 0);
11243 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
11246 case INVPCID_TYPE_INDIV_ADDR:
11247 if ((!pcid_enabled && (operand.pcid != 0)) ||
11248 is_noncanonical_address(operand.gla, vcpu)) {
11249 kvm_inject_gp(vcpu, 0);
11252 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
11253 return kvm_skip_emulated_instruction(vcpu);
11255 case INVPCID_TYPE_SINGLE_CTXT:
11256 if (!pcid_enabled && (operand.pcid != 0)) {
11257 kvm_inject_gp(vcpu, 0);
11261 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
11262 kvm_mmu_sync_roots(vcpu);
11263 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
11266 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
11267 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd)
11269 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
11271 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
11273 * If neither the current cr3 nor any of the prev_roots use the
11274 * given PCID, then nothing needs to be done here because a
11275 * resync will happen anyway before switching to any other CR3.
11278 return kvm_skip_emulated_instruction(vcpu);
11280 case INVPCID_TYPE_ALL_NON_GLOBAL:
11282 * Currently, KVM doesn't mark global entries in the shadow
11283 * page tables, so a non-global flush just degenerates to a
11284 * global flush. If needed, we could optimize this later by
11285 * keeping track of global entries in shadow page tables.
11289 case INVPCID_TYPE_ALL_INCL_GLOBAL:
11290 kvm_mmu_unload(vcpu);
11291 return kvm_skip_emulated_instruction(vcpu);
11294 BUG(); /* We have already checked above that type <= 3 */
11297 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
11299 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
11301 struct kvm_run *run = vcpu->run;
11302 struct kvm_mmio_fragment *frag;
11305 BUG_ON(!vcpu->mmio_needed);
11307 /* Complete previous fragment */
11308 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11309 len = min(8u, frag->len);
11310 if (!vcpu->mmio_is_write)
11311 memcpy(frag->data, run->mmio.data, len);
11313 if (frag->len <= 8) {
11314 /* Switch to the next fragment. */
11316 vcpu->mmio_cur_fragment++;
11318 /* Go forward to the next mmio piece. */
11324 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11325 vcpu->mmio_needed = 0;
11327 // VMG change, at this point, we're always done
11328 // RIP has already been advanced
11332 // More MMIO is needed
11333 run->mmio.phys_addr = frag->gpa;
11334 run->mmio.len = min(8u, frag->len);
11335 run->mmio.is_write = vcpu->mmio_is_write;
11336 if (run->mmio.is_write)
11337 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11338 run->exit_reason = KVM_EXIT_MMIO;
11340 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11345 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11349 struct kvm_mmio_fragment *frag;
11354 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11355 if (handled == bytes)
11362 /*TODO: Check if need to increment number of frags */
11363 frag = vcpu->mmio_fragments;
11364 vcpu->mmio_nr_fragments = 1;
11369 vcpu->mmio_needed = 1;
11370 vcpu->mmio_cur_fragment = 0;
11372 vcpu->run->mmio.phys_addr = gpa;
11373 vcpu->run->mmio.len = min(8u, frag->len);
11374 vcpu->run->mmio.is_write = 1;
11375 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
11376 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11378 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11382 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
11384 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
11388 struct kvm_mmio_fragment *frag;
11393 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
11394 if (handled == bytes)
11401 /*TODO: Check if need to increment number of frags */
11402 frag = vcpu->mmio_fragments;
11403 vcpu->mmio_nr_fragments = 1;
11408 vcpu->mmio_needed = 1;
11409 vcpu->mmio_cur_fragment = 0;
11411 vcpu->run->mmio.phys_addr = gpa;
11412 vcpu->run->mmio.len = min(8u, frag->len);
11413 vcpu->run->mmio.is_write = 0;
11414 vcpu->run->exit_reason = KVM_EXIT_MMIO;
11416 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
11420 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
11422 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
11424 memcpy(vcpu->arch.guest_ins_data, vcpu->arch.pio_data,
11425 vcpu->arch.pio.count * vcpu->arch.pio.size);
11426 vcpu->arch.pio.count = 0;
11431 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
11432 unsigned int port, void *data, unsigned int count)
11436 ret = emulator_pio_out_emulated(vcpu->arch.emulate_ctxt, size, port,
11441 vcpu->arch.pio.count = 0;
11446 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
11447 unsigned int port, void *data, unsigned int count)
11451 ret = emulator_pio_in_emulated(vcpu->arch.emulate_ctxt, size, port,
11454 vcpu->arch.pio.count = 0;
11456 vcpu->arch.guest_ins_data = data;
11457 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
11463 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
11464 unsigned int port, void *data, unsigned int count,
11467 return in ? kvm_sev_es_ins(vcpu, size, port, data, count)
11468 : kvm_sev_es_outs(vcpu, size, port, data, count);
11470 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
11472 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
11473 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
11474 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
11475 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
11476 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
11477 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
11478 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
11479 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
11480 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
11481 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
11482 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
11483 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
11484 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
11485 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
11486 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
11487 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
11488 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
11489 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
11490 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
11491 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
11492 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
11493 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
11494 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
11495 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
11496 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
11497 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);