1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <linux/sched/stat.h>
58 #include <linux/sched/isolation.h>
59 #include <linux/mem_encrypt.h>
60 #include <linux/entry-kvm.h>
61 #include <linux/suspend.h>
63 #include <trace/events/kvm.h>
65 #include <asm/debugreg.h>
70 #include <linux/kernel_stat.h>
71 #include <asm/fpu/api.h>
72 #include <asm/fpu/xcr.h>
73 #include <asm/fpu/xstate.h>
74 #include <asm/pvclock.h>
75 #include <asm/div64.h>
76 #include <asm/irq_remapping.h>
77 #include <asm/mshyperv.h>
78 #include <asm/hypervisor.h>
79 #include <asm/tlbflush.h>
80 #include <asm/intel_pt.h>
81 #include <asm/emulate_prefix.h>
83 #include <clocksource/hyperv_timer.h>
85 #define CREATE_TRACE_POINTS
88 #define MAX_IO_MSRS 256
89 #define KVM_MAX_MCE_BANKS 32
90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
93 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
95 #define emul_to_vcpu(ctxt) \
96 ((struct kvm_vcpu *)(ctxt)->vcpu)
99 * - enable syscall per default because its emulated by KVM
100 * - enable LME and LMA per default on 64 bit KVM
104 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
106 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
109 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
111 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
113 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
115 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
116 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
118 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
119 static void process_nmi(struct kvm_vcpu *vcpu);
120 static void process_smi(struct kvm_vcpu *vcpu);
121 static void enter_smm(struct kvm_vcpu *vcpu);
122 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
123 static void store_regs(struct kvm_vcpu *vcpu);
124 static int sync_regs(struct kvm_vcpu *vcpu);
125 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
127 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
128 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
130 struct kvm_x86_ops kvm_x86_ops __read_mostly;
132 #define KVM_X86_OP(func) \
133 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
134 *(((struct kvm_x86_ops *)0)->func));
135 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
136 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
137 #include <asm/kvm-x86-ops.h>
138 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
139 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
141 static bool __read_mostly ignore_msrs = 0;
142 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
144 bool __read_mostly report_ignored_msrs = true;
145 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
146 EXPORT_SYMBOL_GPL(report_ignored_msrs);
148 unsigned int min_timer_period_us = 200;
149 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
151 static bool __read_mostly kvmclock_periodic_sync = true;
152 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
154 bool __read_mostly kvm_has_tsc_control;
155 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
156 u32 __read_mostly kvm_max_guest_tsc_khz;
157 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
158 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
159 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
160 u64 __read_mostly kvm_max_tsc_scaling_ratio;
161 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
162 u64 __read_mostly kvm_default_tsc_scaling_ratio;
163 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
164 bool __read_mostly kvm_has_bus_lock_exit;
165 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit);
167 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
168 static u32 __read_mostly tsc_tolerance_ppm = 250;
169 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
172 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
173 * adaptive tuning starting from default advancement of 1000ns. '0' disables
174 * advancement entirely. Any other value is used as-is and disables adaptive
175 * tuning, i.e. allows privileged userspace to set an exact advancement time.
177 static int __read_mostly lapic_timer_advance_ns = -1;
178 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
180 static bool __read_mostly vector_hashing = true;
181 module_param(vector_hashing, bool, S_IRUGO);
183 bool __read_mostly enable_vmware_backdoor = false;
184 module_param(enable_vmware_backdoor, bool, S_IRUGO);
185 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
187 static bool __read_mostly force_emulation_prefix = false;
188 module_param(force_emulation_prefix, bool, S_IRUGO);
190 int __read_mostly pi_inject_timer = -1;
191 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
193 /* Enable/disable PMU virtualization */
194 bool __read_mostly enable_pmu = true;
195 EXPORT_SYMBOL_GPL(enable_pmu);
196 module_param(enable_pmu, bool, 0444);
198 bool __read_mostly eager_page_split = true;
199 module_param(eager_page_split, bool, 0644);
202 * Restoring the host value for MSRs that are only consumed when running in
203 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
204 * returns to userspace, i.e. the kernel can run with the guest's value.
206 #define KVM_MAX_NR_USER_RETURN_MSRS 16
208 struct kvm_user_return_msrs {
209 struct user_return_notifier urn;
211 struct kvm_user_return_msr_values {
214 } values[KVM_MAX_NR_USER_RETURN_MSRS];
217 u32 __read_mostly kvm_nr_uret_msrs;
218 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
219 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
220 static struct kvm_user_return_msrs __percpu *user_return_msrs;
222 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
223 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
224 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
225 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
227 u64 __read_mostly host_efer;
228 EXPORT_SYMBOL_GPL(host_efer);
230 bool __read_mostly allow_smaller_maxphyaddr = 0;
231 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
233 bool __read_mostly enable_apicv = true;
234 EXPORT_SYMBOL_GPL(enable_apicv);
236 u64 __read_mostly host_xss;
237 EXPORT_SYMBOL_GPL(host_xss);
238 u64 __read_mostly supported_xss;
239 EXPORT_SYMBOL_GPL(supported_xss);
241 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
242 KVM_GENERIC_VM_STATS(),
243 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
244 STATS_DESC_COUNTER(VM, mmu_pte_write),
245 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
246 STATS_DESC_COUNTER(VM, mmu_flooded),
247 STATS_DESC_COUNTER(VM, mmu_recycled),
248 STATS_DESC_COUNTER(VM, mmu_cache_miss),
249 STATS_DESC_ICOUNTER(VM, mmu_unsync),
250 STATS_DESC_ICOUNTER(VM, pages_4k),
251 STATS_DESC_ICOUNTER(VM, pages_2m),
252 STATS_DESC_ICOUNTER(VM, pages_1g),
253 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
254 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
255 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
258 const struct kvm_stats_header kvm_vm_stats_header = {
259 .name_size = KVM_STATS_NAME_SIZE,
260 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
261 .id_offset = sizeof(struct kvm_stats_header),
262 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
263 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
264 sizeof(kvm_vm_stats_desc),
267 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
268 KVM_GENERIC_VCPU_STATS(),
269 STATS_DESC_COUNTER(VCPU, pf_fixed),
270 STATS_DESC_COUNTER(VCPU, pf_guest),
271 STATS_DESC_COUNTER(VCPU, tlb_flush),
272 STATS_DESC_COUNTER(VCPU, invlpg),
273 STATS_DESC_COUNTER(VCPU, exits),
274 STATS_DESC_COUNTER(VCPU, io_exits),
275 STATS_DESC_COUNTER(VCPU, mmio_exits),
276 STATS_DESC_COUNTER(VCPU, signal_exits),
277 STATS_DESC_COUNTER(VCPU, irq_window_exits),
278 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
279 STATS_DESC_COUNTER(VCPU, l1d_flush),
280 STATS_DESC_COUNTER(VCPU, halt_exits),
281 STATS_DESC_COUNTER(VCPU, request_irq_exits),
282 STATS_DESC_COUNTER(VCPU, irq_exits),
283 STATS_DESC_COUNTER(VCPU, host_state_reload),
284 STATS_DESC_COUNTER(VCPU, fpu_reload),
285 STATS_DESC_COUNTER(VCPU, insn_emulation),
286 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
287 STATS_DESC_COUNTER(VCPU, hypercalls),
288 STATS_DESC_COUNTER(VCPU, irq_injections),
289 STATS_DESC_COUNTER(VCPU, nmi_injections),
290 STATS_DESC_COUNTER(VCPU, req_event),
291 STATS_DESC_COUNTER(VCPU, nested_run),
292 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
293 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
294 STATS_DESC_ICOUNTER(VCPU, guest_mode)
297 const struct kvm_stats_header kvm_vcpu_stats_header = {
298 .name_size = KVM_STATS_NAME_SIZE,
299 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
300 .id_offset = sizeof(struct kvm_stats_header),
301 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
302 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
303 sizeof(kvm_vcpu_stats_desc),
306 u64 __read_mostly host_xcr0;
307 u64 __read_mostly supported_xcr0;
308 EXPORT_SYMBOL_GPL(supported_xcr0);
310 static struct kmem_cache *x86_emulator_cache;
313 * When called, it means the previous get/set msr reached an invalid msr.
314 * Return true if we want to ignore/silent this failed msr access.
316 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
318 const char *op = write ? "wrmsr" : "rdmsr";
321 if (report_ignored_msrs)
322 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
327 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
333 static struct kmem_cache *kvm_alloc_emulator_cache(void)
335 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
336 unsigned int size = sizeof(struct x86_emulate_ctxt);
338 return kmem_cache_create_usercopy("x86_emulator", size,
339 __alignof__(struct x86_emulate_ctxt),
340 SLAB_ACCOUNT, useroffset,
341 size - useroffset, NULL);
344 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
346 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
349 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
350 vcpu->arch.apf.gfns[i] = ~0;
353 static void kvm_on_user_return(struct user_return_notifier *urn)
356 struct kvm_user_return_msrs *msrs
357 = container_of(urn, struct kvm_user_return_msrs, urn);
358 struct kvm_user_return_msr_values *values;
362 * Disabling irqs at this point since the following code could be
363 * interrupted and executed through kvm_arch_hardware_disable()
365 local_irq_save(flags);
366 if (msrs->registered) {
367 msrs->registered = false;
368 user_return_notifier_unregister(urn);
370 local_irq_restore(flags);
371 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
372 values = &msrs->values[slot];
373 if (values->host != values->curr) {
374 wrmsrl(kvm_uret_msrs_list[slot], values->host);
375 values->curr = values->host;
380 static int kvm_probe_user_return_msr(u32 msr)
386 ret = rdmsrl_safe(msr, &val);
389 ret = wrmsrl_safe(msr, val);
395 int kvm_add_user_return_msr(u32 msr)
397 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
399 if (kvm_probe_user_return_msr(msr))
402 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
403 return kvm_nr_uret_msrs++;
405 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
407 int kvm_find_user_return_msr(u32 msr)
411 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
412 if (kvm_uret_msrs_list[i] == msr)
417 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
419 static void kvm_user_return_msr_cpu_online(void)
421 unsigned int cpu = smp_processor_id();
422 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
426 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
427 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
428 msrs->values[i].host = value;
429 msrs->values[i].curr = value;
433 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
435 unsigned int cpu = smp_processor_id();
436 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
439 value = (value & mask) | (msrs->values[slot].host & ~mask);
440 if (value == msrs->values[slot].curr)
442 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
446 msrs->values[slot].curr = value;
447 if (!msrs->registered) {
448 msrs->urn.on_user_return = kvm_on_user_return;
449 user_return_notifier_register(&msrs->urn);
450 msrs->registered = true;
454 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
456 static void drop_user_return_notifiers(void)
458 unsigned int cpu = smp_processor_id();
459 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
461 if (msrs->registered)
462 kvm_on_user_return(&msrs->urn);
465 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
467 return vcpu->arch.apic_base;
469 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
471 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
473 return kvm_apic_mode(kvm_get_apic_base(vcpu));
475 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
477 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
479 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
480 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
481 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
482 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
484 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
486 if (!msr_info->host_initiated) {
487 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
489 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
493 kvm_lapic_set_base(vcpu, msr_info->data);
494 kvm_recalculate_apic_map(vcpu->kvm);
497 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
500 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
502 * Hardware virtualization extension instructions may fault if a reboot turns
503 * off virtualization while processes are running. Usually after catching the
504 * fault we just panic; during reboot instead the instruction is ignored.
506 noinstr void kvm_spurious_fault(void)
508 /* Fault while not rebooting. We want the trace. */
509 BUG_ON(!kvm_rebooting);
511 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
513 #define EXCPT_BENIGN 0
514 #define EXCPT_CONTRIBUTORY 1
517 static int exception_class(int vector)
527 return EXCPT_CONTRIBUTORY;
534 #define EXCPT_FAULT 0
536 #define EXCPT_ABORT 2
537 #define EXCPT_INTERRUPT 3
539 static int exception_type(int vector)
543 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
544 return EXCPT_INTERRUPT;
548 /* #DB is trap, as instruction watchpoints are handled elsewhere */
549 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
552 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
555 /* Reserved exceptions will result in fault */
559 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
561 unsigned nr = vcpu->arch.exception.nr;
562 bool has_payload = vcpu->arch.exception.has_payload;
563 unsigned long payload = vcpu->arch.exception.payload;
571 * "Certain debug exceptions may clear bit 0-3. The
572 * remaining contents of the DR6 register are never
573 * cleared by the processor".
575 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
577 * In order to reflect the #DB exception payload in guest
578 * dr6, three components need to be considered: active low
579 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
581 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
582 * In the target guest dr6:
583 * FIXED_1 bits should always be set.
584 * Active low bits should be cleared if 1-setting in payload.
585 * Active high bits should be set if 1-setting in payload.
587 * Note, the payload is compatible with the pending debug
588 * exceptions/exit qualification under VMX, that active_low bits
589 * are active high in payload.
590 * So they need to be flipped for DR6.
592 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
593 vcpu->arch.dr6 |= payload;
594 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW;
597 * The #DB payload is defined as compatible with the 'pending
598 * debug exceptions' field under VMX, not DR6. While bit 12 is
599 * defined in the 'pending debug exceptions' field (enabled
600 * breakpoint), it is reserved and must be zero in DR6.
602 vcpu->arch.dr6 &= ~BIT(12);
605 vcpu->arch.cr2 = payload;
609 vcpu->arch.exception.has_payload = false;
610 vcpu->arch.exception.payload = 0;
612 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
614 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
615 unsigned nr, bool has_error, u32 error_code,
616 bool has_payload, unsigned long payload, bool reinject)
621 kvm_make_request(KVM_REQ_EVENT, vcpu);
623 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
627 * On vmentry, vcpu->arch.exception.pending is only
628 * true if an event injection was blocked by
629 * nested_run_pending. In that case, however,
630 * vcpu_enter_guest requests an immediate exit,
631 * and the guest shouldn't proceed far enough to
634 WARN_ON_ONCE(vcpu->arch.exception.pending);
635 vcpu->arch.exception.injected = true;
636 if (WARN_ON_ONCE(has_payload)) {
638 * A reinjected event has already
639 * delivered its payload.
645 vcpu->arch.exception.pending = true;
646 vcpu->arch.exception.injected = false;
648 vcpu->arch.exception.has_error_code = has_error;
649 vcpu->arch.exception.nr = nr;
650 vcpu->arch.exception.error_code = error_code;
651 vcpu->arch.exception.has_payload = has_payload;
652 vcpu->arch.exception.payload = payload;
653 if (!is_guest_mode(vcpu))
654 kvm_deliver_exception_payload(vcpu);
658 /* to check exception */
659 prev_nr = vcpu->arch.exception.nr;
660 if (prev_nr == DF_VECTOR) {
661 /* triple fault -> shutdown */
662 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
665 class1 = exception_class(prev_nr);
666 class2 = exception_class(nr);
667 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
668 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
670 * Generate double fault per SDM Table 5-5. Set
671 * exception.pending = true so that the double fault
672 * can trigger a nested vmexit.
674 vcpu->arch.exception.pending = true;
675 vcpu->arch.exception.injected = false;
676 vcpu->arch.exception.has_error_code = true;
677 vcpu->arch.exception.nr = DF_VECTOR;
678 vcpu->arch.exception.error_code = 0;
679 vcpu->arch.exception.has_payload = false;
680 vcpu->arch.exception.payload = 0;
682 /* replace previous exception with a new one in a hope
683 that instruction re-execution will regenerate lost
688 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
690 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
692 EXPORT_SYMBOL_GPL(kvm_queue_exception);
694 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
696 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
698 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
700 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
701 unsigned long payload)
703 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
705 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
707 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
708 u32 error_code, unsigned long payload)
710 kvm_multiple_exception(vcpu, nr, true, error_code,
711 true, payload, false);
714 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
717 kvm_inject_gp(vcpu, 0);
719 return kvm_skip_emulated_instruction(vcpu);
723 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
725 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
728 kvm_inject_gp(vcpu, 0);
732 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
733 EMULTYPE_COMPLETE_USER_EXIT);
736 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
738 ++vcpu->stat.pf_guest;
739 vcpu->arch.exception.nested_apf =
740 is_guest_mode(vcpu) && fault->async_page_fault;
741 if (vcpu->arch.exception.nested_apf) {
742 vcpu->arch.apf.nested_apf_token = fault->address;
743 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
745 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
749 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
751 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
752 struct x86_exception *fault)
754 struct kvm_mmu *fault_mmu;
755 WARN_ON_ONCE(fault->vector != PF_VECTOR);
757 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
761 * Invalidate the TLB entry for the faulting address, if it exists,
762 * else the access will fault indefinitely (and to emulate hardware).
764 if ((fault->error_code & PFERR_PRESENT_MASK) &&
765 !(fault->error_code & PFERR_RSVD_MASK))
766 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
767 fault_mmu->root.hpa);
769 fault_mmu->inject_page_fault(vcpu, fault);
770 return fault->nested_page_fault;
772 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
774 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
776 atomic_inc(&vcpu->arch.nmi_queued);
777 kvm_make_request(KVM_REQ_NMI, vcpu);
779 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
781 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
783 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
785 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
787 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
789 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
791 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
794 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
795 * a #GP and return false.
797 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
799 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
801 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
804 EXPORT_SYMBOL_GPL(kvm_require_cpl);
806 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
808 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
811 kvm_queue_exception(vcpu, UD_VECTOR);
814 EXPORT_SYMBOL_GPL(kvm_require_dr);
816 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
818 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
822 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
824 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
826 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
827 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
831 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
834 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
837 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
838 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
839 if (real_gpa == UNMAPPED_GVA)
842 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
843 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
844 cr3 & GENMASK(11, 5), sizeof(pdpte));
848 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
849 if ((pdpte[i] & PT_PRESENT_MASK) &&
850 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
856 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
857 * Shadow page roots need to be reconstructed instead.
859 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
860 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
862 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
863 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
864 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
865 vcpu->arch.pdptrs_from_userspace = false;
869 EXPORT_SYMBOL_GPL(load_pdptrs);
871 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
873 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
874 kvm_clear_async_pf_completion_queue(vcpu);
875 kvm_async_pf_hash_reset(vcpu);
878 * Clearing CR0.PG is defined to flush the TLB from the guest's
881 if (!(cr0 & X86_CR0_PG))
882 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
885 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
886 kvm_mmu_reset_context(vcpu);
888 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
889 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
890 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
891 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
893 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
895 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
897 unsigned long old_cr0 = kvm_read_cr0(vcpu);
902 if (cr0 & 0xffffffff00000000UL)
906 cr0 &= ~CR0_RESERVED_BITS;
908 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
911 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
915 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
916 (cr0 & X86_CR0_PG)) {
921 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
926 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
927 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
928 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
931 if (!(cr0 & X86_CR0_PG) &&
932 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
935 static_call(kvm_x86_set_cr0)(vcpu, cr0);
937 kvm_post_set_cr0(vcpu, old_cr0, cr0);
941 EXPORT_SYMBOL_GPL(kvm_set_cr0);
943 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
945 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
947 EXPORT_SYMBOL_GPL(kvm_lmsw);
949 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
951 if (vcpu->arch.guest_state_protected)
954 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
956 if (vcpu->arch.xcr0 != host_xcr0)
957 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
959 if (vcpu->arch.xsaves_enabled &&
960 vcpu->arch.ia32_xss != host_xss)
961 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
964 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
965 if (static_cpu_has(X86_FEATURE_PKU) &&
966 vcpu->arch.pkru != vcpu->arch.host_pkru &&
967 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
968 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)))
969 write_pkru(vcpu->arch.pkru);
970 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
972 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
974 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
976 if (vcpu->arch.guest_state_protected)
979 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
980 if (static_cpu_has(X86_FEATURE_PKU) &&
981 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
982 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) {
983 vcpu->arch.pkru = rdpkru();
984 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
985 write_pkru(vcpu->arch.host_pkru);
987 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
989 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
991 if (vcpu->arch.xcr0 != host_xcr0)
992 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
994 if (vcpu->arch.xsaves_enabled &&
995 vcpu->arch.ia32_xss != host_xss)
996 wrmsrl(MSR_IA32_XSS, host_xss);
1000 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1002 static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu)
1004 return vcpu->arch.guest_fpu.fpstate->user_xfeatures;
1007 #ifdef CONFIG_X86_64
1008 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1010 return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC;
1014 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1017 u64 old_xcr0 = vcpu->arch.xcr0;
1020 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1021 if (index != XCR_XFEATURE_ENABLED_MASK)
1023 if (!(xcr0 & XFEATURE_MASK_FP))
1025 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1029 * Do not allow the guest to set bits that we do not support
1030 * saving. However, xcr0 bit 0 is always set, even if the
1031 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1033 valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP;
1034 if (xcr0 & ~valid_bits)
1037 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1038 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1041 if (xcr0 & XFEATURE_MASK_AVX512) {
1042 if (!(xcr0 & XFEATURE_MASK_YMM))
1044 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1048 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1049 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1052 vcpu->arch.xcr0 = xcr0;
1054 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1055 kvm_update_cpuid_runtime(vcpu);
1059 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1061 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1062 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1063 kvm_inject_gp(vcpu, 0);
1067 return kvm_skip_emulated_instruction(vcpu);
1069 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1071 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1073 if (cr4 & cr4_reserved_bits)
1076 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1079 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1081 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
1083 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1085 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1086 kvm_mmu_reset_context(vcpu);
1089 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1090 * according to the SDM; however, stale prev_roots could be reused
1091 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1092 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1093 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1097 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1098 kvm_mmu_unload(vcpu);
1101 * The TLB has to be flushed for all PCIDs if any of the following
1102 * (architecturally required) changes happen:
1103 * - CR4.PCIDE is changed from 1 to 0
1104 * - CR4.PGE is toggled
1106 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1108 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1109 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1110 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1113 * The TLB has to be flushed for the current PCID if any of the
1114 * following (architecturally required) changes happen:
1115 * - CR4.SMEP is changed from 0 to 1
1116 * - CR4.PAE is toggled
1118 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1119 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1120 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1123 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1125 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1127 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1129 if (!kvm_is_valid_cr4(vcpu, cr4))
1132 if (is_long_mode(vcpu)) {
1133 if (!(cr4 & X86_CR4_PAE))
1135 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1137 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1138 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1139 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1142 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1143 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1146 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1147 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1151 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1153 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1157 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1159 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1161 struct kvm_mmu *mmu = vcpu->arch.mmu;
1162 unsigned long roots_to_free = 0;
1166 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1167 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1168 * also via the emulator. KVM's TDP page tables are not in the scope of
1169 * the invalidation, but the guest's TLB entries need to be flushed as
1170 * the CPU may have cached entries in its TLB for the target PCID.
1172 if (unlikely(tdp_enabled)) {
1173 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1178 * If neither the current CR3 nor any of the prev_roots use the given
1179 * PCID, then nothing needs to be done here because a resync will
1180 * happen anyway before switching to any other CR3.
1182 if (kvm_get_active_pcid(vcpu) == pcid) {
1183 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1184 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1188 * If PCID is disabled, there is no need to free prev_roots even if the
1189 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1192 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1195 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1196 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1197 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1199 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1202 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1204 bool skip_tlb_flush = false;
1205 unsigned long pcid = 0;
1206 #ifdef CONFIG_X86_64
1207 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1210 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1211 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1212 pcid = cr3 & X86_CR3_PCID_MASK;
1216 /* PDPTRs are always reloaded for PAE paging. */
1217 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1218 goto handle_tlb_flush;
1221 * Do not condition the GPA check on long mode, this helper is used to
1222 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1223 * the current vCPU mode is accurate.
1225 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1228 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1231 if (cr3 != kvm_read_cr3(vcpu))
1232 kvm_mmu_new_pgd(vcpu, cr3);
1234 vcpu->arch.cr3 = cr3;
1235 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1236 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1240 * A load of CR3 that flushes the TLB flushes only the current PCID,
1241 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1242 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1243 * and it's impossible to use a non-zero PCID when PCID is disabled,
1244 * i.e. only PCID=0 can be relevant.
1246 if (!skip_tlb_flush)
1247 kvm_invalidate_pcid(vcpu, pcid);
1251 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1253 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1255 if (cr8 & CR8_RESERVED_BITS)
1257 if (lapic_in_kernel(vcpu))
1258 kvm_lapic_set_tpr(vcpu, cr8);
1260 vcpu->arch.cr8 = cr8;
1263 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1265 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1267 if (lapic_in_kernel(vcpu))
1268 return kvm_lapic_get_cr8(vcpu);
1270 return vcpu->arch.cr8;
1272 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1274 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1278 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1279 for (i = 0; i < KVM_NR_DB_REGS; i++)
1280 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1284 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1288 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1289 dr7 = vcpu->arch.guest_debug_dr7;
1291 dr7 = vcpu->arch.dr7;
1292 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1293 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1294 if (dr7 & DR7_BP_EN_MASK)
1295 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1297 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1299 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1301 u64 fixed = DR6_FIXED_1;
1303 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1306 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1307 fixed |= DR6_BUS_LOCK;
1311 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1313 size_t size = ARRAY_SIZE(vcpu->arch.db);
1317 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1318 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1319 vcpu->arch.eff_db[dr] = val;
1323 if (!kvm_dr6_valid(val))
1325 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1329 if (!kvm_dr7_valid(val))
1331 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1332 kvm_update_dr7(vcpu);
1338 EXPORT_SYMBOL_GPL(kvm_set_dr);
1340 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1342 size_t size = ARRAY_SIZE(vcpu->arch.db);
1346 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1350 *val = vcpu->arch.dr6;
1354 *val = vcpu->arch.dr7;
1358 EXPORT_SYMBOL_GPL(kvm_get_dr);
1360 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1362 u32 ecx = kvm_rcx_read(vcpu);
1365 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1366 kvm_inject_gp(vcpu, 0);
1370 kvm_rax_write(vcpu, (u32)data);
1371 kvm_rdx_write(vcpu, data >> 32);
1372 return kvm_skip_emulated_instruction(vcpu);
1374 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1377 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1378 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1380 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1381 * extract the supported MSRs from the related const lists.
1382 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1383 * capabilities of the host cpu. This capabilities test skips MSRs that are
1384 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1385 * may depend on host virtualization features rather than host cpu features.
1388 static const u32 msrs_to_save_all[] = {
1389 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1391 #ifdef CONFIG_X86_64
1392 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1394 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1395 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1397 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1398 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1399 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1400 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1401 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1402 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1403 MSR_IA32_UMWAIT_CONTROL,
1405 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1406 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1407 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1408 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1409 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1410 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1411 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1412 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1413 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1414 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1415 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1416 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1417 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1418 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1419 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1420 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1421 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1422 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1423 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1424 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1425 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1426 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1428 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1429 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1430 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1431 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1432 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1433 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1434 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1437 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1438 static unsigned num_msrs_to_save;
1440 static const u32 emulated_msrs_all[] = {
1441 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1442 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1443 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1444 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1445 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1446 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1447 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1449 HV_X64_MSR_VP_INDEX,
1450 HV_X64_MSR_VP_RUNTIME,
1451 HV_X64_MSR_SCONTROL,
1452 HV_X64_MSR_STIMER0_CONFIG,
1453 HV_X64_MSR_VP_ASSIST_PAGE,
1454 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1455 HV_X64_MSR_TSC_EMULATION_STATUS,
1456 HV_X64_MSR_SYNDBG_OPTIONS,
1457 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1458 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1459 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1461 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1462 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1464 MSR_IA32_TSC_ADJUST,
1465 MSR_IA32_TSC_DEADLINE,
1466 MSR_IA32_ARCH_CAPABILITIES,
1467 MSR_IA32_PERF_CAPABILITIES,
1468 MSR_IA32_MISC_ENABLE,
1469 MSR_IA32_MCG_STATUS,
1471 MSR_IA32_MCG_EXT_CTL,
1475 MSR_MISC_FEATURES_ENABLES,
1476 MSR_AMD64_VIRT_SPEC_CTRL,
1477 MSR_AMD64_TSC_RATIO,
1482 * The following list leaves out MSRs whose values are determined
1483 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1484 * We always support the "true" VMX control MSRs, even if the host
1485 * processor does not, so I am putting these registers here rather
1486 * than in msrs_to_save_all.
1489 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1490 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1491 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1492 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1494 MSR_IA32_VMX_CR0_FIXED0,
1495 MSR_IA32_VMX_CR4_FIXED0,
1496 MSR_IA32_VMX_VMCS_ENUM,
1497 MSR_IA32_VMX_PROCBASED_CTLS2,
1498 MSR_IA32_VMX_EPT_VPID_CAP,
1499 MSR_IA32_VMX_VMFUNC,
1502 MSR_KVM_POLL_CONTROL,
1505 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1506 static unsigned num_emulated_msrs;
1509 * List of msr numbers which are used to expose MSR-based features that
1510 * can be used by a hypervisor to validate requested CPU features.
1512 static const u32 msr_based_features_all[] = {
1514 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1515 MSR_IA32_VMX_PINBASED_CTLS,
1516 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1517 MSR_IA32_VMX_PROCBASED_CTLS,
1518 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1519 MSR_IA32_VMX_EXIT_CTLS,
1520 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1521 MSR_IA32_VMX_ENTRY_CTLS,
1523 MSR_IA32_VMX_CR0_FIXED0,
1524 MSR_IA32_VMX_CR0_FIXED1,
1525 MSR_IA32_VMX_CR4_FIXED0,
1526 MSR_IA32_VMX_CR4_FIXED1,
1527 MSR_IA32_VMX_VMCS_ENUM,
1528 MSR_IA32_VMX_PROCBASED_CTLS2,
1529 MSR_IA32_VMX_EPT_VPID_CAP,
1530 MSR_IA32_VMX_VMFUNC,
1534 MSR_IA32_ARCH_CAPABILITIES,
1535 MSR_IA32_PERF_CAPABILITIES,
1538 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1539 static unsigned int num_msr_based_features;
1541 static u64 kvm_get_arch_capabilities(void)
1545 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1546 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1549 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1550 * the nested hypervisor runs with NX huge pages. If it is not,
1551 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1552 * L1 guests, so it need not worry about its own (L2) guests.
1554 data |= ARCH_CAP_PSCHANGE_MC_NO;
1557 * If we're doing cache flushes (either "always" or "cond")
1558 * we will do one whenever the guest does a vmlaunch/vmresume.
1559 * If an outer hypervisor is doing the cache flush for us
1560 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1561 * capability to the guest too, and if EPT is disabled we're not
1562 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1563 * require a nested hypervisor to do a flush of its own.
1565 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1566 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1568 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1569 data |= ARCH_CAP_RDCL_NO;
1570 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1571 data |= ARCH_CAP_SSB_NO;
1572 if (!boot_cpu_has_bug(X86_BUG_MDS))
1573 data |= ARCH_CAP_MDS_NO;
1575 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1577 * If RTM=0 because the kernel has disabled TSX, the host might
1578 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1579 * and therefore knows that there cannot be TAA) but keep
1580 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1581 * and we want to allow migrating those guests to tsx=off hosts.
1583 data &= ~ARCH_CAP_TAA_NO;
1584 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1585 data |= ARCH_CAP_TAA_NO;
1588 * Nothing to do here; we emulate TSX_CTRL if present on the
1589 * host so the guest can choose between disabling TSX or
1590 * using VERW to clear CPU buffers.
1597 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1599 switch (msr->index) {
1600 case MSR_IA32_ARCH_CAPABILITIES:
1601 msr->data = kvm_get_arch_capabilities();
1603 case MSR_IA32_UCODE_REV:
1604 rdmsrl_safe(msr->index, &msr->data);
1607 return static_call(kvm_x86_get_msr_feature)(msr);
1612 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1614 struct kvm_msr_entry msr;
1618 r = kvm_get_msr_feature(&msr);
1620 if (r == KVM_MSR_RET_INVALID) {
1621 /* Unconditionally clear the output for simplicity */
1623 if (kvm_msr_ignored_check(index, 0, false))
1635 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1637 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1640 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1643 if (efer & (EFER_LME | EFER_LMA) &&
1644 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1647 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1653 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1655 if (efer & efer_reserved_bits)
1658 return __kvm_valid_efer(vcpu, efer);
1660 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1662 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1664 u64 old_efer = vcpu->arch.efer;
1665 u64 efer = msr_info->data;
1668 if (efer & efer_reserved_bits)
1671 if (!msr_info->host_initiated) {
1672 if (!__kvm_valid_efer(vcpu, efer))
1675 if (is_paging(vcpu) &&
1676 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1681 efer |= vcpu->arch.efer & EFER_LMA;
1683 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1689 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1690 kvm_mmu_reset_context(vcpu);
1695 void kvm_enable_efer_bits(u64 mask)
1697 efer_reserved_bits &= ~mask;
1699 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1701 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1703 struct kvm_x86_msr_filter *msr_filter;
1704 struct msr_bitmap_range *ranges;
1705 struct kvm *kvm = vcpu->kvm;
1710 /* x2APIC MSRs do not support filtering. */
1711 if (index >= 0x800 && index <= 0x8ff)
1714 idx = srcu_read_lock(&kvm->srcu);
1716 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1722 allowed = msr_filter->default_allow;
1723 ranges = msr_filter->ranges;
1725 for (i = 0; i < msr_filter->count; i++) {
1726 u32 start = ranges[i].base;
1727 u32 end = start + ranges[i].nmsrs;
1728 u32 flags = ranges[i].flags;
1729 unsigned long *bitmap = ranges[i].bitmap;
1731 if ((index >= start) && (index < end) && (flags & type)) {
1732 allowed = !!test_bit(index - start, bitmap);
1738 srcu_read_unlock(&kvm->srcu, idx);
1742 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1745 * Write @data into the MSR specified by @index. Select MSR specific fault
1746 * checks are bypassed if @host_initiated is %true.
1747 * Returns 0 on success, non-0 otherwise.
1748 * Assumes vcpu_load() was already called.
1750 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1751 bool host_initiated)
1753 struct msr_data msr;
1758 case MSR_KERNEL_GS_BASE:
1761 if (is_noncanonical_address(data, vcpu))
1764 case MSR_IA32_SYSENTER_EIP:
1765 case MSR_IA32_SYSENTER_ESP:
1767 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1768 * non-canonical address is written on Intel but not on
1769 * AMD (which ignores the top 32-bits, because it does
1770 * not implement 64-bit SYSENTER).
1772 * 64-bit code should hence be able to write a non-canonical
1773 * value on AMD. Making the address canonical ensures that
1774 * vmentry does not fail on Intel after writing a non-canonical
1775 * value, and that something deterministic happens if the guest
1776 * invokes 64-bit SYSENTER.
1778 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1781 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1784 if (!host_initiated &&
1785 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1786 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1790 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1791 * incomplete and conflicting architectural behavior. Current
1792 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1793 * reserved and always read as zeros. Enforce Intel's reserved
1794 * bits check if and only if the guest CPU is Intel, and clear
1795 * the bits in all other cases. This ensures cross-vendor
1796 * migration will provide consistent behavior for the guest.
1798 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1807 msr.host_initiated = host_initiated;
1809 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1812 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1813 u32 index, u64 data, bool host_initiated)
1815 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1817 if (ret == KVM_MSR_RET_INVALID)
1818 if (kvm_msr_ignored_check(index, data, true))
1825 * Read the MSR specified by @index into @data. Select MSR specific fault
1826 * checks are bypassed if @host_initiated is %true.
1827 * Returns 0 on success, non-0 otherwise.
1828 * Assumes vcpu_load() was already called.
1830 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1831 bool host_initiated)
1833 struct msr_data msr;
1838 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1841 if (!host_initiated &&
1842 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1843 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1849 msr.host_initiated = host_initiated;
1851 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1857 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1858 u32 index, u64 *data, bool host_initiated)
1860 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1862 if (ret == KVM_MSR_RET_INVALID) {
1863 /* Unconditionally clear *data for simplicity */
1865 if (kvm_msr_ignored_check(index, 0, false))
1872 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1874 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1875 return KVM_MSR_RET_FILTERED;
1876 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1879 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1881 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1882 return KVM_MSR_RET_FILTERED;
1883 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1886 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1888 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1890 EXPORT_SYMBOL_GPL(kvm_get_msr);
1892 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1894 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1896 EXPORT_SYMBOL_GPL(kvm_set_msr);
1898 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1900 if (!vcpu->run->msr.error) {
1901 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1902 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1906 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1908 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1911 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1913 complete_userspace_rdmsr(vcpu);
1914 return complete_emulated_msr_access(vcpu);
1917 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1919 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1922 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1924 complete_userspace_rdmsr(vcpu);
1925 return complete_fast_msr_access(vcpu);
1928 static u64 kvm_msr_reason(int r)
1931 case KVM_MSR_RET_INVALID:
1932 return KVM_MSR_EXIT_REASON_UNKNOWN;
1933 case KVM_MSR_RET_FILTERED:
1934 return KVM_MSR_EXIT_REASON_FILTER;
1936 return KVM_MSR_EXIT_REASON_INVAL;
1940 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1941 u32 exit_reason, u64 data,
1942 int (*completion)(struct kvm_vcpu *vcpu),
1945 u64 msr_reason = kvm_msr_reason(r);
1947 /* Check if the user wanted to know about this MSR fault */
1948 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1951 vcpu->run->exit_reason = exit_reason;
1952 vcpu->run->msr.error = 0;
1953 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1954 vcpu->run->msr.reason = msr_reason;
1955 vcpu->run->msr.index = index;
1956 vcpu->run->msr.data = data;
1957 vcpu->arch.complete_userspace_io = completion;
1962 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1964 u32 ecx = kvm_rcx_read(vcpu);
1968 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
1971 trace_kvm_msr_read(ecx, data);
1973 kvm_rax_write(vcpu, data & -1u);
1974 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1976 /* MSR read failed? See if we should ask user space */
1977 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
1978 complete_fast_rdmsr, r))
1980 trace_kvm_msr_read_ex(ecx);
1983 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1985 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1987 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1989 u32 ecx = kvm_rcx_read(vcpu);
1990 u64 data = kvm_read_edx_eax(vcpu);
1993 r = kvm_set_msr_with_filter(vcpu, ecx, data);
1996 trace_kvm_msr_write(ecx, data);
1998 /* MSR write failed? See if we should ask user space */
1999 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2000 complete_fast_msr_access, r))
2002 /* Signal all other negative errors to userspace */
2005 trace_kvm_msr_write_ex(ecx, data);
2008 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2010 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2012 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2014 return kvm_skip_emulated_instruction(vcpu);
2016 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop);
2018 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2020 /* Treat an INVD instruction as a NOP and just skip it. */
2021 return kvm_emulate_as_nop(vcpu);
2023 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2025 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2027 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n");
2028 return kvm_emulate_as_nop(vcpu);
2030 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2032 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2034 kvm_queue_exception(vcpu, UD_VECTOR);
2037 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2039 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2041 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n");
2042 return kvm_emulate_as_nop(vcpu);
2044 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2046 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2048 xfer_to_guest_mode_prepare();
2049 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2050 xfer_to_guest_mode_work_pending();
2054 * The fast path for frequent and performance sensitive wrmsr emulation,
2055 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2056 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2057 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2058 * other cases which must be called after interrupts are enabled on the host.
2060 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2062 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2065 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2066 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2067 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2068 ((u32)(data >> 32) != X2APIC_BROADCAST))
2069 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2074 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2076 if (!kvm_can_use_hv_timer(vcpu))
2079 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2083 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2085 u32 msr = kvm_rcx_read(vcpu);
2087 fastpath_t ret = EXIT_FASTPATH_NONE;
2090 case APIC_BASE_MSR + (APIC_ICR >> 4):
2091 data = kvm_read_edx_eax(vcpu);
2092 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2093 kvm_skip_emulated_instruction(vcpu);
2094 ret = EXIT_FASTPATH_EXIT_HANDLED;
2097 case MSR_IA32_TSC_DEADLINE:
2098 data = kvm_read_edx_eax(vcpu);
2099 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2100 kvm_skip_emulated_instruction(vcpu);
2101 ret = EXIT_FASTPATH_REENTER_GUEST;
2108 if (ret != EXIT_FASTPATH_NONE)
2109 trace_kvm_msr_write(msr, data);
2113 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2116 * Adapt set_msr() to msr_io()'s calling convention
2118 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2120 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2123 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2125 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2128 #ifdef CONFIG_X86_64
2129 struct pvclock_clock {
2139 struct pvclock_gtod_data {
2142 struct pvclock_clock clock; /* extract of a clocksource struct */
2143 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2149 static struct pvclock_gtod_data pvclock_gtod_data;
2151 static void update_pvclock_gtod(struct timekeeper *tk)
2153 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2155 write_seqcount_begin(&vdata->seq);
2157 /* copy pvclock gtod data */
2158 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2159 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2160 vdata->clock.mask = tk->tkr_mono.mask;
2161 vdata->clock.mult = tk->tkr_mono.mult;
2162 vdata->clock.shift = tk->tkr_mono.shift;
2163 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2164 vdata->clock.offset = tk->tkr_mono.base;
2166 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2167 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2168 vdata->raw_clock.mask = tk->tkr_raw.mask;
2169 vdata->raw_clock.mult = tk->tkr_raw.mult;
2170 vdata->raw_clock.shift = tk->tkr_raw.shift;
2171 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2172 vdata->raw_clock.offset = tk->tkr_raw.base;
2174 vdata->wall_time_sec = tk->xtime_sec;
2176 vdata->offs_boot = tk->offs_boot;
2178 write_seqcount_end(&vdata->seq);
2181 static s64 get_kvmclock_base_ns(void)
2183 /* Count up from boot time, but with the frequency of the raw clock. */
2184 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2187 static s64 get_kvmclock_base_ns(void)
2189 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2190 return ktime_get_boottime_ns();
2194 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2198 struct pvclock_wall_clock wc;
2205 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2210 ++version; /* first time write, random junk */
2214 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2218 * The guest calculates current wall clock time by adding
2219 * system time (updated by kvm_guest_time_update below) to the
2220 * wall clock specified here. We do the reverse here.
2222 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2224 wc.nsec = do_div(wall_nsec, 1000000000);
2225 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2226 wc.version = version;
2228 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2231 wc_sec_hi = wall_nsec >> 32;
2232 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2233 &wc_sec_hi, sizeof(wc_sec_hi));
2237 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2240 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2241 bool old_msr, bool host_initiated)
2243 struct kvm_arch *ka = &vcpu->kvm->arch;
2245 if (vcpu->vcpu_id == 0 && !host_initiated) {
2246 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2247 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2249 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2252 vcpu->arch.time = system_time;
2253 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2255 /* we verify if the enable bit is set... */
2256 if (system_time & 1) {
2257 kvm_gfn_to_pfn_cache_init(vcpu->kvm, &vcpu->arch.pv_time, vcpu,
2258 KVM_HOST_USES_PFN, system_time & ~1ULL,
2259 sizeof(struct pvclock_vcpu_time_info));
2261 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time);
2267 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2269 do_shl32_div32(dividend, divisor);
2273 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2274 s8 *pshift, u32 *pmultiplier)
2282 scaled64 = scaled_hz;
2283 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2288 tps32 = (uint32_t)tps64;
2289 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2290 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2298 *pmultiplier = div_frac(scaled64, tps32);
2301 #ifdef CONFIG_X86_64
2302 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2305 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2306 static unsigned long max_tsc_khz;
2308 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2310 u64 v = (u64)khz * (1000000 + ppm);
2315 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2317 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2321 /* Guest TSC same frequency as host TSC? */
2323 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
2327 /* TSC scaling supported? */
2328 if (!kvm_has_tsc_control) {
2329 if (user_tsc_khz > tsc_khz) {
2330 vcpu->arch.tsc_catchup = 1;
2331 vcpu->arch.tsc_always_catchup = 1;
2334 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2339 /* TSC scaling required - calculate ratio */
2340 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2341 user_tsc_khz, tsc_khz);
2343 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2344 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2349 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2353 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2355 u32 thresh_lo, thresh_hi;
2356 int use_scaling = 0;
2358 /* tsc_khz can be zero if TSC calibration fails */
2359 if (user_tsc_khz == 0) {
2360 /* set tsc_scaling_ratio to a safe value */
2361 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
2365 /* Compute a scale to convert nanoseconds in TSC cycles */
2366 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2367 &vcpu->arch.virtual_tsc_shift,
2368 &vcpu->arch.virtual_tsc_mult);
2369 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2372 * Compute the variation in TSC rate which is acceptable
2373 * within the range of tolerance and decide if the
2374 * rate being applied is within that bounds of the hardware
2375 * rate. If so, no scaling or compensation need be done.
2377 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2378 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2379 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2380 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2383 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2386 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2388 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2389 vcpu->arch.virtual_tsc_mult,
2390 vcpu->arch.virtual_tsc_shift);
2391 tsc += vcpu->arch.this_tsc_write;
2395 #ifdef CONFIG_X86_64
2396 static inline int gtod_is_based_on_tsc(int mode)
2398 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2402 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2404 #ifdef CONFIG_X86_64
2406 struct kvm_arch *ka = &vcpu->kvm->arch;
2407 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2409 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2410 atomic_read(&vcpu->kvm->online_vcpus));
2413 * Once the masterclock is enabled, always perform request in
2414 * order to update it.
2416 * In order to enable masterclock, the host clocksource must be TSC
2417 * and the vcpus need to have matched TSCs. When that happens,
2418 * perform request to enable masterclock.
2420 if (ka->use_master_clock ||
2421 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2422 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2424 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2425 atomic_read(&vcpu->kvm->online_vcpus),
2426 ka->use_master_clock, gtod->clock.vclock_mode);
2431 * Multiply tsc by a fixed point number represented by ratio.
2433 * The most significant 64-N bits (mult) of ratio represent the
2434 * integral part of the fixed point number; the remaining N bits
2435 * (frac) represent the fractional part, ie. ratio represents a fixed
2436 * point number (mult + frac * 2^(-N)).
2438 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2440 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2442 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2445 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2449 if (ratio != kvm_default_tsc_scaling_ratio)
2450 _tsc = __scale_tsc(ratio, tsc);
2454 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2456 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2460 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2462 return target_tsc - tsc;
2465 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2467 return vcpu->arch.l1_tsc_offset +
2468 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2470 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2472 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2476 if (l2_multiplier == kvm_default_tsc_scaling_ratio)
2477 nested_offset = l1_offset;
2479 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2480 kvm_tsc_scaling_ratio_frac_bits);
2482 nested_offset += l2_offset;
2483 return nested_offset;
2485 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2487 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2489 if (l2_multiplier != kvm_default_tsc_scaling_ratio)
2490 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2491 kvm_tsc_scaling_ratio_frac_bits);
2493 return l1_multiplier;
2495 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2497 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2499 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2500 vcpu->arch.l1_tsc_offset,
2503 vcpu->arch.l1_tsc_offset = l1_offset;
2506 * If we are here because L1 chose not to trap WRMSR to TSC then
2507 * according to the spec this should set L1's TSC (as opposed to
2508 * setting L1's offset for L2).
2510 if (is_guest_mode(vcpu))
2511 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2513 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2514 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2516 vcpu->arch.tsc_offset = l1_offset;
2518 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2521 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2523 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2525 /* Userspace is changing the multiplier while L2 is active */
2526 if (is_guest_mode(vcpu))
2527 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2529 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2531 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2533 if (kvm_has_tsc_control)
2534 static_call(kvm_x86_write_tsc_multiplier)(
2535 vcpu, vcpu->arch.tsc_scaling_ratio);
2538 static inline bool kvm_check_tsc_unstable(void)
2540 #ifdef CONFIG_X86_64
2542 * TSC is marked unstable when we're running on Hyper-V,
2543 * 'TSC page' clocksource is good.
2545 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2548 return check_tsc_unstable();
2552 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2553 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2556 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2557 u64 ns, bool matched)
2559 struct kvm *kvm = vcpu->kvm;
2561 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2564 * We also track th most recent recorded KHZ, write and time to
2565 * allow the matching interval to be extended at each write.
2567 kvm->arch.last_tsc_nsec = ns;
2568 kvm->arch.last_tsc_write = tsc;
2569 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2570 kvm->arch.last_tsc_offset = offset;
2572 vcpu->arch.last_guest_tsc = tsc;
2574 kvm_vcpu_write_tsc_offset(vcpu, offset);
2578 * We split periods of matched TSC writes into generations.
2579 * For each generation, we track the original measured
2580 * nanosecond time, offset, and write, so if TSCs are in
2581 * sync, we can match exact offset, and if not, we can match
2582 * exact software computation in compute_guest_tsc()
2584 * These values are tracked in kvm->arch.cur_xxx variables.
2586 kvm->arch.cur_tsc_generation++;
2587 kvm->arch.cur_tsc_nsec = ns;
2588 kvm->arch.cur_tsc_write = tsc;
2589 kvm->arch.cur_tsc_offset = offset;
2590 kvm->arch.nr_vcpus_matched_tsc = 0;
2591 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2592 kvm->arch.nr_vcpus_matched_tsc++;
2595 /* Keep track of which generation this VCPU has synchronized to */
2596 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2597 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2598 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2600 kvm_track_tsc_matching(vcpu);
2603 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2605 struct kvm *kvm = vcpu->kvm;
2606 u64 offset, ns, elapsed;
2607 unsigned long flags;
2608 bool matched = false;
2609 bool synchronizing = false;
2611 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2612 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2613 ns = get_kvmclock_base_ns();
2614 elapsed = ns - kvm->arch.last_tsc_nsec;
2616 if (vcpu->arch.virtual_tsc_khz) {
2619 * detection of vcpu initialization -- need to sync
2620 * with other vCPUs. This particularly helps to keep
2621 * kvm_clock stable after CPU hotplug
2623 synchronizing = true;
2625 u64 tsc_exp = kvm->arch.last_tsc_write +
2626 nsec_to_cycles(vcpu, elapsed);
2627 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2629 * Special case: TSC write with a small delta (1 second)
2630 * of virtual cycle time against real time is
2631 * interpreted as an attempt to synchronize the CPU.
2633 synchronizing = data < tsc_exp + tsc_hz &&
2634 data + tsc_hz > tsc_exp;
2639 * For a reliable TSC, we can match TSC offsets, and for an unstable
2640 * TSC, we add elapsed time in this computation. We could let the
2641 * compensation code attempt to catch up if we fall behind, but
2642 * it's better to try to match offsets from the beginning.
2644 if (synchronizing &&
2645 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2646 if (!kvm_check_tsc_unstable()) {
2647 offset = kvm->arch.cur_tsc_offset;
2649 u64 delta = nsec_to_cycles(vcpu, elapsed);
2651 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2656 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2657 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2660 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2663 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2664 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2667 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2669 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2670 WARN_ON(adjustment < 0);
2671 adjustment = kvm_scale_tsc((u64) adjustment,
2672 vcpu->arch.l1_tsc_scaling_ratio);
2673 adjust_tsc_offset_guest(vcpu, adjustment);
2676 #ifdef CONFIG_X86_64
2678 static u64 read_tsc(void)
2680 u64 ret = (u64)rdtsc_ordered();
2681 u64 last = pvclock_gtod_data.clock.cycle_last;
2683 if (likely(ret >= last))
2687 * GCC likes to generate cmov here, but this branch is extremely
2688 * predictable (it's just a function of time and the likely is
2689 * very likely) and there's a data dependence, so force GCC
2690 * to generate a branch instead. I don't barrier() because
2691 * we don't actually need a barrier, and if this function
2692 * ever gets inlined it will generate worse code.
2698 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2704 switch (clock->vclock_mode) {
2705 case VDSO_CLOCKMODE_HVCLOCK:
2706 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2708 if (tsc_pg_val != U64_MAX) {
2709 /* TSC page valid */
2710 *mode = VDSO_CLOCKMODE_HVCLOCK;
2711 v = (tsc_pg_val - clock->cycle_last) &
2714 /* TSC page invalid */
2715 *mode = VDSO_CLOCKMODE_NONE;
2718 case VDSO_CLOCKMODE_TSC:
2719 *mode = VDSO_CLOCKMODE_TSC;
2720 *tsc_timestamp = read_tsc();
2721 v = (*tsc_timestamp - clock->cycle_last) &
2725 *mode = VDSO_CLOCKMODE_NONE;
2728 if (*mode == VDSO_CLOCKMODE_NONE)
2729 *tsc_timestamp = v = 0;
2731 return v * clock->mult;
2734 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2736 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2742 seq = read_seqcount_begin(>od->seq);
2743 ns = gtod->raw_clock.base_cycles;
2744 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2745 ns >>= gtod->raw_clock.shift;
2746 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2747 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2753 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2755 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2761 seq = read_seqcount_begin(>od->seq);
2762 ts->tv_sec = gtod->wall_time_sec;
2763 ns = gtod->clock.base_cycles;
2764 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2765 ns >>= gtod->clock.shift;
2766 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2768 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2774 /* returns true if host is using TSC based clocksource */
2775 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2777 /* checked again under seqlock below */
2778 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2781 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2785 /* returns true if host is using TSC based clocksource */
2786 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2789 /* checked again under seqlock below */
2790 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2793 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2799 * Assuming a stable TSC across physical CPUS, and a stable TSC
2800 * across virtual CPUs, the following condition is possible.
2801 * Each numbered line represents an event visible to both
2802 * CPUs at the next numbered event.
2804 * "timespecX" represents host monotonic time. "tscX" represents
2807 * VCPU0 on CPU0 | VCPU1 on CPU1
2809 * 1. read timespec0,tsc0
2810 * 2. | timespec1 = timespec0 + N
2812 * 3. transition to guest | transition to guest
2813 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2814 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2815 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2817 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2820 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2822 * - 0 < N - M => M < N
2824 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2825 * always the case (the difference between two distinct xtime instances
2826 * might be smaller then the difference between corresponding TSC reads,
2827 * when updating guest vcpus pvclock areas).
2829 * To avoid that problem, do not allow visibility of distinct
2830 * system_timestamp/tsc_timestamp values simultaneously: use a master
2831 * copy of host monotonic time values. Update that master copy
2834 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2838 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2840 #ifdef CONFIG_X86_64
2841 struct kvm_arch *ka = &kvm->arch;
2843 bool host_tsc_clocksource, vcpus_matched;
2845 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2846 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2847 atomic_read(&kvm->online_vcpus));
2850 * If the host uses TSC clock, then passthrough TSC as stable
2853 host_tsc_clocksource = kvm_get_time_and_clockread(
2854 &ka->master_kernel_ns,
2855 &ka->master_cycle_now);
2857 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2858 && !ka->backwards_tsc_observed
2859 && !ka->boot_vcpu_runs_old_kvmclock;
2861 if (ka->use_master_clock)
2862 atomic_set(&kvm_guest_has_master_clock, 1);
2864 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2865 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2870 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2872 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2875 static void __kvm_start_pvclock_update(struct kvm *kvm)
2877 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2878 write_seqcount_begin(&kvm->arch.pvclock_sc);
2881 static void kvm_start_pvclock_update(struct kvm *kvm)
2883 kvm_make_mclock_inprogress_request(kvm);
2885 /* no guest entries from this point */
2886 __kvm_start_pvclock_update(kvm);
2889 static void kvm_end_pvclock_update(struct kvm *kvm)
2891 struct kvm_arch *ka = &kvm->arch;
2892 struct kvm_vcpu *vcpu;
2895 write_seqcount_end(&ka->pvclock_sc);
2896 raw_spin_unlock_irq(&ka->tsc_write_lock);
2897 kvm_for_each_vcpu(i, vcpu, kvm)
2898 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2900 /* guest entries allowed */
2901 kvm_for_each_vcpu(i, vcpu, kvm)
2902 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2905 static void kvm_update_masterclock(struct kvm *kvm)
2907 kvm_hv_request_tsc_page_update(kvm);
2908 kvm_start_pvclock_update(kvm);
2909 pvclock_update_vm_gtod_copy(kvm);
2910 kvm_end_pvclock_update(kvm);
2913 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2914 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2916 struct kvm_arch *ka = &kvm->arch;
2917 struct pvclock_vcpu_time_info hv_clock;
2919 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2923 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) {
2924 #ifdef CONFIG_X86_64
2925 struct timespec64 ts;
2927 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
2928 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
2929 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
2932 data->host_tsc = rdtsc();
2934 data->flags |= KVM_CLOCK_TSC_STABLE;
2935 hv_clock.tsc_timestamp = ka->master_cycle_now;
2936 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2937 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2938 &hv_clock.tsc_shift,
2939 &hv_clock.tsc_to_system_mul);
2940 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
2942 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
2948 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2950 struct kvm_arch *ka = &kvm->arch;
2954 seq = read_seqcount_begin(&ka->pvclock_sc);
2955 __get_kvmclock(kvm, data);
2956 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
2959 u64 get_kvmclock_ns(struct kvm *kvm)
2961 struct kvm_clock_data data;
2963 get_kvmclock(kvm, &data);
2967 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
2968 struct gfn_to_pfn_cache *gpc,
2969 unsigned int offset)
2971 struct kvm_vcpu_arch *vcpu = &v->arch;
2972 struct pvclock_vcpu_time_info *guest_hv_clock;
2973 unsigned long flags;
2975 read_lock_irqsave(&gpc->lock, flags);
2976 while (!kvm_gfn_to_pfn_cache_check(v->kvm, gpc, gpc->gpa,
2977 offset + sizeof(*guest_hv_clock))) {
2978 read_unlock_irqrestore(&gpc->lock, flags);
2980 if (kvm_gfn_to_pfn_cache_refresh(v->kvm, gpc, gpc->gpa,
2981 offset + sizeof(*guest_hv_clock)))
2984 read_lock_irqsave(&gpc->lock, flags);
2987 guest_hv_clock = (void *)(gpc->khva + offset);
2990 * This VCPU is paused, but it's legal for a guest to read another
2991 * VCPU's kvmclock, so we really have to follow the specification where
2992 * it says that version is odd if data is being modified, and even after
2996 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
2999 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3000 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3002 if (vcpu->pvclock_set_guest_stopped_request) {
3003 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3004 vcpu->pvclock_set_guest_stopped_request = false;
3007 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3010 guest_hv_clock->version = ++vcpu->hv_clock.version;
3012 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3013 read_unlock_irqrestore(&gpc->lock, flags);
3015 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3018 static int kvm_guest_time_update(struct kvm_vcpu *v)
3020 unsigned long flags, tgt_tsc_khz;
3022 struct kvm_vcpu_arch *vcpu = &v->arch;
3023 struct kvm_arch *ka = &v->kvm->arch;
3025 u64 tsc_timestamp, host_tsc;
3027 bool use_master_clock;
3033 * If the host uses TSC clock, then passthrough TSC as stable
3037 seq = read_seqcount_begin(&ka->pvclock_sc);
3038 use_master_clock = ka->use_master_clock;
3039 if (use_master_clock) {
3040 host_tsc = ka->master_cycle_now;
3041 kernel_ns = ka->master_kernel_ns;
3043 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3045 /* Keep irq disabled to prevent changes to the clock */
3046 local_irq_save(flags);
3047 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
3048 if (unlikely(tgt_tsc_khz == 0)) {
3049 local_irq_restore(flags);
3050 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3053 if (!use_master_clock) {
3055 kernel_ns = get_kvmclock_base_ns();
3058 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3061 * We may have to catch up the TSC to match elapsed wall clock
3062 * time for two reasons, even if kvmclock is used.
3063 * 1) CPU could have been running below the maximum TSC rate
3064 * 2) Broken TSC compensation resets the base at each VCPU
3065 * entry to avoid unknown leaps of TSC even when running
3066 * again on the same CPU. This may cause apparent elapsed
3067 * time to disappear, and the guest to stand still or run
3070 if (vcpu->tsc_catchup) {
3071 u64 tsc = compute_guest_tsc(v, kernel_ns);
3072 if (tsc > tsc_timestamp) {
3073 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3074 tsc_timestamp = tsc;
3078 local_irq_restore(flags);
3080 /* With all the info we got, fill in the values */
3082 if (kvm_has_tsc_control)
3083 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3084 v->arch.l1_tsc_scaling_ratio);
3086 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3087 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3088 &vcpu->hv_clock.tsc_shift,
3089 &vcpu->hv_clock.tsc_to_system_mul);
3090 vcpu->hw_tsc_khz = tgt_tsc_khz;
3093 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3094 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3095 vcpu->last_guest_tsc = tsc_timestamp;
3097 /* If the host uses TSC clocksource, then it is stable */
3099 if (use_master_clock)
3100 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3102 vcpu->hv_clock.flags = pvclock_flags;
3104 if (vcpu->pv_time.active)
3105 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3106 if (vcpu->xen.vcpu_info_cache.active)
3107 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3108 offsetof(struct compat_vcpu_info, time));
3109 if (vcpu->xen.vcpu_time_info_cache.active)
3110 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3111 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3116 * kvmclock updates which are isolated to a given vcpu, such as
3117 * vcpu->cpu migration, should not allow system_timestamp from
3118 * the rest of the vcpus to remain static. Otherwise ntp frequency
3119 * correction applies to one vcpu's system_timestamp but not
3122 * So in those cases, request a kvmclock update for all vcpus.
3123 * We need to rate-limit these requests though, as they can
3124 * considerably slow guests that have a large number of vcpus.
3125 * The time for a remote vcpu to update its kvmclock is bound
3126 * by the delay we use to rate-limit the updates.
3129 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3131 static void kvmclock_update_fn(struct work_struct *work)
3134 struct delayed_work *dwork = to_delayed_work(work);
3135 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3136 kvmclock_update_work);
3137 struct kvm *kvm = container_of(ka, struct kvm, arch);
3138 struct kvm_vcpu *vcpu;
3140 kvm_for_each_vcpu(i, vcpu, kvm) {
3141 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3142 kvm_vcpu_kick(vcpu);
3146 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3148 struct kvm *kvm = v->kvm;
3150 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3151 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3152 KVMCLOCK_UPDATE_DELAY);
3155 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3157 static void kvmclock_sync_fn(struct work_struct *work)
3159 struct delayed_work *dwork = to_delayed_work(work);
3160 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3161 kvmclock_sync_work);
3162 struct kvm *kvm = container_of(ka, struct kvm, arch);
3164 if (!kvmclock_periodic_sync)
3167 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3168 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3169 KVMCLOCK_SYNC_PERIOD);
3173 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3175 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3177 /* McStatusWrEn enabled? */
3178 if (guest_cpuid_is_amd_or_hygon(vcpu))
3179 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3184 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3186 u64 mcg_cap = vcpu->arch.mcg_cap;
3187 unsigned bank_num = mcg_cap & 0xff;
3188 u32 msr = msr_info->index;
3189 u64 data = msr_info->data;
3192 case MSR_IA32_MCG_STATUS:
3193 vcpu->arch.mcg_status = data;
3195 case MSR_IA32_MCG_CTL:
3196 if (!(mcg_cap & MCG_CTL_P) &&
3197 (data || !msr_info->host_initiated))
3199 if (data != 0 && data != ~(u64)0)
3201 vcpu->arch.mcg_ctl = data;
3204 if (msr >= MSR_IA32_MC0_CTL &&
3205 msr < MSR_IA32_MCx_CTL(bank_num)) {
3206 u32 offset = array_index_nospec(
3207 msr - MSR_IA32_MC0_CTL,
3208 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3210 /* only 0 or all 1s can be written to IA32_MCi_CTL
3211 * some Linux kernels though clear bit 10 in bank 4 to
3212 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
3213 * this to avoid an uncatched #GP in the guest
3215 if ((offset & 0x3) == 0 &&
3216 data != 0 && (data | (1 << 10)) != ~(u64)0)
3220 if (!msr_info->host_initiated &&
3221 (offset & 0x3) == 1 && data != 0) {
3222 if (!can_set_mci_status(vcpu))
3226 vcpu->arch.mce_banks[offset] = data;
3234 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3236 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3238 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3241 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3243 gpa_t gpa = data & ~0x3f;
3245 /* Bits 4:5 are reserved, Should be zero */
3249 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3250 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3253 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3254 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3257 if (!lapic_in_kernel(vcpu))
3258 return data ? 1 : 0;
3260 vcpu->arch.apf.msr_en_val = data;
3262 if (!kvm_pv_async_pf_enabled(vcpu)) {
3263 kvm_clear_async_pf_completion_queue(vcpu);
3264 kvm_async_pf_hash_reset(vcpu);
3268 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3272 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3273 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3275 kvm_async_pf_wakeup_all(vcpu);
3280 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3282 /* Bits 8-63 are reserved */
3286 if (!lapic_in_kernel(vcpu))
3289 vcpu->arch.apf.msr_int_val = data;
3291 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3296 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3298 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time);
3299 vcpu->arch.time = 0;
3302 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3304 ++vcpu->stat.tlb_flush;
3305 static_call(kvm_x86_flush_tlb_all)(vcpu);
3308 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3310 ++vcpu->stat.tlb_flush;
3314 * A TLB flush on behalf of the guest is equivalent to
3315 * INVPCID(all), toggling CR4.PGE, etc., which requires
3316 * a forced sync of the shadow page tables. Ensure all the
3317 * roots are synced and the guest TLB in hardware is clean.
3319 kvm_mmu_sync_roots(vcpu);
3320 kvm_mmu_sync_prev_roots(vcpu);
3323 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3327 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3329 ++vcpu->stat.tlb_flush;
3330 static_call(kvm_x86_flush_tlb_current)(vcpu);
3334 * Service "local" TLB flush requests, which are specific to the current MMU
3335 * context. In addition to the generic event handling in vcpu_enter_guest(),
3336 * TLB flushes that are targeted at an MMU context also need to be serviced
3337 * prior before nested VM-Enter/VM-Exit.
3339 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3341 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3342 kvm_vcpu_flush_tlb_current(vcpu);
3344 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3345 kvm_vcpu_flush_tlb_guest(vcpu);
3347 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3349 static void record_steal_time(struct kvm_vcpu *vcpu)
3351 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3352 struct kvm_steal_time __user *st;
3353 struct kvm_memslots *slots;
3357 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3358 kvm_xen_runstate_set_running(vcpu);
3362 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3365 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3368 slots = kvm_memslots(vcpu->kvm);
3370 if (unlikely(slots->generation != ghc->generation ||
3371 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3372 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3374 /* We rely on the fact that it fits in a single page. */
3375 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3377 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) ||
3378 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3382 st = (struct kvm_steal_time __user *)ghc->hva;
3384 * Doing a TLB flush here, on the guest's behalf, can avoid
3387 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3388 u8 st_preempted = 0;
3391 if (!user_access_begin(st, sizeof(*st)))
3394 asm volatile("1: xchgb %0, %2\n"
3397 _ASM_EXTABLE_UA(1b, 2b)
3398 : "+q" (st_preempted),
3400 "+m" (st->preempted));
3406 vcpu->arch.st.preempted = 0;
3408 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3409 st_preempted & KVM_VCPU_FLUSH_TLB);
3410 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3411 kvm_vcpu_flush_tlb_guest(vcpu);
3413 if (!user_access_begin(st, sizeof(*st)))
3416 if (!user_access_begin(st, sizeof(*st)))
3419 unsafe_put_user(0, &st->preempted, out);
3420 vcpu->arch.st.preempted = 0;
3423 unsafe_get_user(version, &st->version, out);
3425 version += 1; /* first time write, random junk */
3428 unsafe_put_user(version, &st->version, out);
3432 unsafe_get_user(steal, &st->steal, out);
3433 steal += current->sched_info.run_delay -
3434 vcpu->arch.st.last_steal;
3435 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3436 unsafe_put_user(steal, &st->steal, out);
3439 unsafe_put_user(version, &st->version, out);
3444 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3447 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3450 u32 msr = msr_info->index;
3451 u64 data = msr_info->data;
3453 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3454 return kvm_xen_write_hypercall_page(vcpu, data);
3457 case MSR_AMD64_NB_CFG:
3458 case MSR_IA32_UCODE_WRITE:
3459 case MSR_VM_HSAVE_PA:
3460 case MSR_AMD64_PATCH_LOADER:
3461 case MSR_AMD64_BU_CFG2:
3462 case MSR_AMD64_DC_CFG:
3463 case MSR_F15H_EX_CFG:
3466 case MSR_IA32_UCODE_REV:
3467 if (msr_info->host_initiated)
3468 vcpu->arch.microcode_version = data;
3470 case MSR_IA32_ARCH_CAPABILITIES:
3471 if (!msr_info->host_initiated)
3473 vcpu->arch.arch_capabilities = data;
3475 case MSR_IA32_PERF_CAPABILITIES: {
3476 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3478 if (!msr_info->host_initiated)
3480 if (kvm_get_msr_feature(&msr_ent))
3482 if (data & ~msr_ent.data)
3485 vcpu->arch.perf_capabilities = data;
3490 return set_efer(vcpu, msr_info);
3492 data &= ~(u64)0x40; /* ignore flush filter disable */
3493 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3494 data &= ~(u64)0x8; /* ignore TLB cache disable */
3496 /* Handle McStatusWrEn */
3497 if (data == BIT_ULL(18)) {
3498 vcpu->arch.msr_hwcr = data;
3499 } else if (data != 0) {
3500 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3505 case MSR_FAM10H_MMIO_CONF_BASE:
3507 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3512 case 0x200 ... 0x2ff:
3513 return kvm_mtrr_set_msr(vcpu, msr, data);
3514 case MSR_IA32_APICBASE:
3515 return kvm_set_apic_base(vcpu, msr_info);
3516 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3517 return kvm_x2apic_msr_write(vcpu, msr, data);
3518 case MSR_IA32_TSC_DEADLINE:
3519 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3521 case MSR_IA32_TSC_ADJUST:
3522 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3523 if (!msr_info->host_initiated) {
3524 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3525 adjust_tsc_offset_guest(vcpu, adj);
3526 /* Before back to guest, tsc_timestamp must be adjusted
3527 * as well, otherwise guest's percpu pvclock time could jump.
3529 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3531 vcpu->arch.ia32_tsc_adjust_msr = data;
3534 case MSR_IA32_MISC_ENABLE:
3535 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3536 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3537 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3539 vcpu->arch.ia32_misc_enable_msr = data;
3540 kvm_update_cpuid_runtime(vcpu);
3542 vcpu->arch.ia32_misc_enable_msr = data;
3545 case MSR_IA32_SMBASE:
3546 if (!msr_info->host_initiated)
3548 vcpu->arch.smbase = data;
3550 case MSR_IA32_POWER_CTL:
3551 vcpu->arch.msr_ia32_power_ctl = data;
3554 if (msr_info->host_initiated) {
3555 kvm_synchronize_tsc(vcpu, data);
3557 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3558 adjust_tsc_offset_guest(vcpu, adj);
3559 vcpu->arch.ia32_tsc_adjust_msr += adj;
3563 if (!msr_info->host_initiated &&
3564 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3567 * KVM supports exposing PT to the guest, but does not support
3568 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3569 * XSAVES/XRSTORS to save/restore PT MSRs.
3571 if (data & ~supported_xss)
3573 vcpu->arch.ia32_xss = data;
3574 kvm_update_cpuid_runtime(vcpu);
3577 if (!msr_info->host_initiated)
3579 vcpu->arch.smi_count = data;
3581 case MSR_KVM_WALL_CLOCK_NEW:
3582 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3585 vcpu->kvm->arch.wall_clock = data;
3586 kvm_write_wall_clock(vcpu->kvm, data, 0);
3588 case MSR_KVM_WALL_CLOCK:
3589 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3592 vcpu->kvm->arch.wall_clock = data;
3593 kvm_write_wall_clock(vcpu->kvm, data, 0);
3595 case MSR_KVM_SYSTEM_TIME_NEW:
3596 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3599 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3601 case MSR_KVM_SYSTEM_TIME:
3602 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3605 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3607 case MSR_KVM_ASYNC_PF_EN:
3608 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3611 if (kvm_pv_enable_async_pf(vcpu, data))
3614 case MSR_KVM_ASYNC_PF_INT:
3615 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3618 if (kvm_pv_enable_async_pf_int(vcpu, data))
3621 case MSR_KVM_ASYNC_PF_ACK:
3622 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3625 vcpu->arch.apf.pageready_pending = false;
3626 kvm_check_async_pf_completion(vcpu);
3629 case MSR_KVM_STEAL_TIME:
3630 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3633 if (unlikely(!sched_info_on()))
3636 if (data & KVM_STEAL_RESERVED_MASK)
3639 vcpu->arch.st.msr_val = data;
3641 if (!(data & KVM_MSR_ENABLED))
3644 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3647 case MSR_KVM_PV_EOI_EN:
3648 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3651 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3655 case MSR_KVM_POLL_CONTROL:
3656 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3659 /* only enable bit supported */
3660 if (data & (-1ULL << 1))
3663 vcpu->arch.msr_kvm_poll_control = data;
3666 case MSR_IA32_MCG_CTL:
3667 case MSR_IA32_MCG_STATUS:
3668 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3669 return set_msr_mce(vcpu, msr_info);
3671 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3672 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3675 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3676 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3677 if (kvm_pmu_is_valid_msr(vcpu, msr))
3678 return kvm_pmu_set_msr(vcpu, msr_info);
3680 if (pr || data != 0)
3681 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3682 "0x%x data 0x%llx\n", msr, data);
3684 case MSR_K7_CLK_CTL:
3686 * Ignore all writes to this no longer documented MSR.
3687 * Writes are only relevant for old K7 processors,
3688 * all pre-dating SVM, but a recommended workaround from
3689 * AMD for these chips. It is possible to specify the
3690 * affected processor models on the command line, hence
3691 * the need to ignore the workaround.
3694 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3695 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3696 case HV_X64_MSR_SYNDBG_OPTIONS:
3697 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3698 case HV_X64_MSR_CRASH_CTL:
3699 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3700 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3701 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3702 case HV_X64_MSR_TSC_EMULATION_STATUS:
3703 return kvm_hv_set_msr_common(vcpu, msr, data,
3704 msr_info->host_initiated);
3705 case MSR_IA32_BBL_CR_CTL3:
3706 /* Drop writes to this legacy MSR -- see rdmsr
3707 * counterpart for further detail.
3709 if (report_ignored_msrs)
3710 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3713 case MSR_AMD64_OSVW_ID_LENGTH:
3714 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3716 vcpu->arch.osvw.length = data;
3718 case MSR_AMD64_OSVW_STATUS:
3719 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3721 vcpu->arch.osvw.status = data;
3723 case MSR_PLATFORM_INFO:
3724 if (!msr_info->host_initiated ||
3725 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3726 cpuid_fault_enabled(vcpu)))
3728 vcpu->arch.msr_platform_info = data;
3730 case MSR_MISC_FEATURES_ENABLES:
3731 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3732 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3733 !supports_cpuid_fault(vcpu)))
3735 vcpu->arch.msr_misc_features_enables = data;
3737 #ifdef CONFIG_X86_64
3739 if (!msr_info->host_initiated &&
3740 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3743 if (data & ~kvm_guest_supported_xfd(vcpu))
3746 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3748 case MSR_IA32_XFD_ERR:
3749 if (!msr_info->host_initiated &&
3750 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3753 if (data & ~kvm_guest_supported_xfd(vcpu))
3756 vcpu->arch.guest_fpu.xfd_err = data;
3760 if (kvm_pmu_is_valid_msr(vcpu, msr))
3761 return kvm_pmu_set_msr(vcpu, msr_info);
3762 return KVM_MSR_RET_INVALID;
3766 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3768 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3771 u64 mcg_cap = vcpu->arch.mcg_cap;
3772 unsigned bank_num = mcg_cap & 0xff;
3775 case MSR_IA32_P5_MC_ADDR:
3776 case MSR_IA32_P5_MC_TYPE:
3779 case MSR_IA32_MCG_CAP:
3780 data = vcpu->arch.mcg_cap;
3782 case MSR_IA32_MCG_CTL:
3783 if (!(mcg_cap & MCG_CTL_P) && !host)
3785 data = vcpu->arch.mcg_ctl;
3787 case MSR_IA32_MCG_STATUS:
3788 data = vcpu->arch.mcg_status;
3791 if (msr >= MSR_IA32_MC0_CTL &&
3792 msr < MSR_IA32_MCx_CTL(bank_num)) {
3793 u32 offset = array_index_nospec(
3794 msr - MSR_IA32_MC0_CTL,
3795 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3797 data = vcpu->arch.mce_banks[offset];
3806 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3808 switch (msr_info->index) {
3809 case MSR_IA32_PLATFORM_ID:
3810 case MSR_IA32_EBL_CR_POWERON:
3811 case MSR_IA32_LASTBRANCHFROMIP:
3812 case MSR_IA32_LASTBRANCHTOIP:
3813 case MSR_IA32_LASTINTFROMIP:
3814 case MSR_IA32_LASTINTTOIP:
3815 case MSR_AMD64_SYSCFG:
3816 case MSR_K8_TSEG_ADDR:
3817 case MSR_K8_TSEG_MASK:
3818 case MSR_VM_HSAVE_PA:
3819 case MSR_K8_INT_PENDING_MSG:
3820 case MSR_AMD64_NB_CFG:
3821 case MSR_FAM10H_MMIO_CONF_BASE:
3822 case MSR_AMD64_BU_CFG2:
3823 case MSR_IA32_PERF_CTL:
3824 case MSR_AMD64_DC_CFG:
3825 case MSR_F15H_EX_CFG:
3827 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3828 * limit) MSRs. Just return 0, as we do not want to expose the host
3829 * data here. Do not conditionalize this on CPUID, as KVM does not do
3830 * so for existing CPU-specific MSRs.
3832 case MSR_RAPL_POWER_UNIT:
3833 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3834 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3835 case MSR_PKG_ENERGY_STATUS: /* Total package */
3836 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3839 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3840 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3841 return kvm_pmu_get_msr(vcpu, msr_info);
3842 if (!msr_info->host_initiated)
3846 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3847 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3848 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3849 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3850 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3851 return kvm_pmu_get_msr(vcpu, msr_info);
3854 case MSR_IA32_UCODE_REV:
3855 msr_info->data = vcpu->arch.microcode_version;
3857 case MSR_IA32_ARCH_CAPABILITIES:
3858 if (!msr_info->host_initiated &&
3859 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3861 msr_info->data = vcpu->arch.arch_capabilities;
3863 case MSR_IA32_PERF_CAPABILITIES:
3864 if (!msr_info->host_initiated &&
3865 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3867 msr_info->data = vcpu->arch.perf_capabilities;
3869 case MSR_IA32_POWER_CTL:
3870 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3872 case MSR_IA32_TSC: {
3874 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3875 * even when not intercepted. AMD manual doesn't explicitly
3876 * state this but appears to behave the same.
3878 * On userspace reads and writes, however, we unconditionally
3879 * return L1's TSC value to ensure backwards-compatible
3880 * behavior for migration.
3884 if (msr_info->host_initiated) {
3885 offset = vcpu->arch.l1_tsc_offset;
3886 ratio = vcpu->arch.l1_tsc_scaling_ratio;
3888 offset = vcpu->arch.tsc_offset;
3889 ratio = vcpu->arch.tsc_scaling_ratio;
3892 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
3896 case 0x200 ... 0x2ff:
3897 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3898 case 0xcd: /* fsb frequency */
3902 * MSR_EBC_FREQUENCY_ID
3903 * Conservative value valid for even the basic CPU models.
3904 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3905 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3906 * and 266MHz for model 3, or 4. Set Core Clock
3907 * Frequency to System Bus Frequency Ratio to 1 (bits
3908 * 31:24) even though these are only valid for CPU
3909 * models > 2, however guests may end up dividing or
3910 * multiplying by zero otherwise.
3912 case MSR_EBC_FREQUENCY_ID:
3913 msr_info->data = 1 << 24;
3915 case MSR_IA32_APICBASE:
3916 msr_info->data = kvm_get_apic_base(vcpu);
3918 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3919 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3920 case MSR_IA32_TSC_DEADLINE:
3921 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3923 case MSR_IA32_TSC_ADJUST:
3924 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3926 case MSR_IA32_MISC_ENABLE:
3927 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3929 case MSR_IA32_SMBASE:
3930 if (!msr_info->host_initiated)
3932 msr_info->data = vcpu->arch.smbase;
3935 msr_info->data = vcpu->arch.smi_count;
3937 case MSR_IA32_PERF_STATUS:
3938 /* TSC increment by tick */
3939 msr_info->data = 1000ULL;
3940 /* CPU multiplier */
3941 msr_info->data |= (((uint64_t)4ULL) << 40);
3944 msr_info->data = vcpu->arch.efer;
3946 case MSR_KVM_WALL_CLOCK:
3947 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3950 msr_info->data = vcpu->kvm->arch.wall_clock;
3952 case MSR_KVM_WALL_CLOCK_NEW:
3953 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3956 msr_info->data = vcpu->kvm->arch.wall_clock;
3958 case MSR_KVM_SYSTEM_TIME:
3959 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3962 msr_info->data = vcpu->arch.time;
3964 case MSR_KVM_SYSTEM_TIME_NEW:
3965 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3968 msr_info->data = vcpu->arch.time;
3970 case MSR_KVM_ASYNC_PF_EN:
3971 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3974 msr_info->data = vcpu->arch.apf.msr_en_val;
3976 case MSR_KVM_ASYNC_PF_INT:
3977 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3980 msr_info->data = vcpu->arch.apf.msr_int_val;
3982 case MSR_KVM_ASYNC_PF_ACK:
3983 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3988 case MSR_KVM_STEAL_TIME:
3989 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3992 msr_info->data = vcpu->arch.st.msr_val;
3994 case MSR_KVM_PV_EOI_EN:
3995 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3998 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4000 case MSR_KVM_POLL_CONTROL:
4001 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4004 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4006 case MSR_IA32_P5_MC_ADDR:
4007 case MSR_IA32_P5_MC_TYPE:
4008 case MSR_IA32_MCG_CAP:
4009 case MSR_IA32_MCG_CTL:
4010 case MSR_IA32_MCG_STATUS:
4011 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4012 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4013 msr_info->host_initiated);
4015 if (!msr_info->host_initiated &&
4016 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4018 msr_info->data = vcpu->arch.ia32_xss;
4020 case MSR_K7_CLK_CTL:
4022 * Provide expected ramp-up count for K7. All other
4023 * are set to zero, indicating minimum divisors for
4026 * This prevents guest kernels on AMD host with CPU
4027 * type 6, model 8 and higher from exploding due to
4028 * the rdmsr failing.
4030 msr_info->data = 0x20000000;
4032 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4033 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4034 case HV_X64_MSR_SYNDBG_OPTIONS:
4035 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4036 case HV_X64_MSR_CRASH_CTL:
4037 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4038 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4039 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4040 case HV_X64_MSR_TSC_EMULATION_STATUS:
4041 return kvm_hv_get_msr_common(vcpu,
4042 msr_info->index, &msr_info->data,
4043 msr_info->host_initiated);
4044 case MSR_IA32_BBL_CR_CTL3:
4045 /* This legacy MSR exists but isn't fully documented in current
4046 * silicon. It is however accessed by winxp in very narrow
4047 * scenarios where it sets bit #19, itself documented as
4048 * a "reserved" bit. Best effort attempt to source coherent
4049 * read data here should the balance of the register be
4050 * interpreted by the guest:
4052 * L2 cache control register 3: 64GB range, 256KB size,
4053 * enabled, latency 0x1, configured
4055 msr_info->data = 0xbe702111;
4057 case MSR_AMD64_OSVW_ID_LENGTH:
4058 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4060 msr_info->data = vcpu->arch.osvw.length;
4062 case MSR_AMD64_OSVW_STATUS:
4063 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4065 msr_info->data = vcpu->arch.osvw.status;
4067 case MSR_PLATFORM_INFO:
4068 if (!msr_info->host_initiated &&
4069 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4071 msr_info->data = vcpu->arch.msr_platform_info;
4073 case MSR_MISC_FEATURES_ENABLES:
4074 msr_info->data = vcpu->arch.msr_misc_features_enables;
4077 msr_info->data = vcpu->arch.msr_hwcr;
4079 #ifdef CONFIG_X86_64
4081 if (!msr_info->host_initiated &&
4082 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4085 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4087 case MSR_IA32_XFD_ERR:
4088 if (!msr_info->host_initiated &&
4089 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4092 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4096 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4097 return kvm_pmu_get_msr(vcpu, msr_info);
4098 return KVM_MSR_RET_INVALID;
4102 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4105 * Read or write a bunch of msrs. All parameters are kernel addresses.
4107 * @return number of msrs set successfully.
4109 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4110 struct kvm_msr_entry *entries,
4111 int (*do_msr)(struct kvm_vcpu *vcpu,
4112 unsigned index, u64 *data))
4116 for (i = 0; i < msrs->nmsrs; ++i)
4117 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4124 * Read or write a bunch of msrs. Parameters are user addresses.
4126 * @return number of msrs set successfully.
4128 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4129 int (*do_msr)(struct kvm_vcpu *vcpu,
4130 unsigned index, u64 *data),
4133 struct kvm_msrs msrs;
4134 struct kvm_msr_entry *entries;
4139 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4143 if (msrs.nmsrs >= MAX_IO_MSRS)
4146 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4147 entries = memdup_user(user_msrs->entries, size);
4148 if (IS_ERR(entries)) {
4149 r = PTR_ERR(entries);
4153 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
4158 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4169 static inline bool kvm_can_mwait_in_guest(void)
4171 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4172 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4173 boot_cpu_has(X86_FEATURE_ARAT);
4176 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4177 struct kvm_cpuid2 __user *cpuid_arg)
4179 struct kvm_cpuid2 cpuid;
4183 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4186 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4191 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4197 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4202 case KVM_CAP_IRQCHIP:
4204 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4205 case KVM_CAP_SET_TSS_ADDR:
4206 case KVM_CAP_EXT_CPUID:
4207 case KVM_CAP_EXT_EMUL_CPUID:
4208 case KVM_CAP_CLOCKSOURCE:
4210 case KVM_CAP_NOP_IO_DELAY:
4211 case KVM_CAP_MP_STATE:
4212 case KVM_CAP_SYNC_MMU:
4213 case KVM_CAP_USER_NMI:
4214 case KVM_CAP_REINJECT_CONTROL:
4215 case KVM_CAP_IRQ_INJECT_STATUS:
4216 case KVM_CAP_IOEVENTFD:
4217 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4219 case KVM_CAP_PIT_STATE2:
4220 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4221 case KVM_CAP_VCPU_EVENTS:
4222 case KVM_CAP_HYPERV:
4223 case KVM_CAP_HYPERV_VAPIC:
4224 case KVM_CAP_HYPERV_SPIN:
4225 case KVM_CAP_HYPERV_SYNIC:
4226 case KVM_CAP_HYPERV_SYNIC2:
4227 case KVM_CAP_HYPERV_VP_INDEX:
4228 case KVM_CAP_HYPERV_EVENTFD:
4229 case KVM_CAP_HYPERV_TLBFLUSH:
4230 case KVM_CAP_HYPERV_SEND_IPI:
4231 case KVM_CAP_HYPERV_CPUID:
4232 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4233 case KVM_CAP_SYS_HYPERV_CPUID:
4234 case KVM_CAP_PCI_SEGMENT:
4235 case KVM_CAP_DEBUGREGS:
4236 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4238 case KVM_CAP_ASYNC_PF:
4239 case KVM_CAP_ASYNC_PF_INT:
4240 case KVM_CAP_GET_TSC_KHZ:
4241 case KVM_CAP_KVMCLOCK_CTRL:
4242 case KVM_CAP_READONLY_MEM:
4243 case KVM_CAP_HYPERV_TIME:
4244 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4245 case KVM_CAP_TSC_DEADLINE_TIMER:
4246 case KVM_CAP_DISABLE_QUIRKS:
4247 case KVM_CAP_SET_BOOT_CPU_ID:
4248 case KVM_CAP_SPLIT_IRQCHIP:
4249 case KVM_CAP_IMMEDIATE_EXIT:
4250 case KVM_CAP_PMU_EVENT_FILTER:
4251 case KVM_CAP_GET_MSR_FEATURES:
4252 case KVM_CAP_MSR_PLATFORM_INFO:
4253 case KVM_CAP_EXCEPTION_PAYLOAD:
4254 case KVM_CAP_SET_GUEST_DEBUG:
4255 case KVM_CAP_LAST_CPU:
4256 case KVM_CAP_X86_USER_SPACE_MSR:
4257 case KVM_CAP_X86_MSR_FILTER:
4258 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4259 #ifdef CONFIG_X86_SGX_KVM
4260 case KVM_CAP_SGX_ATTRIBUTE:
4262 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4263 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4264 case KVM_CAP_SREGS2:
4265 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4266 case KVM_CAP_VCPU_ATTRIBUTES:
4267 case KVM_CAP_SYS_ATTRIBUTES:
4269 case KVM_CAP_ENABLE_CAP:
4272 case KVM_CAP_EXIT_HYPERCALL:
4273 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4275 case KVM_CAP_SET_GUEST_DEBUG2:
4276 return KVM_GUESTDBG_VALID_MASK;
4277 #ifdef CONFIG_KVM_XEN
4278 case KVM_CAP_XEN_HVM:
4279 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4280 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4281 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4282 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4283 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4284 if (sched_info_on())
4285 r |= KVM_XEN_HVM_CONFIG_RUNSTATE;
4288 case KVM_CAP_SYNC_REGS:
4289 r = KVM_SYNC_X86_VALID_FIELDS;
4291 case KVM_CAP_ADJUST_CLOCK:
4292 r = KVM_CLOCK_VALID_FLAGS;
4294 case KVM_CAP_X86_DISABLE_EXITS:
4295 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
4296 KVM_X86_DISABLE_EXITS_CSTATE;
4297 if(kvm_can_mwait_in_guest())
4298 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4300 case KVM_CAP_X86_SMM:
4301 /* SMBASE is usually relocated above 1M on modern chipsets,
4302 * and SMM handlers might indeed rely on 4G segment limits,
4303 * so do not report SMM to be available if real mode is
4304 * emulated via vm86 mode. Still, do not go to great lengths
4305 * to avoid userspace's usage of the feature, because it is a
4306 * fringe case that is not enabled except via specific settings
4307 * of the module parameters.
4309 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4311 case KVM_CAP_NR_VCPUS:
4312 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4314 case KVM_CAP_MAX_VCPUS:
4317 case KVM_CAP_MAX_VCPU_ID:
4318 r = KVM_MAX_VCPU_IDS;
4320 case KVM_CAP_PV_MMU: /* obsolete */
4324 r = KVM_MAX_MCE_BANKS;
4327 r = boot_cpu_has(X86_FEATURE_XSAVE);
4329 case KVM_CAP_TSC_CONTROL:
4330 case KVM_CAP_VM_TSC_CONTROL:
4331 r = kvm_has_tsc_control;
4333 case KVM_CAP_X2APIC_API:
4334 r = KVM_X2APIC_API_VALID_FLAGS;
4336 case KVM_CAP_NESTED_STATE:
4337 r = kvm_x86_ops.nested_ops->get_state ?
4338 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4340 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4341 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
4343 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4344 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4346 case KVM_CAP_SMALLER_MAXPHYADDR:
4347 r = (int) allow_smaller_maxphyaddr;
4349 case KVM_CAP_STEAL_TIME:
4350 r = sched_info_on();
4352 case KVM_CAP_X86_BUS_LOCK_EXIT:
4353 if (kvm_has_bus_lock_exit)
4354 r = KVM_BUS_LOCK_DETECTION_OFF |
4355 KVM_BUS_LOCK_DETECTION_EXIT;
4359 case KVM_CAP_XSAVE2: {
4360 u64 guest_perm = xstate_get_guest_group_perm();
4362 r = xstate_required_size(supported_xcr0 & guest_perm, false);
4363 if (r < sizeof(struct kvm_xsave))
4364 r = sizeof(struct kvm_xsave);
4366 case KVM_CAP_PMU_CAPABILITY:
4367 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4370 case KVM_CAP_DISABLE_QUIRKS2:
4371 r = KVM_X86_VALID_QUIRKS;
4379 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4381 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4383 if ((u64)(unsigned long)uaddr != attr->addr)
4384 return ERR_PTR_USR(-EFAULT);
4388 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4390 u64 __user *uaddr = kvm_get_attr_addr(attr);
4396 return PTR_ERR(uaddr);
4398 switch (attr->attr) {
4399 case KVM_X86_XCOMP_GUEST_SUPP:
4400 if (put_user(supported_xcr0, uaddr))
4409 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4414 switch (attr->attr) {
4415 case KVM_X86_XCOMP_GUEST_SUPP:
4422 long kvm_arch_dev_ioctl(struct file *filp,
4423 unsigned int ioctl, unsigned long arg)
4425 void __user *argp = (void __user *)arg;
4429 case KVM_GET_MSR_INDEX_LIST: {
4430 struct kvm_msr_list __user *user_msr_list = argp;
4431 struct kvm_msr_list msr_list;
4435 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4438 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4439 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4442 if (n < msr_list.nmsrs)
4445 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4446 num_msrs_to_save * sizeof(u32)))
4448 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4450 num_emulated_msrs * sizeof(u32)))
4455 case KVM_GET_SUPPORTED_CPUID:
4456 case KVM_GET_EMULATED_CPUID: {
4457 struct kvm_cpuid2 __user *cpuid_arg = argp;
4458 struct kvm_cpuid2 cpuid;
4461 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4464 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4470 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4475 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4477 if (copy_to_user(argp, &kvm_mce_cap_supported,
4478 sizeof(kvm_mce_cap_supported)))
4482 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4483 struct kvm_msr_list __user *user_msr_list = argp;
4484 struct kvm_msr_list msr_list;
4488 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4491 msr_list.nmsrs = num_msr_based_features;
4492 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4495 if (n < msr_list.nmsrs)
4498 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4499 num_msr_based_features * sizeof(u32)))
4505 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4507 case KVM_GET_SUPPORTED_HV_CPUID:
4508 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4510 case KVM_GET_DEVICE_ATTR: {
4511 struct kvm_device_attr attr;
4513 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4515 r = kvm_x86_dev_get_attr(&attr);
4518 case KVM_HAS_DEVICE_ATTR: {
4519 struct kvm_device_attr attr;
4521 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4523 r = kvm_x86_dev_has_attr(&attr);
4534 static void wbinvd_ipi(void *garbage)
4539 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4541 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4544 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4546 /* Address WBINVD may be executed by guest */
4547 if (need_emulate_wbinvd(vcpu)) {
4548 if (static_call(kvm_x86_has_wbinvd_exit)())
4549 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4550 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4551 smp_call_function_single(vcpu->cpu,
4552 wbinvd_ipi, NULL, 1);
4555 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4557 /* Save host pkru register if supported */
4558 vcpu->arch.host_pkru = read_pkru();
4560 /* Apply any externally detected TSC adjustments (due to suspend) */
4561 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4562 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4563 vcpu->arch.tsc_offset_adjustment = 0;
4564 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4567 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4568 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4569 rdtsc() - vcpu->arch.last_host_tsc;
4571 mark_tsc_unstable("KVM discovered backwards TSC");
4573 if (kvm_check_tsc_unstable()) {
4574 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4575 vcpu->arch.last_guest_tsc);
4576 kvm_vcpu_write_tsc_offset(vcpu, offset);
4577 vcpu->arch.tsc_catchup = 1;
4580 if (kvm_lapic_hv_timer_in_use(vcpu))
4581 kvm_lapic_restart_hv_timer(vcpu);
4584 * On a host with synchronized TSC, there is no need to update
4585 * kvmclock on vcpu->cpu migration
4587 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4588 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4589 if (vcpu->cpu != cpu)
4590 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4594 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4597 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4599 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4600 struct kvm_steal_time __user *st;
4601 struct kvm_memslots *slots;
4602 static const u8 preempted = KVM_VCPU_PREEMPTED;
4604 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4607 if (vcpu->arch.st.preempted)
4610 /* This happens on process exit */
4611 if (unlikely(current->mm != vcpu->kvm->mm))
4614 slots = kvm_memslots(vcpu->kvm);
4616 if (unlikely(slots->generation != ghc->generation ||
4617 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4620 st = (struct kvm_steal_time __user *)ghc->hva;
4621 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4623 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4624 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4626 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4629 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4633 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4634 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4637 * Take the srcu lock as memslots will be accessed to check the gfn
4638 * cache generation against the memslots generation.
4640 idx = srcu_read_lock(&vcpu->kvm->srcu);
4641 if (kvm_xen_msr_enabled(vcpu->kvm))
4642 kvm_xen_runstate_set_preempted(vcpu);
4644 kvm_steal_time_set_preempted(vcpu);
4645 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4647 static_call(kvm_x86_vcpu_put)(vcpu);
4648 vcpu->arch.last_host_tsc = rdtsc();
4651 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4652 struct kvm_lapic_state *s)
4654 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4656 return kvm_apic_get_state(vcpu, s);
4659 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4660 struct kvm_lapic_state *s)
4664 r = kvm_apic_set_state(vcpu, s);
4667 update_cr8_intercept(vcpu);
4672 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4675 * We can accept userspace's request for interrupt injection
4676 * as long as we have a place to store the interrupt number.
4677 * The actual injection will happen when the CPU is able to
4678 * deliver the interrupt.
4680 if (kvm_cpu_has_extint(vcpu))
4683 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4684 return (!lapic_in_kernel(vcpu) ||
4685 kvm_apic_accept_pic_intr(vcpu));
4688 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4691 * Do not cause an interrupt window exit if an exception
4692 * is pending or an event needs reinjection; userspace
4693 * might want to inject the interrupt manually using KVM_SET_REGS
4694 * or KVM_SET_SREGS. For that to work, we must be at an
4695 * instruction boundary and with no events half-injected.
4697 return (kvm_arch_interrupt_allowed(vcpu) &&
4698 kvm_cpu_accept_dm_intr(vcpu) &&
4699 !kvm_event_needs_reinjection(vcpu) &&
4700 !vcpu->arch.exception.pending);
4703 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4704 struct kvm_interrupt *irq)
4706 if (irq->irq >= KVM_NR_INTERRUPTS)
4709 if (!irqchip_in_kernel(vcpu->kvm)) {
4710 kvm_queue_interrupt(vcpu, irq->irq, false);
4711 kvm_make_request(KVM_REQ_EVENT, vcpu);
4716 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4717 * fail for in-kernel 8259.
4719 if (pic_in_kernel(vcpu->kvm))
4722 if (vcpu->arch.pending_external_vector != -1)
4725 vcpu->arch.pending_external_vector = irq->irq;
4726 kvm_make_request(KVM_REQ_EVENT, vcpu);
4730 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4732 kvm_inject_nmi(vcpu);
4737 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4739 kvm_make_request(KVM_REQ_SMI, vcpu);
4744 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4745 struct kvm_tpr_access_ctl *tac)
4749 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4753 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4757 unsigned bank_num = mcg_cap & 0xff, bank;
4760 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4762 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4765 vcpu->arch.mcg_cap = mcg_cap;
4766 /* Init IA32_MCG_CTL to all 1s */
4767 if (mcg_cap & MCG_CTL_P)
4768 vcpu->arch.mcg_ctl = ~(u64)0;
4769 /* Init IA32_MCi_CTL to all 1s */
4770 for (bank = 0; bank < bank_num; bank++)
4771 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4773 static_call(kvm_x86_setup_mce)(vcpu);
4778 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4779 struct kvm_x86_mce *mce)
4781 u64 mcg_cap = vcpu->arch.mcg_cap;
4782 unsigned bank_num = mcg_cap & 0xff;
4783 u64 *banks = vcpu->arch.mce_banks;
4785 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4788 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4789 * reporting is disabled
4791 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4792 vcpu->arch.mcg_ctl != ~(u64)0)
4794 banks += 4 * mce->bank;
4796 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4797 * reporting is disabled for the bank
4799 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4801 if (mce->status & MCI_STATUS_UC) {
4802 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4803 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4804 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4807 if (banks[1] & MCI_STATUS_VAL)
4808 mce->status |= MCI_STATUS_OVER;
4809 banks[2] = mce->addr;
4810 banks[3] = mce->misc;
4811 vcpu->arch.mcg_status = mce->mcg_status;
4812 banks[1] = mce->status;
4813 kvm_queue_exception(vcpu, MC_VECTOR);
4814 } else if (!(banks[1] & MCI_STATUS_VAL)
4815 || !(banks[1] & MCI_STATUS_UC)) {
4816 if (banks[1] & MCI_STATUS_VAL)
4817 mce->status |= MCI_STATUS_OVER;
4818 banks[2] = mce->addr;
4819 banks[3] = mce->misc;
4820 banks[1] = mce->status;
4822 banks[1] |= MCI_STATUS_OVER;
4826 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4827 struct kvm_vcpu_events *events)
4831 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4835 * In guest mode, payload delivery should be deferred,
4836 * so that the L1 hypervisor can intercept #PF before
4837 * CR2 is modified (or intercept #DB before DR6 is
4838 * modified under nVMX). Unless the per-VM capability,
4839 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4840 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4841 * opportunistically defer the exception payload, deliver it if the
4842 * capability hasn't been requested before processing a
4843 * KVM_GET_VCPU_EVENTS.
4845 if (!vcpu->kvm->arch.exception_payload_enabled &&
4846 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4847 kvm_deliver_exception_payload(vcpu);
4850 * The API doesn't provide the instruction length for software
4851 * exceptions, so don't report them. As long as the guest RIP
4852 * isn't advanced, we should expect to encounter the exception
4855 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4856 events->exception.injected = 0;
4857 events->exception.pending = 0;
4859 events->exception.injected = vcpu->arch.exception.injected;
4860 events->exception.pending = vcpu->arch.exception.pending;
4862 * For ABI compatibility, deliberately conflate
4863 * pending and injected exceptions when
4864 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4866 if (!vcpu->kvm->arch.exception_payload_enabled)
4867 events->exception.injected |=
4868 vcpu->arch.exception.pending;
4870 events->exception.nr = vcpu->arch.exception.nr;
4871 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4872 events->exception.error_code = vcpu->arch.exception.error_code;
4873 events->exception_has_payload = vcpu->arch.exception.has_payload;
4874 events->exception_payload = vcpu->arch.exception.payload;
4876 events->interrupt.injected =
4877 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4878 events->interrupt.nr = vcpu->arch.interrupt.nr;
4879 events->interrupt.soft = 0;
4880 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
4882 events->nmi.injected = vcpu->arch.nmi_injected;
4883 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4884 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
4885 events->nmi.pad = 0;
4887 events->sipi_vector = 0; /* never valid when reporting to user space */
4889 events->smi.smm = is_smm(vcpu);
4890 events->smi.pending = vcpu->arch.smi_pending;
4891 events->smi.smm_inside_nmi =
4892 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4893 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4895 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4896 | KVM_VCPUEVENT_VALID_SHADOW
4897 | KVM_VCPUEVENT_VALID_SMM);
4898 if (vcpu->kvm->arch.exception_payload_enabled)
4899 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4901 memset(&events->reserved, 0, sizeof(events->reserved));
4904 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm);
4906 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4907 struct kvm_vcpu_events *events)
4909 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4910 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4911 | KVM_VCPUEVENT_VALID_SHADOW
4912 | KVM_VCPUEVENT_VALID_SMM
4913 | KVM_VCPUEVENT_VALID_PAYLOAD))
4916 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4917 if (!vcpu->kvm->arch.exception_payload_enabled)
4919 if (events->exception.pending)
4920 events->exception.injected = 0;
4922 events->exception_has_payload = 0;
4924 events->exception.pending = 0;
4925 events->exception_has_payload = 0;
4928 if ((events->exception.injected || events->exception.pending) &&
4929 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4932 /* INITs are latched while in SMM */
4933 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4934 (events->smi.smm || events->smi.pending) &&
4935 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4939 vcpu->arch.exception.injected = events->exception.injected;
4940 vcpu->arch.exception.pending = events->exception.pending;
4941 vcpu->arch.exception.nr = events->exception.nr;
4942 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4943 vcpu->arch.exception.error_code = events->exception.error_code;
4944 vcpu->arch.exception.has_payload = events->exception_has_payload;
4945 vcpu->arch.exception.payload = events->exception_payload;
4947 vcpu->arch.interrupt.injected = events->interrupt.injected;
4948 vcpu->arch.interrupt.nr = events->interrupt.nr;
4949 vcpu->arch.interrupt.soft = events->interrupt.soft;
4950 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4951 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
4952 events->interrupt.shadow);
4954 vcpu->arch.nmi_injected = events->nmi.injected;
4955 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4956 vcpu->arch.nmi_pending = events->nmi.pending;
4957 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
4959 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4960 lapic_in_kernel(vcpu))
4961 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4963 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4964 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4965 kvm_x86_ops.nested_ops->leave_nested(vcpu);
4966 kvm_smm_changed(vcpu, events->smi.smm);
4969 vcpu->arch.smi_pending = events->smi.pending;
4971 if (events->smi.smm) {
4972 if (events->smi.smm_inside_nmi)
4973 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4975 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4978 if (lapic_in_kernel(vcpu)) {
4979 if (events->smi.latched_init)
4980 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4982 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4986 kvm_make_request(KVM_REQ_EVENT, vcpu);
4991 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4992 struct kvm_debugregs *dbgregs)
4996 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4997 kvm_get_dr(vcpu, 6, &val);
4999 dbgregs->dr7 = vcpu->arch.dr7;
5001 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
5004 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5005 struct kvm_debugregs *dbgregs)
5010 if (!kvm_dr6_valid(dbgregs->dr6))
5012 if (!kvm_dr7_valid(dbgregs->dr7))
5015 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5016 kvm_update_dr0123(vcpu);
5017 vcpu->arch.dr6 = dbgregs->dr6;
5018 vcpu->arch.dr7 = dbgregs->dr7;
5019 kvm_update_dr7(vcpu);
5024 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5025 struct kvm_xsave *guest_xsave)
5027 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5030 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5031 guest_xsave->region,
5032 sizeof(guest_xsave->region),
5036 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5037 u8 *state, unsigned int size)
5039 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5042 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5043 state, size, vcpu->arch.pkru);
5046 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5047 struct kvm_xsave *guest_xsave)
5049 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5052 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5053 guest_xsave->region,
5054 supported_xcr0, &vcpu->arch.pkru);
5057 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5058 struct kvm_xcrs *guest_xcrs)
5060 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5061 guest_xcrs->nr_xcrs = 0;
5065 guest_xcrs->nr_xcrs = 1;
5066 guest_xcrs->flags = 0;
5067 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5068 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5071 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5072 struct kvm_xcrs *guest_xcrs)
5076 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5079 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5082 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5083 /* Only support XCR0 currently */
5084 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5085 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5086 guest_xcrs->xcrs[i].value);
5095 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5096 * stopped by the hypervisor. This function will be called from the host only.
5097 * EINVAL is returned when the host attempts to set the flag for a guest that
5098 * does not support pv clocks.
5100 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5102 if (!vcpu->arch.pv_time.active)
5104 vcpu->arch.pvclock_set_guest_stopped_request = true;
5105 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5109 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5110 struct kvm_device_attr *attr)
5114 switch (attr->attr) {
5115 case KVM_VCPU_TSC_OFFSET:
5125 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5126 struct kvm_device_attr *attr)
5128 u64 __user *uaddr = kvm_get_attr_addr(attr);
5132 return PTR_ERR(uaddr);
5134 switch (attr->attr) {
5135 case KVM_VCPU_TSC_OFFSET:
5137 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5148 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5149 struct kvm_device_attr *attr)
5151 u64 __user *uaddr = kvm_get_attr_addr(attr);
5152 struct kvm *kvm = vcpu->kvm;
5156 return PTR_ERR(uaddr);
5158 switch (attr->attr) {
5159 case KVM_VCPU_TSC_OFFSET: {
5160 u64 offset, tsc, ns;
5161 unsigned long flags;
5165 if (get_user(offset, uaddr))
5168 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5170 matched = (vcpu->arch.virtual_tsc_khz &&
5171 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5172 kvm->arch.last_tsc_offset == offset);
5174 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5175 ns = get_kvmclock_base_ns();
5177 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5178 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5190 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5194 struct kvm_device_attr attr;
5197 if (copy_from_user(&attr, argp, sizeof(attr)))
5200 if (attr.group != KVM_VCPU_TSC_CTRL)
5204 case KVM_HAS_DEVICE_ATTR:
5205 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5207 case KVM_GET_DEVICE_ATTR:
5208 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5210 case KVM_SET_DEVICE_ATTR:
5211 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5218 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5219 struct kvm_enable_cap *cap)
5222 uint16_t vmcs_version;
5223 void __user *user_ptr;
5229 case KVM_CAP_HYPERV_SYNIC2:
5234 case KVM_CAP_HYPERV_SYNIC:
5235 if (!irqchip_in_kernel(vcpu->kvm))
5237 return kvm_hv_activate_synic(vcpu, cap->cap ==
5238 KVM_CAP_HYPERV_SYNIC2);
5239 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5240 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5242 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5244 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5245 if (copy_to_user(user_ptr, &vmcs_version,
5246 sizeof(vmcs_version)))
5250 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5251 if (!kvm_x86_ops.enable_direct_tlbflush)
5254 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
5256 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5257 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5259 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5260 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5261 if (vcpu->arch.pv_cpuid.enforce)
5262 kvm_update_pv_runtime(vcpu);
5270 long kvm_arch_vcpu_ioctl(struct file *filp,
5271 unsigned int ioctl, unsigned long arg)
5273 struct kvm_vcpu *vcpu = filp->private_data;
5274 void __user *argp = (void __user *)arg;
5277 struct kvm_sregs2 *sregs2;
5278 struct kvm_lapic_state *lapic;
5279 struct kvm_xsave *xsave;
5280 struct kvm_xcrs *xcrs;
5288 case KVM_GET_LAPIC: {
5290 if (!lapic_in_kernel(vcpu))
5292 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5293 GFP_KERNEL_ACCOUNT);
5298 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5302 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5307 case KVM_SET_LAPIC: {
5309 if (!lapic_in_kernel(vcpu))
5311 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5312 if (IS_ERR(u.lapic)) {
5313 r = PTR_ERR(u.lapic);
5317 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5320 case KVM_INTERRUPT: {
5321 struct kvm_interrupt irq;
5324 if (copy_from_user(&irq, argp, sizeof(irq)))
5326 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5330 r = kvm_vcpu_ioctl_nmi(vcpu);
5334 r = kvm_vcpu_ioctl_smi(vcpu);
5337 case KVM_SET_CPUID: {
5338 struct kvm_cpuid __user *cpuid_arg = argp;
5339 struct kvm_cpuid cpuid;
5342 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5344 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5347 case KVM_SET_CPUID2: {
5348 struct kvm_cpuid2 __user *cpuid_arg = argp;
5349 struct kvm_cpuid2 cpuid;
5352 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5354 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5355 cpuid_arg->entries);
5358 case KVM_GET_CPUID2: {
5359 struct kvm_cpuid2 __user *cpuid_arg = argp;
5360 struct kvm_cpuid2 cpuid;
5363 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5365 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5366 cpuid_arg->entries);
5370 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5375 case KVM_GET_MSRS: {
5376 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5377 r = msr_io(vcpu, argp, do_get_msr, 1);
5378 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5381 case KVM_SET_MSRS: {
5382 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5383 r = msr_io(vcpu, argp, do_set_msr, 0);
5384 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5387 case KVM_TPR_ACCESS_REPORTING: {
5388 struct kvm_tpr_access_ctl tac;
5391 if (copy_from_user(&tac, argp, sizeof(tac)))
5393 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5397 if (copy_to_user(argp, &tac, sizeof(tac)))
5402 case KVM_SET_VAPIC_ADDR: {
5403 struct kvm_vapic_addr va;
5407 if (!lapic_in_kernel(vcpu))
5410 if (copy_from_user(&va, argp, sizeof(va)))
5412 idx = srcu_read_lock(&vcpu->kvm->srcu);
5413 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5414 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5417 case KVM_X86_SETUP_MCE: {
5421 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5423 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5426 case KVM_X86_SET_MCE: {
5427 struct kvm_x86_mce mce;
5430 if (copy_from_user(&mce, argp, sizeof(mce)))
5432 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5435 case KVM_GET_VCPU_EVENTS: {
5436 struct kvm_vcpu_events events;
5438 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5441 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5446 case KVM_SET_VCPU_EVENTS: {
5447 struct kvm_vcpu_events events;
5450 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5453 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5456 case KVM_GET_DEBUGREGS: {
5457 struct kvm_debugregs dbgregs;
5459 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5462 if (copy_to_user(argp, &dbgregs,
5463 sizeof(struct kvm_debugregs)))
5468 case KVM_SET_DEBUGREGS: {
5469 struct kvm_debugregs dbgregs;
5472 if (copy_from_user(&dbgregs, argp,
5473 sizeof(struct kvm_debugregs)))
5476 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5479 case KVM_GET_XSAVE: {
5481 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5484 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5489 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5492 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5497 case KVM_SET_XSAVE: {
5498 int size = vcpu->arch.guest_fpu.uabi_size;
5500 u.xsave = memdup_user(argp, size);
5501 if (IS_ERR(u.xsave)) {
5502 r = PTR_ERR(u.xsave);
5506 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5510 case KVM_GET_XSAVE2: {
5511 int size = vcpu->arch.guest_fpu.uabi_size;
5513 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5518 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5521 if (copy_to_user(argp, u.xsave, size))
5528 case KVM_GET_XCRS: {
5529 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5534 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5537 if (copy_to_user(argp, u.xcrs,
5538 sizeof(struct kvm_xcrs)))
5543 case KVM_SET_XCRS: {
5544 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5545 if (IS_ERR(u.xcrs)) {
5546 r = PTR_ERR(u.xcrs);
5550 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5553 case KVM_SET_TSC_KHZ: {
5557 user_tsc_khz = (u32)arg;
5559 if (kvm_has_tsc_control &&
5560 user_tsc_khz >= kvm_max_guest_tsc_khz)
5563 if (user_tsc_khz == 0)
5564 user_tsc_khz = tsc_khz;
5566 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5571 case KVM_GET_TSC_KHZ: {
5572 r = vcpu->arch.virtual_tsc_khz;
5575 case KVM_KVMCLOCK_CTRL: {
5576 r = kvm_set_guest_paused(vcpu);
5579 case KVM_ENABLE_CAP: {
5580 struct kvm_enable_cap cap;
5583 if (copy_from_user(&cap, argp, sizeof(cap)))
5585 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5588 case KVM_GET_NESTED_STATE: {
5589 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5593 if (!kvm_x86_ops.nested_ops->get_state)
5596 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5598 if (get_user(user_data_size, &user_kvm_nested_state->size))
5601 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5606 if (r > user_data_size) {
5607 if (put_user(r, &user_kvm_nested_state->size))
5617 case KVM_SET_NESTED_STATE: {
5618 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5619 struct kvm_nested_state kvm_state;
5623 if (!kvm_x86_ops.nested_ops->set_state)
5627 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5631 if (kvm_state.size < sizeof(kvm_state))
5634 if (kvm_state.flags &
5635 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5636 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5637 | KVM_STATE_NESTED_GIF_SET))
5640 /* nested_run_pending implies guest_mode. */
5641 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5642 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5645 idx = srcu_read_lock(&vcpu->kvm->srcu);
5646 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5647 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5650 case KVM_GET_SUPPORTED_HV_CPUID:
5651 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5653 #ifdef CONFIG_KVM_XEN
5654 case KVM_XEN_VCPU_GET_ATTR: {
5655 struct kvm_xen_vcpu_attr xva;
5658 if (copy_from_user(&xva, argp, sizeof(xva)))
5660 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5661 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5665 case KVM_XEN_VCPU_SET_ATTR: {
5666 struct kvm_xen_vcpu_attr xva;
5669 if (copy_from_user(&xva, argp, sizeof(xva)))
5671 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5675 case KVM_GET_SREGS2: {
5676 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5680 __get_sregs2(vcpu, u.sregs2);
5682 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5687 case KVM_SET_SREGS2: {
5688 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5689 if (IS_ERR(u.sregs2)) {
5690 r = PTR_ERR(u.sregs2);
5694 r = __set_sregs2(vcpu, u.sregs2);
5697 case KVM_HAS_DEVICE_ATTR:
5698 case KVM_GET_DEVICE_ATTR:
5699 case KVM_SET_DEVICE_ATTR:
5700 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
5712 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5714 return VM_FAULT_SIGBUS;
5717 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5721 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5723 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5727 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5730 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5733 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5734 unsigned long kvm_nr_mmu_pages)
5736 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5739 mutex_lock(&kvm->slots_lock);
5741 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5742 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5744 mutex_unlock(&kvm->slots_lock);
5748 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5750 return kvm->arch.n_max_mmu_pages;
5753 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5755 struct kvm_pic *pic = kvm->arch.vpic;
5759 switch (chip->chip_id) {
5760 case KVM_IRQCHIP_PIC_MASTER:
5761 memcpy(&chip->chip.pic, &pic->pics[0],
5762 sizeof(struct kvm_pic_state));
5764 case KVM_IRQCHIP_PIC_SLAVE:
5765 memcpy(&chip->chip.pic, &pic->pics[1],
5766 sizeof(struct kvm_pic_state));
5768 case KVM_IRQCHIP_IOAPIC:
5769 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5778 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5780 struct kvm_pic *pic = kvm->arch.vpic;
5784 switch (chip->chip_id) {
5785 case KVM_IRQCHIP_PIC_MASTER:
5786 spin_lock(&pic->lock);
5787 memcpy(&pic->pics[0], &chip->chip.pic,
5788 sizeof(struct kvm_pic_state));
5789 spin_unlock(&pic->lock);
5791 case KVM_IRQCHIP_PIC_SLAVE:
5792 spin_lock(&pic->lock);
5793 memcpy(&pic->pics[1], &chip->chip.pic,
5794 sizeof(struct kvm_pic_state));
5795 spin_unlock(&pic->lock);
5797 case KVM_IRQCHIP_IOAPIC:
5798 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5804 kvm_pic_update_irq(pic);
5808 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5810 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5812 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5814 mutex_lock(&kps->lock);
5815 memcpy(ps, &kps->channels, sizeof(*ps));
5816 mutex_unlock(&kps->lock);
5820 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5823 struct kvm_pit *pit = kvm->arch.vpit;
5825 mutex_lock(&pit->pit_state.lock);
5826 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5827 for (i = 0; i < 3; i++)
5828 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5829 mutex_unlock(&pit->pit_state.lock);
5833 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5835 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5836 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5837 sizeof(ps->channels));
5838 ps->flags = kvm->arch.vpit->pit_state.flags;
5839 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5840 memset(&ps->reserved, 0, sizeof(ps->reserved));
5844 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5848 u32 prev_legacy, cur_legacy;
5849 struct kvm_pit *pit = kvm->arch.vpit;
5851 mutex_lock(&pit->pit_state.lock);
5852 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5853 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5854 if (!prev_legacy && cur_legacy)
5856 memcpy(&pit->pit_state.channels, &ps->channels,
5857 sizeof(pit->pit_state.channels));
5858 pit->pit_state.flags = ps->flags;
5859 for (i = 0; i < 3; i++)
5860 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5862 mutex_unlock(&pit->pit_state.lock);
5866 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5867 struct kvm_reinject_control *control)
5869 struct kvm_pit *pit = kvm->arch.vpit;
5871 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5872 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5873 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5875 mutex_lock(&pit->pit_state.lock);
5876 kvm_pit_set_reinject(pit, control->pit_reinject);
5877 mutex_unlock(&pit->pit_state.lock);
5882 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5886 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
5887 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
5888 * on all VM-Exits, thus we only need to kick running vCPUs to force a
5891 struct kvm_vcpu *vcpu;
5894 kvm_for_each_vcpu(i, vcpu, kvm)
5895 kvm_vcpu_kick(vcpu);
5898 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5901 if (!irqchip_in_kernel(kvm))
5904 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5905 irq_event->irq, irq_event->level,
5910 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5911 struct kvm_enable_cap *cap)
5919 case KVM_CAP_DISABLE_QUIRKS2:
5921 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
5924 case KVM_CAP_DISABLE_QUIRKS:
5925 kvm->arch.disabled_quirks = cap->args[0];
5928 case KVM_CAP_SPLIT_IRQCHIP: {
5929 mutex_lock(&kvm->lock);
5931 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5932 goto split_irqchip_unlock;
5934 if (irqchip_in_kernel(kvm))
5935 goto split_irqchip_unlock;
5936 if (kvm->created_vcpus)
5937 goto split_irqchip_unlock;
5938 r = kvm_setup_empty_irq_routing(kvm);
5940 goto split_irqchip_unlock;
5941 /* Pairs with irqchip_in_kernel. */
5943 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5944 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5945 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
5947 split_irqchip_unlock:
5948 mutex_unlock(&kvm->lock);
5951 case KVM_CAP_X2APIC_API:
5953 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5956 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5957 kvm->arch.x2apic_format = true;
5958 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5959 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5963 case KVM_CAP_X86_DISABLE_EXITS:
5965 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5968 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5969 kvm_can_mwait_in_guest())
5970 kvm->arch.mwait_in_guest = true;
5971 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5972 kvm->arch.hlt_in_guest = true;
5973 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5974 kvm->arch.pause_in_guest = true;
5975 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5976 kvm->arch.cstate_in_guest = true;
5979 case KVM_CAP_MSR_PLATFORM_INFO:
5980 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5983 case KVM_CAP_EXCEPTION_PAYLOAD:
5984 kvm->arch.exception_payload_enabled = cap->args[0];
5987 case KVM_CAP_X86_USER_SPACE_MSR:
5988 kvm->arch.user_space_msr_mask = cap->args[0];
5991 case KVM_CAP_X86_BUS_LOCK_EXIT:
5993 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
5996 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
5997 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6000 if (kvm_has_bus_lock_exit &&
6001 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6002 kvm->arch.bus_lock_detection_enabled = true;
6005 #ifdef CONFIG_X86_SGX_KVM
6006 case KVM_CAP_SGX_ATTRIBUTE: {
6007 unsigned long allowed_attributes = 0;
6009 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6013 /* KVM only supports the PROVISIONKEY privileged attribute. */
6014 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6015 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6016 kvm->arch.sgx_provisioning_allowed = true;
6022 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6024 if (!kvm_x86_ops.vm_copy_enc_context_from)
6027 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6029 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6031 if (!kvm_x86_ops.vm_move_enc_context_from)
6034 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6036 case KVM_CAP_EXIT_HYPERCALL:
6037 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6041 kvm->arch.hypercall_exit_enabled = cap->args[0];
6044 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6046 if (cap->args[0] & ~1)
6048 kvm->arch.exit_on_emulation_error = cap->args[0];
6051 case KVM_CAP_PMU_CAPABILITY:
6053 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6056 mutex_lock(&kvm->lock);
6057 if (!kvm->created_vcpus) {
6058 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6061 mutex_unlock(&kvm->lock);
6070 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6072 struct kvm_x86_msr_filter *msr_filter;
6074 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6078 msr_filter->default_allow = default_allow;
6082 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6089 for (i = 0; i < msr_filter->count; i++)
6090 kfree(msr_filter->ranges[i].bitmap);
6095 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6096 struct kvm_msr_filter_range *user_range)
6098 unsigned long *bitmap = NULL;
6101 if (!user_range->nmsrs)
6104 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE))
6107 if (!user_range->flags)
6110 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6111 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6114 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6116 return PTR_ERR(bitmap);
6118 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6119 .flags = user_range->flags,
6120 .base = user_range->base,
6121 .nmsrs = user_range->nmsrs,
6125 msr_filter->count++;
6129 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
6131 struct kvm_msr_filter __user *user_msr_filter = argp;
6132 struct kvm_x86_msr_filter *new_filter, *old_filter;
6133 struct kvm_msr_filter filter;
6139 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
6142 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
6143 empty &= !filter.ranges[i].nmsrs;
6145 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
6146 if (empty && !default_allow)
6149 new_filter = kvm_alloc_msr_filter(default_allow);
6153 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6154 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]);
6156 kvm_free_msr_filter(new_filter);
6161 mutex_lock(&kvm->lock);
6163 /* The per-VM filter is protected by kvm->lock... */
6164 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
6166 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
6167 synchronize_srcu(&kvm->srcu);
6169 kvm_free_msr_filter(old_filter);
6171 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6172 mutex_unlock(&kvm->lock);
6177 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6178 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6180 struct kvm_vcpu *vcpu;
6184 mutex_lock(&kvm->lock);
6185 kvm_for_each_vcpu(i, vcpu, kvm) {
6186 if (!vcpu->arch.pv_time.active)
6189 ret = kvm_set_guest_paused(vcpu);
6191 kvm_err("Failed to pause guest VCPU%d: %d\n",
6192 vcpu->vcpu_id, ret);
6196 mutex_unlock(&kvm->lock);
6198 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6201 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6204 case PM_HIBERNATION_PREPARE:
6205 case PM_SUSPEND_PREPARE:
6206 return kvm_arch_suspend_notifier(kvm);
6211 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6213 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6215 struct kvm_clock_data data = { 0 };
6217 get_kvmclock(kvm, &data);
6218 if (copy_to_user(argp, &data, sizeof(data)))
6224 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6226 struct kvm_arch *ka = &kvm->arch;
6227 struct kvm_clock_data data;
6230 if (copy_from_user(&data, argp, sizeof(data)))
6234 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6235 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6237 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6240 kvm_hv_request_tsc_page_update(kvm);
6241 kvm_start_pvclock_update(kvm);
6242 pvclock_update_vm_gtod_copy(kvm);
6245 * This pairs with kvm_guest_time_update(): when masterclock is
6246 * in use, we use master_kernel_ns + kvmclock_offset to set
6247 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6248 * is slightly ahead) here we risk going negative on unsigned
6249 * 'system_time' when 'data.clock' is very small.
6251 if (data.flags & KVM_CLOCK_REALTIME) {
6252 u64 now_real_ns = ktime_get_real_ns();
6255 * Avoid stepping the kvmclock backwards.
6257 if (now_real_ns > data.realtime)
6258 data.clock += now_real_ns - data.realtime;
6261 if (ka->use_master_clock)
6262 now_raw_ns = ka->master_kernel_ns;
6264 now_raw_ns = get_kvmclock_base_ns();
6265 ka->kvmclock_offset = data.clock - now_raw_ns;
6266 kvm_end_pvclock_update(kvm);
6270 long kvm_arch_vm_ioctl(struct file *filp,
6271 unsigned int ioctl, unsigned long arg)
6273 struct kvm *kvm = filp->private_data;
6274 void __user *argp = (void __user *)arg;
6277 * This union makes it completely explicit to gcc-3.x
6278 * that these two variables' stack usage should be
6279 * combined, not added together.
6282 struct kvm_pit_state ps;
6283 struct kvm_pit_state2 ps2;
6284 struct kvm_pit_config pit_config;
6288 case KVM_SET_TSS_ADDR:
6289 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6291 case KVM_SET_IDENTITY_MAP_ADDR: {
6294 mutex_lock(&kvm->lock);
6296 if (kvm->created_vcpus)
6297 goto set_identity_unlock;
6299 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6300 goto set_identity_unlock;
6301 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6302 set_identity_unlock:
6303 mutex_unlock(&kvm->lock);
6306 case KVM_SET_NR_MMU_PAGES:
6307 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6309 case KVM_GET_NR_MMU_PAGES:
6310 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
6312 case KVM_CREATE_IRQCHIP: {
6313 mutex_lock(&kvm->lock);
6316 if (irqchip_in_kernel(kvm))
6317 goto create_irqchip_unlock;
6320 if (kvm->created_vcpus)
6321 goto create_irqchip_unlock;
6323 r = kvm_pic_init(kvm);
6325 goto create_irqchip_unlock;
6327 r = kvm_ioapic_init(kvm);
6329 kvm_pic_destroy(kvm);
6330 goto create_irqchip_unlock;
6333 r = kvm_setup_default_irq_routing(kvm);
6335 kvm_ioapic_destroy(kvm);
6336 kvm_pic_destroy(kvm);
6337 goto create_irqchip_unlock;
6339 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6341 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6342 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6343 create_irqchip_unlock:
6344 mutex_unlock(&kvm->lock);
6347 case KVM_CREATE_PIT:
6348 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6350 case KVM_CREATE_PIT2:
6352 if (copy_from_user(&u.pit_config, argp,
6353 sizeof(struct kvm_pit_config)))
6356 mutex_lock(&kvm->lock);
6359 goto create_pit_unlock;
6361 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6365 mutex_unlock(&kvm->lock);
6367 case KVM_GET_IRQCHIP: {
6368 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6369 struct kvm_irqchip *chip;
6371 chip = memdup_user(argp, sizeof(*chip));
6378 if (!irqchip_kernel(kvm))
6379 goto get_irqchip_out;
6380 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6382 goto get_irqchip_out;
6384 if (copy_to_user(argp, chip, sizeof(*chip)))
6385 goto get_irqchip_out;
6391 case KVM_SET_IRQCHIP: {
6392 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6393 struct kvm_irqchip *chip;
6395 chip = memdup_user(argp, sizeof(*chip));
6402 if (!irqchip_kernel(kvm))
6403 goto set_irqchip_out;
6404 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6411 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6414 if (!kvm->arch.vpit)
6416 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6420 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6427 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6429 mutex_lock(&kvm->lock);
6431 if (!kvm->arch.vpit)
6433 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6435 mutex_unlock(&kvm->lock);
6438 case KVM_GET_PIT2: {
6440 if (!kvm->arch.vpit)
6442 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6446 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6451 case KVM_SET_PIT2: {
6453 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6455 mutex_lock(&kvm->lock);
6457 if (!kvm->arch.vpit)
6459 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6461 mutex_unlock(&kvm->lock);
6464 case KVM_REINJECT_CONTROL: {
6465 struct kvm_reinject_control control;
6467 if (copy_from_user(&control, argp, sizeof(control)))
6470 if (!kvm->arch.vpit)
6472 r = kvm_vm_ioctl_reinject(kvm, &control);
6475 case KVM_SET_BOOT_CPU_ID:
6477 mutex_lock(&kvm->lock);
6478 if (kvm->created_vcpus)
6481 kvm->arch.bsp_vcpu_id = arg;
6482 mutex_unlock(&kvm->lock);
6484 #ifdef CONFIG_KVM_XEN
6485 case KVM_XEN_HVM_CONFIG: {
6486 struct kvm_xen_hvm_config xhc;
6488 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6490 r = kvm_xen_hvm_config(kvm, &xhc);
6493 case KVM_XEN_HVM_GET_ATTR: {
6494 struct kvm_xen_hvm_attr xha;
6497 if (copy_from_user(&xha, argp, sizeof(xha)))
6499 r = kvm_xen_hvm_get_attr(kvm, &xha);
6500 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6504 case KVM_XEN_HVM_SET_ATTR: {
6505 struct kvm_xen_hvm_attr xha;
6508 if (copy_from_user(&xha, argp, sizeof(xha)))
6510 r = kvm_xen_hvm_set_attr(kvm, &xha);
6513 case KVM_XEN_HVM_EVTCHN_SEND: {
6514 struct kvm_irq_routing_xen_evtchn uxe;
6517 if (copy_from_user(&uxe, argp, sizeof(uxe)))
6519 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
6524 r = kvm_vm_ioctl_set_clock(kvm, argp);
6527 r = kvm_vm_ioctl_get_clock(kvm, argp);
6529 case KVM_SET_TSC_KHZ: {
6533 user_tsc_khz = (u32)arg;
6535 if (kvm_has_tsc_control &&
6536 user_tsc_khz >= kvm_max_guest_tsc_khz)
6539 if (user_tsc_khz == 0)
6540 user_tsc_khz = tsc_khz;
6542 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
6547 case KVM_GET_TSC_KHZ: {
6548 r = READ_ONCE(kvm->arch.default_tsc_khz);
6551 case KVM_MEMORY_ENCRYPT_OP: {
6553 if (!kvm_x86_ops.mem_enc_ioctl)
6556 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6559 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6560 struct kvm_enc_region region;
6563 if (copy_from_user(®ion, argp, sizeof(region)))
6567 if (!kvm_x86_ops.mem_enc_register_region)
6570 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6573 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6574 struct kvm_enc_region region;
6577 if (copy_from_user(®ion, argp, sizeof(region)))
6581 if (!kvm_x86_ops.mem_enc_unregister_region)
6584 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
6587 case KVM_HYPERV_EVENTFD: {
6588 struct kvm_hyperv_eventfd hvevfd;
6591 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
6593 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
6596 case KVM_SET_PMU_EVENT_FILTER:
6597 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
6599 case KVM_X86_SET_MSR_FILTER:
6600 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
6609 static void kvm_init_msr_list(void)
6611 struct x86_pmu_capability x86_pmu;
6615 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
6616 "Please update the fixed PMCs in msrs_to_saved_all[]");
6618 perf_get_x86_pmu_capability(&x86_pmu);
6620 num_msrs_to_save = 0;
6621 num_emulated_msrs = 0;
6622 num_msr_based_features = 0;
6624 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
6625 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
6629 * Even MSRs that are valid in the host may not be exposed
6630 * to the guests in some cases.
6632 switch (msrs_to_save_all[i]) {
6633 case MSR_IA32_BNDCFGS:
6634 if (!kvm_mpx_supported())
6638 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
6639 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
6642 case MSR_IA32_UMWAIT_CONTROL:
6643 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
6646 case MSR_IA32_RTIT_CTL:
6647 case MSR_IA32_RTIT_STATUS:
6648 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
6651 case MSR_IA32_RTIT_CR3_MATCH:
6652 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6653 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
6656 case MSR_IA32_RTIT_OUTPUT_BASE:
6657 case MSR_IA32_RTIT_OUTPUT_MASK:
6658 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6659 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
6660 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
6663 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
6664 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6665 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
6666 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
6669 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
6670 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
6671 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
6674 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
6675 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
6676 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
6680 case MSR_IA32_XFD_ERR:
6681 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
6688 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
6691 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
6692 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
6695 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
6698 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
6699 struct kvm_msr_entry msr;
6701 msr.index = msr_based_features_all[i];
6702 if (kvm_get_msr_feature(&msr))
6705 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
6709 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
6717 if (!(lapic_in_kernel(vcpu) &&
6718 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
6719 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
6730 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
6737 if (!(lapic_in_kernel(vcpu) &&
6738 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
6740 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
6742 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
6752 static void kvm_set_segment(struct kvm_vcpu *vcpu,
6753 struct kvm_segment *var, int seg)
6755 static_call(kvm_x86_set_segment)(vcpu, var, seg);
6758 void kvm_get_segment(struct kvm_vcpu *vcpu,
6759 struct kvm_segment *var, int seg)
6761 static_call(kvm_x86_get_segment)(vcpu, var, seg);
6764 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
6765 struct x86_exception *exception)
6767 struct kvm_mmu *mmu = vcpu->arch.mmu;
6770 BUG_ON(!mmu_is_nested(vcpu));
6772 /* NPT walks are always user-walks */
6773 access |= PFERR_USER_MASK;
6774 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
6779 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
6780 struct x86_exception *exception)
6782 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6784 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6785 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6787 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
6789 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
6790 struct x86_exception *exception)
6792 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6794 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6795 access |= PFERR_FETCH_MASK;
6796 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6799 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
6800 struct x86_exception *exception)
6802 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6804 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6805 access |= PFERR_WRITE_MASK;
6806 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6808 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
6810 /* uses this to access any guest's mapped memory without checking CPL */
6811 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
6812 struct x86_exception *exception)
6814 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6816 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
6819 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6820 struct kvm_vcpu *vcpu, u64 access,
6821 struct x86_exception *exception)
6823 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6825 int r = X86EMUL_CONTINUE;
6828 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
6829 unsigned offset = addr & (PAGE_SIZE-1);
6830 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
6833 if (gpa == UNMAPPED_GVA)
6834 return X86EMUL_PROPAGATE_FAULT;
6835 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
6838 r = X86EMUL_IO_NEEDED;
6850 /* used for instruction fetching */
6851 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
6852 gva_t addr, void *val, unsigned int bytes,
6853 struct x86_exception *exception)
6855 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6856 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6857 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6861 /* Inline kvm_read_guest_virt_helper for speed. */
6862 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
6864 if (unlikely(gpa == UNMAPPED_GVA))
6865 return X86EMUL_PROPAGATE_FAULT;
6867 offset = addr & (PAGE_SIZE-1);
6868 if (WARN_ON(offset + bytes > PAGE_SIZE))
6869 bytes = (unsigned)PAGE_SIZE - offset;
6870 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
6872 if (unlikely(ret < 0))
6873 return X86EMUL_IO_NEEDED;
6875 return X86EMUL_CONTINUE;
6878 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
6879 gva_t addr, void *val, unsigned int bytes,
6880 struct x86_exception *exception)
6882 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6885 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
6886 * is returned, but our callers are not ready for that and they blindly
6887 * call kvm_inject_page_fault. Ensure that they at least do not leak
6888 * uninitialized kernel stack memory into cr2 and error code.
6890 memset(exception, 0, sizeof(*exception));
6891 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6894 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6896 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6897 gva_t addr, void *val, unsigned int bytes,
6898 struct x86_exception *exception, bool system)
6900 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6904 access |= PFERR_IMPLICIT_ACCESS;
6905 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
6906 access |= PFERR_USER_MASK;
6908 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6911 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6912 unsigned long addr, void *val, unsigned int bytes)
6914 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6915 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6917 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6920 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6921 struct kvm_vcpu *vcpu, u64 access,
6922 struct x86_exception *exception)
6924 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6926 int r = X86EMUL_CONTINUE;
6929 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
6930 unsigned offset = addr & (PAGE_SIZE-1);
6931 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6934 if (gpa == UNMAPPED_GVA)
6935 return X86EMUL_PROPAGATE_FAULT;
6936 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6938 r = X86EMUL_IO_NEEDED;
6950 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6951 unsigned int bytes, struct x86_exception *exception,
6954 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6955 u64 access = PFERR_WRITE_MASK;
6958 access |= PFERR_IMPLICIT_ACCESS;
6959 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
6960 access |= PFERR_USER_MASK;
6962 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6966 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6967 unsigned int bytes, struct x86_exception *exception)
6969 /* kvm_write_guest_virt_system can pull in tons of pages. */
6970 vcpu->arch.l1tf_flush_l1d = true;
6972 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6973 PFERR_WRITE_MASK, exception);
6975 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6977 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
6978 void *insn, int insn_len)
6980 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
6984 int handle_ud(struct kvm_vcpu *vcpu)
6986 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6987 int emul_type = EMULTYPE_TRAP_UD;
6988 char sig[5]; /* ud2; .ascii "kvm" */
6989 struct x86_exception e;
6991 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
6994 if (force_emulation_prefix &&
6995 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6996 sig, sizeof(sig), &e) == 0 &&
6997 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6998 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6999 emul_type = EMULTYPE_TRAP_UD_FORCED;
7002 return kvm_emulate_instruction(vcpu, emul_type);
7004 EXPORT_SYMBOL_GPL(handle_ud);
7006 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7007 gpa_t gpa, bool write)
7009 /* For APIC access vmexit */
7010 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7013 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7014 trace_vcpu_match_mmio(gva, gpa, write, true);
7021 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7022 gpa_t *gpa, struct x86_exception *exception,
7025 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7026 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7027 | (write ? PFERR_WRITE_MASK : 0);
7030 * currently PKRU is only applied to ept enabled guest so
7031 * there is no pkey in EPT page table for L1 guest or EPT
7032 * shadow page table for L2 guest.
7034 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7035 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7036 vcpu->arch.mmio_access, 0, access))) {
7037 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7038 (gva & (PAGE_SIZE - 1));
7039 trace_vcpu_match_mmio(gva, *gpa, write, false);
7043 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7045 if (*gpa == UNMAPPED_GVA)
7048 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7051 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7052 const void *val, int bytes)
7056 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7059 kvm_page_track_write(vcpu, gpa, val, bytes);
7063 struct read_write_emulator_ops {
7064 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7066 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7067 void *val, int bytes);
7068 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7069 int bytes, void *val);
7070 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7071 void *val, int bytes);
7075 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7077 if (vcpu->mmio_read_completed) {
7078 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7079 vcpu->mmio_fragments[0].gpa, val);
7080 vcpu->mmio_read_completed = 0;
7087 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7088 void *val, int bytes)
7090 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7093 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7094 void *val, int bytes)
7096 return emulator_write_phys(vcpu, gpa, val, bytes);
7099 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7101 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7102 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7105 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7106 void *val, int bytes)
7108 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7109 return X86EMUL_IO_NEEDED;
7112 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7113 void *val, int bytes)
7115 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7117 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7118 return X86EMUL_CONTINUE;
7121 static const struct read_write_emulator_ops read_emultor = {
7122 .read_write_prepare = read_prepare,
7123 .read_write_emulate = read_emulate,
7124 .read_write_mmio = vcpu_mmio_read,
7125 .read_write_exit_mmio = read_exit_mmio,
7128 static const struct read_write_emulator_ops write_emultor = {
7129 .read_write_emulate = write_emulate,
7130 .read_write_mmio = write_mmio,
7131 .read_write_exit_mmio = write_exit_mmio,
7135 static int emulator_read_write_onepage(unsigned long addr, void *val,
7137 struct x86_exception *exception,
7138 struct kvm_vcpu *vcpu,
7139 const struct read_write_emulator_ops *ops)
7143 bool write = ops->write;
7144 struct kvm_mmio_fragment *frag;
7145 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7148 * If the exit was due to a NPF we may already have a GPA.
7149 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7150 * Note, this cannot be used on string operations since string
7151 * operation using rep will only have the initial GPA from the NPF
7154 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7155 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7156 gpa = ctxt->gpa_val;
7157 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7159 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7161 return X86EMUL_PROPAGATE_FAULT;
7164 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7165 return X86EMUL_CONTINUE;
7168 * Is this MMIO handled locally?
7170 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7171 if (handled == bytes)
7172 return X86EMUL_CONTINUE;
7178 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7179 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7183 return X86EMUL_CONTINUE;
7186 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7188 void *val, unsigned int bytes,
7189 struct x86_exception *exception,
7190 const struct read_write_emulator_ops *ops)
7192 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7196 if (ops->read_write_prepare &&
7197 ops->read_write_prepare(vcpu, val, bytes))
7198 return X86EMUL_CONTINUE;
7200 vcpu->mmio_nr_fragments = 0;
7202 /* Crossing a page boundary? */
7203 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7206 now = -addr & ~PAGE_MASK;
7207 rc = emulator_read_write_onepage(addr, val, now, exception,
7210 if (rc != X86EMUL_CONTINUE)
7213 if (ctxt->mode != X86EMUL_MODE_PROT64)
7219 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7221 if (rc != X86EMUL_CONTINUE)
7224 if (!vcpu->mmio_nr_fragments)
7227 gpa = vcpu->mmio_fragments[0].gpa;
7229 vcpu->mmio_needed = 1;
7230 vcpu->mmio_cur_fragment = 0;
7232 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7233 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7234 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7235 vcpu->run->mmio.phys_addr = gpa;
7237 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7240 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7244 struct x86_exception *exception)
7246 return emulator_read_write(ctxt, addr, val, bytes,
7247 exception, &read_emultor);
7250 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7254 struct x86_exception *exception)
7256 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7257 exception, &write_emultor);
7260 #define CMPXCHG_TYPE(t, ptr, old, new) \
7261 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
7263 #ifdef CONFIG_X86_64
7264 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
7266 # define CMPXCHG64(ptr, old, new) \
7267 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
7270 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7275 struct x86_exception *exception)
7277 struct kvm_host_map map;
7278 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7284 /* guests cmpxchg8b have to be emulated atomically */
7285 if (bytes > 8 || (bytes & (bytes - 1)))
7288 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7290 if (gpa == UNMAPPED_GVA ||
7291 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7295 * Emulate the atomic as a straight write to avoid #AC if SLD is
7296 * enabled in the host and the access splits a cache line.
7298 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7299 page_line_mask = ~(cache_line_size() - 1);
7301 page_line_mask = PAGE_MASK;
7303 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7306 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
7309 kaddr = map.hva + offset_in_page(gpa);
7313 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
7316 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
7319 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
7322 exchanged = CMPXCHG64(kaddr, old, new);
7328 kvm_vcpu_unmap(vcpu, &map, true);
7331 return X86EMUL_CMPXCHG_FAILED;
7333 kvm_page_track_write(vcpu, gpa, new, bytes);
7335 return X86EMUL_CONTINUE;
7338 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
7340 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7343 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
7347 for (i = 0; i < vcpu->arch.pio.count; i++) {
7348 if (vcpu->arch.pio.in)
7349 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
7350 vcpu->arch.pio.size, pd);
7352 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
7353 vcpu->arch.pio.port, vcpu->arch.pio.size,
7357 pd += vcpu->arch.pio.size;
7362 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7363 unsigned short port,
7364 unsigned int count, bool in)
7366 vcpu->arch.pio.port = port;
7367 vcpu->arch.pio.in = in;
7368 vcpu->arch.pio.count = count;
7369 vcpu->arch.pio.size = size;
7371 if (!kernel_pio(vcpu, vcpu->arch.pio_data))
7374 vcpu->run->exit_reason = KVM_EXIT_IO;
7375 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7376 vcpu->run->io.size = size;
7377 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7378 vcpu->run->io.count = count;
7379 vcpu->run->io.port = port;
7384 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7385 unsigned short port, unsigned int count)
7387 WARN_ON(vcpu->arch.pio.count);
7388 memset(vcpu->arch.pio_data, 0, size * count);
7389 return emulator_pio_in_out(vcpu, size, port, count, true);
7392 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7394 int size = vcpu->arch.pio.size;
7395 unsigned count = vcpu->arch.pio.count;
7396 memcpy(val, vcpu->arch.pio_data, size * count);
7397 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7398 vcpu->arch.pio.count = 0;
7401 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7402 unsigned short port, void *val, unsigned int count)
7404 if (vcpu->arch.pio.count) {
7406 * Complete a previous iteration that required userspace I/O.
7407 * Note, @count isn't guaranteed to match pio.count as userspace
7408 * can modify ECX before rerunning the vCPU. Ignore any such
7409 * shenanigans as KVM doesn't support modifying the rep count,
7410 * and the emulator ensures @count doesn't overflow the buffer.
7413 int r = __emulator_pio_in(vcpu, size, port, count);
7417 /* Results already available, fall through. */
7420 complete_emulator_pio_in(vcpu, val);
7424 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7425 int size, unsigned short port, void *val,
7428 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
7432 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7433 unsigned short port, const void *val,
7438 memcpy(vcpu->arch.pio_data, val, size * count);
7439 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
7440 ret = emulator_pio_in_out(vcpu, size, port, count, false);
7442 vcpu->arch.pio.count = 0;
7447 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7448 int size, unsigned short port,
7449 const void *val, unsigned int count)
7451 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7454 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7456 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7459 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7461 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7464 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7466 if (!need_emulate_wbinvd(vcpu))
7467 return X86EMUL_CONTINUE;
7469 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7470 int cpu = get_cpu();
7472 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7473 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7474 wbinvd_ipi, NULL, 1);
7476 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7479 return X86EMUL_CONTINUE;
7482 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7484 kvm_emulate_wbinvd_noskip(vcpu);
7485 return kvm_skip_emulated_instruction(vcpu);
7487 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7491 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7493 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7496 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7497 unsigned long *dest)
7499 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7502 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7503 unsigned long value)
7506 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7509 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7511 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7514 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7517 unsigned long value;
7521 value = kvm_read_cr0(vcpu);
7524 value = vcpu->arch.cr2;
7527 value = kvm_read_cr3(vcpu);
7530 value = kvm_read_cr4(vcpu);
7533 value = kvm_get_cr8(vcpu);
7536 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7543 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7545 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7550 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7553 vcpu->arch.cr2 = val;
7556 res = kvm_set_cr3(vcpu, val);
7559 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7562 res = kvm_set_cr8(vcpu, val);
7565 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7572 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7574 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7577 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7579 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7582 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7584 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7587 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7589 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
7592 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7594 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
7597 static unsigned long emulator_get_cached_segment_base(
7598 struct x86_emulate_ctxt *ctxt, int seg)
7600 return get_segment_base(emul_to_vcpu(ctxt), seg);
7603 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
7604 struct desc_struct *desc, u32 *base3,
7607 struct kvm_segment var;
7609 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
7610 *selector = var.selector;
7613 memset(desc, 0, sizeof(*desc));
7621 set_desc_limit(desc, var.limit);
7622 set_desc_base(desc, (unsigned long)var.base);
7623 #ifdef CONFIG_X86_64
7625 *base3 = var.base >> 32;
7627 desc->type = var.type;
7629 desc->dpl = var.dpl;
7630 desc->p = var.present;
7631 desc->avl = var.avl;
7639 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
7640 struct desc_struct *desc, u32 base3,
7643 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7644 struct kvm_segment var;
7646 var.selector = selector;
7647 var.base = get_desc_base(desc);
7648 #ifdef CONFIG_X86_64
7649 var.base |= ((u64)base3) << 32;
7651 var.limit = get_desc_limit(desc);
7653 var.limit = (var.limit << 12) | 0xfff;
7654 var.type = desc->type;
7655 var.dpl = desc->dpl;
7660 var.avl = desc->avl;
7661 var.present = desc->p;
7662 var.unusable = !var.present;
7665 kvm_set_segment(vcpu, &var, seg);
7669 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7670 u32 msr_index, u64 *pdata)
7672 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7675 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
7677 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
7678 complete_emulated_rdmsr, r)) {
7679 /* Bounce to user space */
7680 return X86EMUL_IO_NEEDED;
7686 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7687 u32 msr_index, u64 data)
7689 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7692 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
7694 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
7695 complete_emulated_msr_access, r)) {
7696 /* Bounce to user space */
7697 return X86EMUL_IO_NEEDED;
7703 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
7704 u32 msr_index, u64 *pdata)
7706 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
7709 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
7710 u32 msr_index, u64 data)
7712 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
7715 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
7717 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7719 return vcpu->arch.smbase;
7722 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
7724 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7726 vcpu->arch.smbase = smbase;
7729 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
7732 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
7737 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
7738 u32 pmc, u64 *pdata)
7740 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
7743 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
7745 emul_to_vcpu(ctxt)->arch.halt_request = 1;
7748 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
7749 struct x86_instruction_info *info,
7750 enum x86_intercept_stage stage)
7752 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
7756 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
7757 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
7760 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
7763 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
7765 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
7768 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
7770 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
7773 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
7775 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
7778 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
7780 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
7783 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
7785 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
7788 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
7790 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
7793 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
7795 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
7798 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
7800 return emul_to_vcpu(ctxt)->arch.hflags;
7803 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt)
7805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7807 kvm_smm_changed(vcpu, false);
7810 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt,
7811 const char *smstate)
7813 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate);
7816 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
7818 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
7821 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
7823 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
7826 static const struct x86_emulate_ops emulate_ops = {
7827 .read_gpr = emulator_read_gpr,
7828 .write_gpr = emulator_write_gpr,
7829 .read_std = emulator_read_std,
7830 .write_std = emulator_write_std,
7831 .read_phys = kvm_read_guest_phys_system,
7832 .fetch = kvm_fetch_guest_virt,
7833 .read_emulated = emulator_read_emulated,
7834 .write_emulated = emulator_write_emulated,
7835 .cmpxchg_emulated = emulator_cmpxchg_emulated,
7836 .invlpg = emulator_invlpg,
7837 .pio_in_emulated = emulator_pio_in_emulated,
7838 .pio_out_emulated = emulator_pio_out_emulated,
7839 .get_segment = emulator_get_segment,
7840 .set_segment = emulator_set_segment,
7841 .get_cached_segment_base = emulator_get_cached_segment_base,
7842 .get_gdt = emulator_get_gdt,
7843 .get_idt = emulator_get_idt,
7844 .set_gdt = emulator_set_gdt,
7845 .set_idt = emulator_set_idt,
7846 .get_cr = emulator_get_cr,
7847 .set_cr = emulator_set_cr,
7848 .cpl = emulator_get_cpl,
7849 .get_dr = emulator_get_dr,
7850 .set_dr = emulator_set_dr,
7851 .get_smbase = emulator_get_smbase,
7852 .set_smbase = emulator_set_smbase,
7853 .set_msr_with_filter = emulator_set_msr_with_filter,
7854 .get_msr_with_filter = emulator_get_msr_with_filter,
7855 .set_msr = emulator_set_msr,
7856 .get_msr = emulator_get_msr,
7857 .check_pmc = emulator_check_pmc,
7858 .read_pmc = emulator_read_pmc,
7859 .halt = emulator_halt,
7860 .wbinvd = emulator_wbinvd,
7861 .fix_hypercall = emulator_fix_hypercall,
7862 .intercept = emulator_intercept,
7863 .get_cpuid = emulator_get_cpuid,
7864 .guest_has_long_mode = emulator_guest_has_long_mode,
7865 .guest_has_movbe = emulator_guest_has_movbe,
7866 .guest_has_fxsr = emulator_guest_has_fxsr,
7867 .guest_has_rdpid = emulator_guest_has_rdpid,
7868 .set_nmi_mask = emulator_set_nmi_mask,
7869 .get_hflags = emulator_get_hflags,
7870 .exiting_smm = emulator_exiting_smm,
7871 .leave_smm = emulator_leave_smm,
7872 .triple_fault = emulator_triple_fault,
7873 .set_xcr = emulator_set_xcr,
7876 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
7878 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
7880 * an sti; sti; sequence only disable interrupts for the first
7881 * instruction. So, if the last instruction, be it emulated or
7882 * not, left the system with the INT_STI flag enabled, it
7883 * means that the last instruction is an sti. We should not
7884 * leave the flag on in this case. The same goes for mov ss
7886 if (int_shadow & mask)
7888 if (unlikely(int_shadow || mask)) {
7889 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
7891 kvm_make_request(KVM_REQ_EVENT, vcpu);
7895 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
7897 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7898 if (ctxt->exception.vector == PF_VECTOR)
7899 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
7901 if (ctxt->exception.error_code_valid)
7902 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
7903 ctxt->exception.error_code);
7905 kvm_queue_exception(vcpu, ctxt->exception.vector);
7909 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
7911 struct x86_emulate_ctxt *ctxt;
7913 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
7915 pr_err("kvm: failed to allocate vcpu's emulator\n");
7920 ctxt->ops = &emulate_ops;
7921 vcpu->arch.emulate_ctxt = ctxt;
7926 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
7928 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7931 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
7933 ctxt->gpa_available = false;
7934 ctxt->eflags = kvm_get_rflags(vcpu);
7935 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
7937 ctxt->eip = kvm_rip_read(vcpu);
7938 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
7939 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
7940 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
7941 cs_db ? X86EMUL_MODE_PROT32 :
7942 X86EMUL_MODE_PROT16;
7943 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
7944 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
7945 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
7947 ctxt->interruptibility = 0;
7948 ctxt->have_exception = false;
7949 ctxt->exception.vector = -1;
7950 ctxt->perm_ok = false;
7952 init_decode_cache(ctxt);
7953 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7956 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7958 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7961 init_emulate_ctxt(vcpu);
7965 ctxt->_eip = ctxt->eip + inc_eip;
7966 ret = emulate_int_real(ctxt, irq);
7968 if (ret != X86EMUL_CONTINUE) {
7969 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7971 ctxt->eip = ctxt->_eip;
7972 kvm_rip_write(vcpu, ctxt->eip);
7973 kvm_set_rflags(vcpu, ctxt->eflags);
7976 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7978 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
7979 u8 ndata, u8 *insn_bytes, u8 insn_size)
7981 struct kvm_run *run = vcpu->run;
7986 * Zero the whole array used to retrieve the exit info, as casting to
7987 * u32 for select entries will leave some chunks uninitialized.
7989 memset(&info, 0, sizeof(info));
7991 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
7992 &info[2], (u32 *)&info[3],
7995 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7996 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
7999 * There's currently space for 13 entries, but 5 are used for the exit
8000 * reason and info. Restrict to 4 to reduce the maintenance burden
8001 * when expanding kvm_run.emulation_failure in the future.
8003 if (WARN_ON_ONCE(ndata > 4))
8006 /* Always include the flags as a 'data' entry. */
8008 run->emulation_failure.flags = 0;
8011 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8012 sizeof(run->emulation_failure.insn_bytes) != 16));
8014 run->emulation_failure.flags |=
8015 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8016 run->emulation_failure.insn_size = insn_size;
8017 memset(run->emulation_failure.insn_bytes, 0x90,
8018 sizeof(run->emulation_failure.insn_bytes));
8019 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8022 memcpy(&run->internal.data[info_start], info, sizeof(info));
8023 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8024 ndata * sizeof(data[0]));
8026 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8029 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8031 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8033 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8034 ctxt->fetch.end - ctxt->fetch.data);
8037 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8040 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8042 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8044 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8046 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8048 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8050 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8052 struct kvm *kvm = vcpu->kvm;
8054 ++vcpu->stat.insn_emulation_fail;
8055 trace_kvm_emulate_insn_failed(vcpu);
8057 if (emulation_type & EMULTYPE_VMWARE_GP) {
8058 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8062 if (kvm->arch.exit_on_emulation_error ||
8063 (emulation_type & EMULTYPE_SKIP)) {
8064 prepare_emulation_ctxt_failure_exit(vcpu);
8068 kvm_queue_exception(vcpu, UD_VECTOR);
8070 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8071 prepare_emulation_ctxt_failure_exit(vcpu);
8078 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8079 bool write_fault_to_shadow_pgtable,
8082 gpa_t gpa = cr2_or_gpa;
8085 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8088 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8089 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8092 if (!vcpu->arch.mmu->direct_map) {
8094 * Write permission should be allowed since only
8095 * write access need to be emulated.
8097 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8100 * If the mapping is invalid in guest, let cpu retry
8101 * it to generate fault.
8103 if (gpa == UNMAPPED_GVA)
8108 * Do not retry the unhandleable instruction if it faults on the
8109 * readonly host memory, otherwise it will goto a infinite loop:
8110 * retry instruction -> write #PF -> emulation fail -> retry
8111 * instruction -> ...
8113 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8116 * If the instruction failed on the error pfn, it can not be fixed,
8117 * report the error to userspace.
8119 if (is_error_noslot_pfn(pfn))
8122 kvm_release_pfn_clean(pfn);
8124 /* The instructions are well-emulated on direct mmu. */
8125 if (vcpu->arch.mmu->direct_map) {
8126 unsigned int indirect_shadow_pages;
8128 write_lock(&vcpu->kvm->mmu_lock);
8129 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8130 write_unlock(&vcpu->kvm->mmu_lock);
8132 if (indirect_shadow_pages)
8133 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8139 * if emulation was due to access to shadowed page table
8140 * and it failed try to unshadow page and re-enter the
8141 * guest to let CPU execute the instruction.
8143 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8146 * If the access faults on its page table, it can not
8147 * be fixed by unprotecting shadow page and it should
8148 * be reported to userspace.
8150 return !write_fault_to_shadow_pgtable;
8153 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8154 gpa_t cr2_or_gpa, int emulation_type)
8156 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8157 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8159 last_retry_eip = vcpu->arch.last_retry_eip;
8160 last_retry_addr = vcpu->arch.last_retry_addr;
8163 * If the emulation is caused by #PF and it is non-page_table
8164 * writing instruction, it means the VM-EXIT is caused by shadow
8165 * page protected, we can zap the shadow page and retry this
8166 * instruction directly.
8168 * Note: if the guest uses a non-page-table modifying instruction
8169 * on the PDE that points to the instruction, then we will unmap
8170 * the instruction and go to an infinite loop. So, we cache the
8171 * last retried eip and the last fault address, if we meet the eip
8172 * and the address again, we can break out of the potential infinite
8175 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8177 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8180 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8181 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8184 if (x86_page_table_writing_insn(ctxt))
8187 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8190 vcpu->arch.last_retry_eip = ctxt->eip;
8191 vcpu->arch.last_retry_addr = cr2_or_gpa;
8193 if (!vcpu->arch.mmu->direct_map)
8194 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8196 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8201 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8202 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8204 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm)
8206 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm);
8209 vcpu->arch.hflags |= HF_SMM_MASK;
8211 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK);
8213 /* Process a latched INIT or SMI, if any. */
8214 kvm_make_request(KVM_REQ_EVENT, vcpu);
8217 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band,
8218 * on SMM exit we still need to reload them from
8221 vcpu->arch.pdptrs_from_userspace = false;
8224 kvm_mmu_reset_context(vcpu);
8227 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8236 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8237 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8242 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8244 struct kvm_run *kvm_run = vcpu->run;
8246 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8247 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8248 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8249 kvm_run->debug.arch.exception = DB_VECTOR;
8250 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8253 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8257 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8259 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8262 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8266 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8269 * rflags is the old, "raw" value of the flags. The new value has
8270 * not been saved yet.
8272 * This is correct even for TF set by the guest, because "the
8273 * processor will not generate this exception after the instruction
8274 * that sets the TF flag".
8276 if (unlikely(rflags & X86_EFLAGS_TF))
8277 r = kvm_vcpu_do_singlestep(vcpu);
8280 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8282 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
8284 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8285 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8286 struct kvm_run *kvm_run = vcpu->run;
8287 unsigned long eip = kvm_get_linear_rip(vcpu);
8288 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8289 vcpu->arch.guest_debug_dr7,
8293 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8294 kvm_run->debug.arch.pc = eip;
8295 kvm_run->debug.arch.exception = DB_VECTOR;
8296 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8302 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8303 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
8304 unsigned long eip = kvm_get_linear_rip(vcpu);
8305 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8310 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8319 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8321 switch (ctxt->opcode_len) {
8328 case 0xe6: /* OUT */
8332 case 0x6c: /* INS */
8334 case 0x6e: /* OUTS */
8341 case 0x33: /* RDPMC */
8351 * Decode to be emulated instruction. Return EMULATION_OK if success.
8353 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8354 void *insn, int insn_len)
8356 int r = EMULATION_OK;
8357 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8359 init_emulate_ctxt(vcpu);
8362 * We will reenter on the same instruction since we do not set
8363 * complete_userspace_io. This does not handle watchpoints yet,
8364 * those would be handled in the emulate_ops.
8366 if (!(emulation_type & EMULTYPE_SKIP) &&
8367 kvm_vcpu_check_breakpoint(vcpu, &r))
8370 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8372 trace_kvm_emulate_insn_start(vcpu);
8373 ++vcpu->stat.insn_emulation;
8377 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8379 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8380 int emulation_type, void *insn, int insn_len)
8383 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8384 bool writeback = true;
8385 bool write_fault_to_spt;
8387 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8390 vcpu->arch.l1tf_flush_l1d = true;
8393 * Clear write_fault_to_shadow_pgtable here to ensure it is
8396 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
8397 vcpu->arch.write_fault_to_shadow_pgtable = false;
8399 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8400 kvm_clear_exception_queue(vcpu);
8402 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8404 if (r != EMULATION_OK) {
8405 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8406 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8407 kvm_queue_exception(vcpu, UD_VECTOR);
8410 if (reexecute_instruction(vcpu, cr2_or_gpa,
8414 if (ctxt->have_exception) {
8416 * #UD should result in just EMULATION_FAILED, and trap-like
8417 * exception should not be encountered during decode.
8419 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8420 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8421 inject_emulated_exception(vcpu);
8424 return handle_emulation_failure(vcpu, emulation_type);
8428 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8429 !is_vmware_backdoor_opcode(ctxt)) {
8430 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8435 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8436 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8437 * The caller is responsible for updating interruptibility state and
8438 * injecting single-step #DBs.
8440 if (emulation_type & EMULTYPE_SKIP) {
8441 if (ctxt->mode != X86EMUL_MODE_PROT64)
8442 ctxt->eip = (u32)ctxt->_eip;
8444 ctxt->eip = ctxt->_eip;
8446 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8451 kvm_rip_write(vcpu, ctxt->eip);
8452 if (ctxt->eflags & X86_EFLAGS_RF)
8453 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8457 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8460 /* this is needed for vmware backdoor interface to work since it
8461 changes registers values during IO operation */
8462 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8463 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8464 emulator_invalidate_register_cache(ctxt);
8468 if (emulation_type & EMULTYPE_PF) {
8469 /* Save the faulting GPA (cr2) in the address field */
8470 ctxt->exception.address = cr2_or_gpa;
8472 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8473 if (vcpu->arch.mmu->direct_map) {
8474 ctxt->gpa_available = true;
8475 ctxt->gpa_val = cr2_or_gpa;
8478 /* Sanitize the address out of an abundance of paranoia. */
8479 ctxt->exception.address = 0;
8482 r = x86_emulate_insn(ctxt);
8484 if (r == EMULATION_INTERCEPTED)
8487 if (r == EMULATION_FAILED) {
8488 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
8492 return handle_emulation_failure(vcpu, emulation_type);
8495 if (ctxt->have_exception) {
8497 if (inject_emulated_exception(vcpu))
8499 } else if (vcpu->arch.pio.count) {
8500 if (!vcpu->arch.pio.in) {
8501 /* FIXME: return into emulator if single-stepping. */
8502 vcpu->arch.pio.count = 0;
8505 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8508 } else if (vcpu->mmio_needed) {
8509 ++vcpu->stat.mmio_exits;
8511 if (!vcpu->mmio_is_write)
8514 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8515 } else if (vcpu->arch.complete_userspace_io) {
8518 } else if (r == EMULATION_RESTART)
8525 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8526 toggle_interruptibility(vcpu, ctxt->interruptibility);
8527 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8528 if (!ctxt->have_exception ||
8529 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8530 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8531 if (ctxt->is_branch)
8532 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8533 kvm_rip_write(vcpu, ctxt->eip);
8534 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8535 r = kvm_vcpu_do_singlestep(vcpu);
8536 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8537 __kvm_set_rflags(vcpu, ctxt->eflags);
8541 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8542 * do nothing, and it will be requested again as soon as
8543 * the shadow expires. But we still need to check here,
8544 * because POPF has no interrupt shadow.
8546 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8547 kvm_make_request(KVM_REQ_EVENT, vcpu);
8549 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8554 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8556 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8558 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8560 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8561 void *insn, int insn_len)
8563 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8565 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8567 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
8569 vcpu->arch.pio.count = 0;
8573 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
8575 vcpu->arch.pio.count = 0;
8577 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
8580 return kvm_skip_emulated_instruction(vcpu);
8583 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
8584 unsigned short port)
8586 unsigned long val = kvm_rax_read(vcpu);
8587 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
8593 * Workaround userspace that relies on old KVM behavior of %rip being
8594 * incremented prior to exiting to userspace to handle "OUT 0x7e".
8597 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
8598 vcpu->arch.complete_userspace_io =
8599 complete_fast_pio_out_port_0x7e;
8600 kvm_skip_emulated_instruction(vcpu);
8602 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8603 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
8608 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
8612 /* We should only ever be called with arch.pio.count equal to 1 */
8613 BUG_ON(vcpu->arch.pio.count != 1);
8615 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
8616 vcpu->arch.pio.count = 0;
8620 /* For size less than 4 we merge, else we zero extend */
8621 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8624 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
8625 * the copy and tracing
8627 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
8628 kvm_rax_write(vcpu, val);
8630 return kvm_skip_emulated_instruction(vcpu);
8633 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
8634 unsigned short port)
8639 /* For size less than 4 we merge, else we zero extend */
8640 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8642 ret = emulator_pio_in(vcpu, size, port, &val, 1);
8644 kvm_rax_write(vcpu, val);
8648 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8649 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
8654 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
8659 ret = kvm_fast_pio_in(vcpu, size, port);
8661 ret = kvm_fast_pio_out(vcpu, size, port);
8662 return ret && kvm_skip_emulated_instruction(vcpu);
8664 EXPORT_SYMBOL_GPL(kvm_fast_pio);
8666 static int kvmclock_cpu_down_prep(unsigned int cpu)
8668 __this_cpu_write(cpu_tsc_khz, 0);
8672 static void tsc_khz_changed(void *data)
8674 struct cpufreq_freqs *freq = data;
8675 unsigned long khz = 0;
8679 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8680 khz = cpufreq_quick_get(raw_smp_processor_id());
8683 __this_cpu_write(cpu_tsc_khz, khz);
8686 #ifdef CONFIG_X86_64
8687 static void kvm_hyperv_tsc_notifier(void)
8692 mutex_lock(&kvm_lock);
8693 list_for_each_entry(kvm, &vm_list, vm_list)
8694 kvm_make_mclock_inprogress_request(kvm);
8696 /* no guest entries from this point */
8697 hyperv_stop_tsc_emulation();
8699 /* TSC frequency always matches when on Hyper-V */
8700 for_each_present_cpu(cpu)
8701 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
8702 kvm_max_guest_tsc_khz = tsc_khz;
8704 list_for_each_entry(kvm, &vm_list, vm_list) {
8705 __kvm_start_pvclock_update(kvm);
8706 pvclock_update_vm_gtod_copy(kvm);
8707 kvm_end_pvclock_update(kvm);
8710 mutex_unlock(&kvm_lock);
8714 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
8717 struct kvm_vcpu *vcpu;
8722 * We allow guests to temporarily run on slowing clocks,
8723 * provided we notify them after, or to run on accelerating
8724 * clocks, provided we notify them before. Thus time never
8727 * However, we have a problem. We can't atomically update
8728 * the frequency of a given CPU from this function; it is
8729 * merely a notifier, which can be called from any CPU.
8730 * Changing the TSC frequency at arbitrary points in time
8731 * requires a recomputation of local variables related to
8732 * the TSC for each VCPU. We must flag these local variables
8733 * to be updated and be sure the update takes place with the
8734 * new frequency before any guests proceed.
8736 * Unfortunately, the combination of hotplug CPU and frequency
8737 * change creates an intractable locking scenario; the order
8738 * of when these callouts happen is undefined with respect to
8739 * CPU hotplug, and they can race with each other. As such,
8740 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
8741 * undefined; you can actually have a CPU frequency change take
8742 * place in between the computation of X and the setting of the
8743 * variable. To protect against this problem, all updates of
8744 * the per_cpu tsc_khz variable are done in an interrupt
8745 * protected IPI, and all callers wishing to update the value
8746 * must wait for a synchronous IPI to complete (which is trivial
8747 * if the caller is on the CPU already). This establishes the
8748 * necessary total order on variable updates.
8750 * Note that because a guest time update may take place
8751 * anytime after the setting of the VCPU's request bit, the
8752 * correct TSC value must be set before the request. However,
8753 * to ensure the update actually makes it to any guest which
8754 * starts running in hardware virtualization between the set
8755 * and the acquisition of the spinlock, we must also ping the
8756 * CPU after setting the request bit.
8760 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
8762 mutex_lock(&kvm_lock);
8763 list_for_each_entry(kvm, &vm_list, vm_list) {
8764 kvm_for_each_vcpu(i, vcpu, kvm) {
8765 if (vcpu->cpu != cpu)
8767 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8768 if (vcpu->cpu != raw_smp_processor_id())
8772 mutex_unlock(&kvm_lock);
8774 if (freq->old < freq->new && send_ipi) {
8776 * We upscale the frequency. Must make the guest
8777 * doesn't see old kvmclock values while running with
8778 * the new frequency, otherwise we risk the guest sees
8779 * time go backwards.
8781 * In case we update the frequency for another cpu
8782 * (which might be in guest context) send an interrupt
8783 * to kick the cpu out of guest context. Next time
8784 * guest context is entered kvmclock will be updated,
8785 * so the guest will not see stale values.
8787 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
8791 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
8794 struct cpufreq_freqs *freq = data;
8797 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
8799 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
8802 for_each_cpu(cpu, freq->policy->cpus)
8803 __kvmclock_cpufreq_notifier(freq, cpu);
8808 static struct notifier_block kvmclock_cpufreq_notifier_block = {
8809 .notifier_call = kvmclock_cpufreq_notifier
8812 static int kvmclock_cpu_online(unsigned int cpu)
8814 tsc_khz_changed(NULL);
8818 static void kvm_timer_init(void)
8820 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
8821 max_tsc_khz = tsc_khz;
8823 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
8824 struct cpufreq_policy *policy;
8828 policy = cpufreq_cpu_get(cpu);
8830 if (policy->cpuinfo.max_freq)
8831 max_tsc_khz = policy->cpuinfo.max_freq;
8832 cpufreq_cpu_put(policy);
8836 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
8837 CPUFREQ_TRANSITION_NOTIFIER);
8840 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
8841 kvmclock_cpu_online, kvmclock_cpu_down_prep);
8844 #ifdef CONFIG_X86_64
8845 static void pvclock_gtod_update_fn(struct work_struct *work)
8848 struct kvm_vcpu *vcpu;
8851 mutex_lock(&kvm_lock);
8852 list_for_each_entry(kvm, &vm_list, vm_list)
8853 kvm_for_each_vcpu(i, vcpu, kvm)
8854 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8855 atomic_set(&kvm_guest_has_master_clock, 0);
8856 mutex_unlock(&kvm_lock);
8859 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
8862 * Indirection to move queue_work() out of the tk_core.seq write held
8863 * region to prevent possible deadlocks against time accessors which
8864 * are invoked with work related locks held.
8866 static void pvclock_irq_work_fn(struct irq_work *w)
8868 queue_work(system_long_wq, &pvclock_gtod_work);
8871 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
8874 * Notification about pvclock gtod data update.
8876 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
8879 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
8880 struct timekeeper *tk = priv;
8882 update_pvclock_gtod(tk);
8885 * Disable master clock if host does not trust, or does not use,
8886 * TSC based clocksource. Delegate queue_work() to irq_work as
8887 * this is invoked with tk_core.seq write held.
8889 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
8890 atomic_read(&kvm_guest_has_master_clock) != 0)
8891 irq_work_queue(&pvclock_irq_work);
8895 static struct notifier_block pvclock_gtod_notifier = {
8896 .notifier_call = pvclock_gtod_notify,
8900 int kvm_arch_init(void *opaque)
8902 struct kvm_x86_init_ops *ops = opaque;
8905 if (kvm_x86_ops.hardware_enable) {
8906 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name);
8911 if (!ops->cpu_has_kvm_support()) {
8912 pr_err_ratelimited("kvm: no hardware support for '%s'\n",
8913 ops->runtime_ops->name);
8917 if (ops->disabled_by_bios()) {
8918 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n",
8919 ops->runtime_ops->name);
8925 * KVM explicitly assumes that the guest has an FPU and
8926 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
8927 * vCPU's FPU state as a fxregs_state struct.
8929 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
8930 printk(KERN_ERR "kvm: inadequate fpu\n");
8935 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
8936 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
8943 x86_emulator_cache = kvm_alloc_emulator_cache();
8944 if (!x86_emulator_cache) {
8945 pr_err("kvm: failed to allocate cache for x86 emulator\n");
8949 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
8950 if (!user_return_msrs) {
8951 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
8952 goto out_free_x86_emulator_cache;
8954 kvm_nr_uret_msrs = 0;
8956 r = kvm_mmu_vendor_module_init();
8958 goto out_free_percpu;
8962 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
8963 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
8964 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
8967 if (pi_inject_timer == -1)
8968 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
8969 #ifdef CONFIG_X86_64
8970 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
8972 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8973 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
8979 free_percpu(user_return_msrs);
8980 out_free_x86_emulator_cache:
8981 kmem_cache_destroy(x86_emulator_cache);
8986 void kvm_arch_exit(void)
8988 #ifdef CONFIG_X86_64
8989 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8990 clear_hv_tscchange_cb();
8994 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8995 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
8996 CPUFREQ_TRANSITION_NOTIFIER);
8997 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
8998 #ifdef CONFIG_X86_64
8999 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9000 irq_work_sync(&pvclock_irq_work);
9001 cancel_work_sync(&pvclock_gtod_work);
9003 kvm_x86_ops.hardware_enable = NULL;
9004 kvm_mmu_vendor_module_exit();
9005 free_percpu(user_return_msrs);
9006 kmem_cache_destroy(x86_emulator_cache);
9007 #ifdef CONFIG_KVM_XEN
9008 static_key_deferred_flush(&kvm_xen_enabled);
9009 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9013 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9016 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9017 * local APIC is in-kernel, the run loop will detect the non-runnable
9018 * state and halt the vCPU. Exit to userspace if the local APIC is
9019 * managed by userspace, in which case userspace is responsible for
9020 * handling wake events.
9022 ++vcpu->stat.halt_exits;
9023 if (lapic_in_kernel(vcpu)) {
9024 vcpu->arch.mp_state = state;
9027 vcpu->run->exit_reason = reason;
9032 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9034 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9036 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9038 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9040 int ret = kvm_skip_emulated_instruction(vcpu);
9042 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9043 * KVM_EXIT_DEBUG here.
9045 return kvm_emulate_halt_noskip(vcpu) && ret;
9047 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9049 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9051 int ret = kvm_skip_emulated_instruction(vcpu);
9053 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9054 KVM_EXIT_AP_RESET_HOLD) && ret;
9056 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9058 #ifdef CONFIG_X86_64
9059 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9060 unsigned long clock_type)
9062 struct kvm_clock_pairing clock_pairing;
9063 struct timespec64 ts;
9067 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9068 return -KVM_EOPNOTSUPP;
9071 * When tsc is in permanent catchup mode guests won't be able to use
9072 * pvclock_read_retry loop to get consistent view of pvclock
9074 if (vcpu->arch.tsc_always_catchup)
9075 return -KVM_EOPNOTSUPP;
9077 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9078 return -KVM_EOPNOTSUPP;
9080 clock_pairing.sec = ts.tv_sec;
9081 clock_pairing.nsec = ts.tv_nsec;
9082 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9083 clock_pairing.flags = 0;
9084 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9087 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9088 sizeof(struct kvm_clock_pairing)))
9096 * kvm_pv_kick_cpu_op: Kick a vcpu.
9098 * @apicid - apicid of vcpu to be kicked.
9100 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9102 struct kvm_lapic_irq lapic_irq;
9104 lapic_irq.shorthand = APIC_DEST_NOSHORT;
9105 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
9106 lapic_irq.level = 0;
9107 lapic_irq.dest_id = apicid;
9108 lapic_irq.msi_redir_hint = false;
9110 lapic_irq.delivery_mode = APIC_DM_REMRD;
9111 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9114 bool kvm_apicv_activated(struct kvm *kvm)
9116 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9118 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9120 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9122 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9123 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9125 return (vm_reasons | vcpu_reasons) == 0;
9127 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9129 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9130 enum kvm_apicv_inhibit reason, bool set)
9133 __set_bit(reason, inhibits);
9135 __clear_bit(reason, inhibits);
9137 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9140 static void kvm_apicv_init(struct kvm *kvm)
9142 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9144 init_rwsem(&kvm->arch.apicv_update_lock);
9146 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9149 set_or_clear_apicv_inhibit(inhibits,
9150 APICV_INHIBIT_REASON_ABSENT, true);
9153 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9155 struct kvm_vcpu *target = NULL;
9156 struct kvm_apic_map *map;
9158 vcpu->stat.directed_yield_attempted++;
9160 if (single_task_running())
9164 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9166 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9167 target = map->phys_map[dest_id]->vcpu;
9171 if (!target || !READ_ONCE(target->ready))
9174 /* Ignore requests to yield to self */
9178 if (kvm_vcpu_yield_to(target) <= 0)
9181 vcpu->stat.directed_yield_successful++;
9187 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9189 u64 ret = vcpu->run->hypercall.ret;
9191 if (!is_64_bit_mode(vcpu))
9193 kvm_rax_write(vcpu, ret);
9194 ++vcpu->stat.hypercalls;
9195 return kvm_skip_emulated_instruction(vcpu);
9198 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9200 unsigned long nr, a0, a1, a2, a3, ret;
9203 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9204 return kvm_xen_hypercall(vcpu);
9206 if (kvm_hv_hypercall_enabled(vcpu))
9207 return kvm_hv_hypercall(vcpu);
9209 nr = kvm_rax_read(vcpu);
9210 a0 = kvm_rbx_read(vcpu);
9211 a1 = kvm_rcx_read(vcpu);
9212 a2 = kvm_rdx_read(vcpu);
9213 a3 = kvm_rsi_read(vcpu);
9215 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9217 op_64_bit = is_64_bit_hypercall(vcpu);
9226 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9234 case KVM_HC_VAPIC_POLL_IRQ:
9237 case KVM_HC_KICK_CPU:
9238 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9241 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9242 kvm_sched_yield(vcpu, a1);
9245 #ifdef CONFIG_X86_64
9246 case KVM_HC_CLOCK_PAIRING:
9247 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9250 case KVM_HC_SEND_IPI:
9251 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9254 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9256 case KVM_HC_SCHED_YIELD:
9257 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9260 kvm_sched_yield(vcpu, a0);
9263 case KVM_HC_MAP_GPA_RANGE: {
9264 u64 gpa = a0, npages = a1, attrs = a2;
9267 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9270 if (!PAGE_ALIGNED(gpa) || !npages ||
9271 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9276 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9277 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9278 vcpu->run->hypercall.args[0] = gpa;
9279 vcpu->run->hypercall.args[1] = npages;
9280 vcpu->run->hypercall.args[2] = attrs;
9281 vcpu->run->hypercall.longmode = op_64_bit;
9282 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9292 kvm_rax_write(vcpu, ret);
9294 ++vcpu->stat.hypercalls;
9295 return kvm_skip_emulated_instruction(vcpu);
9297 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9299 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9301 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9302 char instruction[3];
9303 unsigned long rip = kvm_rip_read(vcpu);
9306 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9309 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9310 ctxt->exception.error_code_valid = false;
9311 ctxt->exception.vector = UD_VECTOR;
9312 ctxt->have_exception = true;
9313 return X86EMUL_PROPAGATE_FAULT;
9316 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9318 return emulator_write_emulated(ctxt, rip, instruction, 3,
9322 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9324 return vcpu->run->request_interrupt_window &&
9325 likely(!pic_in_kernel(vcpu->kvm));
9328 /* Called within kvm->srcu read side. */
9329 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9331 struct kvm_run *kvm_run = vcpu->run;
9333 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9334 kvm_run->cr8 = kvm_get_cr8(vcpu);
9335 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9337 kvm_run->ready_for_interrupt_injection =
9338 pic_in_kernel(vcpu->kvm) ||
9339 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9342 kvm_run->flags |= KVM_RUN_X86_SMM;
9345 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9349 if (!kvm_x86_ops.update_cr8_intercept)
9352 if (!lapic_in_kernel(vcpu))
9355 if (vcpu->arch.apicv_active)
9358 if (!vcpu->arch.apic->vapic_addr)
9359 max_irr = kvm_lapic_find_highest_irr(vcpu);
9366 tpr = kvm_lapic_get_cr8(vcpu);
9368 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9372 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9374 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9375 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9379 return kvm_x86_ops.nested_ops->check_events(vcpu);
9382 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9384 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9385 vcpu->arch.exception.error_code = false;
9386 static_call(kvm_x86_queue_exception)(vcpu);
9389 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
9392 bool can_inject = true;
9394 /* try to reinject previous events if any */
9396 if (vcpu->arch.exception.injected) {
9397 kvm_inject_exception(vcpu);
9401 * Do not inject an NMI or interrupt if there is a pending
9402 * exception. Exceptions and interrupts are recognized at
9403 * instruction boundaries, i.e. the start of an instruction.
9404 * Trap-like exceptions, e.g. #DB, have higher priority than
9405 * NMIs and interrupts, i.e. traps are recognized before an
9406 * NMI/interrupt that's pending on the same instruction.
9407 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
9408 * priority, but are only generated (pended) during instruction
9409 * execution, i.e. a pending fault-like exception means the
9410 * fault occurred on the *previous* instruction and must be
9411 * serviced prior to recognizing any new events in order to
9412 * fully complete the previous instruction.
9414 else if (!vcpu->arch.exception.pending) {
9415 if (vcpu->arch.nmi_injected) {
9416 static_call(kvm_x86_inject_nmi)(vcpu);
9418 } else if (vcpu->arch.interrupt.injected) {
9419 static_call(kvm_x86_inject_irq)(vcpu);
9424 WARN_ON_ONCE(vcpu->arch.exception.injected &&
9425 vcpu->arch.exception.pending);
9428 * Call check_nested_events() even if we reinjected a previous event
9429 * in order for caller to determine if it should require immediate-exit
9430 * from L2 to L1 due to pending L1 events which require exit
9433 if (is_guest_mode(vcpu)) {
9434 r = kvm_check_nested_events(vcpu);
9439 /* try to inject new event if pending */
9440 if (vcpu->arch.exception.pending) {
9441 trace_kvm_inj_exception(vcpu->arch.exception.nr,
9442 vcpu->arch.exception.has_error_code,
9443 vcpu->arch.exception.error_code);
9445 vcpu->arch.exception.pending = false;
9446 vcpu->arch.exception.injected = true;
9448 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
9449 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
9452 if (vcpu->arch.exception.nr == DB_VECTOR) {
9453 kvm_deliver_exception_payload(vcpu);
9454 if (vcpu->arch.dr7 & DR7_GD) {
9455 vcpu->arch.dr7 &= ~DR7_GD;
9456 kvm_update_dr7(vcpu);
9460 kvm_inject_exception(vcpu);
9464 /* Don't inject interrupts if the user asked to avoid doing so */
9465 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
9469 * Finally, inject interrupt events. If an event cannot be injected
9470 * due to architectural conditions (e.g. IF=0) a window-open exit
9471 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
9472 * and can architecturally be injected, but we cannot do it right now:
9473 * an interrupt could have arrived just now and we have to inject it
9474 * as a vmexit, or there could already an event in the queue, which is
9475 * indicated by can_inject. In that case we request an immediate exit
9476 * in order to make progress and get back here for another iteration.
9477 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
9479 if (vcpu->arch.smi_pending) {
9480 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
9484 vcpu->arch.smi_pending = false;
9485 ++vcpu->arch.smi_count;
9489 static_call(kvm_x86_enable_smi_window)(vcpu);
9492 if (vcpu->arch.nmi_pending) {
9493 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
9497 --vcpu->arch.nmi_pending;
9498 vcpu->arch.nmi_injected = true;
9499 static_call(kvm_x86_inject_nmi)(vcpu);
9501 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
9503 if (vcpu->arch.nmi_pending)
9504 static_call(kvm_x86_enable_nmi_window)(vcpu);
9507 if (kvm_cpu_has_injectable_intr(vcpu)) {
9508 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
9512 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
9513 static_call(kvm_x86_inject_irq)(vcpu);
9514 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
9516 if (kvm_cpu_has_injectable_intr(vcpu))
9517 static_call(kvm_x86_enable_irq_window)(vcpu);
9520 if (is_guest_mode(vcpu) &&
9521 kvm_x86_ops.nested_ops->hv_timer_pending &&
9522 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
9523 *req_immediate_exit = true;
9525 WARN_ON(vcpu->arch.exception.pending);
9530 *req_immediate_exit = true;
9536 static void process_nmi(struct kvm_vcpu *vcpu)
9541 * x86 is limited to one NMI running, and one NMI pending after it.
9542 * If an NMI is already in progress, limit further NMIs to just one.
9543 * Otherwise, allow two (and we'll inject the first one immediately).
9545 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
9548 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
9549 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
9550 kvm_make_request(KVM_REQ_EVENT, vcpu);
9553 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
9556 flags |= seg->g << 23;
9557 flags |= seg->db << 22;
9558 flags |= seg->l << 21;
9559 flags |= seg->avl << 20;
9560 flags |= seg->present << 15;
9561 flags |= seg->dpl << 13;
9562 flags |= seg->s << 12;
9563 flags |= seg->type << 8;
9567 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
9569 struct kvm_segment seg;
9572 kvm_get_segment(vcpu, &seg, n);
9573 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
9576 offset = 0x7f84 + n * 12;
9578 offset = 0x7f2c + (n - 3) * 12;
9580 put_smstate(u32, buf, offset + 8, seg.base);
9581 put_smstate(u32, buf, offset + 4, seg.limit);
9582 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
9585 #ifdef CONFIG_X86_64
9586 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
9588 struct kvm_segment seg;
9592 kvm_get_segment(vcpu, &seg, n);
9593 offset = 0x7e00 + n * 16;
9595 flags = enter_smm_get_segment_flags(&seg) >> 8;
9596 put_smstate(u16, buf, offset, seg.selector);
9597 put_smstate(u16, buf, offset + 2, flags);
9598 put_smstate(u32, buf, offset + 4, seg.limit);
9599 put_smstate(u64, buf, offset + 8, seg.base);
9603 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
9606 struct kvm_segment seg;
9610 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
9611 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
9612 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
9613 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
9615 for (i = 0; i < 8; i++)
9616 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i));
9618 kvm_get_dr(vcpu, 6, &val);
9619 put_smstate(u32, buf, 0x7fcc, (u32)val);
9620 kvm_get_dr(vcpu, 7, &val);
9621 put_smstate(u32, buf, 0x7fc8, (u32)val);
9623 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9624 put_smstate(u32, buf, 0x7fc4, seg.selector);
9625 put_smstate(u32, buf, 0x7f64, seg.base);
9626 put_smstate(u32, buf, 0x7f60, seg.limit);
9627 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
9629 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9630 put_smstate(u32, buf, 0x7fc0, seg.selector);
9631 put_smstate(u32, buf, 0x7f80, seg.base);
9632 put_smstate(u32, buf, 0x7f7c, seg.limit);
9633 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
9635 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9636 put_smstate(u32, buf, 0x7f74, dt.address);
9637 put_smstate(u32, buf, 0x7f70, dt.size);
9639 static_call(kvm_x86_get_idt)(vcpu, &dt);
9640 put_smstate(u32, buf, 0x7f58, dt.address);
9641 put_smstate(u32, buf, 0x7f54, dt.size);
9643 for (i = 0; i < 6; i++)
9644 enter_smm_save_seg_32(vcpu, buf, i);
9646 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
9649 put_smstate(u32, buf, 0x7efc, 0x00020000);
9650 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
9653 #ifdef CONFIG_X86_64
9654 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
9657 struct kvm_segment seg;
9661 for (i = 0; i < 16; i++)
9662 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i));
9664 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
9665 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
9667 kvm_get_dr(vcpu, 6, &val);
9668 put_smstate(u64, buf, 0x7f68, val);
9669 kvm_get_dr(vcpu, 7, &val);
9670 put_smstate(u64, buf, 0x7f60, val);
9672 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
9673 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
9674 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
9676 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
9679 put_smstate(u32, buf, 0x7efc, 0x00020064);
9681 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
9683 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9684 put_smstate(u16, buf, 0x7e90, seg.selector);
9685 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
9686 put_smstate(u32, buf, 0x7e94, seg.limit);
9687 put_smstate(u64, buf, 0x7e98, seg.base);
9689 static_call(kvm_x86_get_idt)(vcpu, &dt);
9690 put_smstate(u32, buf, 0x7e84, dt.size);
9691 put_smstate(u64, buf, 0x7e88, dt.address);
9693 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9694 put_smstate(u16, buf, 0x7e70, seg.selector);
9695 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
9696 put_smstate(u32, buf, 0x7e74, seg.limit);
9697 put_smstate(u64, buf, 0x7e78, seg.base);
9699 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9700 put_smstate(u32, buf, 0x7e64, dt.size);
9701 put_smstate(u64, buf, 0x7e68, dt.address);
9703 for (i = 0; i < 6; i++)
9704 enter_smm_save_seg_64(vcpu, buf, i);
9708 static void enter_smm(struct kvm_vcpu *vcpu)
9710 struct kvm_segment cs, ds;
9715 memset(buf, 0, 512);
9716 #ifdef CONFIG_X86_64
9717 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9718 enter_smm_save_state_64(vcpu, buf);
9721 enter_smm_save_state_32(vcpu, buf);
9724 * Give enter_smm() a chance to make ISA-specific changes to the vCPU
9725 * state (e.g. leave guest mode) after we've saved the state into the
9726 * SMM state-save area.
9728 static_call(kvm_x86_enter_smm)(vcpu, buf);
9730 kvm_smm_changed(vcpu, true);
9731 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
9733 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
9734 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
9736 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
9738 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
9739 kvm_rip_write(vcpu, 0x8000);
9741 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
9742 static_call(kvm_x86_set_cr0)(vcpu, cr0);
9743 vcpu->arch.cr0 = cr0;
9745 static_call(kvm_x86_set_cr4)(vcpu, 0);
9747 /* Undocumented: IDT limit is set to zero on entry to SMM. */
9748 dt.address = dt.size = 0;
9749 static_call(kvm_x86_set_idt)(vcpu, &dt);
9751 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
9753 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
9754 cs.base = vcpu->arch.smbase;
9759 cs.limit = ds.limit = 0xffffffff;
9760 cs.type = ds.type = 0x3;
9761 cs.dpl = ds.dpl = 0;
9766 cs.avl = ds.avl = 0;
9767 cs.present = ds.present = 1;
9768 cs.unusable = ds.unusable = 0;
9769 cs.padding = ds.padding = 0;
9771 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9772 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
9773 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
9774 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
9775 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
9776 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
9778 #ifdef CONFIG_X86_64
9779 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9780 static_call(kvm_x86_set_efer)(vcpu, 0);
9783 kvm_update_cpuid_runtime(vcpu);
9784 kvm_mmu_reset_context(vcpu);
9787 static void process_smi(struct kvm_vcpu *vcpu)
9789 vcpu->arch.smi_pending = true;
9790 kvm_make_request(KVM_REQ_EVENT, vcpu);
9793 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
9794 unsigned long *vcpu_bitmap)
9796 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
9799 void kvm_make_scan_ioapic_request(struct kvm *kvm)
9801 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
9804 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
9808 if (!lapic_in_kernel(vcpu))
9811 down_read(&vcpu->kvm->arch.apicv_update_lock);
9813 activate = kvm_vcpu_apicv_activated(vcpu);
9815 if (vcpu->arch.apicv_active == activate)
9818 vcpu->arch.apicv_active = activate;
9819 kvm_apic_update_apicv(vcpu);
9820 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
9823 * When APICv gets disabled, we may still have injected interrupts
9824 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
9825 * still active when the interrupt got accepted. Make sure
9826 * inject_pending_event() is called to check for that.
9828 if (!vcpu->arch.apicv_active)
9829 kvm_make_request(KVM_REQ_EVENT, vcpu);
9832 up_read(&vcpu->kvm->arch.apicv_update_lock);
9834 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
9836 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
9837 enum kvm_apicv_inhibit reason, bool set)
9839 unsigned long old, new;
9841 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
9843 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason))
9846 old = new = kvm->arch.apicv_inhibit_reasons;
9848 set_or_clear_apicv_inhibit(&new, reason, set);
9850 if (!!old != !!new) {
9852 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
9853 * false positives in the sanity check WARN in svm_vcpu_run().
9854 * This task will wait for all vCPUs to ack the kick IRQ before
9855 * updating apicv_inhibit_reasons, and all other vCPUs will
9856 * block on acquiring apicv_update_lock so that vCPUs can't
9857 * redo svm_vcpu_run() without seeing the new inhibit state.
9859 * Note, holding apicv_update_lock and taking it in the read
9860 * side (handling the request) also prevents other vCPUs from
9861 * servicing the request with a stale apicv_inhibit_reasons.
9863 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
9864 kvm->arch.apicv_inhibit_reasons = new;
9866 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
9867 kvm_zap_gfn_range(kvm, gfn, gfn+1);
9870 kvm->arch.apicv_inhibit_reasons = new;
9874 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
9875 enum kvm_apicv_inhibit reason, bool set)
9880 down_write(&kvm->arch.apicv_update_lock);
9881 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
9882 up_write(&kvm->arch.apicv_update_lock);
9884 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
9886 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
9888 if (!kvm_apic_present(vcpu))
9891 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
9893 if (irqchip_split(vcpu->kvm))
9894 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
9896 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
9897 if (ioapic_in_kernel(vcpu->kvm))
9898 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
9901 if (is_guest_mode(vcpu))
9902 vcpu->arch.load_eoi_exitmap_pending = true;
9904 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
9907 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
9909 u64 eoi_exit_bitmap[4];
9911 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
9914 if (to_hv_vcpu(vcpu)) {
9915 bitmap_or((ulong *)eoi_exit_bitmap,
9916 vcpu->arch.ioapic_handled_vectors,
9917 to_hv_synic(vcpu)->vec_bitmap, 256);
9918 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
9922 static_call_cond(kvm_x86_load_eoi_exitmap)(
9923 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
9926 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
9927 unsigned long start, unsigned long end)
9929 unsigned long apic_address;
9932 * The physical address of apic access page is stored in the VMCS.
9933 * Update it when it becomes invalid.
9935 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
9936 if (start <= apic_address && apic_address < end)
9937 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
9940 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
9942 if (!lapic_in_kernel(vcpu))
9945 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
9948 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
9950 smp_send_reschedule(vcpu->cpu);
9952 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
9955 * Called within kvm->srcu read side.
9956 * Returns 1 to let vcpu_run() continue the guest execution loop without
9957 * exiting to the userspace. Otherwise, the value will be returned to the
9960 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
9964 dm_request_for_irq_injection(vcpu) &&
9965 kvm_cpu_accept_dm_intr(vcpu);
9966 fastpath_t exit_fastpath;
9968 bool req_immediate_exit = false;
9970 /* Forbid vmenter if vcpu dirty ring is soft-full */
9971 if (unlikely(vcpu->kvm->dirty_ring_size &&
9972 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
9973 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
9974 trace_kvm_dirty_ring_exit(vcpu);
9979 if (kvm_request_pending(vcpu)) {
9980 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
9984 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
9985 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
9990 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
9991 kvm_mmu_free_obsolete_roots(vcpu);
9992 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
9993 __kvm_migrate_timers(vcpu);
9994 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
9995 kvm_update_masterclock(vcpu->kvm);
9996 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
9997 kvm_gen_kvmclock_update(vcpu);
9998 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
9999 r = kvm_guest_time_update(vcpu);
10003 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10004 kvm_mmu_sync_roots(vcpu);
10005 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10006 kvm_mmu_load_pgd(vcpu);
10007 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
10008 kvm_vcpu_flush_tlb_all(vcpu);
10010 /* Flushing all ASIDs flushes the current ASID... */
10011 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
10013 kvm_service_local_tlb_flush_requests(vcpu);
10015 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10016 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10020 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10021 if (is_guest_mode(vcpu)) {
10022 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10024 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10025 vcpu->mmio_needed = 0;
10030 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10031 /* Page is swapped out. Do synthetic halt */
10032 vcpu->arch.apf.halted = true;
10036 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10037 record_steal_time(vcpu);
10038 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10040 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10042 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10043 kvm_pmu_handle_event(vcpu);
10044 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10045 kvm_pmu_deliver_pmi(vcpu);
10046 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10047 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10048 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10049 vcpu->arch.ioapic_handled_vectors)) {
10050 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10051 vcpu->run->eoi.vector =
10052 vcpu->arch.pending_ioapic_eoi;
10057 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10058 vcpu_scan_ioapic(vcpu);
10059 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10060 vcpu_load_eoi_exitmap(vcpu);
10061 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10062 kvm_vcpu_reload_apic_access_page(vcpu);
10063 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10064 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10065 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10069 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10070 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10071 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10075 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10076 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10078 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10079 vcpu->run->hyperv = hv_vcpu->exit;
10085 * KVM_REQ_HV_STIMER has to be processed after
10086 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10087 * depend on the guest clock being up-to-date
10089 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10090 kvm_hv_process_stimers(vcpu);
10091 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10092 kvm_vcpu_update_apicv(vcpu);
10093 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10094 kvm_check_async_pf_completion(vcpu);
10095 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10096 static_call(kvm_x86_msr_filter_changed)(vcpu);
10098 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10099 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10102 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10103 kvm_xen_has_interrupt(vcpu)) {
10104 ++vcpu->stat.req_event;
10105 r = kvm_apic_accept_events(vcpu);
10110 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10115 r = inject_pending_event(vcpu, &req_immediate_exit);
10121 static_call(kvm_x86_enable_irq_window)(vcpu);
10123 if (kvm_lapic_enabled(vcpu)) {
10124 update_cr8_intercept(vcpu);
10125 kvm_lapic_sync_to_vapic(vcpu);
10129 r = kvm_mmu_reload(vcpu);
10131 goto cancel_injection;
10136 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10139 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10140 * IPI are then delayed after guest entry, which ensures that they
10141 * result in virtual interrupt delivery.
10143 local_irq_disable();
10145 /* Store vcpu->apicv_active before vcpu->mode. */
10146 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10148 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
10151 * 1) We should set ->mode before checking ->requests. Please see
10152 * the comment in kvm_vcpu_exiting_guest_mode().
10154 * 2) For APICv, we should set ->mode before checking PID.ON. This
10155 * pairs with the memory barrier implicit in pi_test_and_set_on
10156 * (see vmx_deliver_posted_interrupt).
10158 * 3) This also orders the write to mode from any reads to the page
10159 * tables done while the VCPU is running. Please see the comment
10160 * in kvm_flush_remote_tlbs.
10162 smp_mb__after_srcu_read_unlock();
10165 * Process pending posted interrupts to handle the case where the
10166 * notification IRQ arrived in the host, or was never sent (because the
10167 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10168 * status, KVM doesn't update assigned devices when APICv is inhibited,
10169 * i.e. they can post interrupts even if APICv is temporarily disabled.
10171 if (kvm_lapic_enabled(vcpu))
10172 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10174 if (kvm_vcpu_exit_request(vcpu)) {
10175 vcpu->mode = OUTSIDE_GUEST_MODE;
10177 local_irq_enable();
10179 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10181 goto cancel_injection;
10184 if (req_immediate_exit) {
10185 kvm_make_request(KVM_REQ_EVENT, vcpu);
10186 static_call(kvm_x86_request_immediate_exit)(vcpu);
10189 fpregs_assert_state_consistent();
10190 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10191 switch_fpu_return();
10193 if (vcpu->arch.guest_fpu.xfd_err)
10194 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10196 if (unlikely(vcpu->arch.switch_db_regs)) {
10197 set_debugreg(0, 7);
10198 set_debugreg(vcpu->arch.eff_db[0], 0);
10199 set_debugreg(vcpu->arch.eff_db[1], 1);
10200 set_debugreg(vcpu->arch.eff_db[2], 2);
10201 set_debugreg(vcpu->arch.eff_db[3], 3);
10202 } else if (unlikely(hw_breakpoint_active())) {
10203 set_debugreg(0, 7);
10206 guest_timing_enter_irqoff();
10210 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10211 * update must kick and wait for all vCPUs before toggling the
10212 * per-VM state, and responsing vCPUs must wait for the update
10213 * to complete before servicing KVM_REQ_APICV_UPDATE.
10215 WARN_ON_ONCE(kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu));
10217 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10218 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10221 if (kvm_lapic_enabled(vcpu))
10222 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10224 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10225 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10231 * Do this here before restoring debug registers on the host. And
10232 * since we do this before handling the vmexit, a DR access vmexit
10233 * can (a) read the correct value of the debug registers, (b) set
10234 * KVM_DEBUGREG_WONT_EXIT again.
10236 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10237 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10238 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10239 kvm_update_dr0123(vcpu);
10240 kvm_update_dr7(vcpu);
10244 * If the guest has used debug registers, at least dr7
10245 * will be disabled while returning to the host.
10246 * If we don't have active breakpoints in the host, we don't
10247 * care about the messed up debug address registers. But if
10248 * we have some of them active, restore the old state.
10250 if (hw_breakpoint_active())
10251 hw_breakpoint_restore();
10253 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10254 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10256 vcpu->mode = OUTSIDE_GUEST_MODE;
10260 * Sync xfd before calling handle_exit_irqoff() which may
10261 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10262 * in #NM irqoff handler).
10264 if (vcpu->arch.xfd_no_write_intercept)
10265 fpu_sync_guest_vmexit_xfd_state();
10267 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10269 if (vcpu->arch.guest_fpu.xfd_err)
10270 wrmsrl(MSR_IA32_XFD_ERR, 0);
10273 * Consume any pending interrupts, including the possible source of
10274 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10275 * An instruction is required after local_irq_enable() to fully unblock
10276 * interrupts on processors that implement an interrupt shadow, the
10277 * stat.exits increment will do nicely.
10279 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10280 local_irq_enable();
10281 ++vcpu->stat.exits;
10282 local_irq_disable();
10283 kvm_after_interrupt(vcpu);
10286 * Wait until after servicing IRQs to account guest time so that any
10287 * ticks that occurred while running the guest are properly accounted
10288 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10289 * of accounting via context tracking, but the loss of accuracy is
10290 * acceptable for all known use cases.
10292 guest_timing_exit_irqoff();
10294 if (lapic_in_kernel(vcpu)) {
10295 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
10296 if (delta != S64_MIN) {
10297 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
10298 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
10302 local_irq_enable();
10305 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10308 * Profile KVM exit RIPs:
10310 if (unlikely(prof_on == KVM_PROFILING)) {
10311 unsigned long rip = kvm_rip_read(vcpu);
10312 profile_hit(KVM_PROFILING, (void *)rip);
10315 if (unlikely(vcpu->arch.tsc_always_catchup))
10316 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10318 if (vcpu->arch.apic_attention)
10319 kvm_lapic_sync_from_vapic(vcpu);
10321 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10325 if (req_immediate_exit)
10326 kvm_make_request(KVM_REQ_EVENT, vcpu);
10327 static_call(kvm_x86_cancel_injection)(vcpu);
10328 if (unlikely(vcpu->arch.apic_attention))
10329 kvm_lapic_sync_from_vapic(vcpu);
10334 /* Called within kvm->srcu read side. */
10335 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
10339 if (!kvm_arch_vcpu_runnable(vcpu)) {
10341 * Switch to the software timer before halt-polling/blocking as
10342 * the guest's timer may be a break event for the vCPU, and the
10343 * hypervisor timer runs only when the CPU is in guest mode.
10344 * Switch before halt-polling so that KVM recognizes an expired
10345 * timer before blocking.
10347 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10349 kvm_lapic_switch_to_sw_timer(vcpu);
10351 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10352 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10353 kvm_vcpu_halt(vcpu);
10355 kvm_vcpu_block(vcpu);
10356 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10359 kvm_lapic_switch_to_hv_timer(vcpu);
10361 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
10365 if (kvm_apic_accept_events(vcpu) < 0)
10367 switch(vcpu->arch.mp_state) {
10368 case KVM_MP_STATE_HALTED:
10369 case KVM_MP_STATE_AP_RESET_HOLD:
10370 vcpu->arch.pv.pv_unhalted = false;
10371 vcpu->arch.mp_state =
10372 KVM_MP_STATE_RUNNABLE;
10374 case KVM_MP_STATE_RUNNABLE:
10375 vcpu->arch.apf.halted = false;
10377 case KVM_MP_STATE_INIT_RECEIVED:
10385 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10387 if (is_guest_mode(vcpu))
10388 kvm_check_nested_events(vcpu);
10390 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10391 !vcpu->arch.apf.halted);
10394 /* Called within kvm->srcu read side. */
10395 static int vcpu_run(struct kvm_vcpu *vcpu)
10398 struct kvm *kvm = vcpu->kvm;
10400 vcpu->arch.l1tf_flush_l1d = true;
10403 if (kvm_vcpu_running(vcpu)) {
10404 r = vcpu_enter_guest(vcpu);
10406 r = vcpu_block(kvm, vcpu);
10412 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10413 if (kvm_xen_has_pending_events(vcpu))
10414 kvm_xen_inject_pending_events(vcpu);
10416 if (kvm_cpu_has_pending_timer(vcpu))
10417 kvm_inject_pending_timer_irqs(vcpu);
10419 if (dm_request_for_irq_injection(vcpu) &&
10420 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10422 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10423 ++vcpu->stat.request_irq_exits;
10427 if (__xfer_to_guest_mode_work_pending()) {
10428 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10429 r = xfer_to_guest_mode_handle_work(vcpu);
10430 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10439 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10443 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10444 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10445 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
10449 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10451 BUG_ON(!vcpu->arch.pio.count);
10453 return complete_emulated_io(vcpu);
10457 * Implements the following, as a state machine:
10460 * for each fragment
10461 * for each mmio piece in the fragment
10468 * for each fragment
10469 * for each mmio piece in the fragment
10474 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10476 struct kvm_run *run = vcpu->run;
10477 struct kvm_mmio_fragment *frag;
10480 BUG_ON(!vcpu->mmio_needed);
10482 /* Complete previous fragment */
10483 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10484 len = min(8u, frag->len);
10485 if (!vcpu->mmio_is_write)
10486 memcpy(frag->data, run->mmio.data, len);
10488 if (frag->len <= 8) {
10489 /* Switch to the next fragment. */
10491 vcpu->mmio_cur_fragment++;
10493 /* Go forward to the next mmio piece. */
10499 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10500 vcpu->mmio_needed = 0;
10502 /* FIXME: return into emulator if single-stepping. */
10503 if (vcpu->mmio_is_write)
10505 vcpu->mmio_read_completed = 1;
10506 return complete_emulated_io(vcpu);
10509 run->exit_reason = KVM_EXIT_MMIO;
10510 run->mmio.phys_addr = frag->gpa;
10511 if (vcpu->mmio_is_write)
10512 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10513 run->mmio.len = min(8u, frag->len);
10514 run->mmio.is_write = vcpu->mmio_is_write;
10515 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10519 /* Swap (qemu) user FPU context for the guest FPU context. */
10520 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10522 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10523 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10527 /* When vcpu_run ends, restore user space FPU context. */
10528 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10530 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10531 ++vcpu->stat.fpu_reload;
10535 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10537 struct kvm_run *kvm_run = vcpu->run;
10538 struct kvm *kvm = vcpu->kvm;
10542 kvm_sigset_activate(vcpu);
10543 kvm_run->flags = 0;
10544 kvm_load_guest_fpu(vcpu);
10546 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10547 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
10548 if (kvm_run->immediate_exit) {
10553 * It should be impossible for the hypervisor timer to be in
10554 * use before KVM has ever run the vCPU.
10556 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
10558 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10559 kvm_vcpu_block(vcpu);
10560 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10562 if (kvm_apic_accept_events(vcpu) < 0) {
10566 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
10568 if (signal_pending(current)) {
10570 kvm_run->exit_reason = KVM_EXIT_INTR;
10571 ++vcpu->stat.signal_exits;
10576 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
10577 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
10582 if (kvm_run->kvm_dirty_regs) {
10583 r = sync_regs(vcpu);
10588 /* re-sync apic's tpr */
10589 if (!lapic_in_kernel(vcpu)) {
10590 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
10596 if (unlikely(vcpu->arch.complete_userspace_io)) {
10597 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
10598 vcpu->arch.complete_userspace_io = NULL;
10603 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
10605 if (kvm_run->immediate_exit) {
10610 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
10614 r = vcpu_run(vcpu);
10617 kvm_put_guest_fpu(vcpu);
10618 if (kvm_run->kvm_valid_regs)
10620 post_kvm_run_save(vcpu);
10621 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10623 kvm_sigset_deactivate(vcpu);
10628 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10630 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
10632 * We are here if userspace calls get_regs() in the middle of
10633 * instruction emulation. Registers state needs to be copied
10634 * back from emulation context to vcpu. Userspace shouldn't do
10635 * that usually, but some bad designed PV devices (vmware
10636 * backdoor interface) need this to work
10638 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
10639 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10641 regs->rax = kvm_rax_read(vcpu);
10642 regs->rbx = kvm_rbx_read(vcpu);
10643 regs->rcx = kvm_rcx_read(vcpu);
10644 regs->rdx = kvm_rdx_read(vcpu);
10645 regs->rsi = kvm_rsi_read(vcpu);
10646 regs->rdi = kvm_rdi_read(vcpu);
10647 regs->rsp = kvm_rsp_read(vcpu);
10648 regs->rbp = kvm_rbp_read(vcpu);
10649 #ifdef CONFIG_X86_64
10650 regs->r8 = kvm_r8_read(vcpu);
10651 regs->r9 = kvm_r9_read(vcpu);
10652 regs->r10 = kvm_r10_read(vcpu);
10653 regs->r11 = kvm_r11_read(vcpu);
10654 regs->r12 = kvm_r12_read(vcpu);
10655 regs->r13 = kvm_r13_read(vcpu);
10656 regs->r14 = kvm_r14_read(vcpu);
10657 regs->r15 = kvm_r15_read(vcpu);
10660 regs->rip = kvm_rip_read(vcpu);
10661 regs->rflags = kvm_get_rflags(vcpu);
10664 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10667 __get_regs(vcpu, regs);
10672 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10674 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
10675 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10677 kvm_rax_write(vcpu, regs->rax);
10678 kvm_rbx_write(vcpu, regs->rbx);
10679 kvm_rcx_write(vcpu, regs->rcx);
10680 kvm_rdx_write(vcpu, regs->rdx);
10681 kvm_rsi_write(vcpu, regs->rsi);
10682 kvm_rdi_write(vcpu, regs->rdi);
10683 kvm_rsp_write(vcpu, regs->rsp);
10684 kvm_rbp_write(vcpu, regs->rbp);
10685 #ifdef CONFIG_X86_64
10686 kvm_r8_write(vcpu, regs->r8);
10687 kvm_r9_write(vcpu, regs->r9);
10688 kvm_r10_write(vcpu, regs->r10);
10689 kvm_r11_write(vcpu, regs->r11);
10690 kvm_r12_write(vcpu, regs->r12);
10691 kvm_r13_write(vcpu, regs->r13);
10692 kvm_r14_write(vcpu, regs->r14);
10693 kvm_r15_write(vcpu, regs->r15);
10696 kvm_rip_write(vcpu, regs->rip);
10697 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
10699 vcpu->arch.exception.pending = false;
10701 kvm_make_request(KVM_REQ_EVENT, vcpu);
10704 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10707 __set_regs(vcpu, regs);
10712 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10714 struct desc_ptr dt;
10716 if (vcpu->arch.guest_state_protected)
10717 goto skip_protected_regs;
10719 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10720 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10721 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10722 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10723 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10724 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10726 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10727 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10729 static_call(kvm_x86_get_idt)(vcpu, &dt);
10730 sregs->idt.limit = dt.size;
10731 sregs->idt.base = dt.address;
10732 static_call(kvm_x86_get_gdt)(vcpu, &dt);
10733 sregs->gdt.limit = dt.size;
10734 sregs->gdt.base = dt.address;
10736 sregs->cr2 = vcpu->arch.cr2;
10737 sregs->cr3 = kvm_read_cr3(vcpu);
10739 skip_protected_regs:
10740 sregs->cr0 = kvm_read_cr0(vcpu);
10741 sregs->cr4 = kvm_read_cr4(vcpu);
10742 sregs->cr8 = kvm_get_cr8(vcpu);
10743 sregs->efer = vcpu->arch.efer;
10744 sregs->apic_base = kvm_get_apic_base(vcpu);
10747 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10749 __get_sregs_common(vcpu, sregs);
10751 if (vcpu->arch.guest_state_protected)
10754 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
10755 set_bit(vcpu->arch.interrupt.nr,
10756 (unsigned long *)sregs->interrupt_bitmap);
10759 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
10763 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
10765 if (vcpu->arch.guest_state_protected)
10768 if (is_pae_paging(vcpu)) {
10769 for (i = 0 ; i < 4 ; i++)
10770 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
10771 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
10775 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
10776 struct kvm_sregs *sregs)
10779 __get_sregs(vcpu, sregs);
10784 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
10785 struct kvm_mp_state *mp_state)
10790 if (kvm_mpx_supported())
10791 kvm_load_guest_fpu(vcpu);
10793 r = kvm_apic_accept_events(vcpu);
10798 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
10799 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
10800 vcpu->arch.pv.pv_unhalted)
10801 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
10803 mp_state->mp_state = vcpu->arch.mp_state;
10806 if (kvm_mpx_supported())
10807 kvm_put_guest_fpu(vcpu);
10812 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
10813 struct kvm_mp_state *mp_state)
10819 if (!lapic_in_kernel(vcpu) &&
10820 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
10824 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
10825 * INIT state; latched init should be reported using
10826 * KVM_SET_VCPU_EVENTS, so reject it here.
10828 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
10829 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
10830 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
10833 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
10834 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
10835 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
10837 vcpu->arch.mp_state = mp_state->mp_state;
10838 kvm_make_request(KVM_REQ_EVENT, vcpu);
10846 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
10847 int reason, bool has_error_code, u32 error_code)
10849 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
10852 init_emulate_ctxt(vcpu);
10854 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
10855 has_error_code, error_code);
10857 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10858 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
10859 vcpu->run->internal.ndata = 0;
10863 kvm_rip_write(vcpu, ctxt->eip);
10864 kvm_set_rflags(vcpu, ctxt->eflags);
10867 EXPORT_SYMBOL_GPL(kvm_task_switch);
10869 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10871 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
10873 * When EFER.LME and CR0.PG are set, the processor is in
10874 * 64-bit mode (though maybe in a 32-bit code segment).
10875 * CR4.PAE and EFER.LMA must be set.
10877 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
10879 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
10883 * Not in 64-bit mode: EFER.LMA is clear and the code
10884 * segment cannot be 64-bit.
10886 if (sregs->efer & EFER_LMA || sregs->cs.l)
10890 return kvm_is_valid_cr4(vcpu, sregs->cr4);
10893 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
10894 int *mmu_reset_needed, bool update_pdptrs)
10896 struct msr_data apic_base_msr;
10898 struct desc_ptr dt;
10900 if (!kvm_is_valid_sregs(vcpu, sregs))
10903 apic_base_msr.data = sregs->apic_base;
10904 apic_base_msr.host_initiated = true;
10905 if (kvm_set_apic_base(vcpu, &apic_base_msr))
10908 if (vcpu->arch.guest_state_protected)
10911 dt.size = sregs->idt.limit;
10912 dt.address = sregs->idt.base;
10913 static_call(kvm_x86_set_idt)(vcpu, &dt);
10914 dt.size = sregs->gdt.limit;
10915 dt.address = sregs->gdt.base;
10916 static_call(kvm_x86_set_gdt)(vcpu, &dt);
10918 vcpu->arch.cr2 = sregs->cr2;
10919 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
10920 vcpu->arch.cr3 = sregs->cr3;
10921 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
10922 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
10924 kvm_set_cr8(vcpu, sregs->cr8);
10926 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
10927 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
10929 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
10930 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
10931 vcpu->arch.cr0 = sregs->cr0;
10933 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
10934 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
10936 if (update_pdptrs) {
10937 idx = srcu_read_lock(&vcpu->kvm->srcu);
10938 if (is_pae_paging(vcpu)) {
10939 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
10940 *mmu_reset_needed = 1;
10942 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10945 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10946 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10947 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10948 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10949 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10950 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10952 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10953 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10955 update_cr8_intercept(vcpu);
10957 /* Older userspace won't unhalt the vcpu on reset. */
10958 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
10959 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
10960 !is_protmode(vcpu))
10961 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10966 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10968 int pending_vec, max_bits;
10969 int mmu_reset_needed = 0;
10970 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
10975 if (mmu_reset_needed)
10976 kvm_mmu_reset_context(vcpu);
10978 max_bits = KVM_NR_INTERRUPTS;
10979 pending_vec = find_first_bit(
10980 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
10982 if (pending_vec < max_bits) {
10983 kvm_queue_interrupt(vcpu, pending_vec, false);
10984 pr_debug("Set back pending irq %d\n", pending_vec);
10985 kvm_make_request(KVM_REQ_EVENT, vcpu);
10990 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
10992 int mmu_reset_needed = 0;
10993 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
10994 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
10995 !(sregs2->efer & EFER_LMA);
10998 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11001 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11004 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11005 &mmu_reset_needed, !valid_pdptrs);
11009 if (valid_pdptrs) {
11010 for (i = 0; i < 4 ; i++)
11011 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11013 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11014 mmu_reset_needed = 1;
11015 vcpu->arch.pdptrs_from_userspace = true;
11017 if (mmu_reset_needed)
11018 kvm_mmu_reset_context(vcpu);
11022 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11023 struct kvm_sregs *sregs)
11028 ret = __set_sregs(vcpu, sregs);
11033 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11036 struct kvm_vcpu *vcpu;
11039 down_write(&kvm->arch.apicv_update_lock);
11041 kvm_for_each_vcpu(i, vcpu, kvm) {
11042 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11047 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11048 up_write(&kvm->arch.apicv_update_lock);
11051 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11052 struct kvm_guest_debug *dbg)
11054 unsigned long rflags;
11057 if (vcpu->arch.guest_state_protected)
11062 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11064 if (vcpu->arch.exception.pending)
11066 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11067 kvm_queue_exception(vcpu, DB_VECTOR);
11069 kvm_queue_exception(vcpu, BP_VECTOR);
11073 * Read rflags as long as potentially injected trace flags are still
11076 rflags = kvm_get_rflags(vcpu);
11078 vcpu->guest_debug = dbg->control;
11079 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11080 vcpu->guest_debug = 0;
11082 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11083 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11084 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11085 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11087 for (i = 0; i < KVM_NR_DB_REGS; i++)
11088 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11090 kvm_update_dr7(vcpu);
11092 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11093 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11096 * Trigger an rflags update that will inject or remove the trace
11099 kvm_set_rflags(vcpu, rflags);
11101 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11103 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11113 * Translate a guest virtual address to a guest physical address.
11115 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11116 struct kvm_translation *tr)
11118 unsigned long vaddr = tr->linear_address;
11124 idx = srcu_read_lock(&vcpu->kvm->srcu);
11125 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11126 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11127 tr->physical_address = gpa;
11128 tr->valid = gpa != UNMAPPED_GVA;
11136 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11138 struct fxregs_state *fxsave;
11140 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11145 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11146 memcpy(fpu->fpr, fxsave->st_space, 128);
11147 fpu->fcw = fxsave->cwd;
11148 fpu->fsw = fxsave->swd;
11149 fpu->ftwx = fxsave->twd;
11150 fpu->last_opcode = fxsave->fop;
11151 fpu->last_ip = fxsave->rip;
11152 fpu->last_dp = fxsave->rdp;
11153 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11159 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11161 struct fxregs_state *fxsave;
11163 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11168 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11170 memcpy(fxsave->st_space, fpu->fpr, 128);
11171 fxsave->cwd = fpu->fcw;
11172 fxsave->swd = fpu->fsw;
11173 fxsave->twd = fpu->ftwx;
11174 fxsave->fop = fpu->last_opcode;
11175 fxsave->rip = fpu->last_ip;
11176 fxsave->rdp = fpu->last_dp;
11177 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11183 static void store_regs(struct kvm_vcpu *vcpu)
11185 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11187 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11188 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11190 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11191 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11193 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11194 kvm_vcpu_ioctl_x86_get_vcpu_events(
11195 vcpu, &vcpu->run->s.regs.events);
11198 static int sync_regs(struct kvm_vcpu *vcpu)
11200 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11201 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11202 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11204 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11205 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11207 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11209 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11210 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11211 vcpu, &vcpu->run->s.regs.events))
11213 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11219 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11221 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
11222 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
11223 "guest TSC will not be reliable\n");
11228 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11233 vcpu->arch.last_vmentry_cpu = -1;
11234 vcpu->arch.regs_avail = ~0;
11235 vcpu->arch.regs_dirty = ~0;
11237 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11238 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11240 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11242 r = kvm_mmu_create(vcpu);
11246 if (irqchip_in_kernel(vcpu->kvm)) {
11247 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11249 goto fail_mmu_destroy;
11250 if (kvm_apicv_activated(vcpu->kvm))
11251 vcpu->arch.apicv_active = true;
11253 static_branch_inc(&kvm_has_noapic_vcpu);
11257 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11259 goto fail_free_lapic;
11260 vcpu->arch.pio_data = page_address(page);
11262 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
11263 GFP_KERNEL_ACCOUNT);
11264 if (!vcpu->arch.mce_banks)
11265 goto fail_free_pio_data;
11266 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11268 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11269 GFP_KERNEL_ACCOUNT))
11270 goto fail_free_mce_banks;
11272 if (!alloc_emulate_ctxt(vcpu))
11273 goto free_wbinvd_dirty_mask;
11275 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11276 pr_err("kvm: failed to allocate vcpu's fpu\n");
11277 goto free_emulate_ctxt;
11280 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11281 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11283 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11285 kvm_async_pf_hash_reset(vcpu);
11286 kvm_pmu_init(vcpu);
11288 vcpu->arch.pending_external_vector = -1;
11289 vcpu->arch.preempted_in_kernel = false;
11291 #if IS_ENABLED(CONFIG_HYPERV)
11292 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11295 r = static_call(kvm_x86_vcpu_create)(vcpu);
11297 goto free_guest_fpu;
11299 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11300 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11301 kvm_xen_init_vcpu(vcpu);
11302 kvm_vcpu_mtrr_init(vcpu);
11304 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11305 kvm_vcpu_reset(vcpu, false);
11306 kvm_init_mmu(vcpu);
11311 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11313 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11314 free_wbinvd_dirty_mask:
11315 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11316 fail_free_mce_banks:
11317 kfree(vcpu->arch.mce_banks);
11318 fail_free_pio_data:
11319 free_page((unsigned long)vcpu->arch.pio_data);
11321 kvm_free_lapic(vcpu);
11323 kvm_mmu_destroy(vcpu);
11327 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11329 struct kvm *kvm = vcpu->kvm;
11331 if (mutex_lock_killable(&vcpu->mutex))
11334 kvm_synchronize_tsc(vcpu, 0);
11337 /* poll control enabled by default */
11338 vcpu->arch.msr_kvm_poll_control = 1;
11340 mutex_unlock(&vcpu->mutex);
11342 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11343 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11344 KVMCLOCK_SYNC_PERIOD);
11347 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11351 kvmclock_reset(vcpu);
11353 static_call(kvm_x86_vcpu_free)(vcpu);
11355 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11356 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11357 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11359 kvm_xen_destroy_vcpu(vcpu);
11360 kvm_hv_vcpu_uninit(vcpu);
11361 kvm_pmu_destroy(vcpu);
11362 kfree(vcpu->arch.mce_banks);
11363 kvm_free_lapic(vcpu);
11364 idx = srcu_read_lock(&vcpu->kvm->srcu);
11365 kvm_mmu_destroy(vcpu);
11366 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11367 free_page((unsigned long)vcpu->arch.pio_data);
11368 kvfree(vcpu->arch.cpuid_entries);
11369 if (!lapic_in_kernel(vcpu))
11370 static_branch_dec(&kvm_has_noapic_vcpu);
11373 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11375 struct kvm_cpuid_entry2 *cpuid_0x1;
11376 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11377 unsigned long new_cr0;
11380 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11381 * to handle side effects. RESET emulation hits those flows and relies
11382 * on emulated/virtualized registers, including those that are loaded
11383 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11384 * to detect improper or missing initialization.
11386 WARN_ON_ONCE(!init_event &&
11387 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11389 kvm_lapic_reset(vcpu, init_event);
11391 vcpu->arch.hflags = 0;
11393 vcpu->arch.smi_pending = 0;
11394 vcpu->arch.smi_count = 0;
11395 atomic_set(&vcpu->arch.nmi_queued, 0);
11396 vcpu->arch.nmi_pending = 0;
11397 vcpu->arch.nmi_injected = false;
11398 kvm_clear_interrupt_queue(vcpu);
11399 kvm_clear_exception_queue(vcpu);
11401 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11402 kvm_update_dr0123(vcpu);
11403 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11404 vcpu->arch.dr7 = DR7_FIXED_1;
11405 kvm_update_dr7(vcpu);
11407 vcpu->arch.cr2 = 0;
11409 kvm_make_request(KVM_REQ_EVENT, vcpu);
11410 vcpu->arch.apf.msr_en_val = 0;
11411 vcpu->arch.apf.msr_int_val = 0;
11412 vcpu->arch.st.msr_val = 0;
11414 kvmclock_reset(vcpu);
11416 kvm_clear_async_pf_completion_queue(vcpu);
11417 kvm_async_pf_hash_reset(vcpu);
11418 vcpu->arch.apf.halted = false;
11420 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11421 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11424 * To avoid have the INIT path from kvm_apic_has_events() that be
11425 * called with loaded FPU and does not let userspace fix the state.
11428 kvm_put_guest_fpu(vcpu);
11430 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11431 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11434 kvm_load_guest_fpu(vcpu);
11438 kvm_pmu_reset(vcpu);
11439 vcpu->arch.smbase = 0x30000;
11441 vcpu->arch.msr_misc_features_enables = 0;
11443 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11444 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11447 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11448 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11449 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11452 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11453 * if no CPUID match is found. Note, it's impossible to get a match at
11454 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11455 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11456 * on RESET. But, go through the motions in case that's ever remedied.
11458 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0);
11459 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11461 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11463 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11464 kvm_rip_write(vcpu, 0xfff0);
11466 vcpu->arch.cr3 = 0;
11467 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11470 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
11471 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
11472 * (or qualify) that with a footnote stating that CD/NW are preserved.
11474 new_cr0 = X86_CR0_ET;
11476 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
11478 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
11480 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
11481 static_call(kvm_x86_set_cr4)(vcpu, 0);
11482 static_call(kvm_x86_set_efer)(vcpu, 0);
11483 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11486 * On the standard CR0/CR4/EFER modification paths, there are several
11487 * complex conditions determining whether the MMU has to be reset and/or
11488 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
11489 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
11490 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
11491 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
11493 if (old_cr0 & X86_CR0_PG) {
11494 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11495 kvm_mmu_reset_context(vcpu);
11499 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
11500 * APM states the TLBs are untouched by INIT, but it also states that
11501 * the TLBs are flushed on "External initialization of the processor."
11502 * Flush the guest TLB regardless of vendor, there is no meaningful
11503 * benefit in relying on the guest to flush the TLB immediately after
11504 * INIT. A spurious TLB flush is benign and likely negligible from a
11505 * performance perspective.
11508 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11510 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
11512 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
11514 struct kvm_segment cs;
11516 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
11517 cs.selector = vector << 8;
11518 cs.base = vector << 12;
11519 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
11520 kvm_rip_write(vcpu, 0);
11522 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
11524 int kvm_arch_hardware_enable(void)
11527 struct kvm_vcpu *vcpu;
11532 bool stable, backwards_tsc = false;
11534 kvm_user_return_msr_cpu_online();
11535 ret = static_call(kvm_x86_hardware_enable)();
11539 local_tsc = rdtsc();
11540 stable = !kvm_check_tsc_unstable();
11541 list_for_each_entry(kvm, &vm_list, vm_list) {
11542 kvm_for_each_vcpu(i, vcpu, kvm) {
11543 if (!stable && vcpu->cpu == smp_processor_id())
11544 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11545 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
11546 backwards_tsc = true;
11547 if (vcpu->arch.last_host_tsc > max_tsc)
11548 max_tsc = vcpu->arch.last_host_tsc;
11554 * Sometimes, even reliable TSCs go backwards. This happens on
11555 * platforms that reset TSC during suspend or hibernate actions, but
11556 * maintain synchronization. We must compensate. Fortunately, we can
11557 * detect that condition here, which happens early in CPU bringup,
11558 * before any KVM threads can be running. Unfortunately, we can't
11559 * bring the TSCs fully up to date with real time, as we aren't yet far
11560 * enough into CPU bringup that we know how much real time has actually
11561 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
11562 * variables that haven't been updated yet.
11564 * So we simply find the maximum observed TSC above, then record the
11565 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
11566 * the adjustment will be applied. Note that we accumulate
11567 * adjustments, in case multiple suspend cycles happen before some VCPU
11568 * gets a chance to run again. In the event that no KVM threads get a
11569 * chance to run, we will miss the entire elapsed period, as we'll have
11570 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
11571 * loose cycle time. This isn't too big a deal, since the loss will be
11572 * uniform across all VCPUs (not to mention the scenario is extremely
11573 * unlikely). It is possible that a second hibernate recovery happens
11574 * much faster than a first, causing the observed TSC here to be
11575 * smaller; this would require additional padding adjustment, which is
11576 * why we set last_host_tsc to the local tsc observed here.
11578 * N.B. - this code below runs only on platforms with reliable TSC,
11579 * as that is the only way backwards_tsc is set above. Also note
11580 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
11581 * have the same delta_cyc adjustment applied if backwards_tsc
11582 * is detected. Note further, this adjustment is only done once,
11583 * as we reset last_host_tsc on all VCPUs to stop this from being
11584 * called multiple times (one for each physical CPU bringup).
11586 * Platforms with unreliable TSCs don't have to deal with this, they
11587 * will be compensated by the logic in vcpu_load, which sets the TSC to
11588 * catchup mode. This will catchup all VCPUs to real time, but cannot
11589 * guarantee that they stay in perfect synchronization.
11591 if (backwards_tsc) {
11592 u64 delta_cyc = max_tsc - local_tsc;
11593 list_for_each_entry(kvm, &vm_list, vm_list) {
11594 kvm->arch.backwards_tsc_observed = true;
11595 kvm_for_each_vcpu(i, vcpu, kvm) {
11596 vcpu->arch.tsc_offset_adjustment += delta_cyc;
11597 vcpu->arch.last_host_tsc = local_tsc;
11598 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
11602 * We have to disable TSC offset matching.. if you were
11603 * booting a VM while issuing an S4 host suspend....
11604 * you may have some problem. Solving this issue is
11605 * left as an exercise to the reader.
11607 kvm->arch.last_tsc_nsec = 0;
11608 kvm->arch.last_tsc_write = 0;
11615 void kvm_arch_hardware_disable(void)
11617 static_call(kvm_x86_hardware_disable)();
11618 drop_user_return_notifiers();
11621 int kvm_arch_hardware_setup(void *opaque)
11623 struct kvm_x86_init_ops *ops = opaque;
11626 rdmsrl_safe(MSR_EFER, &host_efer);
11628 if (boot_cpu_has(X86_FEATURE_XSAVES))
11629 rdmsrl(MSR_IA32_XSS, host_xss);
11631 r = ops->hardware_setup();
11635 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
11636 kvm_ops_static_call_update();
11638 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
11640 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
11643 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
11644 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
11645 #undef __kvm_cpu_cap_has
11647 if (kvm_has_tsc_control) {
11649 * Make sure the user can only configure tsc_khz values that
11650 * fit into a signed integer.
11651 * A min value is not calculated because it will always
11652 * be 1 on all machines.
11654 u64 max = min(0x7fffffffULL,
11655 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
11656 kvm_max_guest_tsc_khz = max;
11658 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
11659 kvm_init_msr_list();
11663 void kvm_arch_hardware_unsetup(void)
11665 kvm_unregister_perf_callbacks();
11667 static_call(kvm_x86_hardware_unsetup)();
11670 int kvm_arch_check_processor_compat(void *opaque)
11672 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
11673 struct kvm_x86_init_ops *ops = opaque;
11675 WARN_ON(!irqs_disabled());
11677 if (__cr4_reserved_bits(cpu_has, c) !=
11678 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
11681 return ops->check_processor_compatibility();
11684 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
11686 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
11688 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
11690 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
11692 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
11695 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
11696 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
11698 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
11700 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
11702 vcpu->arch.l1tf_flush_l1d = true;
11703 if (pmu->version && unlikely(pmu->event_count)) {
11704 pmu->need_cleanup = true;
11705 kvm_make_request(KVM_REQ_PMU, vcpu);
11707 static_call(kvm_x86_sched_in)(vcpu, cpu);
11710 void kvm_arch_free_vm(struct kvm *kvm)
11712 kfree(to_kvm_hv(kvm)->hv_pa_pg);
11713 __kvm_arch_free_vm(kvm);
11717 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
11720 unsigned long flags;
11725 ret = kvm_page_track_init(kvm);
11729 ret = kvm_mmu_init_vm(kvm);
11731 goto out_page_track;
11733 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
11734 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
11735 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
11737 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
11738 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
11739 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
11740 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
11741 &kvm->arch.irq_sources_bitmap);
11743 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
11744 mutex_init(&kvm->arch.apic_map_lock);
11745 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
11746 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
11748 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
11749 pvclock_update_vm_gtod_copy(kvm);
11750 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
11752 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
11753 kvm->arch.guest_can_read_msr_platform_info = true;
11754 kvm->arch.enable_pmu = enable_pmu;
11756 #if IS_ENABLED(CONFIG_HYPERV)
11757 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
11758 kvm->arch.hv_root_tdp = INVALID_PAGE;
11761 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
11762 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
11764 kvm_apicv_init(kvm);
11765 kvm_hv_init_vm(kvm);
11766 kvm_xen_init_vm(kvm);
11768 return static_call(kvm_x86_vm_init)(kvm);
11771 kvm_page_track_cleanup(kvm);
11776 int kvm_arch_post_init_vm(struct kvm *kvm)
11778 return kvm_mmu_post_init_vm(kvm);
11781 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
11784 kvm_mmu_unload(vcpu);
11788 static void kvm_free_vcpus(struct kvm *kvm)
11791 struct kvm_vcpu *vcpu;
11794 * Unpin any mmu pages first.
11796 kvm_for_each_vcpu(i, vcpu, kvm) {
11797 kvm_clear_async_pf_completion_queue(vcpu);
11798 kvm_unload_vcpu_mmu(vcpu);
11801 kvm_destroy_vcpus(kvm);
11804 void kvm_arch_sync_events(struct kvm *kvm)
11806 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
11807 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
11812 * __x86_set_memory_region: Setup KVM internal memory slot
11814 * @kvm: the kvm pointer to the VM.
11815 * @id: the slot ID to setup.
11816 * @gpa: the GPA to install the slot (unused when @size == 0).
11817 * @size: the size of the slot. Set to zero to uninstall a slot.
11819 * This function helps to setup a KVM internal memory slot. Specify
11820 * @size > 0 to install a new slot, while @size == 0 to uninstall a
11821 * slot. The return code can be one of the following:
11823 * HVA: on success (uninstall will return a bogus HVA)
11826 * The caller should always use IS_ERR() to check the return value
11827 * before use. Note, the KVM internal memory slots are guaranteed to
11828 * remain valid and unchanged until the VM is destroyed, i.e., the
11829 * GPA->HVA translation will not change. However, the HVA is a user
11830 * address, i.e. its accessibility is not guaranteed, and must be
11831 * accessed via __copy_{to,from}_user().
11833 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
11837 unsigned long hva, old_npages;
11838 struct kvm_memslots *slots = kvm_memslots(kvm);
11839 struct kvm_memory_slot *slot;
11841 /* Called with kvm->slots_lock held. */
11842 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
11843 return ERR_PTR_USR(-EINVAL);
11845 slot = id_to_memslot(slots, id);
11847 if (slot && slot->npages)
11848 return ERR_PTR_USR(-EEXIST);
11851 * MAP_SHARED to prevent internal slot pages from being moved
11854 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
11855 MAP_SHARED | MAP_ANONYMOUS, 0);
11856 if (IS_ERR((void *)hva))
11857 return (void __user *)hva;
11859 if (!slot || !slot->npages)
11862 old_npages = slot->npages;
11863 hva = slot->userspace_addr;
11866 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
11867 struct kvm_userspace_memory_region m;
11869 m.slot = id | (i << 16);
11871 m.guest_phys_addr = gpa;
11872 m.userspace_addr = hva;
11873 m.memory_size = size;
11874 r = __kvm_set_memory_region(kvm, &m);
11876 return ERR_PTR_USR(r);
11880 vm_munmap(hva, old_npages * PAGE_SIZE);
11882 return (void __user *)hva;
11884 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
11886 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
11888 kvm_mmu_pre_destroy_vm(kvm);
11891 void kvm_arch_destroy_vm(struct kvm *kvm)
11893 if (current->mm == kvm->mm) {
11895 * Free memory regions allocated on behalf of userspace,
11896 * unless the the memory map has changed due to process exit
11899 mutex_lock(&kvm->slots_lock);
11900 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
11902 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
11904 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
11905 mutex_unlock(&kvm->slots_lock);
11907 static_call_cond(kvm_x86_vm_destroy)(kvm);
11908 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
11909 kvm_pic_destroy(kvm);
11910 kvm_ioapic_destroy(kvm);
11911 kvm_free_vcpus(kvm);
11912 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
11913 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
11914 kvm_mmu_uninit_vm(kvm);
11915 kvm_page_track_cleanup(kvm);
11916 kvm_xen_destroy_vm(kvm);
11917 kvm_hv_destroy_vm(kvm);
11920 static void memslot_rmap_free(struct kvm_memory_slot *slot)
11924 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
11925 kvfree(slot->arch.rmap[i]);
11926 slot->arch.rmap[i] = NULL;
11930 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
11934 memslot_rmap_free(slot);
11936 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11937 kvfree(slot->arch.lpage_info[i - 1]);
11938 slot->arch.lpage_info[i - 1] = NULL;
11941 kvm_page_track_free_memslot(slot);
11944 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
11946 const int sz = sizeof(*slot->arch.rmap[0]);
11949 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
11951 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
11953 if (slot->arch.rmap[i])
11956 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
11957 if (!slot->arch.rmap[i]) {
11958 memslot_rmap_free(slot);
11966 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
11967 struct kvm_memory_slot *slot)
11969 unsigned long npages = slot->npages;
11973 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
11974 * old arrays will be freed by __kvm_set_memory_region() if installing
11975 * the new memslot is successful.
11977 memset(&slot->arch, 0, sizeof(slot->arch));
11979 if (kvm_memslots_have_rmaps(kvm)) {
11980 r = memslot_rmap_alloc(slot, npages);
11985 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11986 struct kvm_lpage_info *linfo;
11987 unsigned long ugfn;
11991 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
11993 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
11997 slot->arch.lpage_info[i - 1] = linfo;
11999 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12000 linfo[0].disallow_lpage = 1;
12001 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12002 linfo[lpages - 1].disallow_lpage = 1;
12003 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12005 * If the gfn and userspace address are not aligned wrt each
12006 * other, disable large page support for this slot.
12008 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12011 for (j = 0; j < lpages; ++j)
12012 linfo[j].disallow_lpage = 1;
12016 if (kvm_page_track_create_memslot(kvm, slot, npages))
12022 memslot_rmap_free(slot);
12024 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12025 kvfree(slot->arch.lpage_info[i - 1]);
12026 slot->arch.lpage_info[i - 1] = NULL;
12031 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12033 struct kvm_vcpu *vcpu;
12037 * memslots->generation has been incremented.
12038 * mmio generation may have reached its maximum value.
12040 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12042 /* Force re-initialization of steal_time cache */
12043 kvm_for_each_vcpu(i, vcpu, kvm)
12044 kvm_vcpu_kick(vcpu);
12047 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12048 const struct kvm_memory_slot *old,
12049 struct kvm_memory_slot *new,
12050 enum kvm_mr_change change)
12052 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
12053 return kvm_alloc_memslot_metadata(kvm, new);
12055 if (change == KVM_MR_FLAGS_ONLY)
12056 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12057 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12064 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12066 struct kvm_arch *ka = &kvm->arch;
12068 if (!kvm_x86_ops.cpu_dirty_log_size)
12071 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
12072 (!enable && --ka->cpu_dirty_logging_count == 0))
12073 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12075 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
12078 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12079 struct kvm_memory_slot *old,
12080 const struct kvm_memory_slot *new,
12081 enum kvm_mr_change change)
12083 u32 old_flags = old ? old->flags : 0;
12084 u32 new_flags = new ? new->flags : 0;
12085 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12088 * Update CPU dirty logging if dirty logging is being toggled. This
12089 * applies to all operations.
12091 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12092 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12095 * Nothing more to do for RO slots (which can't be dirtied and can't be
12096 * made writable) or CREATE/MOVE/DELETE of a slot.
12098 * For a memslot with dirty logging disabled:
12099 * CREATE: No dirty mappings will already exist.
12100 * MOVE/DELETE: The old mappings will already have been cleaned up by
12101 * kvm_arch_flush_shadow_memslot()
12103 * For a memslot with dirty logging enabled:
12104 * CREATE: No shadow pages exist, thus nothing to write-protect
12105 * and no dirty bits to clear.
12106 * MOVE/DELETE: The old mappings will already have been cleaned up by
12107 * kvm_arch_flush_shadow_memslot().
12109 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12113 * READONLY and non-flags changes were filtered out above, and the only
12114 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12115 * logging isn't being toggled on or off.
12117 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12120 if (!log_dirty_pages) {
12122 * Dirty logging tracks sptes in 4k granularity, meaning that
12123 * large sptes have to be split. If live migration succeeds,
12124 * the guest in the source machine will be destroyed and large
12125 * sptes will be created in the destination. However, if the
12126 * guest continues to run in the source machine (for example if
12127 * live migration fails), small sptes will remain around and
12128 * cause bad performance.
12130 * Scan sptes if dirty logging has been stopped, dropping those
12131 * which can be collapsed into a single large-page spte. Later
12132 * page faults will create the large-page sptes.
12134 kvm_mmu_zap_collapsible_sptes(kvm, new);
12137 * Initially-all-set does not require write protecting any page,
12138 * because they're all assumed to be dirty.
12140 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12143 if (READ_ONCE(eager_page_split))
12144 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12146 if (kvm_x86_ops.cpu_dirty_log_size) {
12147 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12148 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12150 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12155 void kvm_arch_commit_memory_region(struct kvm *kvm,
12156 struct kvm_memory_slot *old,
12157 const struct kvm_memory_slot *new,
12158 enum kvm_mr_change change)
12160 if (!kvm->arch.n_requested_mmu_pages &&
12161 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12162 unsigned long nr_mmu_pages;
12164 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12165 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12166 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12169 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12171 /* Free the arrays associated with the old memslot. */
12172 if (change == KVM_MR_MOVE)
12173 kvm_arch_free_memslot(kvm, old);
12176 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12178 kvm_mmu_zap_all(kvm);
12181 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12182 struct kvm_memory_slot *slot)
12184 kvm_page_track_flush_slot(kvm, slot);
12187 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12189 return (is_guest_mode(vcpu) &&
12190 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12193 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12195 if (!list_empty_careful(&vcpu->async_pf.done))
12198 if (kvm_apic_has_events(vcpu))
12201 if (vcpu->arch.pv.pv_unhalted)
12204 if (vcpu->arch.exception.pending)
12207 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12208 (vcpu->arch.nmi_pending &&
12209 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12212 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12213 (vcpu->arch.smi_pending &&
12214 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12217 if (kvm_arch_interrupt_allowed(vcpu) &&
12218 (kvm_cpu_has_interrupt(vcpu) ||
12219 kvm_guest_apic_has_interrupt(vcpu)))
12222 if (kvm_hv_has_stimer_pending(vcpu))
12225 if (is_guest_mode(vcpu) &&
12226 kvm_x86_ops.nested_ops->hv_timer_pending &&
12227 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
12230 if (kvm_xen_has_pending_events(vcpu))
12236 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12238 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12241 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12243 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12249 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12251 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12254 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12255 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12256 kvm_test_request(KVM_REQ_EVENT, vcpu))
12259 return kvm_arch_dy_has_pending_interrupt(vcpu);
12262 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12264 if (vcpu->arch.guest_state_protected)
12267 return vcpu->arch.preempted_in_kernel;
12270 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12272 return kvm_rip_read(vcpu);
12275 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12277 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12280 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12282 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12285 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12287 /* Can't read the RIP when guest state is protected, just return 0 */
12288 if (vcpu->arch.guest_state_protected)
12291 if (is_64_bit_mode(vcpu))
12292 return kvm_rip_read(vcpu);
12293 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12294 kvm_rip_read(vcpu));
12296 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12298 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12300 return kvm_get_linear_rip(vcpu) == linear_rip;
12302 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12304 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12306 unsigned long rflags;
12308 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12309 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12310 rflags &= ~X86_EFLAGS_TF;
12313 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12315 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12317 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12318 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12319 rflags |= X86_EFLAGS_TF;
12320 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12323 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12325 __kvm_set_rflags(vcpu, rflags);
12326 kvm_make_request(KVM_REQ_EVENT, vcpu);
12328 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12330 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
12334 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
12338 r = kvm_mmu_reload(vcpu);
12342 if (!vcpu->arch.mmu->direct_map &&
12343 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
12346 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
12349 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12351 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12353 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12356 static inline u32 kvm_async_pf_next_probe(u32 key)
12358 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12361 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12363 u32 key = kvm_async_pf_hash_fn(gfn);
12365 while (vcpu->arch.apf.gfns[key] != ~0)
12366 key = kvm_async_pf_next_probe(key);
12368 vcpu->arch.apf.gfns[key] = gfn;
12371 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12374 u32 key = kvm_async_pf_hash_fn(gfn);
12376 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12377 (vcpu->arch.apf.gfns[key] != gfn &&
12378 vcpu->arch.apf.gfns[key] != ~0); i++)
12379 key = kvm_async_pf_next_probe(key);
12384 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12386 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12389 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12393 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12395 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12399 vcpu->arch.apf.gfns[i] = ~0;
12401 j = kvm_async_pf_next_probe(j);
12402 if (vcpu->arch.apf.gfns[j] == ~0)
12404 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12406 * k lies cyclically in ]i,j]
12408 * |....j i.k.| or |.k..j i...|
12410 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12411 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12416 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12418 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12420 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12424 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12426 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12428 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12429 &token, offset, sizeof(token));
12432 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12434 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12437 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12438 &val, offset, sizeof(val)))
12444 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12447 if (!kvm_pv_async_pf_enabled(vcpu))
12450 if (vcpu->arch.apf.send_user_only &&
12451 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12454 if (is_guest_mode(vcpu)) {
12456 * L1 needs to opt into the special #PF vmexits that are
12457 * used to deliver async page faults.
12459 return vcpu->arch.apf.delivery_as_pf_vmexit;
12462 * Play it safe in case the guest temporarily disables paging.
12463 * The real mode IDT in particular is unlikely to have a #PF
12466 return is_paging(vcpu);
12470 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12472 if (unlikely(!lapic_in_kernel(vcpu) ||
12473 kvm_event_needs_reinjection(vcpu) ||
12474 vcpu->arch.exception.pending))
12477 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12481 * If interrupts are off we cannot even use an artificial
12484 return kvm_arch_interrupt_allowed(vcpu);
12487 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12488 struct kvm_async_pf *work)
12490 struct x86_exception fault;
12492 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
12493 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
12495 if (kvm_can_deliver_async_pf(vcpu) &&
12496 !apf_put_user_notpresent(vcpu)) {
12497 fault.vector = PF_VECTOR;
12498 fault.error_code_valid = true;
12499 fault.error_code = 0;
12500 fault.nested_page_fault = false;
12501 fault.address = work->arch.token;
12502 fault.async_page_fault = true;
12503 kvm_inject_page_fault(vcpu, &fault);
12507 * It is not possible to deliver a paravirtualized asynchronous
12508 * page fault, but putting the guest in an artificial halt state
12509 * can be beneficial nevertheless: if an interrupt arrives, we
12510 * can deliver it timely and perhaps the guest will schedule
12511 * another process. When the instruction that triggered a page
12512 * fault is retried, hopefully the page will be ready in the host.
12514 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
12519 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
12520 struct kvm_async_pf *work)
12522 struct kvm_lapic_irq irq = {
12523 .delivery_mode = APIC_DM_FIXED,
12524 .vector = vcpu->arch.apf.vec
12527 if (work->wakeup_all)
12528 work->arch.token = ~0; /* broadcast wakeup */
12530 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
12531 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
12533 if ((work->wakeup_all || work->notpresent_injected) &&
12534 kvm_pv_async_pf_enabled(vcpu) &&
12535 !apf_put_user_ready(vcpu, work->arch.token)) {
12536 vcpu->arch.apf.pageready_pending = true;
12537 kvm_apic_set_irq(vcpu, &irq, NULL);
12540 vcpu->arch.apf.halted = false;
12541 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12544 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
12546 kvm_make_request(KVM_REQ_APF_READY, vcpu);
12547 if (!vcpu->arch.apf.pageready_pending)
12548 kvm_vcpu_kick(vcpu);
12551 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
12553 if (!kvm_pv_async_pf_enabled(vcpu))
12556 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
12559 void kvm_arch_start_assignment(struct kvm *kvm)
12561 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
12562 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
12564 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
12566 void kvm_arch_end_assignment(struct kvm *kvm)
12568 atomic_dec(&kvm->arch.assigned_device_count);
12570 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
12572 bool kvm_arch_has_assigned_device(struct kvm *kvm)
12574 return atomic_read(&kvm->arch.assigned_device_count);
12576 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
12578 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
12580 atomic_inc(&kvm->arch.noncoherent_dma_count);
12582 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
12584 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
12586 atomic_dec(&kvm->arch.noncoherent_dma_count);
12588 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
12590 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
12592 return atomic_read(&kvm->arch.noncoherent_dma_count);
12594 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
12596 bool kvm_arch_has_irq_bypass(void)
12601 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
12602 struct irq_bypass_producer *prod)
12604 struct kvm_kernel_irqfd *irqfd =
12605 container_of(cons, struct kvm_kernel_irqfd, consumer);
12608 irqfd->producer = prod;
12609 kvm_arch_start_assignment(irqfd->kvm);
12610 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
12611 prod->irq, irqfd->gsi, 1);
12614 kvm_arch_end_assignment(irqfd->kvm);
12619 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
12620 struct irq_bypass_producer *prod)
12623 struct kvm_kernel_irqfd *irqfd =
12624 container_of(cons, struct kvm_kernel_irqfd, consumer);
12626 WARN_ON(irqfd->producer != prod);
12627 irqfd->producer = NULL;
12630 * When producer of consumer is unregistered, we change back to
12631 * remapped mode, so we can re-use the current implementation
12632 * when the irq is masked/disabled or the consumer side (KVM
12633 * int this case doesn't want to receive the interrupts.
12635 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
12637 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
12638 " fails: %d\n", irqfd->consumer.token, ret);
12640 kvm_arch_end_assignment(irqfd->kvm);
12643 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
12644 uint32_t guest_irq, bool set)
12646 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
12649 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
12650 struct kvm_kernel_irq_routing_entry *new)
12652 if (new->type != KVM_IRQ_ROUTING_MSI)
12655 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
12658 bool kvm_vector_hashing_enabled(void)
12660 return vector_hashing;
12663 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
12665 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
12667 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
12670 int kvm_spec_ctrl_test_value(u64 value)
12673 * test that setting IA32_SPEC_CTRL to given value
12674 * is allowed by the host processor
12678 unsigned long flags;
12681 local_irq_save(flags);
12683 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
12685 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
12688 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
12690 local_irq_restore(flags);
12694 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
12696 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
12698 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
12699 struct x86_exception fault;
12700 u64 access = error_code &
12701 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
12703 if (!(error_code & PFERR_PRESENT_MASK) ||
12704 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) {
12706 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
12707 * tables probably do not match the TLB. Just proceed
12708 * with the error code that the processor gave.
12710 fault.vector = PF_VECTOR;
12711 fault.error_code_valid = true;
12712 fault.error_code = error_code;
12713 fault.nested_page_fault = false;
12714 fault.address = gva;
12716 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
12718 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
12721 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
12722 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
12723 * indicates whether exit to userspace is needed.
12725 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
12726 struct x86_exception *e)
12728 if (r == X86EMUL_PROPAGATE_FAULT) {
12729 kvm_inject_emulated_page_fault(vcpu, e);
12734 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
12735 * while handling a VMX instruction KVM could've handled the request
12736 * correctly by exiting to userspace and performing I/O but there
12737 * doesn't seem to be a real use-case behind such requests, just return
12738 * KVM_EXIT_INTERNAL_ERROR for now.
12740 kvm_prepare_emulation_failure_exit(vcpu);
12744 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
12746 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
12749 struct x86_exception e;
12756 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
12757 if (r != X86EMUL_CONTINUE)
12758 return kvm_handle_memory_failure(vcpu, r, &e);
12760 if (operand.pcid >> 12 != 0) {
12761 kvm_inject_gp(vcpu, 0);
12765 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
12768 case INVPCID_TYPE_INDIV_ADDR:
12769 if ((!pcid_enabled && (operand.pcid != 0)) ||
12770 is_noncanonical_address(operand.gla, vcpu)) {
12771 kvm_inject_gp(vcpu, 0);
12774 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
12775 return kvm_skip_emulated_instruction(vcpu);
12777 case INVPCID_TYPE_SINGLE_CTXT:
12778 if (!pcid_enabled && (operand.pcid != 0)) {
12779 kvm_inject_gp(vcpu, 0);
12783 kvm_invalidate_pcid(vcpu, operand.pcid);
12784 return kvm_skip_emulated_instruction(vcpu);
12786 case INVPCID_TYPE_ALL_NON_GLOBAL:
12788 * Currently, KVM doesn't mark global entries in the shadow
12789 * page tables, so a non-global flush just degenerates to a
12790 * global flush. If needed, we could optimize this later by
12791 * keeping track of global entries in shadow page tables.
12795 case INVPCID_TYPE_ALL_INCL_GLOBAL:
12796 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12797 return kvm_skip_emulated_instruction(vcpu);
12800 kvm_inject_gp(vcpu, 0);
12804 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
12806 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
12808 struct kvm_run *run = vcpu->run;
12809 struct kvm_mmio_fragment *frag;
12812 BUG_ON(!vcpu->mmio_needed);
12814 /* Complete previous fragment */
12815 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
12816 len = min(8u, frag->len);
12817 if (!vcpu->mmio_is_write)
12818 memcpy(frag->data, run->mmio.data, len);
12820 if (frag->len <= 8) {
12821 /* Switch to the next fragment. */
12823 vcpu->mmio_cur_fragment++;
12825 /* Go forward to the next mmio piece. */
12831 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
12832 vcpu->mmio_needed = 0;
12834 // VMG change, at this point, we're always done
12835 // RIP has already been advanced
12839 // More MMIO is needed
12840 run->mmio.phys_addr = frag->gpa;
12841 run->mmio.len = min(8u, frag->len);
12842 run->mmio.is_write = vcpu->mmio_is_write;
12843 if (run->mmio.is_write)
12844 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
12845 run->exit_reason = KVM_EXIT_MMIO;
12847 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12852 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
12856 struct kvm_mmio_fragment *frag;
12861 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
12862 if (handled == bytes)
12869 /*TODO: Check if need to increment number of frags */
12870 frag = vcpu->mmio_fragments;
12871 vcpu->mmio_nr_fragments = 1;
12876 vcpu->mmio_needed = 1;
12877 vcpu->mmio_cur_fragment = 0;
12879 vcpu->run->mmio.phys_addr = gpa;
12880 vcpu->run->mmio.len = min(8u, frag->len);
12881 vcpu->run->mmio.is_write = 1;
12882 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
12883 vcpu->run->exit_reason = KVM_EXIT_MMIO;
12885 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12889 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
12891 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
12895 struct kvm_mmio_fragment *frag;
12900 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
12901 if (handled == bytes)
12908 /*TODO: Check if need to increment number of frags */
12909 frag = vcpu->mmio_fragments;
12910 vcpu->mmio_nr_fragments = 1;
12915 vcpu->mmio_needed = 1;
12916 vcpu->mmio_cur_fragment = 0;
12918 vcpu->run->mmio.phys_addr = gpa;
12919 vcpu->run->mmio.len = min(8u, frag->len);
12920 vcpu->run->mmio.is_write = 0;
12921 vcpu->run->exit_reason = KVM_EXIT_MMIO;
12923 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12927 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
12929 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
12930 unsigned int port);
12932 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
12934 int size = vcpu->arch.pio.size;
12935 int port = vcpu->arch.pio.port;
12937 vcpu->arch.pio.count = 0;
12938 if (vcpu->arch.sev_pio_count)
12939 return kvm_sev_es_outs(vcpu, size, port);
12943 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
12947 unsigned int count =
12948 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
12949 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
12951 /* memcpy done already by emulator_pio_out. */
12952 vcpu->arch.sev_pio_count -= count;
12953 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size;
12957 /* Emulation done by the kernel. */
12958 if (!vcpu->arch.sev_pio_count)
12962 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
12966 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
12967 unsigned int port);
12969 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
12971 unsigned count = vcpu->arch.pio.count;
12972 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
12973 vcpu->arch.sev_pio_count -= count;
12974 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size;
12977 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
12979 int size = vcpu->arch.pio.size;
12980 int port = vcpu->arch.pio.port;
12982 advance_sev_es_emulated_ins(vcpu);
12983 if (vcpu->arch.sev_pio_count)
12984 return kvm_sev_es_ins(vcpu, size, port);
12988 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
12992 unsigned int count =
12993 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
12994 if (!__emulator_pio_in(vcpu, size, port, count))
12997 /* Emulation done by the kernel. */
12998 advance_sev_es_emulated_ins(vcpu);
12999 if (!vcpu->arch.sev_pio_count)
13003 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13007 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13008 unsigned int port, void *data, unsigned int count,
13011 vcpu->arch.sev_pio_data = data;
13012 vcpu->arch.sev_pio_count = count;
13013 return in ? kvm_sev_es_ins(vcpu, size, port)
13014 : kvm_sev_es_outs(vcpu, size, port);
13016 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13018 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13019 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13020 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13021 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13022 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13023 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13024 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13025 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
13026 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13027 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13028 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13029 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13030 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13031 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13032 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13033 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13034 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13035 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13036 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13037 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13038 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13039 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13040 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13041 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13042 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13043 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13044 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13046 static int __init kvm_x86_init(void)
13048 kvm_mmu_x86_module_init();
13051 module_init(kvm_x86_init);
13053 static void __exit kvm_x86_exit(void)
13056 * If module_init() is implemented, module_exit() must also be
13057 * implemented to allow module unload.
13060 module_exit(kvm_x86_exit);