1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
5 #include <linux/kvm_host.h>
8 #include <asm/intel_pt.h>
10 #include "capabilities.h"
14 extern const u32 vmx_msr_index[];
21 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
24 #define NR_SHARED_MSRS 7
26 #define NR_SHARED_MSRS 4
29 #define NR_LOADSTORE_MSRS 8
33 struct vmx_msr_entry val[NR_LOADSTORE_MSRS];
36 struct shared_msr_entry {
42 enum segment_cache_field {
51 /* Posted-Interrupt Descriptor */
53 u32 pir[8]; /* Posted interrupt requested */
56 /* bit 256 - Outstanding Notification */
58 /* bit 257 - Suppress Notification */
60 /* bit 271:258 - Reserved */
62 /* bit 279:272 - Notification Vector */
64 /* bit 287:280 - Reserved */
66 /* bit 319:288 - Notification Destination */
74 #define RTIT_ADDR_RANGE 4
82 u64 addr_a[RTIT_ADDR_RANGE];
83 u64 addr_b[RTIT_ADDR_RANGE];
89 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
95 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
96 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
99 /* Has the level1 guest done vmxon? */
104 /* The guest-physical address of the current VMCS L1 keeps for L2 */
107 * Cache of the guest's VMCS, existing outside of guest memory.
108 * Loaded from guest memory during VMPTRLD. Flushed to guest
109 * memory during VMCLEAR and VMPTRLD.
111 struct vmcs12 *cached_vmcs12;
113 * Cache of the guest's shadow VMCS, existing outside of guest
114 * memory. Loaded from guest memory during VM entry. Flushed
115 * to guest memory during VM exit.
117 struct vmcs12 *cached_shadow_vmcs12;
120 * Indicates if the shadow vmcs or enlightened vmcs must be updated
121 * with the data held by struct vmcs12.
123 bool need_vmcs12_to_shadow_sync;
127 * Indicates lazily loaded guest state has not yet been decached from
130 bool need_sync_vmcs02_to_vmcs12_rare;
133 * vmcs02 has been initialized, i.e. state that is constant for
134 * vmcs02 has been written to the backing VMCS. Initialization
135 * is delayed until L1 actually attempts to run a nested VM.
137 bool vmcs02_initialized;
139 bool change_vmcs01_virtual_apic_mode;
142 * Enlightened VMCS has been enabled. It does not mean that L1 has to
143 * use it. However, VMX features available to L1 will be limited based
144 * on what the enlightened VMCS supports.
146 bool enlightened_vmcs_enabled;
148 /* L2 must run next, and mustn't decide to exit to L1. */
149 bool nested_run_pending;
151 /* Pending MTF VM-exit into L1. */
154 struct loaded_vmcs vmcs02;
157 * Guest pages referred to in the vmcs02 with host-physical
158 * pointers, so we must keep them pinned while L2 runs.
160 struct page *apic_access_page;
161 struct kvm_host_map virtual_apic_map;
162 struct kvm_host_map pi_desc_map;
164 struct kvm_host_map msr_bitmap_map;
166 struct pi_desc *pi_desc;
170 struct hrtimer preemption_timer;
171 bool preemption_timer_expired;
173 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
175 u64 vmcs01_guest_bndcfgs;
177 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
178 int l1_tpr_threshold;
183 struct nested_vmx_msrs msrs;
185 /* SMM related state */
187 /* in VMX operation on SMM entry? */
189 /* in guest mode on SMM entry? */
193 gpa_t hv_evmcs_vmptr;
194 struct kvm_host_map hv_evmcs_map;
195 struct hv_enlightened_vmcs *hv_evmcs;
199 struct kvm_vcpu vcpu;
204 * If true, host state has been stored in vmx->loaded_vmcs for
205 * the CPU registers that only need to be switched when transitioning
206 * to/from the kernel, and the registers have been loaded with guest
207 * values. If false, host state is loaded in the CPU registers
208 * and vmx->loaded_vmcs->host_state is invalid.
210 bool guest_state_loaded;
213 u32 idt_vectoring_info;
216 struct shared_msr_entry guest_msrs[NR_SHARED_MSRS];
219 bool guest_msrs_ready;
221 u64 msr_host_kernel_gs_base;
222 u64 msr_guest_kernel_gs_base;
226 u32 msr_ia32_umwait_control;
228 u32 secondary_exec_control;
231 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
232 * non-nested (L1) guest, it always points to vmcs01. For a nested
233 * guest (L2), it points to a different VMCS.
235 struct loaded_vmcs vmcs01;
236 struct loaded_vmcs *loaded_vmcs;
238 struct msr_autoload {
239 struct vmx_msrs guest;
240 struct vmx_msrs host;
243 struct msr_autostore {
244 struct vmx_msrs guest;
250 struct kvm_segment segs[8];
253 u32 bitmask; /* 4 bits per segment (1 bit per field) */
254 struct kvm_save_segment {
262 bool emulation_required;
266 /* Posted interrupt descriptor */
267 struct pi_desc pi_desc;
269 /* Support for a guest hypervisor (nested VMX) */
270 struct nested_vmx nested;
272 /* Dynamic PLE window. */
273 unsigned int ple_window;
274 bool ple_window_dirty;
276 bool req_immediate_exit;
278 /* Support for PML */
279 #define PML_ENTITY_NUM 512
282 /* apic deadline value in host tsc */
285 u64 current_tsc_ratio;
289 unsigned long host_debugctlmsr;
292 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
293 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
294 * in msr_ia32_feature_control_valid_bits.
296 u64 msr_ia32_feature_control;
297 u64 msr_ia32_feature_control_valid_bits;
300 struct pt_desc pt_desc;
303 enum ept_pointers_status {
304 EPT_POINTERS_CHECK = 0,
305 EPT_POINTERS_MATCH = 1,
306 EPT_POINTERS_MISMATCH = 2
312 unsigned int tss_addr;
313 bool ept_identity_pagetable_done;
314 gpa_t ept_identity_map_addr;
316 enum ept_pointers_status ept_pointers_match;
317 spinlock_t ept_pointer_lock;
320 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
321 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu);
322 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
323 int allocate_vpid(void);
324 void free_vpid(int vpid);
325 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
326 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
327 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
328 unsigned long fs_base, unsigned long gs_base);
329 int vmx_get_cpl(struct kvm_vcpu *vcpu);
330 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
331 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
332 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
333 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
334 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
335 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
336 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
337 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
338 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
339 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
340 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
341 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
342 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
343 void update_exception_bitmap(struct kvm_vcpu *vcpu);
344 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
345 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
346 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
347 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
348 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr);
349 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx);
350 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
351 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr);
353 #define POSTED_INTR_ON 0
354 #define POSTED_INTR_SN 1
356 static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
358 return test_and_set_bit(POSTED_INTR_ON,
359 (unsigned long *)&pi_desc->control);
362 static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
364 return test_and_clear_bit(POSTED_INTR_ON,
365 (unsigned long *)&pi_desc->control);
368 static inline int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
370 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
373 static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
375 return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
378 static inline void pi_set_sn(struct pi_desc *pi_desc)
380 set_bit(POSTED_INTR_SN,
381 (unsigned long *)&pi_desc->control);
384 static inline void pi_set_on(struct pi_desc *pi_desc)
386 set_bit(POSTED_INTR_ON,
387 (unsigned long *)&pi_desc->control);
390 static inline void pi_clear_on(struct pi_desc *pi_desc)
392 clear_bit(POSTED_INTR_ON,
393 (unsigned long *)&pi_desc->control);
396 static inline void pi_clear_sn(struct pi_desc *pi_desc)
398 clear_bit(POSTED_INTR_SN,
399 (unsigned long *)&pi_desc->control);
402 static inline int pi_test_on(struct pi_desc *pi_desc)
404 return test_bit(POSTED_INTR_ON,
405 (unsigned long *)&pi_desc->control);
408 static inline int pi_test_sn(struct pi_desc *pi_desc)
410 return test_bit(POSTED_INTR_SN,
411 (unsigned long *)&pi_desc->control);
414 static inline u8 vmx_get_rvi(void)
416 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
419 #define BUILD_CONTROLS_SHADOW(lname, uname) \
420 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
422 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
423 vmcs_write32(uname, val); \
424 vmx->loaded_vmcs->controls_shadow.lname = val; \
427 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
429 return vmx->loaded_vmcs->controls_shadow.lname; \
431 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
433 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
435 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
437 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
439 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
440 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
441 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
442 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
443 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
445 static inline void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
447 vmx->segment_cache.bitmask = 0;
450 static inline u32 vmx_vmentry_ctrl(void)
452 u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
453 if (pt_mode == PT_MODE_SYSTEM)
454 vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
455 VM_ENTRY_LOAD_IA32_RTIT_CTL);
456 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
457 return vmentry_ctrl &
458 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
461 static inline u32 vmx_vmexit_ctrl(void)
463 u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
464 if (pt_mode == PT_MODE_SYSTEM)
465 vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
466 VM_EXIT_CLEAR_IA32_RTIT_CTL);
467 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
469 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
472 u32 vmx_exec_control(struct vcpu_vmx *vmx);
473 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
475 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
477 return container_of(kvm, struct kvm_vmx, kvm);
480 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
482 return container_of(vcpu, struct vcpu_vmx, vcpu);
485 static inline struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
487 return &(to_vmx(vcpu)->pi_desc);
490 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
491 void free_vmcs(struct vmcs *vmcs);
492 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
493 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
494 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs);
495 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
497 static inline struct vmcs *alloc_vmcs(bool shadow)
499 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
503 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
505 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid,
508 if (enable_ept && (invalidate_gpa || !enable_vpid)) {
509 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
511 ept_sync_context(construct_eptp(vcpu,
512 vcpu->arch.mmu->root_hpa));
514 vpid_sync_context(vpid);
518 static inline void vmx_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
520 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid, invalidate_gpa);
523 static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
525 vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
526 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
529 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
531 return vmx->secondary_exec_control &
532 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
535 void dump_vmcs(void);
537 #endif /* __KVM_X86_VMX_H */