arch/x86/kvm/vmx/pmu_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * KVM PMU support for Intel CPUs
   4  *
   5  * Copyright 2011 Red Hat, Inc. and/or its affiliates.
   6  *
   7  * Authors:
   8  *   Avi Kivity   <avi@redhat.com>
   9  *   Gleb Natapov <gleb@redhat.com>
  10  */
  11 #include <linux/types.h>
  12 #include <linux/kvm_host.h>
  13 #include <linux/perf_event.h>
  14 #include <asm/perf_event.h>
  15 #include "x86.h"
  16 #include "cpuid.h"
  17 #include "lapic.h"
  18 #include "pmu.h"
  19
  20 static struct kvm_event_hw_type_mapping intel_arch_events[] = {
  21         /* Index must match CPUID 0x0A.EBX bit vector */
  22         [0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
  23         [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
  24         [2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES  },
  25         [3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
  26         [4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
  27         [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
  28         [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
  29         [7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES },
  30 };
  31
  32 /* mapping between fixed pmc index and intel_arch_events array */
  33 static int fixed_pmc_events[] = {1, 0, 7};
  34
  35 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
  36 {
  37         int i;
  38
  39         for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
  40                 u8 new_ctrl = fixed_ctrl_field(data, i);
  41                 u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
  42                 struct kvm_pmc *pmc;
  43
  44                 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
  45
  46                 if (old_ctrl == new_ctrl)
  47                         continue;
  48
  49                 reprogram_fixed_counter(pmc, new_ctrl, i);
  50         }
  51
  52         pmu->fixed_ctr_ctrl = data;
  53 }
  54
  55 /* function is called when global control register has been updated. */
  56 static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
  57 {
  58         int bit;
  59         u64 diff = pmu->global_ctrl ^ data;
  60
  61         pmu->global_ctrl = data;
  62
  63         for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
  64                 reprogram_counter(pmu, bit);
  65 }
  66
  67 static unsigned intel_find_arch_event(struct kvm_pmu *pmu,
  68                                       u8 event_select,
  69                                       u8 unit_mask)
  70 {
  71         int i;
  72
  73         for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++)
  74                 if (intel_arch_events[i].eventsel == event_select
  75                     && intel_arch_events[i].unit_mask == unit_mask
  76                     && (pmu->available_event_types & (1 << i)))
  77                         break;
  78
  79         if (i == ARRAY_SIZE(intel_arch_events))
  80                 return PERF_COUNT_HW_MAX;
  81
  82         return intel_arch_events[i].event_type;
  83 }
  84
  85 static unsigned intel_find_fixed_event(int idx)
  86 {
  87         if (idx >= ARRAY_SIZE(fixed_pmc_events))
  88                 return PERF_COUNT_HW_MAX;
  89
  90         return intel_arch_events[fixed_pmc_events[idx]].event_type;
  91 }
  92
  93 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */
  94 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)
  95 {
  96         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
  97
  98         return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
  99 }
 100
 101 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
 102 {
 103         if (pmc_idx < INTEL_PMC_IDX_FIXED)
 104                 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,
 105                                   MSR_P6_EVNTSEL0);
 106         else {
 107                 u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
 108
 109                 return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
 110         }
 111 }
 112
 113 /* returns 0 if idx's corresponding MSR exists; otherwise returns 1. */
 114 static int intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
 115 {
 116         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 117         bool fixed = idx & (1u << 30);
 118
 119         idx &= ~(3u << 30);
 120
 121         return (!fixed && idx >= pmu->nr_arch_gp_counters) ||
 122                 (fixed && idx >= pmu->nr_arch_fixed_counters);
 123 }
 124
 125 static struct kvm_pmc *intel_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu,
 126                                             unsigned int idx, u64 *mask)
 127 {
 128         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 129         bool fixed = idx & (1u << 30);
 130         struct kvm_pmc *counters;
 131
 132         idx &= ~(3u << 30);
 133         if (!fixed && idx >= pmu->nr_arch_gp_counters)
 134                 return NULL;
 135         if (fixed && idx >= pmu->nr_arch_fixed_counters)
 136                 return NULL;
 137         counters = fixed ? pmu->fixed_counters : pmu->gp_counters;
 138         *mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP];
 139
 140         return &counters[idx];
 141 }
 142
 143 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
 144 {
 145         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 146         int ret;
 147
 148         switch (msr) {
 149         case MSR_CORE_PERF_FIXED_CTR_CTRL:
 150         case MSR_CORE_PERF_GLOBAL_STATUS:
 151         case MSR_CORE_PERF_GLOBAL_CTRL:
 152         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
 153                 ret = pmu->version > 1;
 154                 break;
 155         default:
 156                 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
 157                         get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
 158                         get_fixed_pmc(pmu, msr);
 159                 break;
 160         }
 161
 162         return ret;
 163 }
 164
 165 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr)
 166 {
 167         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 168         struct kvm_pmc *pmc;
 169
 170         pmc = get_fixed_pmc(pmu, msr);
 171         pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);
 172         pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0);
 173
 174         return pmc;
 175 }
 176
 177 static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
 178 {
 179         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 180         struct kvm_pmc *pmc;
 181
 182         switch (msr) {
 183         case MSR_CORE_PERF_FIXED_CTR_CTRL:
 184                 *data = pmu->fixed_ctr_ctrl;
 185                 return 0;
 186         case MSR_CORE_PERF_GLOBAL_STATUS:
 187                 *data = pmu->global_status;
 188                 return 0;
 189         case MSR_CORE_PERF_GLOBAL_CTRL:
 190                 *data = pmu->global_ctrl;
 191                 return 0;
 192         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
 193                 *data = pmu->global_ovf_ctrl;
 194                 return 0;
 195         default:
 196                 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0))) {
 197                         u64 val = pmc_read_counter(pmc);
 198                         *data = val & pmu->counter_bitmask[KVM_PMC_GP];
 199                         return 0;
 200                 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
 201                         u64 val = pmc_read_counter(pmc);
 202                         *data = val & pmu->counter_bitmask[KVM_PMC_FIXED];
 203                         return 0;
 204                 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
 205                         *data = pmc->eventsel;
 206                         return 0;
 207                 }
 208         }
 209
 210         return 1;
 211 }
 212
 213 static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 214 {
 215         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 216         struct kvm_pmc *pmc;
 217         u32 msr = msr_info->index;
 218         u64 data = msr_info->data;
 219
 220         switch (msr) {
 221         case MSR_CORE_PERF_FIXED_CTR_CTRL:
 222                 if (pmu->fixed_ctr_ctrl == data)
 223                         return 0;
 224                 if (!(data & 0xfffffffffffff444ull)) {
 225                         reprogram_fixed_counters(pmu, data);
 226                         return 0;
 227                 }
 228                 break;
 229         case MSR_CORE_PERF_GLOBAL_STATUS:
 230                 if (msr_info->host_initiated) {
 231                         pmu->global_status = data;
 232                         return 0;
 233                 }
 234                 break; /* RO MSR */
 235         case MSR_CORE_PERF_GLOBAL_CTRL:
 236                 if (pmu->global_ctrl == data)
 237                         return 0;
 238                 if (!(data & pmu->global_ctrl_mask)) {
 239                         global_ctrl_changed(pmu, data);
 240                         return 0;
 241                 }
 242                 break;
 243         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
 244                 if (!(data & pmu->global_ovf_ctrl_mask)) {
 245                         if (!msr_info->host_initiated)
 246                                 pmu->global_status &= ~data;
 247                         pmu->global_ovf_ctrl = data;
 248                         return 0;
 249                 }
 250                 break;
 251         default:
 252                 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0))) {
 253                         if (msr_info->host_initiated)
 254                                 pmc->counter = data;
 255                         else
 256                                 pmc->counter = (s32)data;
 257                         return 0;
 258                 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
 259                         pmc->counter = data;
 260                         return 0;
 261                 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
 262                         if (data == pmc->eventsel)
 263                                 return 0;
 264                         if (!(data & pmu->reserved_bits)) {
 265                                 reprogram_gp_counter(pmc, data);
 266                                 return 0;
 267                         }
 268                 }
 269         }
 270
 271         return 1;
 272 }
 273
 274 static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 275 {
 276         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 277         struct x86_pmu_capability x86_pmu;
 278         struct kvm_cpuid_entry2 *entry;
 279         union cpuid10_eax eax;
 280         union cpuid10_edx edx;
 281
 282         pmu->nr_arch_gp_counters = 0;
 283         pmu->nr_arch_fixed_counters = 0;
 284         pmu->counter_bitmask[KVM_PMC_GP] = 0;
 285         pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
 286         pmu->version = 0;
 287         pmu->reserved_bits = 0xffffffff00200000ull;
 288
 289         entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
 290         if (!entry)
 291                 return;
 292         eax.full = entry->eax;
 293         edx.full = entry->edx;
 294
 295         pmu->version = eax.split.version_id;
 296         if (!pmu->version)
 297                 return;
 298
 299         perf_get_x86_pmu_capability(&x86_pmu);
 300
 301         pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
 302                                          x86_pmu.num_counters_gp);
 303         pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
 304         pmu->available_event_types = ~entry->ebx &
 305                                         ((1ull << eax.split.mask_length) - 1);
 306
 307         if (pmu->version == 1) {
 308                 pmu->nr_arch_fixed_counters = 0;
 309         } else {
 310                 pmu->nr_arch_fixed_counters =
 311                         min_t(int, edx.split.num_counters_fixed,
 312                               x86_pmu.num_counters_fixed);
 313                 pmu->counter_bitmask[KVM_PMC_FIXED] =
 314                         ((u64)1 << edx.split.bit_width_fixed) - 1;
 315         }
 316
 317         pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
 318                 (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
 319         pmu->global_ctrl_mask = ~pmu->global_ctrl;
 320         pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
 321                         & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
 322                             MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
 323         if (kvm_x86_ops->pt_supported())
 324                 pmu->global_ovf_ctrl_mask &=
 325                                 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI;
 326
 327         entry = kvm_find_cpuid_entry(vcpu, 7, 0);
 328         if (entry &&
 329             (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
 330             (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM)))
 331                 pmu->reserved_bits ^= HSW_IN_TX|HSW_IN_TX_CHECKPOINTED;
 332 }
 333
 334 static void intel_pmu_init(struct kvm_vcpu *vcpu)
 335 {
 336         int i;
 337         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 338
 339         for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
 340                 pmu->gp_counters[i].type = KVM_PMC_GP;
 341                 pmu->gp_counters[i].vcpu = vcpu;
 342                 pmu->gp_counters[i].idx = i;
 343                 pmu->gp_counters[i].current_config = 0;
 344         }
 345
 346         for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
 347                 pmu->fixed_counters[i].type = KVM_PMC_FIXED;
 348                 pmu->fixed_counters[i].vcpu = vcpu;
 349                 pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
 350                 pmu->fixed_counters[i].current_config = 0;
 351         }
 352 }
 353
 354 static void intel_pmu_reset(struct kvm_vcpu *vcpu)
 355 {
 356         struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 357         struct kvm_pmc *pmc = NULL;
 358         int i;
 359
 360         for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
 361                 pmc = &pmu->gp_counters[i];
 362
 363                 pmc_stop_counter(pmc);
 364                 pmc->counter = pmc->eventsel = 0;
 365         }
 366
 367         for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
 368                 pmc = &pmu->fixed_counters[i];
 369
 370                 pmc_stop_counter(pmc);
 371                 pmc->counter = 0;
 372         }
 373
 374         pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
 375                 pmu->global_ovf_ctrl = 0;
 376 }
 377
 378 struct kvm_pmu_ops intel_pmu_ops = {
 379         .find_arch_event = intel_find_arch_event,
 380         .find_fixed_event = intel_find_fixed_event,
 381         .pmc_is_enabled = intel_pmc_is_enabled,
 382         .pmc_idx_to_pmc = intel_pmc_idx_to_pmc,
 383         .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc,
 384         .msr_idx_to_pmc = intel_msr_idx_to_pmc,
 385         .is_valid_rdpmc_ecx = intel_is_valid_rdpmc_ecx,
 386         .is_valid_msr = intel_is_valid_msr,
 387         .get_msr = intel_pmu_get_msr,
 388         .set_msr = intel_pmu_set_msr,
 389         .refresh = intel_pmu_refresh,
 390         .init = intel_pmu_init,
 391         .reset = intel_pmu_reset,
 392 };