arch/x86/kvm/vmx/capabilities.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_VMX_CAPS_H
   3 #define __KVM_X86_VMX_CAPS_H
   4
   5 #include <asm/vmx.h>
   6
   7 #include "lapic.h"
   8 #include "x86.h"
   9
  10 extern bool __read_mostly enable_vpid;
  11 extern bool __read_mostly flexpriority_enabled;
  12 extern bool __read_mostly enable_ept;
  13 extern bool __read_mostly enable_unrestricted_guest;
  14 extern bool __read_mostly enable_ept_ad_bits;
  15 extern bool __read_mostly enable_pml;
  16 extern int __read_mostly pt_mode;
  17
  18 #define PT_MODE_SYSTEM          0
  19 #define PT_MODE_HOST_GUEST      1
  20
  21 #define PMU_CAP_FW_WRITES       (1ULL << 13)
  22 #define PMU_CAP_LBR_FMT         0x3f
  23
  24 #define DEBUGCTLMSR_LBR_MASK            (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI)
  25
  26 struct nested_vmx_msrs {
  27         /*
  28          * We only store the "true" versions of the VMX capability MSRs. We
  29          * generate the "non-true" versions by setting the must-be-1 bits
  30          * according to the SDM.
  31          */
  32         u32 procbased_ctls_low;
  33         u32 procbased_ctls_high;
  34         u32 secondary_ctls_low;
  35         u32 secondary_ctls_high;
  36         u32 pinbased_ctls_low;
  37         u32 pinbased_ctls_high;
  38         u32 exit_ctls_low;
  39         u32 exit_ctls_high;
  40         u32 entry_ctls_low;
  41         u32 entry_ctls_high;
  42         u32 misc_low;
  43         u32 misc_high;
  44         u32 ept_caps;
  45         u32 vpid_caps;
  46         u64 basic;
  47         u64 cr0_fixed0;
  48         u64 cr0_fixed1;
  49         u64 cr4_fixed0;
  50         u64 cr4_fixed1;
  51         u64 vmcs_enum;
  52         u64 vmfunc_controls;
  53 };
  54
  55 struct vmcs_config {
  56         int size;
  57         int order;
  58         u32 basic_cap;
  59         u32 revision_id;
  60         u32 pin_based_exec_ctrl;
  61         u32 cpu_based_exec_ctrl;
  62         u32 cpu_based_2nd_exec_ctrl;
  63         u32 vmexit_ctrl;
  64         u32 vmentry_ctrl;
  65         struct nested_vmx_msrs nested;
  66 };
  67 extern struct vmcs_config vmcs_config;
  68
  69 struct vmx_capability {
  70         u32 ept;
  71         u32 vpid;
  72 };
  73 extern struct vmx_capability vmx_capability;
  74
  75 static inline bool cpu_has_vmx_basic_inout(void)
  76 {
  77         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
  78 }
  79
  80 static inline bool cpu_has_virtual_nmis(void)
  81 {
  82         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
  83 }
  84
  85 static inline bool cpu_has_vmx_preemption_timer(void)
  86 {
  87         return vmcs_config.pin_based_exec_ctrl &
  88                 PIN_BASED_VMX_PREEMPTION_TIMER;
  89 }
  90
  91 static inline bool cpu_has_vmx_posted_intr(void)
  92 {
  93         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
  94 }
  95
  96 static inline bool cpu_has_load_ia32_efer(void)
  97 {
  98         return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_EFER) &&
  99                (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_EFER);
 100 }
 101
 102 static inline bool cpu_has_load_perf_global_ctrl(void)
 103 {
 104         return (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) &&
 105                (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
 106 }
 107
 108 static inline bool cpu_has_vmx_mpx(void)
 109 {
 110         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
 111                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
 112 }
 113
 114 static inline bool cpu_has_vmx_tpr_shadow(void)
 115 {
 116         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 117 }
 118
 119 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
 120 {
 121         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
 122 }
 123
 124 static inline bool cpu_has_vmx_msr_bitmap(void)
 125 {
 126         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 127 }
 128
 129 static inline bool cpu_has_secondary_exec_ctrls(void)
 130 {
 131         return vmcs_config.cpu_based_exec_ctrl &
 132                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 133 }
 134
 135 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 136 {
 137         return vmcs_config.cpu_based_2nd_exec_ctrl &
 138                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 139 }
 140
 141 static inline bool cpu_has_vmx_ept(void)
 142 {
 143         return vmcs_config.cpu_based_2nd_exec_ctrl &
 144                 SECONDARY_EXEC_ENABLE_EPT;
 145 }
 146
 147 static inline bool vmx_umip_emulated(void)
 148 {
 149         return vmcs_config.cpu_based_2nd_exec_ctrl &
 150                 SECONDARY_EXEC_DESC;
 151 }
 152
 153 static inline bool cpu_has_vmx_rdtscp(void)
 154 {
 155         return vmcs_config.cpu_based_2nd_exec_ctrl &
 156                 SECONDARY_EXEC_ENABLE_RDTSCP;
 157 }
 158
 159 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 160 {
 161         return vmcs_config.cpu_based_2nd_exec_ctrl &
 162                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 163 }
 164
 165 static inline bool cpu_has_vmx_vpid(void)
 166 {
 167         return vmcs_config.cpu_based_2nd_exec_ctrl &
 168                 SECONDARY_EXEC_ENABLE_VPID;
 169 }
 170
 171 static inline bool cpu_has_vmx_wbinvd_exit(void)
 172 {
 173         return vmcs_config.cpu_based_2nd_exec_ctrl &
 174                 SECONDARY_EXEC_WBINVD_EXITING;
 175 }
 176
 177 static inline bool cpu_has_vmx_unrestricted_guest(void)
 178 {
 179         return vmcs_config.cpu_based_2nd_exec_ctrl &
 180                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 181 }
 182
 183 static inline bool cpu_has_vmx_apic_register_virt(void)
 184 {
 185         return vmcs_config.cpu_based_2nd_exec_ctrl &
 186                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
 187 }
 188
 189 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
 190 {
 191         return vmcs_config.cpu_based_2nd_exec_ctrl &
 192                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 193 }
 194
 195 static inline bool cpu_has_vmx_ple(void)
 196 {
 197         return vmcs_config.cpu_based_2nd_exec_ctrl &
 198                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 199 }
 200
 201 static inline bool cpu_has_vmx_rdrand(void)
 202 {
 203         return vmcs_config.cpu_based_2nd_exec_ctrl &
 204                 SECONDARY_EXEC_RDRAND_EXITING;
 205 }
 206
 207 static inline bool cpu_has_vmx_invpcid(void)
 208 {
 209         return vmcs_config.cpu_based_2nd_exec_ctrl &
 210                 SECONDARY_EXEC_ENABLE_INVPCID;
 211 }
 212
 213 static inline bool cpu_has_vmx_vmfunc(void)
 214 {
 215         return vmcs_config.cpu_based_2nd_exec_ctrl &
 216                 SECONDARY_EXEC_ENABLE_VMFUNC;
 217 }
 218
 219 static inline bool cpu_has_vmx_shadow_vmcs(void)
 220 {
 221         u64 vmx_msr;
 222
 223         /* check if the cpu supports writing r/o exit information fields */
 224         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
 225         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
 226                 return false;
 227
 228         return vmcs_config.cpu_based_2nd_exec_ctrl &
 229                 SECONDARY_EXEC_SHADOW_VMCS;
 230 }
 231
 232 static inline bool cpu_has_vmx_encls_vmexit(void)
 233 {
 234         return vmcs_config.cpu_based_2nd_exec_ctrl &
 235                 SECONDARY_EXEC_ENCLS_EXITING;
 236 }
 237
 238 static inline bool cpu_has_vmx_rdseed(void)
 239 {
 240         return vmcs_config.cpu_based_2nd_exec_ctrl &
 241                 SECONDARY_EXEC_RDSEED_EXITING;
 242 }
 243
 244 static inline bool cpu_has_vmx_pml(void)
 245 {
 246         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
 247 }
 248
 249 static inline bool cpu_has_vmx_xsaves(void)
 250 {
 251         return vmcs_config.cpu_based_2nd_exec_ctrl &
 252                 SECONDARY_EXEC_XSAVES;
 253 }
 254
 255 static inline bool cpu_has_vmx_waitpkg(void)
 256 {
 257         return vmcs_config.cpu_based_2nd_exec_ctrl &
 258                 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
 259 }
 260
 261 static inline bool cpu_has_vmx_tsc_scaling(void)
 262 {
 263         return vmcs_config.cpu_based_2nd_exec_ctrl &
 264                 SECONDARY_EXEC_TSC_SCALING;
 265 }
 266
 267 static inline bool cpu_has_vmx_bus_lock_detection(void)
 268 {
 269         return vmcs_config.cpu_based_2nd_exec_ctrl &
 270             SECONDARY_EXEC_BUS_LOCK_DETECTION;
 271 }
 272
 273 static inline bool cpu_has_vmx_apicv(void)
 274 {
 275         return cpu_has_vmx_apic_register_virt() &&
 276                 cpu_has_vmx_virtual_intr_delivery() &&
 277                 cpu_has_vmx_posted_intr();
 278 }
 279
 280 static inline bool cpu_has_vmx_flexpriority(void)
 281 {
 282         return cpu_has_vmx_tpr_shadow() &&
 283                 cpu_has_vmx_virtualize_apic_accesses();
 284 }
 285
 286 static inline bool cpu_has_vmx_ept_execute_only(void)
 287 {
 288         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 289 }
 290
 291 static inline bool cpu_has_vmx_ept_4levels(void)
 292 {
 293         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 294 }
 295
 296 static inline bool cpu_has_vmx_ept_5levels(void)
 297 {
 298         return vmx_capability.ept & VMX_EPT_PAGE_WALK_5_BIT;
 299 }
 300
 301 static inline bool cpu_has_vmx_ept_mt_wb(void)
 302 {
 303         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 304 }
 305
 306 static inline bool cpu_has_vmx_ept_2m_page(void)
 307 {
 308         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 309 }
 310
 311 static inline bool cpu_has_vmx_ept_1g_page(void)
 312 {
 313         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 314 }
 315
 316 static inline int ept_caps_to_lpage_level(u32 ept_caps)
 317 {
 318         if (ept_caps & VMX_EPT_1GB_PAGE_BIT)
 319                 return PG_LEVEL_1G;
 320         if (ept_caps & VMX_EPT_2MB_PAGE_BIT)
 321                 return PG_LEVEL_2M;
 322         return PG_LEVEL_4K;
 323 }
 324
 325 static inline bool cpu_has_vmx_ept_ad_bits(void)
 326 {
 327         return vmx_capability.ept & VMX_EPT_AD_BIT;
 328 }
 329
 330 static inline bool cpu_has_vmx_invept_context(void)
 331 {
 332         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 333 }
 334
 335 static inline bool cpu_has_vmx_invept_global(void)
 336 {
 337         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 338 }
 339
 340 static inline bool cpu_has_vmx_invvpid(void)
 341 {
 342         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
 343 }
 344
 345 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
 346 {
 347         return vmx_capability.vpid & VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT;
 348 }
 349
 350 static inline bool cpu_has_vmx_invvpid_single(void)
 351 {
 352         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 353 }
 354
 355 static inline bool cpu_has_vmx_invvpid_global(void)
 356 {
 357         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 358 }
 359
 360 static inline bool cpu_has_vmx_intel_pt(void)
 361 {
 362         u64 vmx_msr;
 363
 364         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
 365         return (vmx_msr & MSR_IA32_VMX_MISC_INTEL_PT) &&
 366                 (vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_PT_USE_GPA) &&
 367                 (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_IA32_RTIT_CTL) &&
 368                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_RTIT_CTL);
 369 }
 370
 371 /*
 372  * Processor Trace can operate in one of three modes:
 373  *  a. system-wide: trace both host/guest and output to host buffer
 374  *  b. host-only:   only trace host and output to host buffer
 375  *  c. host-guest:  trace host and guest simultaneously and output to their
 376  *                  respective buffer
 377  *
 378  * KVM currently only supports (a) and (c).
 379  */
 380 static inline bool vmx_pt_mode_is_system(void)
 381 {
 382         return pt_mode == PT_MODE_SYSTEM;
 383 }
 384 static inline bool vmx_pt_mode_is_host_guest(void)
 385 {
 386         return pt_mode == PT_MODE_HOST_GUEST;
 387 }
 388
 389 static inline u64 vmx_get_perf_capabilities(void)
 390 {
 391         u64 perf_cap = 0;
 392
 393         if (!enable_pmu)
 394                 return perf_cap;
 395
 396         if (boot_cpu_has(X86_FEATURE_PDCM))
 397                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap);
 398
 399         perf_cap &= PMU_CAP_LBR_FMT;
 400
 401         /*
 402          * Since counters are virtualized, KVM would support full
 403          * width counting unconditionally, even if the host lacks it.
 404          */
 405         return PMU_CAP_FW_WRITES | perf_cap;
 406 }
 407
 408 static inline u64 vmx_supported_debugctl(void)
 409 {
 410         u64 debugctl = 0;
 411
 412         if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
 413                 debugctl |= DEBUGCTLMSR_BUS_LOCK_DETECT;
 414
 415         if (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT)
 416                 debugctl |= DEBUGCTLMSR_LBR_MASK;
 417
 418         return debugctl;
 419 }
 420
 421 #endif /* __KVM_X86_VMX_CAPS_H */