2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
52 static int __read_mostly bypass_guest_pf = 1;
53 module_param(bypass_guest_pf, bool, S_IRUGO);
55 static int __read_mostly enable_vpid = 1;
56 module_param_named(vpid, enable_vpid, bool, 0444);
58 static int __read_mostly flexpriority_enabled = 1;
59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
61 static int __read_mostly enable_ept = 1;
62 module_param_named(ept, enable_ept, bool, S_IRUGO);
64 static int __read_mostly enable_unrestricted_guest = 1;
65 module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
68 static int __read_mostly emulate_invalid_guest_state = 0;
69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
71 static int __read_mostly vmm_exclusive = 1;
72 module_param(vmm_exclusive, bool, S_IRUGO);
74 static int __read_mostly yield_on_hlt = 1;
75 module_param(yield_on_hlt, bool, S_IRUGO);
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
82 static int __read_mostly nested = 0;
83 module_param(nested, bool, S_IRUGO);
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
90 (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
106 * According to test, this time is usually smaller than 128 cycles.
107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 #define KVM_VMX_DEFAULT_PLE_GAP 128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116 module_param(ple_gap, int, S_IRUGO);
118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119 module_param(ple_window, int, S_IRUGO);
121 #define NR_AUTOLOAD_MSRS 1
130 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
131 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
132 * loaded on this CPU (so we can clear them if the CPU goes down).
138 struct list_head loaded_vmcss_on_cpu_link;
141 struct shared_msr_entry {
148 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
149 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
152 /* Has the level1 guest done vmxon? */
157 struct kvm_vcpu vcpu;
158 unsigned long host_rsp;
161 bool nmi_known_unmasked;
163 u32 idt_vectoring_info;
165 struct shared_msr_entry *guest_msrs;
169 u64 msr_host_kernel_gs_base;
170 u64 msr_guest_kernel_gs_base;
173 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
174 * non-nested (L1) guest, it always points to vmcs01. For a nested
175 * guest (L2), it points to a different VMCS.
177 struct loaded_vmcs vmcs01;
178 struct loaded_vmcs *loaded_vmcs;
179 bool __launched; /* temporary, used in vmx_vcpu_run */
180 struct msr_autoload {
182 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
183 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
187 u16 fs_sel, gs_sel, ldt_sel;
188 int gs_ldt_reload_needed;
189 int fs_reload_needed;
194 struct kvm_save_segment {
199 } tr, es, ds, fs, gs;
202 u32 bitmask; /* 4 bits per segment (1 bit per field) */
203 struct kvm_save_segment seg[8];
206 bool emulation_required;
208 /* Support for vnmi-less CPUs */
209 int soft_vnmi_blocked;
211 s64 vnmi_blocked_time;
216 /* Support for a guest hypervisor (nested VMX) */
217 struct nested_vmx nested;
220 enum segment_cache_field {
229 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
231 return container_of(vcpu, struct vcpu_vmx, vcpu);
234 static u64 construct_eptp(unsigned long root_hpa);
235 static void kvm_cpu_vmxon(u64 addr);
236 static void kvm_cpu_vmxoff(void);
237 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
238 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
240 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
241 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
243 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
244 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
246 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
247 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
249 static unsigned long *vmx_io_bitmap_a;
250 static unsigned long *vmx_io_bitmap_b;
251 static unsigned long *vmx_msr_bitmap_legacy;
252 static unsigned long *vmx_msr_bitmap_longmode;
254 static bool cpu_has_load_ia32_efer;
256 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
257 static DEFINE_SPINLOCK(vmx_vpid_lock);
259 static struct vmcs_config {
263 u32 pin_based_exec_ctrl;
264 u32 cpu_based_exec_ctrl;
265 u32 cpu_based_2nd_exec_ctrl;
270 static struct vmx_capability {
275 #define VMX_SEGMENT_FIELD(seg) \
276 [VCPU_SREG_##seg] = { \
277 .selector = GUEST_##seg##_SELECTOR, \
278 .base = GUEST_##seg##_BASE, \
279 .limit = GUEST_##seg##_LIMIT, \
280 .ar_bytes = GUEST_##seg##_AR_BYTES, \
283 static struct kvm_vmx_segment_field {
288 } kvm_vmx_segment_fields[] = {
289 VMX_SEGMENT_FIELD(CS),
290 VMX_SEGMENT_FIELD(DS),
291 VMX_SEGMENT_FIELD(ES),
292 VMX_SEGMENT_FIELD(FS),
293 VMX_SEGMENT_FIELD(GS),
294 VMX_SEGMENT_FIELD(SS),
295 VMX_SEGMENT_FIELD(TR),
296 VMX_SEGMENT_FIELD(LDTR),
299 static u64 host_efer;
301 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
304 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
305 * away by decrementing the array size.
307 static const u32 vmx_msr_index[] = {
309 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
311 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
313 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
315 static inline bool is_page_fault(u32 intr_info)
317 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
318 INTR_INFO_VALID_MASK)) ==
319 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
322 static inline bool is_no_device(u32 intr_info)
324 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
325 INTR_INFO_VALID_MASK)) ==
326 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
329 static inline bool is_invalid_opcode(u32 intr_info)
331 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
332 INTR_INFO_VALID_MASK)) ==
333 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
336 static inline bool is_external_interrupt(u32 intr_info)
338 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
339 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
342 static inline bool is_machine_check(u32 intr_info)
344 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
345 INTR_INFO_VALID_MASK)) ==
346 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
349 static inline bool cpu_has_vmx_msr_bitmap(void)
351 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
354 static inline bool cpu_has_vmx_tpr_shadow(void)
356 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
359 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
361 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
364 static inline bool cpu_has_secondary_exec_ctrls(void)
366 return vmcs_config.cpu_based_exec_ctrl &
367 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
370 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
372 return vmcs_config.cpu_based_2nd_exec_ctrl &
373 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
376 static inline bool cpu_has_vmx_flexpriority(void)
378 return cpu_has_vmx_tpr_shadow() &&
379 cpu_has_vmx_virtualize_apic_accesses();
382 static inline bool cpu_has_vmx_ept_execute_only(void)
384 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
387 static inline bool cpu_has_vmx_eptp_uncacheable(void)
389 return vmx_capability.ept & VMX_EPTP_UC_BIT;
392 static inline bool cpu_has_vmx_eptp_writeback(void)
394 return vmx_capability.ept & VMX_EPTP_WB_BIT;
397 static inline bool cpu_has_vmx_ept_2m_page(void)
399 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
402 static inline bool cpu_has_vmx_ept_1g_page(void)
404 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
407 static inline bool cpu_has_vmx_ept_4levels(void)
409 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
412 static inline bool cpu_has_vmx_invept_individual_addr(void)
414 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
417 static inline bool cpu_has_vmx_invept_context(void)
419 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
422 static inline bool cpu_has_vmx_invept_global(void)
424 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
427 static inline bool cpu_has_vmx_invvpid_single(void)
429 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
432 static inline bool cpu_has_vmx_invvpid_global(void)
434 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
437 static inline bool cpu_has_vmx_ept(void)
439 return vmcs_config.cpu_based_2nd_exec_ctrl &
440 SECONDARY_EXEC_ENABLE_EPT;
443 static inline bool cpu_has_vmx_unrestricted_guest(void)
445 return vmcs_config.cpu_based_2nd_exec_ctrl &
446 SECONDARY_EXEC_UNRESTRICTED_GUEST;
449 static inline bool cpu_has_vmx_ple(void)
451 return vmcs_config.cpu_based_2nd_exec_ctrl &
452 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
455 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
457 return flexpriority_enabled && irqchip_in_kernel(kvm);
460 static inline bool cpu_has_vmx_vpid(void)
462 return vmcs_config.cpu_based_2nd_exec_ctrl &
463 SECONDARY_EXEC_ENABLE_VPID;
466 static inline bool cpu_has_vmx_rdtscp(void)
468 return vmcs_config.cpu_based_2nd_exec_ctrl &
469 SECONDARY_EXEC_RDTSCP;
472 static inline bool cpu_has_virtual_nmis(void)
474 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
477 static inline bool cpu_has_vmx_wbinvd_exit(void)
479 return vmcs_config.cpu_based_2nd_exec_ctrl &
480 SECONDARY_EXEC_WBINVD_EXITING;
483 static inline bool report_flexpriority(void)
485 return flexpriority_enabled;
488 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
492 for (i = 0; i < vmx->nmsrs; ++i)
493 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
498 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
504 } operand = { vpid, 0, gva };
506 asm volatile (__ex(ASM_VMX_INVVPID)
507 /* CF==1 or ZF==1 --> rc = -1 */
509 : : "a"(&operand), "c"(ext) : "cc", "memory");
512 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
516 } operand = {eptp, gpa};
518 asm volatile (__ex(ASM_VMX_INVEPT)
519 /* CF==1 or ZF==1 --> rc = -1 */
520 "; ja 1f ; ud2 ; 1:\n"
521 : : "a" (&operand), "c" (ext) : "cc", "memory");
524 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
528 i = __find_msr_index(vmx, msr);
530 return &vmx->guest_msrs[i];
534 static void vmcs_clear(struct vmcs *vmcs)
536 u64 phys_addr = __pa(vmcs);
539 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
540 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
543 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
547 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
549 vmcs_clear(loaded_vmcs->vmcs);
550 loaded_vmcs->cpu = -1;
551 loaded_vmcs->launched = 0;
554 static void vmcs_load(struct vmcs *vmcs)
556 u64 phys_addr = __pa(vmcs);
559 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
560 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
563 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
567 static void __loaded_vmcs_clear(void *arg)
569 struct loaded_vmcs *loaded_vmcs = arg;
570 int cpu = raw_smp_processor_id();
572 if (loaded_vmcs->cpu != cpu)
573 return; /* vcpu migration can race with cpu offline */
574 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
575 per_cpu(current_vmcs, cpu) = NULL;
576 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
577 loaded_vmcs_init(loaded_vmcs);
580 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
582 if (loaded_vmcs->cpu != -1)
583 smp_call_function_single(
584 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
587 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
592 if (cpu_has_vmx_invvpid_single())
593 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
596 static inline void vpid_sync_vcpu_global(void)
598 if (cpu_has_vmx_invvpid_global())
599 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
602 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
604 if (cpu_has_vmx_invvpid_single())
605 vpid_sync_vcpu_single(vmx);
607 vpid_sync_vcpu_global();
610 static inline void ept_sync_global(void)
612 if (cpu_has_vmx_invept_global())
613 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
616 static inline void ept_sync_context(u64 eptp)
619 if (cpu_has_vmx_invept_context())
620 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
626 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
629 if (cpu_has_vmx_invept_individual_addr())
630 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
633 ept_sync_context(eptp);
637 static __always_inline unsigned long vmcs_readl(unsigned long field)
641 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
642 : "=a"(value) : "d"(field) : "cc");
646 static __always_inline u16 vmcs_read16(unsigned long field)
648 return vmcs_readl(field);
651 static __always_inline u32 vmcs_read32(unsigned long field)
653 return vmcs_readl(field);
656 static __always_inline u64 vmcs_read64(unsigned long field)
659 return vmcs_readl(field);
661 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
665 static noinline void vmwrite_error(unsigned long field, unsigned long value)
667 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
668 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
672 static void vmcs_writel(unsigned long field, unsigned long value)
676 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
677 : "=q"(error) : "a"(value), "d"(field) : "cc");
679 vmwrite_error(field, value);
682 static void vmcs_write16(unsigned long field, u16 value)
684 vmcs_writel(field, value);
687 static void vmcs_write32(unsigned long field, u32 value)
689 vmcs_writel(field, value);
692 static void vmcs_write64(unsigned long field, u64 value)
694 vmcs_writel(field, value);
695 #ifndef CONFIG_X86_64
697 vmcs_writel(field+1, value >> 32);
701 static void vmcs_clear_bits(unsigned long field, u32 mask)
703 vmcs_writel(field, vmcs_readl(field) & ~mask);
706 static void vmcs_set_bits(unsigned long field, u32 mask)
708 vmcs_writel(field, vmcs_readl(field) | mask);
711 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
713 vmx->segment_cache.bitmask = 0;
716 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
720 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
722 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
723 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
724 vmx->segment_cache.bitmask = 0;
726 ret = vmx->segment_cache.bitmask & mask;
727 vmx->segment_cache.bitmask |= mask;
731 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
733 u16 *p = &vmx->segment_cache.seg[seg].selector;
735 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
736 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
740 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
742 ulong *p = &vmx->segment_cache.seg[seg].base;
744 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
745 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
749 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
751 u32 *p = &vmx->segment_cache.seg[seg].limit;
753 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
754 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
758 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
760 u32 *p = &vmx->segment_cache.seg[seg].ar;
762 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
763 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
767 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
771 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
772 (1u << NM_VECTOR) | (1u << DB_VECTOR);
773 if ((vcpu->guest_debug &
774 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
775 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
776 eb |= 1u << BP_VECTOR;
777 if (to_vmx(vcpu)->rmode.vm86_active)
780 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
781 if (vcpu->fpu_active)
782 eb &= ~(1u << NM_VECTOR);
783 vmcs_write32(EXCEPTION_BITMAP, eb);
786 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
789 struct msr_autoload *m = &vmx->msr_autoload;
791 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
792 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
793 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
797 for (i = 0; i < m->nr; ++i)
798 if (m->guest[i].index == msr)
804 m->guest[i] = m->guest[m->nr];
805 m->host[i] = m->host[m->nr];
806 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
807 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
810 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
811 u64 guest_val, u64 host_val)
814 struct msr_autoload *m = &vmx->msr_autoload;
816 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
817 vmcs_write64(GUEST_IA32_EFER, guest_val);
818 vmcs_write64(HOST_IA32_EFER, host_val);
819 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
820 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
824 for (i = 0; i < m->nr; ++i)
825 if (m->guest[i].index == msr)
830 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
831 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
834 m->guest[i].index = msr;
835 m->guest[i].value = guest_val;
836 m->host[i].index = msr;
837 m->host[i].value = host_val;
840 static void reload_tss(void)
843 * VT restores TR but not its size. Useless.
845 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
846 struct desc_struct *descs;
848 descs = (void *)gdt->address;
849 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
853 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
858 guest_efer = vmx->vcpu.arch.efer;
861 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
864 ignore_bits = EFER_NX | EFER_SCE;
866 ignore_bits |= EFER_LMA | EFER_LME;
867 /* SCE is meaningful only in long mode on Intel */
868 if (guest_efer & EFER_LMA)
869 ignore_bits &= ~(u64)EFER_SCE;
871 guest_efer &= ~ignore_bits;
872 guest_efer |= host_efer & ignore_bits;
873 vmx->guest_msrs[efer_offset].data = guest_efer;
874 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
876 clear_atomic_switch_msr(vmx, MSR_EFER);
877 /* On ept, can't emulate nx, and must switch nx atomically */
878 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
879 guest_efer = vmx->vcpu.arch.efer;
880 if (!(guest_efer & EFER_LMA))
881 guest_efer &= ~EFER_LME;
882 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
889 static unsigned long segment_base(u16 selector)
891 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
892 struct desc_struct *d;
893 unsigned long table_base;
896 if (!(selector & ~3))
899 table_base = gdt->address;
901 if (selector & 4) { /* from ldt */
902 u16 ldt_selector = kvm_read_ldt();
904 if (!(ldt_selector & ~3))
907 table_base = segment_base(ldt_selector);
909 d = (struct desc_struct *)(table_base + (selector & ~7));
910 v = get_desc_base(d);
912 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
913 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
918 static inline unsigned long kvm_read_tr_base(void)
921 asm("str %0" : "=g"(tr));
922 return segment_base(tr);
925 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
927 struct vcpu_vmx *vmx = to_vmx(vcpu);
930 if (vmx->host_state.loaded)
933 vmx->host_state.loaded = 1;
935 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
936 * allow segment selectors with cpl > 0 or ti == 1.
938 vmx->host_state.ldt_sel = kvm_read_ldt();
939 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
940 savesegment(fs, vmx->host_state.fs_sel);
941 if (!(vmx->host_state.fs_sel & 7)) {
942 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
943 vmx->host_state.fs_reload_needed = 0;
945 vmcs_write16(HOST_FS_SELECTOR, 0);
946 vmx->host_state.fs_reload_needed = 1;
948 savesegment(gs, vmx->host_state.gs_sel);
949 if (!(vmx->host_state.gs_sel & 7))
950 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
952 vmcs_write16(HOST_GS_SELECTOR, 0);
953 vmx->host_state.gs_ldt_reload_needed = 1;
957 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
958 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
960 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
961 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
965 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
966 if (is_long_mode(&vmx->vcpu))
967 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
969 for (i = 0; i < vmx->save_nmsrs; ++i)
970 kvm_set_shared_msr(vmx->guest_msrs[i].index,
971 vmx->guest_msrs[i].data,
972 vmx->guest_msrs[i].mask);
975 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
977 if (!vmx->host_state.loaded)
980 ++vmx->vcpu.stat.host_state_reload;
981 vmx->host_state.loaded = 0;
983 if (is_long_mode(&vmx->vcpu))
984 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
986 if (vmx->host_state.gs_ldt_reload_needed) {
987 kvm_load_ldt(vmx->host_state.ldt_sel);
989 load_gs_index(vmx->host_state.gs_sel);
991 loadsegment(gs, vmx->host_state.gs_sel);
994 if (vmx->host_state.fs_reload_needed)
995 loadsegment(fs, vmx->host_state.fs_sel);
998 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1000 if (current_thread_info()->status & TS_USEDFPU)
1002 load_gdt(&__get_cpu_var(host_gdt));
1005 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1008 __vmx_load_host_state(vmx);
1013 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1014 * vcpu mutex is already taken.
1016 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1018 struct vcpu_vmx *vmx = to_vmx(vcpu);
1019 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1022 kvm_cpu_vmxon(phys_addr);
1023 else if (vmx->loaded_vmcs->cpu != cpu)
1024 loaded_vmcs_clear(vmx->loaded_vmcs);
1026 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1027 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1028 vmcs_load(vmx->loaded_vmcs->vmcs);
1031 if (vmx->loaded_vmcs->cpu != cpu) {
1032 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1033 unsigned long sysenter_esp;
1035 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1036 local_irq_disable();
1037 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1038 &per_cpu(loaded_vmcss_on_cpu, cpu));
1042 * Linux uses per-cpu TSS and GDT, so set these when switching
1045 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1046 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1048 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1049 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1050 vmx->loaded_vmcs->cpu = cpu;
1054 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1056 __vmx_load_host_state(to_vmx(vcpu));
1057 if (!vmm_exclusive) {
1058 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1064 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1068 if (vcpu->fpu_active)
1070 vcpu->fpu_active = 1;
1071 cr0 = vmcs_readl(GUEST_CR0);
1072 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1073 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1074 vmcs_writel(GUEST_CR0, cr0);
1075 update_exception_bitmap(vcpu);
1076 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1077 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1080 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1082 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1084 vmx_decache_cr0_guest_bits(vcpu);
1085 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1086 update_exception_bitmap(vcpu);
1087 vcpu->arch.cr0_guest_owned_bits = 0;
1088 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1089 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1092 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1094 unsigned long rflags, save_rflags;
1096 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1097 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1098 rflags = vmcs_readl(GUEST_RFLAGS);
1099 if (to_vmx(vcpu)->rmode.vm86_active) {
1100 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1101 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1102 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1104 to_vmx(vcpu)->rflags = rflags;
1106 return to_vmx(vcpu)->rflags;
1109 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1111 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1112 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1113 to_vmx(vcpu)->rflags = rflags;
1114 if (to_vmx(vcpu)->rmode.vm86_active) {
1115 to_vmx(vcpu)->rmode.save_rflags = rflags;
1116 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1118 vmcs_writel(GUEST_RFLAGS, rflags);
1121 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1123 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1126 if (interruptibility & GUEST_INTR_STATE_STI)
1127 ret |= KVM_X86_SHADOW_INT_STI;
1128 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1129 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1134 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1136 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1137 u32 interruptibility = interruptibility_old;
1139 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1141 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1142 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1143 else if (mask & KVM_X86_SHADOW_INT_STI)
1144 interruptibility |= GUEST_INTR_STATE_STI;
1146 if ((interruptibility != interruptibility_old))
1147 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1150 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1154 rip = kvm_rip_read(vcpu);
1155 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1156 kvm_rip_write(vcpu, rip);
1158 /* skipping an emulated instruction also counts */
1159 vmx_set_interrupt_shadow(vcpu, 0);
1162 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1164 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1165 * explicitly skip the instruction because if the HLT state is set, then
1166 * the instruction is already executing and RIP has already been
1168 if (!yield_on_hlt &&
1169 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1170 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1173 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1174 bool has_error_code, u32 error_code,
1177 struct vcpu_vmx *vmx = to_vmx(vcpu);
1178 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1180 if (has_error_code) {
1181 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1182 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1185 if (vmx->rmode.vm86_active) {
1187 if (kvm_exception_is_soft(nr))
1188 inc_eip = vcpu->arch.event_exit_inst_len;
1189 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1190 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1194 if (kvm_exception_is_soft(nr)) {
1195 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1196 vmx->vcpu.arch.event_exit_inst_len);
1197 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1199 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1201 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1202 vmx_clear_hlt(vcpu);
1205 static bool vmx_rdtscp_supported(void)
1207 return cpu_has_vmx_rdtscp();
1211 * Swap MSR entry in host/guest MSR entry array.
1213 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1215 struct shared_msr_entry tmp;
1217 tmp = vmx->guest_msrs[to];
1218 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1219 vmx->guest_msrs[from] = tmp;
1223 * Set up the vmcs to automatically save and restore system
1224 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1225 * mode, as fiddling with msrs is very expensive.
1227 static void setup_msrs(struct vcpu_vmx *vmx)
1229 int save_nmsrs, index;
1230 unsigned long *msr_bitmap;
1232 vmx_load_host_state(vmx);
1234 #ifdef CONFIG_X86_64
1235 if (is_long_mode(&vmx->vcpu)) {
1236 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1238 move_msr_up(vmx, index, save_nmsrs++);
1239 index = __find_msr_index(vmx, MSR_LSTAR);
1241 move_msr_up(vmx, index, save_nmsrs++);
1242 index = __find_msr_index(vmx, MSR_CSTAR);
1244 move_msr_up(vmx, index, save_nmsrs++);
1245 index = __find_msr_index(vmx, MSR_TSC_AUX);
1246 if (index >= 0 && vmx->rdtscp_enabled)
1247 move_msr_up(vmx, index, save_nmsrs++);
1249 * MSR_STAR is only needed on long mode guests, and only
1250 * if efer.sce is enabled.
1252 index = __find_msr_index(vmx, MSR_STAR);
1253 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1254 move_msr_up(vmx, index, save_nmsrs++);
1257 index = __find_msr_index(vmx, MSR_EFER);
1258 if (index >= 0 && update_transition_efer(vmx, index))
1259 move_msr_up(vmx, index, save_nmsrs++);
1261 vmx->save_nmsrs = save_nmsrs;
1263 if (cpu_has_vmx_msr_bitmap()) {
1264 if (is_long_mode(&vmx->vcpu))
1265 msr_bitmap = vmx_msr_bitmap_longmode;
1267 msr_bitmap = vmx_msr_bitmap_legacy;
1269 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1274 * reads and returns guest's timestamp counter "register"
1275 * guest_tsc = host_tsc + tsc_offset -- 21.3
1277 static u64 guest_read_tsc(void)
1279 u64 host_tsc, tsc_offset;
1282 tsc_offset = vmcs_read64(TSC_OFFSET);
1283 return host_tsc + tsc_offset;
1287 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1288 * ioctl. In this case the call-back should update internal vmx state to make
1289 * the changes effective.
1291 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1293 /* Nothing to do here */
1297 * writes 'offset' into guest's timestamp counter offset register
1299 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1301 vmcs_write64(TSC_OFFSET, offset);
1304 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1306 u64 offset = vmcs_read64(TSC_OFFSET);
1307 vmcs_write64(TSC_OFFSET, offset + adjustment);
1310 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1312 return target_tsc - native_read_tsc();
1315 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1317 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1318 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1322 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1323 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1324 * all guests if the "nested" module option is off, and can also be disabled
1325 * for a single guest by disabling its VMX cpuid bit.
1327 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1329 return nested && guest_cpuid_has_vmx(vcpu);
1333 * Reads an msr value (of 'msr_index') into 'pdata'.
1334 * Returns 0 on success, non-0 otherwise.
1335 * Assumes vcpu_load() was already called.
1337 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1340 struct shared_msr_entry *msr;
1343 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1347 switch (msr_index) {
1348 #ifdef CONFIG_X86_64
1350 data = vmcs_readl(GUEST_FS_BASE);
1353 data = vmcs_readl(GUEST_GS_BASE);
1355 case MSR_KERNEL_GS_BASE:
1356 vmx_load_host_state(to_vmx(vcpu));
1357 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1361 return kvm_get_msr_common(vcpu, msr_index, pdata);
1363 data = guest_read_tsc();
1365 case MSR_IA32_SYSENTER_CS:
1366 data = vmcs_read32(GUEST_SYSENTER_CS);
1368 case MSR_IA32_SYSENTER_EIP:
1369 data = vmcs_readl(GUEST_SYSENTER_EIP);
1371 case MSR_IA32_SYSENTER_ESP:
1372 data = vmcs_readl(GUEST_SYSENTER_ESP);
1375 if (!to_vmx(vcpu)->rdtscp_enabled)
1377 /* Otherwise falls through */
1379 vmx_load_host_state(to_vmx(vcpu));
1380 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1382 vmx_load_host_state(to_vmx(vcpu));
1386 return kvm_get_msr_common(vcpu, msr_index, pdata);
1394 * Writes msr value into into the appropriate "register".
1395 * Returns 0 on success, non-0 otherwise.
1396 * Assumes vcpu_load() was already called.
1398 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1400 struct vcpu_vmx *vmx = to_vmx(vcpu);
1401 struct shared_msr_entry *msr;
1404 switch (msr_index) {
1406 vmx_load_host_state(vmx);
1407 ret = kvm_set_msr_common(vcpu, msr_index, data);
1409 #ifdef CONFIG_X86_64
1411 vmx_segment_cache_clear(vmx);
1412 vmcs_writel(GUEST_FS_BASE, data);
1415 vmx_segment_cache_clear(vmx);
1416 vmcs_writel(GUEST_GS_BASE, data);
1418 case MSR_KERNEL_GS_BASE:
1419 vmx_load_host_state(vmx);
1420 vmx->msr_guest_kernel_gs_base = data;
1423 case MSR_IA32_SYSENTER_CS:
1424 vmcs_write32(GUEST_SYSENTER_CS, data);
1426 case MSR_IA32_SYSENTER_EIP:
1427 vmcs_writel(GUEST_SYSENTER_EIP, data);
1429 case MSR_IA32_SYSENTER_ESP:
1430 vmcs_writel(GUEST_SYSENTER_ESP, data);
1433 kvm_write_tsc(vcpu, data);
1435 case MSR_IA32_CR_PAT:
1436 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1437 vmcs_write64(GUEST_IA32_PAT, data);
1438 vcpu->arch.pat = data;
1441 ret = kvm_set_msr_common(vcpu, msr_index, data);
1444 if (!vmx->rdtscp_enabled)
1446 /* Check reserved bit, higher 32 bits should be zero */
1447 if ((data >> 32) != 0)
1449 /* Otherwise falls through */
1451 msr = find_msr_entry(vmx, msr_index);
1453 vmx_load_host_state(vmx);
1457 ret = kvm_set_msr_common(vcpu, msr_index, data);
1463 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1465 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1468 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1471 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1473 case VCPU_EXREG_PDPTR:
1475 ept_save_pdptrs(vcpu);
1482 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1484 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1485 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1487 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1489 update_exception_bitmap(vcpu);
1492 static __init int cpu_has_kvm_support(void)
1494 return cpu_has_vmx();
1497 static __init int vmx_disabled_by_bios(void)
1501 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1502 if (msr & FEATURE_CONTROL_LOCKED) {
1503 /* launched w/ TXT and VMX disabled */
1504 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1507 /* launched w/o TXT and VMX only enabled w/ TXT */
1508 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1509 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1510 && !tboot_enabled()) {
1511 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1512 "activate TXT before enabling KVM\n");
1515 /* launched w/o TXT and VMX disabled */
1516 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1517 && !tboot_enabled())
1524 static void kvm_cpu_vmxon(u64 addr)
1526 asm volatile (ASM_VMX_VMXON_RAX
1527 : : "a"(&addr), "m"(addr)
1531 static int hardware_enable(void *garbage)
1533 int cpu = raw_smp_processor_id();
1534 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1537 if (read_cr4() & X86_CR4_VMXE)
1540 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
1541 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1543 test_bits = FEATURE_CONTROL_LOCKED;
1544 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1545 if (tboot_enabled())
1546 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1548 if ((old & test_bits) != test_bits) {
1549 /* enable and lock */
1550 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1552 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1554 if (vmm_exclusive) {
1555 kvm_cpu_vmxon(phys_addr);
1559 store_gdt(&__get_cpu_var(host_gdt));
1564 static void vmclear_local_loaded_vmcss(void)
1566 int cpu = raw_smp_processor_id();
1567 struct loaded_vmcs *v, *n;
1569 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
1570 loaded_vmcss_on_cpu_link)
1571 __loaded_vmcs_clear(v);
1575 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1578 static void kvm_cpu_vmxoff(void)
1580 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1583 static void hardware_disable(void *garbage)
1585 if (vmm_exclusive) {
1586 vmclear_local_loaded_vmcss();
1589 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1592 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1593 u32 msr, u32 *result)
1595 u32 vmx_msr_low, vmx_msr_high;
1596 u32 ctl = ctl_min | ctl_opt;
1598 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1600 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1601 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1603 /* Ensure minimum (required) set of control bits are supported. */
1611 static __init bool allow_1_setting(u32 msr, u32 ctl)
1613 u32 vmx_msr_low, vmx_msr_high;
1615 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1616 return vmx_msr_high & ctl;
1619 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1621 u32 vmx_msr_low, vmx_msr_high;
1622 u32 min, opt, min2, opt2;
1623 u32 _pin_based_exec_control = 0;
1624 u32 _cpu_based_exec_control = 0;
1625 u32 _cpu_based_2nd_exec_control = 0;
1626 u32 _vmexit_control = 0;
1627 u32 _vmentry_control = 0;
1629 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1630 opt = PIN_BASED_VIRTUAL_NMIS;
1631 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1632 &_pin_based_exec_control) < 0)
1636 #ifdef CONFIG_X86_64
1637 CPU_BASED_CR8_LOAD_EXITING |
1638 CPU_BASED_CR8_STORE_EXITING |
1640 CPU_BASED_CR3_LOAD_EXITING |
1641 CPU_BASED_CR3_STORE_EXITING |
1642 CPU_BASED_USE_IO_BITMAPS |
1643 CPU_BASED_MOV_DR_EXITING |
1644 CPU_BASED_USE_TSC_OFFSETING |
1645 CPU_BASED_MWAIT_EXITING |
1646 CPU_BASED_MONITOR_EXITING |
1647 CPU_BASED_INVLPG_EXITING;
1650 min |= CPU_BASED_HLT_EXITING;
1652 opt = CPU_BASED_TPR_SHADOW |
1653 CPU_BASED_USE_MSR_BITMAPS |
1654 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1655 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1656 &_cpu_based_exec_control) < 0)
1658 #ifdef CONFIG_X86_64
1659 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1660 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1661 ~CPU_BASED_CR8_STORE_EXITING;
1663 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1665 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1666 SECONDARY_EXEC_WBINVD_EXITING |
1667 SECONDARY_EXEC_ENABLE_VPID |
1668 SECONDARY_EXEC_ENABLE_EPT |
1669 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1670 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1671 SECONDARY_EXEC_RDTSCP;
1672 if (adjust_vmx_controls(min2, opt2,
1673 MSR_IA32_VMX_PROCBASED_CTLS2,
1674 &_cpu_based_2nd_exec_control) < 0)
1677 #ifndef CONFIG_X86_64
1678 if (!(_cpu_based_2nd_exec_control &
1679 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1680 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1682 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1683 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1685 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1686 CPU_BASED_CR3_STORE_EXITING |
1687 CPU_BASED_INVLPG_EXITING);
1688 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1689 vmx_capability.ept, vmx_capability.vpid);
1693 #ifdef CONFIG_X86_64
1694 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1696 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1697 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1698 &_vmexit_control) < 0)
1702 opt = VM_ENTRY_LOAD_IA32_PAT;
1703 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1704 &_vmentry_control) < 0)
1707 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1709 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1710 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1713 #ifdef CONFIG_X86_64
1714 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1715 if (vmx_msr_high & (1u<<16))
1719 /* Require Write-Back (WB) memory type for VMCS accesses. */
1720 if (((vmx_msr_high >> 18) & 15) != 6)
1723 vmcs_conf->size = vmx_msr_high & 0x1fff;
1724 vmcs_conf->order = get_order(vmcs_config.size);
1725 vmcs_conf->revision_id = vmx_msr_low;
1727 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1728 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1729 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1730 vmcs_conf->vmexit_ctrl = _vmexit_control;
1731 vmcs_conf->vmentry_ctrl = _vmentry_control;
1733 cpu_has_load_ia32_efer =
1734 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1735 VM_ENTRY_LOAD_IA32_EFER)
1736 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1737 VM_EXIT_LOAD_IA32_EFER);
1742 static struct vmcs *alloc_vmcs_cpu(int cpu)
1744 int node = cpu_to_node(cpu);
1748 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1751 vmcs = page_address(pages);
1752 memset(vmcs, 0, vmcs_config.size);
1753 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1757 static struct vmcs *alloc_vmcs(void)
1759 return alloc_vmcs_cpu(raw_smp_processor_id());
1762 static void free_vmcs(struct vmcs *vmcs)
1764 free_pages((unsigned long)vmcs, vmcs_config.order);
1768 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
1770 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
1772 if (!loaded_vmcs->vmcs)
1774 loaded_vmcs_clear(loaded_vmcs);
1775 free_vmcs(loaded_vmcs->vmcs);
1776 loaded_vmcs->vmcs = NULL;
1779 static void free_kvm_area(void)
1783 for_each_possible_cpu(cpu) {
1784 free_vmcs(per_cpu(vmxarea, cpu));
1785 per_cpu(vmxarea, cpu) = NULL;
1789 static __init int alloc_kvm_area(void)
1793 for_each_possible_cpu(cpu) {
1796 vmcs = alloc_vmcs_cpu(cpu);
1802 per_cpu(vmxarea, cpu) = vmcs;
1807 static __init int hardware_setup(void)
1809 if (setup_vmcs_config(&vmcs_config) < 0)
1812 if (boot_cpu_has(X86_FEATURE_NX))
1813 kvm_enable_efer_bits(EFER_NX);
1815 if (!cpu_has_vmx_vpid())
1818 if (!cpu_has_vmx_ept() ||
1819 !cpu_has_vmx_ept_4levels()) {
1821 enable_unrestricted_guest = 0;
1824 if (!cpu_has_vmx_unrestricted_guest())
1825 enable_unrestricted_guest = 0;
1827 if (!cpu_has_vmx_flexpriority())
1828 flexpriority_enabled = 0;
1830 if (!cpu_has_vmx_tpr_shadow())
1831 kvm_x86_ops->update_cr8_intercept = NULL;
1833 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1834 kvm_disable_largepages();
1836 if (!cpu_has_vmx_ple())
1839 return alloc_kvm_area();
1842 static __exit void hardware_unsetup(void)
1847 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1849 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1851 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1852 vmcs_write16(sf->selector, save->selector);
1853 vmcs_writel(sf->base, save->base);
1854 vmcs_write32(sf->limit, save->limit);
1855 vmcs_write32(sf->ar_bytes, save->ar);
1857 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1859 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1863 static void enter_pmode(struct kvm_vcpu *vcpu)
1865 unsigned long flags;
1866 struct vcpu_vmx *vmx = to_vmx(vcpu);
1868 vmx->emulation_required = 1;
1869 vmx->rmode.vm86_active = 0;
1871 vmx_segment_cache_clear(vmx);
1873 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
1874 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1875 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1876 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1878 flags = vmcs_readl(GUEST_RFLAGS);
1879 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1880 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1881 vmcs_writel(GUEST_RFLAGS, flags);
1883 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1884 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1886 update_exception_bitmap(vcpu);
1888 if (emulate_invalid_guest_state)
1891 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1892 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1893 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1894 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1896 vmx_segment_cache_clear(vmx);
1898 vmcs_write16(GUEST_SS_SELECTOR, 0);
1899 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1901 vmcs_write16(GUEST_CS_SELECTOR,
1902 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1903 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1906 static gva_t rmode_tss_base(struct kvm *kvm)
1908 if (!kvm->arch.tss_addr) {
1909 struct kvm_memslots *slots;
1912 slots = kvm_memslots(kvm);
1913 base_gfn = slots->memslots[0].base_gfn +
1914 kvm->memslots->memslots[0].npages - 3;
1915 return base_gfn << PAGE_SHIFT;
1917 return kvm->arch.tss_addr;
1920 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1922 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1924 save->selector = vmcs_read16(sf->selector);
1925 save->base = vmcs_readl(sf->base);
1926 save->limit = vmcs_read32(sf->limit);
1927 save->ar = vmcs_read32(sf->ar_bytes);
1928 vmcs_write16(sf->selector, save->base >> 4);
1929 vmcs_write32(sf->base, save->base & 0xffff0);
1930 vmcs_write32(sf->limit, 0xffff);
1931 vmcs_write32(sf->ar_bytes, 0xf3);
1932 if (save->base & 0xf)
1933 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1934 " aligned when entering protected mode (seg=%d)",
1938 static void enter_rmode(struct kvm_vcpu *vcpu)
1940 unsigned long flags;
1941 struct vcpu_vmx *vmx = to_vmx(vcpu);
1943 if (enable_unrestricted_guest)
1946 vmx->emulation_required = 1;
1947 vmx->rmode.vm86_active = 1;
1950 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1951 * vcpu. Call it here with phys address pointing 16M below 4G.
1953 if (!vcpu->kvm->arch.tss_addr) {
1954 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1955 "called before entering vcpu\n");
1956 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1957 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1958 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1961 vmx_segment_cache_clear(vmx);
1963 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
1964 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1965 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1967 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1968 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1970 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1971 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1973 flags = vmcs_readl(GUEST_RFLAGS);
1974 vmx->rmode.save_rflags = flags;
1976 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1978 vmcs_writel(GUEST_RFLAGS, flags);
1979 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1980 update_exception_bitmap(vcpu);
1982 if (emulate_invalid_guest_state)
1983 goto continue_rmode;
1985 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1986 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1987 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1989 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1990 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1991 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1992 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1993 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1995 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1996 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1997 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1998 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2001 kvm_mmu_reset_context(vcpu);
2004 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2006 struct vcpu_vmx *vmx = to_vmx(vcpu);
2007 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2013 * Force kernel_gs_base reloading before EFER changes, as control
2014 * of this msr depends on is_long_mode().
2016 vmx_load_host_state(to_vmx(vcpu));
2017 vcpu->arch.efer = efer;
2018 if (efer & EFER_LMA) {
2019 vmcs_write32(VM_ENTRY_CONTROLS,
2020 vmcs_read32(VM_ENTRY_CONTROLS) |
2021 VM_ENTRY_IA32E_MODE);
2024 vmcs_write32(VM_ENTRY_CONTROLS,
2025 vmcs_read32(VM_ENTRY_CONTROLS) &
2026 ~VM_ENTRY_IA32E_MODE);
2028 msr->data = efer & ~EFER_LME;
2033 #ifdef CONFIG_X86_64
2035 static void enter_lmode(struct kvm_vcpu *vcpu)
2039 vmx_segment_cache_clear(to_vmx(vcpu));
2041 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2042 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2043 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2045 vmcs_write32(GUEST_TR_AR_BYTES,
2046 (guest_tr_ar & ~AR_TYPE_MASK)
2047 | AR_TYPE_BUSY_64_TSS);
2049 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2052 static void exit_lmode(struct kvm_vcpu *vcpu)
2054 vmcs_write32(VM_ENTRY_CONTROLS,
2055 vmcs_read32(VM_ENTRY_CONTROLS)
2056 & ~VM_ENTRY_IA32E_MODE);
2057 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2062 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2064 vpid_sync_context(to_vmx(vcpu));
2066 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2068 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2072 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2074 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2076 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2077 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2080 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2082 if (enable_ept && is_paging(vcpu))
2083 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2084 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2087 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2089 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2091 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2092 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2095 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2097 if (!test_bit(VCPU_EXREG_PDPTR,
2098 (unsigned long *)&vcpu->arch.regs_dirty))
2101 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2102 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2103 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2104 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2105 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2109 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2111 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2112 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2113 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2114 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2115 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2118 __set_bit(VCPU_EXREG_PDPTR,
2119 (unsigned long *)&vcpu->arch.regs_avail);
2120 __set_bit(VCPU_EXREG_PDPTR,
2121 (unsigned long *)&vcpu->arch.regs_dirty);
2124 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2126 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2128 struct kvm_vcpu *vcpu)
2130 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2131 vmx_decache_cr3(vcpu);
2132 if (!(cr0 & X86_CR0_PG)) {
2133 /* From paging/starting to nonpaging */
2134 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2135 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2136 (CPU_BASED_CR3_LOAD_EXITING |
2137 CPU_BASED_CR3_STORE_EXITING));
2138 vcpu->arch.cr0 = cr0;
2139 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2140 } else if (!is_paging(vcpu)) {
2141 /* From nonpaging to paging */
2142 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2143 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2144 ~(CPU_BASED_CR3_LOAD_EXITING |
2145 CPU_BASED_CR3_STORE_EXITING));
2146 vcpu->arch.cr0 = cr0;
2147 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2150 if (!(cr0 & X86_CR0_WP))
2151 *hw_cr0 &= ~X86_CR0_WP;
2154 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2156 struct vcpu_vmx *vmx = to_vmx(vcpu);
2157 unsigned long hw_cr0;
2159 if (enable_unrestricted_guest)
2160 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2161 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2163 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2165 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2168 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2171 #ifdef CONFIG_X86_64
2172 if (vcpu->arch.efer & EFER_LME) {
2173 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2175 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2181 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2183 if (!vcpu->fpu_active)
2184 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2186 vmcs_writel(CR0_READ_SHADOW, cr0);
2187 vmcs_writel(GUEST_CR0, hw_cr0);
2188 vcpu->arch.cr0 = cr0;
2189 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2192 static u64 construct_eptp(unsigned long root_hpa)
2196 /* TODO write the value reading from MSR */
2197 eptp = VMX_EPT_DEFAULT_MT |
2198 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2199 eptp |= (root_hpa & PAGE_MASK);
2204 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2206 unsigned long guest_cr3;
2211 eptp = construct_eptp(cr3);
2212 vmcs_write64(EPT_POINTER, eptp);
2213 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2214 vcpu->kvm->arch.ept_identity_map_addr;
2215 ept_load_pdptrs(vcpu);
2218 vmx_flush_tlb(vcpu);
2219 vmcs_writel(GUEST_CR3, guest_cr3);
2222 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2224 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2225 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2227 if (cr4 & X86_CR4_VMXE) {
2229 * To use VMXON (and later other VMX instructions), a guest
2230 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2231 * So basically the check on whether to allow nested VMX
2234 if (!nested_vmx_allowed(vcpu))
2236 } else if (to_vmx(vcpu)->nested.vmxon)
2239 vcpu->arch.cr4 = cr4;
2241 if (!is_paging(vcpu)) {
2242 hw_cr4 &= ~X86_CR4_PAE;
2243 hw_cr4 |= X86_CR4_PSE;
2244 } else if (!(cr4 & X86_CR4_PAE)) {
2245 hw_cr4 &= ~X86_CR4_PAE;
2249 vmcs_writel(CR4_READ_SHADOW, cr4);
2250 vmcs_writel(GUEST_CR4, hw_cr4);
2254 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2255 struct kvm_segment *var, int seg)
2257 struct vcpu_vmx *vmx = to_vmx(vcpu);
2258 struct kvm_save_segment *save;
2261 if (vmx->rmode.vm86_active
2262 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2263 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2264 || seg == VCPU_SREG_GS)
2265 && !emulate_invalid_guest_state) {
2267 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2268 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2269 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2270 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2271 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2274 var->selector = save->selector;
2275 var->base = save->base;
2276 var->limit = save->limit;
2278 if (seg == VCPU_SREG_TR
2279 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2280 goto use_saved_rmode_seg;
2282 var->base = vmx_read_guest_seg_base(vmx, seg);
2283 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2284 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2285 ar = vmx_read_guest_seg_ar(vmx, seg);
2286 use_saved_rmode_seg:
2287 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2289 var->type = ar & 15;
2290 var->s = (ar >> 4) & 1;
2291 var->dpl = (ar >> 5) & 3;
2292 var->present = (ar >> 7) & 1;
2293 var->avl = (ar >> 12) & 1;
2294 var->l = (ar >> 13) & 1;
2295 var->db = (ar >> 14) & 1;
2296 var->g = (ar >> 15) & 1;
2297 var->unusable = (ar >> 16) & 1;
2300 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2302 struct kvm_segment s;
2304 if (to_vmx(vcpu)->rmode.vm86_active) {
2305 vmx_get_segment(vcpu, &s, seg);
2308 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
2311 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2313 if (!is_protmode(vcpu))
2316 if (!is_long_mode(vcpu)
2317 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2320 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2323 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2325 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2326 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2327 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2329 return to_vmx(vcpu)->cpl;
2333 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2340 ar = var->type & 15;
2341 ar |= (var->s & 1) << 4;
2342 ar |= (var->dpl & 3) << 5;
2343 ar |= (var->present & 1) << 7;
2344 ar |= (var->avl & 1) << 12;
2345 ar |= (var->l & 1) << 13;
2346 ar |= (var->db & 1) << 14;
2347 ar |= (var->g & 1) << 15;
2349 if (ar == 0) /* a 0 value means unusable */
2350 ar = AR_UNUSABLE_MASK;
2355 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2356 struct kvm_segment *var, int seg)
2358 struct vcpu_vmx *vmx = to_vmx(vcpu);
2359 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2362 vmx_segment_cache_clear(vmx);
2364 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2365 vmcs_write16(sf->selector, var->selector);
2366 vmx->rmode.tr.selector = var->selector;
2367 vmx->rmode.tr.base = var->base;
2368 vmx->rmode.tr.limit = var->limit;
2369 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2372 vmcs_writel(sf->base, var->base);
2373 vmcs_write32(sf->limit, var->limit);
2374 vmcs_write16(sf->selector, var->selector);
2375 if (vmx->rmode.vm86_active && var->s) {
2377 * Hack real-mode segments into vm86 compatibility.
2379 if (var->base == 0xffff0000 && var->selector == 0xf000)
2380 vmcs_writel(sf->base, 0xf0000);
2383 ar = vmx_segment_access_rights(var);
2386 * Fix the "Accessed" bit in AR field of segment registers for older
2388 * IA32 arch specifies that at the time of processor reset the
2389 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2390 * is setting it to 0 in the usedland code. This causes invalid guest
2391 * state vmexit when "unrestricted guest" mode is turned on.
2392 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2393 * tree. Newer qemu binaries with that qemu fix would not need this
2396 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2397 ar |= 0x1; /* Accessed */
2399 vmcs_write32(sf->ar_bytes, ar);
2400 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2403 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2405 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
2407 *db = (ar >> 14) & 1;
2408 *l = (ar >> 13) & 1;
2411 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2413 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2414 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2417 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2419 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2420 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2423 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2425 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2426 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2429 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2431 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2432 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2435 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2437 struct kvm_segment var;
2440 vmx_get_segment(vcpu, &var, seg);
2441 ar = vmx_segment_access_rights(&var);
2443 if (var.base != (var.selector << 4))
2445 if (var.limit != 0xffff)
2453 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2455 struct kvm_segment cs;
2456 unsigned int cs_rpl;
2458 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2459 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2463 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2467 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2468 if (cs.dpl > cs_rpl)
2471 if (cs.dpl != cs_rpl)
2477 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2481 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2483 struct kvm_segment ss;
2484 unsigned int ss_rpl;
2486 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2487 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2491 if (ss.type != 3 && ss.type != 7)
2495 if (ss.dpl != ss_rpl) /* DPL != RPL */
2503 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2505 struct kvm_segment var;
2508 vmx_get_segment(vcpu, &var, seg);
2509 rpl = var.selector & SELECTOR_RPL_MASK;
2517 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2518 if (var.dpl < rpl) /* DPL < RPL */
2522 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2528 static bool tr_valid(struct kvm_vcpu *vcpu)
2530 struct kvm_segment tr;
2532 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2536 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2538 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2546 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2548 struct kvm_segment ldtr;
2550 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2554 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2564 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2566 struct kvm_segment cs, ss;
2568 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2569 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2571 return ((cs.selector & SELECTOR_RPL_MASK) ==
2572 (ss.selector & SELECTOR_RPL_MASK));
2576 * Check if guest state is valid. Returns true if valid, false if
2578 * We assume that registers are always usable
2580 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2582 /* real mode guest state checks */
2583 if (!is_protmode(vcpu)) {
2584 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2586 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2588 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2590 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2592 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2594 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2597 /* protected mode guest state checks */
2598 if (!cs_ss_rpl_check(vcpu))
2600 if (!code_segment_valid(vcpu))
2602 if (!stack_segment_valid(vcpu))
2604 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2606 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2608 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2610 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2612 if (!tr_valid(vcpu))
2614 if (!ldtr_valid(vcpu))
2618 * - Add checks on RIP
2619 * - Add checks on RFLAGS
2625 static int init_rmode_tss(struct kvm *kvm)
2629 int r, idx, ret = 0;
2631 idx = srcu_read_lock(&kvm->srcu);
2632 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2633 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2636 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2637 r = kvm_write_guest_page(kvm, fn++, &data,
2638 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2641 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2644 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2648 r = kvm_write_guest_page(kvm, fn, &data,
2649 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2656 srcu_read_unlock(&kvm->srcu, idx);
2660 static int init_rmode_identity_map(struct kvm *kvm)
2663 pfn_t identity_map_pfn;
2668 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2669 printk(KERN_ERR "EPT: identity-mapping pagetable "
2670 "haven't been allocated!\n");
2673 if (likely(kvm->arch.ept_identity_pagetable_done))
2676 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2677 idx = srcu_read_lock(&kvm->srcu);
2678 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2681 /* Set up identity-mapping pagetable for EPT in real mode */
2682 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2683 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2684 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2685 r = kvm_write_guest_page(kvm, identity_map_pfn,
2686 &tmp, i * sizeof(tmp), sizeof(tmp));
2690 kvm->arch.ept_identity_pagetable_done = true;
2693 srcu_read_unlock(&kvm->srcu, idx);
2697 static void seg_setup(int seg)
2699 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2702 vmcs_write16(sf->selector, 0);
2703 vmcs_writel(sf->base, 0);
2704 vmcs_write32(sf->limit, 0xffff);
2705 if (enable_unrestricted_guest) {
2707 if (seg == VCPU_SREG_CS)
2708 ar |= 0x08; /* code segment */
2712 vmcs_write32(sf->ar_bytes, ar);
2715 static int alloc_apic_access_page(struct kvm *kvm)
2717 struct kvm_userspace_memory_region kvm_userspace_mem;
2720 mutex_lock(&kvm->slots_lock);
2721 if (kvm->arch.apic_access_page)
2723 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2724 kvm_userspace_mem.flags = 0;
2725 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2726 kvm_userspace_mem.memory_size = PAGE_SIZE;
2727 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2731 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2733 mutex_unlock(&kvm->slots_lock);
2737 static int alloc_identity_pagetable(struct kvm *kvm)
2739 struct kvm_userspace_memory_region kvm_userspace_mem;
2742 mutex_lock(&kvm->slots_lock);
2743 if (kvm->arch.ept_identity_pagetable)
2745 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2746 kvm_userspace_mem.flags = 0;
2747 kvm_userspace_mem.guest_phys_addr =
2748 kvm->arch.ept_identity_map_addr;
2749 kvm_userspace_mem.memory_size = PAGE_SIZE;
2750 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2754 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2755 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2757 mutex_unlock(&kvm->slots_lock);
2761 static void allocate_vpid(struct vcpu_vmx *vmx)
2768 spin_lock(&vmx_vpid_lock);
2769 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2770 if (vpid < VMX_NR_VPIDS) {
2772 __set_bit(vpid, vmx_vpid_bitmap);
2774 spin_unlock(&vmx_vpid_lock);
2777 static void free_vpid(struct vcpu_vmx *vmx)
2781 spin_lock(&vmx_vpid_lock);
2783 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2784 spin_unlock(&vmx_vpid_lock);
2787 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2789 int f = sizeof(unsigned long);
2791 if (!cpu_has_vmx_msr_bitmap())
2795 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2796 * have the write-low and read-high bitmap offsets the wrong way round.
2797 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2799 if (msr <= 0x1fff) {
2800 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2801 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2802 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2804 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2805 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2809 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2812 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2813 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2817 * Sets up the vmcs for emulated real mode.
2819 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2821 u32 host_sysenter_cs, msr_low, msr_high;
2827 unsigned long kvm_vmx_return;
2831 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2832 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2834 if (cpu_has_vmx_msr_bitmap())
2835 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2837 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2840 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2841 vmcs_config.pin_based_exec_ctrl);
2843 exec_control = vmcs_config.cpu_based_exec_ctrl;
2844 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2845 exec_control &= ~CPU_BASED_TPR_SHADOW;
2846 #ifdef CONFIG_X86_64
2847 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2848 CPU_BASED_CR8_LOAD_EXITING;
2852 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2853 CPU_BASED_CR3_LOAD_EXITING |
2854 CPU_BASED_INVLPG_EXITING;
2855 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2857 if (cpu_has_secondary_exec_ctrls()) {
2858 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2859 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2861 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2863 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2865 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2866 enable_unrestricted_guest = 0;
2868 if (!enable_unrestricted_guest)
2869 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2871 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2872 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2876 vmcs_write32(PLE_GAP, ple_gap);
2877 vmcs_write32(PLE_WINDOW, ple_window);
2880 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2881 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2882 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2884 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2885 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2886 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2888 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2889 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2890 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2891 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2892 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2893 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2894 #ifdef CONFIG_X86_64
2895 rdmsrl(MSR_FS_BASE, a);
2896 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2897 rdmsrl(MSR_GS_BASE, a);
2898 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2900 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2901 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2904 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2906 native_store_idt(&dt);
2907 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2909 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2910 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2911 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2912 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2913 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2914 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2915 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2917 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2918 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2919 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2920 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2921 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2922 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2924 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2925 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2926 host_pat = msr_low | ((u64) msr_high << 32);
2927 vmcs_write64(HOST_IA32_PAT, host_pat);
2929 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2930 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2931 host_pat = msr_low | ((u64) msr_high << 32);
2932 /* Write the default value follow host pat */
2933 vmcs_write64(GUEST_IA32_PAT, host_pat);
2934 /* Keep arch.pat sync with GUEST_IA32_PAT */
2935 vmx->vcpu.arch.pat = host_pat;
2938 for (i = 0; i < NR_VMX_MSR; ++i) {
2939 u32 index = vmx_msr_index[i];
2940 u32 data_low, data_high;
2943 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2945 if (wrmsr_safe(index, data_low, data_high) < 0)
2947 vmx->guest_msrs[j].index = i;
2948 vmx->guest_msrs[j].data = 0;
2949 vmx->guest_msrs[j].mask = -1ull;
2953 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2955 /* 22.2.1, 20.8.1 */
2956 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2958 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2959 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2961 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2962 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2964 kvm_write_tsc(&vmx->vcpu, 0);
2969 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2971 struct vcpu_vmx *vmx = to_vmx(vcpu);
2975 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2977 vmx->rmode.vm86_active = 0;
2979 vmx->soft_vnmi_blocked = 0;
2981 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2982 kvm_set_cr8(&vmx->vcpu, 0);
2983 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2984 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2985 msr |= MSR_IA32_APICBASE_BSP;
2986 kvm_set_apic_base(&vmx->vcpu, msr);
2988 ret = fx_init(&vmx->vcpu);
2992 vmx_segment_cache_clear(vmx);
2994 seg_setup(VCPU_SREG_CS);
2996 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2997 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2999 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3000 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3001 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3003 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3004 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3007 seg_setup(VCPU_SREG_DS);
3008 seg_setup(VCPU_SREG_ES);
3009 seg_setup(VCPU_SREG_FS);
3010 seg_setup(VCPU_SREG_GS);
3011 seg_setup(VCPU_SREG_SS);
3013 vmcs_write16(GUEST_TR_SELECTOR, 0);
3014 vmcs_writel(GUEST_TR_BASE, 0);
3015 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3016 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3018 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3019 vmcs_writel(GUEST_LDTR_BASE, 0);
3020 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3021 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3023 vmcs_write32(GUEST_SYSENTER_CS, 0);
3024 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3025 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3027 vmcs_writel(GUEST_RFLAGS, 0x02);
3028 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3029 kvm_rip_write(vcpu, 0xfff0);
3031 kvm_rip_write(vcpu, 0);
3032 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3034 vmcs_writel(GUEST_DR7, 0x400);
3036 vmcs_writel(GUEST_GDTR_BASE, 0);
3037 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3039 vmcs_writel(GUEST_IDTR_BASE, 0);
3040 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3042 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3043 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3044 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3046 /* Special registers */
3047 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3053 if (cpu_has_vmx_tpr_shadow()) {
3054 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3055 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3056 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3057 __pa(vmx->vcpu.arch.apic->regs));
3058 vmcs_write32(TPR_THRESHOLD, 0);
3061 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3062 vmcs_write64(APIC_ACCESS_ADDR,
3063 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3066 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3068 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3069 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3070 vmx_set_cr4(&vmx->vcpu, 0);
3071 vmx_set_efer(&vmx->vcpu, 0);
3072 vmx_fpu_activate(&vmx->vcpu);
3073 update_exception_bitmap(&vmx->vcpu);
3075 vpid_sync_context(vmx);
3079 /* HACK: Don't enable emulation on guest boot/reset */
3080 vmx->emulation_required = 0;
3086 static void enable_irq_window(struct kvm_vcpu *vcpu)
3088 u32 cpu_based_vm_exec_control;
3090 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3091 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3092 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3095 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3097 u32 cpu_based_vm_exec_control;
3099 if (!cpu_has_virtual_nmis()) {
3100 enable_irq_window(vcpu);
3104 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3105 enable_irq_window(vcpu);
3108 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3109 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3110 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3113 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3115 struct vcpu_vmx *vmx = to_vmx(vcpu);
3117 int irq = vcpu->arch.interrupt.nr;
3119 trace_kvm_inj_virq(irq);
3121 ++vcpu->stat.irq_injections;
3122 if (vmx->rmode.vm86_active) {
3124 if (vcpu->arch.interrupt.soft)
3125 inc_eip = vcpu->arch.event_exit_inst_len;
3126 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3127 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3130 intr = irq | INTR_INFO_VALID_MASK;
3131 if (vcpu->arch.interrupt.soft) {
3132 intr |= INTR_TYPE_SOFT_INTR;
3133 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3134 vmx->vcpu.arch.event_exit_inst_len);
3136 intr |= INTR_TYPE_EXT_INTR;
3137 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3138 vmx_clear_hlt(vcpu);
3141 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3143 struct vcpu_vmx *vmx = to_vmx(vcpu);
3145 if (!cpu_has_virtual_nmis()) {
3147 * Tracking the NMI-blocked state in software is built upon
3148 * finding the next open IRQ window. This, in turn, depends on
3149 * well-behaving guests: They have to keep IRQs disabled at
3150 * least as long as the NMI handler runs. Otherwise we may
3151 * cause NMI nesting, maybe breaking the guest. But as this is
3152 * highly unlikely, we can live with the residual risk.
3154 vmx->soft_vnmi_blocked = 1;
3155 vmx->vnmi_blocked_time = 0;
3158 ++vcpu->stat.nmi_injections;
3159 vmx->nmi_known_unmasked = false;
3160 if (vmx->rmode.vm86_active) {
3161 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3162 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3165 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3166 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3167 vmx_clear_hlt(vcpu);
3170 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3172 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3175 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3176 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3177 | GUEST_INTR_STATE_NMI));
3180 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3182 if (!cpu_has_virtual_nmis())
3183 return to_vmx(vcpu)->soft_vnmi_blocked;
3184 if (to_vmx(vcpu)->nmi_known_unmasked)
3186 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3189 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3191 struct vcpu_vmx *vmx = to_vmx(vcpu);
3193 if (!cpu_has_virtual_nmis()) {
3194 if (vmx->soft_vnmi_blocked != masked) {
3195 vmx->soft_vnmi_blocked = masked;
3196 vmx->vnmi_blocked_time = 0;
3199 vmx->nmi_known_unmasked = !masked;
3201 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3202 GUEST_INTR_STATE_NMI);
3204 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3205 GUEST_INTR_STATE_NMI);
3209 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3211 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3212 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3213 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3216 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3219 struct kvm_userspace_memory_region tss_mem = {
3220 .slot = TSS_PRIVATE_MEMSLOT,
3221 .guest_phys_addr = addr,
3222 .memory_size = PAGE_SIZE * 3,
3226 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3229 kvm->arch.tss_addr = addr;
3230 if (!init_rmode_tss(kvm))
3236 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3237 int vec, u32 err_code)
3240 * Instruction with address size override prefix opcode 0x67
3241 * Cause the #SS fault with 0 error code in VM86 mode.
3243 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3244 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
3247 * Forward all other exceptions that are valid in real mode.
3248 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3249 * the required debugging infrastructure rework.
3253 if (vcpu->guest_debug &
3254 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3256 kvm_queue_exception(vcpu, vec);
3260 * Update instruction length as we may reinject the exception
3261 * from user space while in guest debugging mode.
3263 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3264 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3265 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3276 kvm_queue_exception(vcpu, vec);
3283 * Trigger machine check on the host. We assume all the MSRs are already set up
3284 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3285 * We pass a fake environment to the machine check handler because we want
3286 * the guest to be always treated like user space, no matter what context
3287 * it used internally.
3289 static void kvm_machine_check(void)
3291 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3292 struct pt_regs regs = {
3293 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3294 .flags = X86_EFLAGS_IF,
3297 do_machine_check(®s, 0);
3301 static int handle_machine_check(struct kvm_vcpu *vcpu)
3303 /* already handled by vcpu_run */
3307 static int handle_exception(struct kvm_vcpu *vcpu)
3309 struct vcpu_vmx *vmx = to_vmx(vcpu);
3310 struct kvm_run *kvm_run = vcpu->run;
3311 u32 intr_info, ex_no, error_code;
3312 unsigned long cr2, rip, dr6;
3314 enum emulation_result er;
3316 vect_info = vmx->idt_vectoring_info;
3317 intr_info = vmx->exit_intr_info;
3319 if (is_machine_check(intr_info))
3320 return handle_machine_check(vcpu);
3322 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3323 !is_page_fault(intr_info)) {
3324 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3325 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3326 vcpu->run->internal.ndata = 2;
3327 vcpu->run->internal.data[0] = vect_info;
3328 vcpu->run->internal.data[1] = intr_info;
3332 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3333 return 1; /* already handled by vmx_vcpu_run() */
3335 if (is_no_device(intr_info)) {
3336 vmx_fpu_activate(vcpu);
3340 if (is_invalid_opcode(intr_info)) {
3341 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
3342 if (er != EMULATE_DONE)
3343 kvm_queue_exception(vcpu, UD_VECTOR);
3348 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3349 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3350 if (is_page_fault(intr_info)) {
3351 /* EPT won't cause page fault directly */
3354 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3355 trace_kvm_page_fault(cr2, error_code);
3357 if (kvm_event_needs_reinjection(vcpu))
3358 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3359 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
3362 if (vmx->rmode.vm86_active &&
3363 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3365 if (vcpu->arch.halt_request) {
3366 vcpu->arch.halt_request = 0;
3367 return kvm_emulate_halt(vcpu);
3372 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3375 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3376 if (!(vcpu->guest_debug &
3377 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3378 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3379 kvm_queue_exception(vcpu, DB_VECTOR);
3382 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3383 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3387 * Update instruction length as we may reinject #BP from
3388 * user space while in guest debugging mode. Reading it for
3389 * #DB as well causes no harm, it is not used in that case.
3391 vmx->vcpu.arch.event_exit_inst_len =
3392 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3393 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3394 rip = kvm_rip_read(vcpu);
3395 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3396 kvm_run->debug.arch.exception = ex_no;
3399 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3400 kvm_run->ex.exception = ex_no;
3401 kvm_run->ex.error_code = error_code;
3407 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3409 ++vcpu->stat.irq_exits;
3413 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3415 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3419 static int handle_io(struct kvm_vcpu *vcpu)
3421 unsigned long exit_qualification;
3422 int size, in, string;
3425 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3426 string = (exit_qualification & 16) != 0;
3427 in = (exit_qualification & 8) != 0;
3429 ++vcpu->stat.io_exits;
3432 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3434 port = exit_qualification >> 16;
3435 size = (exit_qualification & 7) + 1;
3436 skip_emulated_instruction(vcpu);
3438 return kvm_fast_pio_out(vcpu, size, port);
3442 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3445 * Patch in the VMCALL instruction:
3447 hypercall[0] = 0x0f;
3448 hypercall[1] = 0x01;
3449 hypercall[2] = 0xc1;
3452 static int handle_cr(struct kvm_vcpu *vcpu)
3454 unsigned long exit_qualification, val;
3459 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3460 cr = exit_qualification & 15;
3461 reg = (exit_qualification >> 8) & 15;
3462 switch ((exit_qualification >> 4) & 3) {
3463 case 0: /* mov to cr */
3464 val = kvm_register_read(vcpu, reg);
3465 trace_kvm_cr_write(cr, val);
3468 err = kvm_set_cr0(vcpu, val);
3469 kvm_complete_insn_gp(vcpu, err);
3472 err = kvm_set_cr3(vcpu, val);
3473 kvm_complete_insn_gp(vcpu, err);
3476 err = kvm_set_cr4(vcpu, val);
3477 kvm_complete_insn_gp(vcpu, err);
3480 u8 cr8_prev = kvm_get_cr8(vcpu);
3481 u8 cr8 = kvm_register_read(vcpu, reg);
3482 err = kvm_set_cr8(vcpu, cr8);
3483 kvm_complete_insn_gp(vcpu, err);
3484 if (irqchip_in_kernel(vcpu->kvm))
3486 if (cr8_prev <= cr8)
3488 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3494 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3495 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3496 skip_emulated_instruction(vcpu);
3497 vmx_fpu_activate(vcpu);
3499 case 1: /*mov from cr*/
3502 val = kvm_read_cr3(vcpu);
3503 kvm_register_write(vcpu, reg, val);
3504 trace_kvm_cr_read(cr, val);
3505 skip_emulated_instruction(vcpu);
3508 val = kvm_get_cr8(vcpu);
3509 kvm_register_write(vcpu, reg, val);
3510 trace_kvm_cr_read(cr, val);
3511 skip_emulated_instruction(vcpu);
3516 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3517 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3518 kvm_lmsw(vcpu, val);
3520 skip_emulated_instruction(vcpu);
3525 vcpu->run->exit_reason = 0;
3526 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3527 (int)(exit_qualification >> 4) & 3, cr);
3531 static int handle_dr(struct kvm_vcpu *vcpu)
3533 unsigned long exit_qualification;
3536 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3537 if (!kvm_require_cpl(vcpu, 0))
3539 dr = vmcs_readl(GUEST_DR7);
3542 * As the vm-exit takes precedence over the debug trap, we
3543 * need to emulate the latter, either for the host or the
3544 * guest debugging itself.
3546 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3547 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3548 vcpu->run->debug.arch.dr7 = dr;
3549 vcpu->run->debug.arch.pc =
3550 vmcs_readl(GUEST_CS_BASE) +
3551 vmcs_readl(GUEST_RIP);
3552 vcpu->run->debug.arch.exception = DB_VECTOR;
3553 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3556 vcpu->arch.dr7 &= ~DR7_GD;
3557 vcpu->arch.dr6 |= DR6_BD;
3558 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3559 kvm_queue_exception(vcpu, DB_VECTOR);
3564 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3565 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3566 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3567 if (exit_qualification & TYPE_MOV_FROM_DR) {
3569 if (!kvm_get_dr(vcpu, dr, &val))
3570 kvm_register_write(vcpu, reg, val);
3572 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3573 skip_emulated_instruction(vcpu);
3577 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3579 vmcs_writel(GUEST_DR7, val);
3582 static int handle_cpuid(struct kvm_vcpu *vcpu)
3584 kvm_emulate_cpuid(vcpu);
3588 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3590 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3593 if (vmx_get_msr(vcpu, ecx, &data)) {
3594 trace_kvm_msr_read_ex(ecx);
3595 kvm_inject_gp(vcpu, 0);
3599 trace_kvm_msr_read(ecx, data);
3601 /* FIXME: handling of bits 32:63 of rax, rdx */
3602 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3603 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3604 skip_emulated_instruction(vcpu);
3608 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3610 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3611 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3612 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3614 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3615 trace_kvm_msr_write_ex(ecx, data);
3616 kvm_inject_gp(vcpu, 0);
3620 trace_kvm_msr_write(ecx, data);
3621 skip_emulated_instruction(vcpu);
3625 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3627 kvm_make_request(KVM_REQ_EVENT, vcpu);
3631 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3633 u32 cpu_based_vm_exec_control;
3635 /* clear pending irq */
3636 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3637 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3638 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3640 kvm_make_request(KVM_REQ_EVENT, vcpu);
3642 ++vcpu->stat.irq_window_exits;
3645 * If the user space waits to inject interrupts, exit as soon as
3648 if (!irqchip_in_kernel(vcpu->kvm) &&
3649 vcpu->run->request_interrupt_window &&
3650 !kvm_cpu_has_interrupt(vcpu)) {
3651 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3657 static int handle_halt(struct kvm_vcpu *vcpu)
3659 skip_emulated_instruction(vcpu);
3660 return kvm_emulate_halt(vcpu);
3663 static int handle_vmcall(struct kvm_vcpu *vcpu)
3665 skip_emulated_instruction(vcpu);
3666 kvm_emulate_hypercall(vcpu);
3670 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3672 kvm_queue_exception(vcpu, UD_VECTOR);
3676 static int handle_invd(struct kvm_vcpu *vcpu)
3678 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3681 static int handle_invlpg(struct kvm_vcpu *vcpu)
3683 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3685 kvm_mmu_invlpg(vcpu, exit_qualification);
3686 skip_emulated_instruction(vcpu);
3690 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3692 skip_emulated_instruction(vcpu);
3693 kvm_emulate_wbinvd(vcpu);
3697 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3699 u64 new_bv = kvm_read_edx_eax(vcpu);
3700 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3702 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3703 skip_emulated_instruction(vcpu);
3707 static int handle_apic_access(struct kvm_vcpu *vcpu)
3709 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
3712 static int handle_task_switch(struct kvm_vcpu *vcpu)
3714 struct vcpu_vmx *vmx = to_vmx(vcpu);
3715 unsigned long exit_qualification;
3716 bool has_error_code = false;
3719 int reason, type, idt_v;
3721 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3722 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3724 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3726 reason = (u32)exit_qualification >> 30;
3727 if (reason == TASK_SWITCH_GATE && idt_v) {
3729 case INTR_TYPE_NMI_INTR:
3730 vcpu->arch.nmi_injected = false;
3731 vmx_set_nmi_mask(vcpu, true);
3733 case INTR_TYPE_EXT_INTR:
3734 case INTR_TYPE_SOFT_INTR:
3735 kvm_clear_interrupt_queue(vcpu);
3737 case INTR_TYPE_HARD_EXCEPTION:
3738 if (vmx->idt_vectoring_info &
3739 VECTORING_INFO_DELIVER_CODE_MASK) {
3740 has_error_code = true;
3742 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3745 case INTR_TYPE_SOFT_EXCEPTION:
3746 kvm_clear_exception_queue(vcpu);
3752 tss_selector = exit_qualification;
3754 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3755 type != INTR_TYPE_EXT_INTR &&
3756 type != INTR_TYPE_NMI_INTR))
3757 skip_emulated_instruction(vcpu);
3759 if (kvm_task_switch(vcpu, tss_selector, reason,
3760 has_error_code, error_code) == EMULATE_FAIL) {
3761 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3762 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3763 vcpu->run->internal.ndata = 0;
3767 /* clear all local breakpoint enable flags */
3768 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3771 * TODO: What about debug traps on tss switch?
3772 * Are we supposed to inject them and update dr6?
3778 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3780 unsigned long exit_qualification;
3784 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3786 if (exit_qualification & (1 << 6)) {
3787 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3791 gla_validity = (exit_qualification >> 7) & 0x3;
3792 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3793 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3794 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3795 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3796 vmcs_readl(GUEST_LINEAR_ADDRESS));
3797 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3798 (long unsigned int)exit_qualification);
3799 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3800 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3804 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3805 trace_kvm_page_fault(gpa, exit_qualification);
3806 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
3809 static u64 ept_rsvd_mask(u64 spte, int level)
3814 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3815 mask |= (1ULL << i);
3818 /* bits 7:3 reserved */
3820 else if (level == 2) {
3821 if (spte & (1ULL << 7))
3822 /* 2MB ref, bits 20:12 reserved */
3825 /* bits 6:3 reserved */
3832 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3835 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3837 /* 010b (write-only) */
3838 WARN_ON((spte & 0x7) == 0x2);
3840 /* 110b (write/execute) */
3841 WARN_ON((spte & 0x7) == 0x6);
3843 /* 100b (execute-only) and value not supported by logical processor */
3844 if (!cpu_has_vmx_ept_execute_only())
3845 WARN_ON((spte & 0x7) == 0x4);
3849 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3851 if (rsvd_bits != 0) {
3852 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3853 __func__, rsvd_bits);
3857 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3858 u64 ept_mem_type = (spte & 0x38) >> 3;
3860 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3861 ept_mem_type == 7) {
3862 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3863 __func__, ept_mem_type);
3870 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3876 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3878 printk(KERN_ERR "EPT: Misconfiguration.\n");
3879 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3881 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3883 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3884 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3886 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3887 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3892 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3894 u32 cpu_based_vm_exec_control;
3896 /* clear pending NMI */
3897 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3898 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3899 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3900 ++vcpu->stat.nmi_window_exits;
3901 kvm_make_request(KVM_REQ_EVENT, vcpu);
3906 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3908 struct vcpu_vmx *vmx = to_vmx(vcpu);
3909 enum emulation_result err = EMULATE_DONE;
3912 bool intr_window_requested;
3914 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3915 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3917 while (!guest_state_valid(vcpu)) {
3918 if (intr_window_requested
3919 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3920 return handle_interrupt_window(&vmx->vcpu);
3922 err = emulate_instruction(vcpu, 0);
3924 if (err == EMULATE_DO_MMIO) {
3929 if (err != EMULATE_DONE)
3932 if (signal_pending(current))
3938 vmx->emulation_required = 0;
3944 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3945 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3947 static int handle_pause(struct kvm_vcpu *vcpu)
3949 skip_emulated_instruction(vcpu);
3950 kvm_vcpu_on_spin(vcpu);
3955 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3957 kvm_queue_exception(vcpu, UD_VECTOR);
3962 * Emulate the VMXON instruction.
3963 * Currently, we just remember that VMX is active, and do not save or even
3964 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
3965 * do not currently need to store anything in that guest-allocated memory
3966 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
3967 * argument is different from the VMXON pointer (which the spec says they do).
3969 static int handle_vmon(struct kvm_vcpu *vcpu)
3971 struct kvm_segment cs;
3972 struct vcpu_vmx *vmx = to_vmx(vcpu);
3974 /* The Intel VMX Instruction Reference lists a bunch of bits that
3975 * are prerequisite to running VMXON, most notably cr4.VMXE must be
3976 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
3977 * Otherwise, we should fail with #UD. We test these now:
3979 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
3980 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
3981 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
3982 kvm_queue_exception(vcpu, UD_VECTOR);
3986 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3987 if (is_long_mode(vcpu) && !cs.l) {
3988 kvm_queue_exception(vcpu, UD_VECTOR);
3992 if (vmx_get_cpl(vcpu)) {
3993 kvm_inject_gp(vcpu, 0);
3997 vmx->nested.vmxon = true;
3999 skip_emulated_instruction(vcpu);
4004 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4005 * for running VMX instructions (except VMXON, whose prerequisites are
4006 * slightly different). It also specifies what exception to inject otherwise.
4008 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4010 struct kvm_segment cs;
4011 struct vcpu_vmx *vmx = to_vmx(vcpu);
4013 if (!vmx->nested.vmxon) {
4014 kvm_queue_exception(vcpu, UD_VECTOR);
4018 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4019 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4020 (is_long_mode(vcpu) && !cs.l)) {
4021 kvm_queue_exception(vcpu, UD_VECTOR);
4025 if (vmx_get_cpl(vcpu)) {
4026 kvm_inject_gp(vcpu, 0);
4034 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4035 * just stops using VMX.
4037 static void free_nested(struct vcpu_vmx *vmx)
4039 if (!vmx->nested.vmxon)
4041 vmx->nested.vmxon = false;
4044 /* Emulate the VMXOFF instruction */
4045 static int handle_vmoff(struct kvm_vcpu *vcpu)
4047 if (!nested_vmx_check_permission(vcpu))
4049 free_nested(to_vmx(vcpu));
4050 skip_emulated_instruction(vcpu);
4055 * The exit handlers return 1 if the exit was handled fully and guest execution
4056 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
4057 * to be done to userspace and return 0.
4059 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
4060 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
4061 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
4062 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
4063 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
4064 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
4065 [EXIT_REASON_CR_ACCESS] = handle_cr,
4066 [EXIT_REASON_DR_ACCESS] = handle_dr,
4067 [EXIT_REASON_CPUID] = handle_cpuid,
4068 [EXIT_REASON_MSR_READ] = handle_rdmsr,
4069 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
4070 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
4071 [EXIT_REASON_HLT] = handle_halt,
4072 [EXIT_REASON_INVD] = handle_invd,
4073 [EXIT_REASON_INVLPG] = handle_invlpg,
4074 [EXIT_REASON_VMCALL] = handle_vmcall,
4075 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
4076 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
4077 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
4078 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
4079 [EXIT_REASON_VMREAD] = handle_vmx_insn,
4080 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
4081 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
4082 [EXIT_REASON_VMOFF] = handle_vmoff,
4083 [EXIT_REASON_VMON] = handle_vmon,
4084 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
4085 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
4086 [EXIT_REASON_WBINVD] = handle_wbinvd,
4087 [EXIT_REASON_XSETBV] = handle_xsetbv,
4088 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
4089 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
4090 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
4091 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4092 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
4093 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
4094 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
4097 static const int kvm_vmx_max_exit_handlers =
4098 ARRAY_SIZE(kvm_vmx_exit_handlers);
4100 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4102 *info1 = vmcs_readl(EXIT_QUALIFICATION);
4103 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
4107 * The guest has exited. See if we can fix it or if we need userspace
4110 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
4112 struct vcpu_vmx *vmx = to_vmx(vcpu);
4113 u32 exit_reason = vmx->exit_reason;
4114 u32 vectoring_info = vmx->idt_vectoring_info;
4116 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
4118 /* If guest state is invalid, start emulating */
4119 if (vmx->emulation_required && emulate_invalid_guest_state)
4120 return handle_invalid_guest_state(vcpu);
4122 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
4123 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4124 vcpu->run->fail_entry.hardware_entry_failure_reason
4129 if (unlikely(vmx->fail)) {
4130 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4131 vcpu->run->fail_entry.hardware_entry_failure_reason
4132 = vmcs_read32(VM_INSTRUCTION_ERROR);
4136 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
4137 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
4138 exit_reason != EXIT_REASON_EPT_VIOLATION &&
4139 exit_reason != EXIT_REASON_TASK_SWITCH))
4140 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
4141 "(0x%x) and exit reason is 0x%x\n",
4142 __func__, vectoring_info, exit_reason);
4144 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
4145 if (vmx_interrupt_allowed(vcpu)) {
4146 vmx->soft_vnmi_blocked = 0;
4147 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4148 vcpu->arch.nmi_pending) {
4150 * This CPU don't support us in finding the end of an
4151 * NMI-blocked window if the guest runs with IRQs
4152 * disabled. So we pull the trigger after 1 s of
4153 * futile waiting, but inform the user about this.
4155 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
4156 "state on VCPU %d after 1 s timeout\n",
4157 __func__, vcpu->vcpu_id);
4158 vmx->soft_vnmi_blocked = 0;
4162 if (exit_reason < kvm_vmx_max_exit_handlers
4163 && kvm_vmx_exit_handlers[exit_reason])
4164 return kvm_vmx_exit_handlers[exit_reason](vcpu);
4166 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4167 vcpu->run->hw.hardware_exit_reason = exit_reason;
4172 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4174 if (irr == -1 || tpr < irr) {
4175 vmcs_write32(TPR_THRESHOLD, 0);
4179 vmcs_write32(TPR_THRESHOLD, irr);
4182 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
4186 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
4187 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
4190 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4191 exit_intr_info = vmx->exit_intr_info;
4193 /* Handle machine checks before interrupts are enabled */
4194 if (is_machine_check(exit_intr_info))
4195 kvm_machine_check();
4197 /* We need to handle NMIs before interrupts are enabled */
4198 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
4199 (exit_intr_info & INTR_INFO_VALID_MASK)) {
4200 kvm_before_handle_nmi(&vmx->vcpu);
4202 kvm_after_handle_nmi(&vmx->vcpu);
4206 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
4211 bool idtv_info_valid;
4213 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4215 if (cpu_has_virtual_nmis()) {
4216 if (vmx->nmi_known_unmasked)
4219 * Can't use vmx->exit_intr_info since we're not sure what
4220 * the exit reason is.
4222 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4223 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
4224 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
4226 * SDM 3: 27.7.1.2 (September 2008)
4227 * Re-set bit "block by NMI" before VM entry if vmexit caused by
4228 * a guest IRET fault.
4229 * SDM 3: 23.2.2 (September 2008)
4230 * Bit 12 is undefined in any of the following cases:
4231 * If the VM exit sets the valid bit in the IDT-vectoring
4232 * information field.
4233 * If the VM exit is due to a double fault.
4235 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
4236 vector != DF_VECTOR && !idtv_info_valid)
4237 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4238 GUEST_INTR_STATE_NMI);
4240 vmx->nmi_known_unmasked =
4241 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
4242 & GUEST_INTR_STATE_NMI);
4243 } else if (unlikely(vmx->soft_vnmi_blocked))
4244 vmx->vnmi_blocked_time +=
4245 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
4248 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
4249 u32 idt_vectoring_info,
4250 int instr_len_field,
4251 int error_code_field)
4255 bool idtv_info_valid;
4257 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
4259 vmx->vcpu.arch.nmi_injected = false;
4260 kvm_clear_exception_queue(&vmx->vcpu);
4261 kvm_clear_interrupt_queue(&vmx->vcpu);
4263 if (!idtv_info_valid)
4266 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
4268 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
4269 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
4272 case INTR_TYPE_NMI_INTR:
4273 vmx->vcpu.arch.nmi_injected = true;
4275 * SDM 3: 27.7.1.2 (September 2008)
4276 * Clear bit "block by NMI" before VM entry if a NMI
4279 vmx_set_nmi_mask(&vmx->vcpu, false);
4281 case INTR_TYPE_SOFT_EXCEPTION:
4282 vmx->vcpu.arch.event_exit_inst_len =
4283 vmcs_read32(instr_len_field);
4285 case INTR_TYPE_HARD_EXCEPTION:
4286 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
4287 u32 err = vmcs_read32(error_code_field);
4288 kvm_queue_exception_e(&vmx->vcpu, vector, err);
4290 kvm_queue_exception(&vmx->vcpu, vector);
4292 case INTR_TYPE_SOFT_INTR:
4293 vmx->vcpu.arch.event_exit_inst_len =
4294 vmcs_read32(instr_len_field);
4296 case INTR_TYPE_EXT_INTR:
4297 kvm_queue_interrupt(&vmx->vcpu, vector,
4298 type == INTR_TYPE_SOFT_INTR);
4305 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4307 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4308 VM_EXIT_INSTRUCTION_LEN,
4309 IDT_VECTORING_ERROR_CODE);
4312 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4314 __vmx_complete_interrupts(to_vmx(vcpu),
4315 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4316 VM_ENTRY_INSTRUCTION_LEN,
4317 VM_ENTRY_EXCEPTION_ERROR_CODE);
4319 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4322 #ifdef CONFIG_X86_64
4330 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
4332 struct vcpu_vmx *vmx = to_vmx(vcpu);
4334 /* Record the guest's net vcpu time for enforced NMI injections. */
4335 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4336 vmx->entry_time = ktime_get();
4338 /* Don't enter VMX if guest state is invalid, let the exit handler
4339 start emulation until we arrive back to a valid state */
4340 if (vmx->emulation_required && emulate_invalid_guest_state)
4343 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4344 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4345 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4346 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4348 /* When single-stepping over STI and MOV SS, we must clear the
4349 * corresponding interruptibility bits in the guest state. Otherwise
4350 * vmentry fails as it then expects bit 14 (BS) in pending debug
4351 * exceptions being set, but that's not correct for the guest debugging
4353 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4354 vmx_set_interrupt_shadow(vcpu, 0);
4356 vmx->__launched = vmx->loaded_vmcs->launched;
4358 /* Store host registers */
4359 "push %%"R"dx; push %%"R"bp;"
4360 "push %%"R"cx \n\t" /* placeholder for guest rcx */
4362 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4364 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4365 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
4367 /* Reload cr2 if changed */
4368 "mov %c[cr2](%0), %%"R"ax \n\t"
4369 "mov %%cr2, %%"R"dx \n\t"
4370 "cmp %%"R"ax, %%"R"dx \n\t"
4372 "mov %%"R"ax, %%cr2 \n\t"
4374 /* Check if vmlaunch of vmresume is needed */
4375 "cmpl $0, %c[launched](%0) \n\t"
4376 /* Load guest registers. Don't clobber flags. */
4377 "mov %c[rax](%0), %%"R"ax \n\t"
4378 "mov %c[rbx](%0), %%"R"bx \n\t"
4379 "mov %c[rdx](%0), %%"R"dx \n\t"
4380 "mov %c[rsi](%0), %%"R"si \n\t"
4381 "mov %c[rdi](%0), %%"R"di \n\t"
4382 "mov %c[rbp](%0), %%"R"bp \n\t"
4383 #ifdef CONFIG_X86_64
4384 "mov %c[r8](%0), %%r8 \n\t"
4385 "mov %c[r9](%0), %%r9 \n\t"
4386 "mov %c[r10](%0), %%r10 \n\t"
4387 "mov %c[r11](%0), %%r11 \n\t"
4388 "mov %c[r12](%0), %%r12 \n\t"
4389 "mov %c[r13](%0), %%r13 \n\t"
4390 "mov %c[r14](%0), %%r14 \n\t"
4391 "mov %c[r15](%0), %%r15 \n\t"
4393 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4395 /* Enter guest mode */
4396 "jne .Llaunched \n\t"
4397 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4398 "jmp .Lkvm_vmx_return \n\t"
4399 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4400 ".Lkvm_vmx_return: "
4401 /* Save guest registers, load host registers, keep flags */
4402 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4404 "mov %%"R"ax, %c[rax](%0) \n\t"
4405 "mov %%"R"bx, %c[rbx](%0) \n\t"
4406 "pop"Q" %c[rcx](%0) \n\t"
4407 "mov %%"R"dx, %c[rdx](%0) \n\t"
4408 "mov %%"R"si, %c[rsi](%0) \n\t"
4409 "mov %%"R"di, %c[rdi](%0) \n\t"
4410 "mov %%"R"bp, %c[rbp](%0) \n\t"
4411 #ifdef CONFIG_X86_64
4412 "mov %%r8, %c[r8](%0) \n\t"
4413 "mov %%r9, %c[r9](%0) \n\t"
4414 "mov %%r10, %c[r10](%0) \n\t"
4415 "mov %%r11, %c[r11](%0) \n\t"
4416 "mov %%r12, %c[r12](%0) \n\t"
4417 "mov %%r13, %c[r13](%0) \n\t"
4418 "mov %%r14, %c[r14](%0) \n\t"
4419 "mov %%r15, %c[r15](%0) \n\t"
4421 "mov %%cr2, %%"R"ax \n\t"
4422 "mov %%"R"ax, %c[cr2](%0) \n\t"
4424 "pop %%"R"bp; pop %%"R"dx \n\t"
4425 "setbe %c[fail](%0) \n\t"
4426 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4427 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
4428 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4429 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4430 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4431 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4432 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4433 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4434 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4435 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4436 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4437 #ifdef CONFIG_X86_64
4438 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4439 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4440 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4441 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4442 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4443 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4444 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4445 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4447 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4448 [wordsize]"i"(sizeof(ulong))
4450 , R"ax", R"bx", R"di", R"si"
4451 #ifdef CONFIG_X86_64
4452 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4456 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4457 | (1 << VCPU_EXREG_RFLAGS)
4458 | (1 << VCPU_EXREG_CPL)
4459 | (1 << VCPU_EXREG_PDPTR)
4460 | (1 << VCPU_EXREG_SEGMENTS)
4461 | (1 << VCPU_EXREG_CR3));
4462 vcpu->arch.regs_dirty = 0;
4464 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4466 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4467 vmx->loaded_vmcs->launched = 1;
4469 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4471 vmx_complete_atomic_exit(vmx);
4472 vmx_recover_nmi_blocking(vmx);
4473 vmx_complete_interrupts(vmx);
4479 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4481 struct vcpu_vmx *vmx = to_vmx(vcpu);
4485 free_loaded_vmcs(vmx->loaded_vmcs);
4486 kfree(vmx->guest_msrs);
4487 kvm_vcpu_uninit(vcpu);
4488 kmem_cache_free(kvm_vcpu_cache, vmx);
4491 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4494 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4498 return ERR_PTR(-ENOMEM);
4502 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4506 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4508 if (!vmx->guest_msrs) {
4512 vmx->loaded_vmcs = &vmx->vmcs01;
4513 vmx->loaded_vmcs->vmcs = alloc_vmcs();
4514 if (!vmx->loaded_vmcs->vmcs)
4517 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
4518 loaded_vmcs_init(vmx->loaded_vmcs);
4523 vmx_vcpu_load(&vmx->vcpu, cpu);
4524 vmx->vcpu.cpu = cpu;
4525 err = vmx_vcpu_setup(vmx);
4526 vmx_vcpu_put(&vmx->vcpu);
4530 if (vm_need_virtualize_apic_accesses(kvm))
4531 err = alloc_apic_access_page(kvm);
4536 if (!kvm->arch.ept_identity_map_addr)
4537 kvm->arch.ept_identity_map_addr =
4538 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4540 if (alloc_identity_pagetable(kvm) != 0)
4542 if (!init_rmode_identity_map(kvm))
4549 free_vmcs(vmx->loaded_vmcs->vmcs);
4551 kfree(vmx->guest_msrs);
4553 kvm_vcpu_uninit(&vmx->vcpu);
4556 kmem_cache_free(kvm_vcpu_cache, vmx);
4557 return ERR_PTR(err);
4560 static void __init vmx_check_processor_compat(void *rtn)
4562 struct vmcs_config vmcs_conf;
4565 if (setup_vmcs_config(&vmcs_conf) < 0)
4567 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4568 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4569 smp_processor_id());
4574 static int get_ept_level(void)
4576 return VMX_EPT_DEFAULT_GAW + 1;
4579 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4583 /* For VT-d and EPT combination
4584 * 1. MMIO: always map as UC
4586 * a. VT-d without snooping control feature: can't guarantee the
4587 * result, try to trust guest.
4588 * b. VT-d with snooping control feature: snooping control feature of
4589 * VT-d engine can guarantee the cache correctness. Just set it
4590 * to WB to keep consistent with host. So the same as item 3.
4591 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4592 * consistent with host MTRR
4595 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4596 else if (vcpu->kvm->arch.iommu_domain &&
4597 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4598 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4599 VMX_EPT_MT_EPTE_SHIFT;
4601 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4607 #define _ER(x) { EXIT_REASON_##x, #x }
4609 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4611 _ER(EXTERNAL_INTERRUPT),
4613 _ER(PENDING_INTERRUPT),
4633 _ER(IO_INSTRUCTION),
4636 _ER(MWAIT_INSTRUCTION),
4637 _ER(MONITOR_INSTRUCTION),
4638 _ER(PAUSE_INSTRUCTION),
4639 _ER(MCE_DURING_VMENTRY),
4640 _ER(TPR_BELOW_THRESHOLD),
4650 static int vmx_get_lpage_level(void)
4652 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4653 return PT_DIRECTORY_LEVEL;
4655 /* For shadow and EPT supported 1GB page */
4656 return PT_PDPE_LEVEL;
4659 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4661 struct kvm_cpuid_entry2 *best;
4662 struct vcpu_vmx *vmx = to_vmx(vcpu);
4665 vmx->rdtscp_enabled = false;
4666 if (vmx_rdtscp_supported()) {
4667 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4668 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4669 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4670 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4671 vmx->rdtscp_enabled = true;
4673 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4674 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4681 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4685 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
4686 struct x86_instruction_info *info,
4687 enum x86_intercept_stage stage)
4689 return X86EMUL_CONTINUE;
4692 static struct kvm_x86_ops vmx_x86_ops = {
4693 .cpu_has_kvm_support = cpu_has_kvm_support,
4694 .disabled_by_bios = vmx_disabled_by_bios,
4695 .hardware_setup = hardware_setup,
4696 .hardware_unsetup = hardware_unsetup,
4697 .check_processor_compatibility = vmx_check_processor_compat,
4698 .hardware_enable = hardware_enable,
4699 .hardware_disable = hardware_disable,
4700 .cpu_has_accelerated_tpr = report_flexpriority,
4702 .vcpu_create = vmx_create_vcpu,
4703 .vcpu_free = vmx_free_vcpu,
4704 .vcpu_reset = vmx_vcpu_reset,
4706 .prepare_guest_switch = vmx_save_host_state,
4707 .vcpu_load = vmx_vcpu_load,
4708 .vcpu_put = vmx_vcpu_put,
4710 .set_guest_debug = set_guest_debug,
4711 .get_msr = vmx_get_msr,
4712 .set_msr = vmx_set_msr,
4713 .get_segment_base = vmx_get_segment_base,
4714 .get_segment = vmx_get_segment,
4715 .set_segment = vmx_set_segment,
4716 .get_cpl = vmx_get_cpl,
4717 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4718 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4719 .decache_cr3 = vmx_decache_cr3,
4720 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4721 .set_cr0 = vmx_set_cr0,
4722 .set_cr3 = vmx_set_cr3,
4723 .set_cr4 = vmx_set_cr4,
4724 .set_efer = vmx_set_efer,
4725 .get_idt = vmx_get_idt,
4726 .set_idt = vmx_set_idt,
4727 .get_gdt = vmx_get_gdt,
4728 .set_gdt = vmx_set_gdt,
4729 .set_dr7 = vmx_set_dr7,
4730 .cache_reg = vmx_cache_reg,
4731 .get_rflags = vmx_get_rflags,
4732 .set_rflags = vmx_set_rflags,
4733 .fpu_activate = vmx_fpu_activate,
4734 .fpu_deactivate = vmx_fpu_deactivate,
4736 .tlb_flush = vmx_flush_tlb,
4738 .run = vmx_vcpu_run,
4739 .handle_exit = vmx_handle_exit,
4740 .skip_emulated_instruction = skip_emulated_instruction,
4741 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4742 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4743 .patch_hypercall = vmx_patch_hypercall,
4744 .set_irq = vmx_inject_irq,
4745 .set_nmi = vmx_inject_nmi,
4746 .queue_exception = vmx_queue_exception,
4747 .cancel_injection = vmx_cancel_injection,
4748 .interrupt_allowed = vmx_interrupt_allowed,
4749 .nmi_allowed = vmx_nmi_allowed,
4750 .get_nmi_mask = vmx_get_nmi_mask,
4751 .set_nmi_mask = vmx_set_nmi_mask,
4752 .enable_nmi_window = enable_nmi_window,
4753 .enable_irq_window = enable_irq_window,
4754 .update_cr8_intercept = update_cr8_intercept,
4756 .set_tss_addr = vmx_set_tss_addr,
4757 .get_tdp_level = get_ept_level,
4758 .get_mt_mask = vmx_get_mt_mask,
4760 .get_exit_info = vmx_get_exit_info,
4761 .exit_reasons_str = vmx_exit_reasons_str,
4763 .get_lpage_level = vmx_get_lpage_level,
4765 .cpuid_update = vmx_cpuid_update,
4767 .rdtscp_supported = vmx_rdtscp_supported,
4769 .set_supported_cpuid = vmx_set_supported_cpuid,
4771 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4773 .set_tsc_khz = vmx_set_tsc_khz,
4774 .write_tsc_offset = vmx_write_tsc_offset,
4775 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4776 .compute_tsc_offset = vmx_compute_tsc_offset,
4778 .set_tdp_cr3 = vmx_set_cr3,
4780 .check_intercept = vmx_check_intercept,
4783 static int __init vmx_init(void)
4787 rdmsrl_safe(MSR_EFER, &host_efer);
4789 for (i = 0; i < NR_VMX_MSR; ++i)
4790 kvm_define_shared_msr(i, vmx_msr_index[i]);
4792 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4793 if (!vmx_io_bitmap_a)
4796 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4797 if (!vmx_io_bitmap_b) {
4802 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4803 if (!vmx_msr_bitmap_legacy) {
4808 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4809 if (!vmx_msr_bitmap_longmode) {
4815 * Allow direct access to the PC debug port (it is often used for I/O
4816 * delays, but the vmexits simply slow things down).
4818 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4819 clear_bit(0x80, vmx_io_bitmap_a);
4821 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4823 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4824 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4826 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4828 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4829 __alignof__(struct vcpu_vmx), THIS_MODULE);
4833 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4834 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4835 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4836 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4837 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4838 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4841 bypass_guest_pf = 0;
4842 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4843 VMX_EPT_EXECUTABLE_MASK);
4848 if (bypass_guest_pf)
4849 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4854 free_page((unsigned long)vmx_msr_bitmap_longmode);
4856 free_page((unsigned long)vmx_msr_bitmap_legacy);
4858 free_page((unsigned long)vmx_io_bitmap_b);
4860 free_page((unsigned long)vmx_io_bitmap_a);
4864 static void __exit vmx_exit(void)
4866 free_page((unsigned long)vmx_msr_bitmap_legacy);
4867 free_page((unsigned long)vmx_msr_bitmap_longmode);
4868 free_page((unsigned long)vmx_io_bitmap_b);
4869 free_page((unsigned long)vmx_io_bitmap_a);
4874 module_init(vmx_init)
4875 module_exit(vmx_exit)