arch/x86/kvm/svm/svm.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * AMD SVM support
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *   Avi Kivity   <avi@qumranet.com>
  13  */
  14
  15 #ifndef __SVM_SVM_H
  16 #define __SVM_SVM_H
  17
  18 #include <linux/kvm_types.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/bits.h>
  21
  22 #include <asm/svm.h>
  23
  24 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
  25
  26 static const u32 host_save_user_msrs[] = {
  27         MSR_TSC_AUX,
  28 };
  29 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  30
  31 #define IOPM_SIZE PAGE_SIZE * 3
  32 #define MSRPM_SIZE PAGE_SIZE * 2
  33
  34 #define MAX_DIRECT_ACCESS_MSRS  20
  35 #define MSRPM_OFFSETS   16
  36 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  37 extern bool npt_enabled;
  38
  39 enum {
  40         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
  41                             pause filter count */
  42         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
  43         VMCB_ASID,       /* ASID */
  44         VMCB_INTR,       /* int_ctl, int_vector */
  45         VMCB_NPT,        /* npt_en, nCR3, gPAT */
  46         VMCB_CR,         /* CR0, CR3, CR4, EFER */
  47         VMCB_DR,         /* DR6, DR7 */
  48         VMCB_DT,         /* GDT, IDT */
  49         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
  50         VMCB_CR2,        /* CR2 only */
  51         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
  52         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
  53                           * AVIC PHYSICAL_TABLE pointer,
  54                           * AVIC LOGICAL_TABLE pointer
  55                           */
  56         VMCB_DIRTY_MAX,
  57 };
  58
  59 /* TPR and CR2 are always written before VMRUN */
  60 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
  61
  62 struct kvm_sev_info {
  63         bool active;            /* SEV enabled guest */
  64         bool es_active;         /* SEV-ES enabled guest */
  65         unsigned int asid;      /* ASID used for this guest */
  66         unsigned int handle;    /* SEV firmware handle */
  67         int fd;                 /* SEV device fd */
  68         unsigned long pages_locked; /* Number of pages locked */
  69         struct list_head regions_list;  /* List of registered regions */
  70         u64 ap_jump_table;      /* SEV-ES AP Jump Table address */
  71         struct kvm *enc_context_owner; /* Owner of copied encryption context */
  72         struct misc_cg *misc_cg; /* For misc cgroup accounting */
  73 };
  74
  75 struct kvm_svm {
  76         struct kvm kvm;
  77
  78         /* Struct members for AVIC */
  79         u32 avic_vm_id;
  80         struct page *avic_logical_id_table_page;
  81         struct page *avic_physical_id_table_page;
  82         struct hlist_node hnode;
  83
  84         struct kvm_sev_info sev_info;
  85 };
  86
  87 struct kvm_vcpu;
  88
  89 struct kvm_vmcb_info {
  90         struct vmcb *ptr;
  91         unsigned long pa;
  92         int cpu;
  93         uint64_t asid_generation;
  94 };
  95
  96 struct svm_nested_state {
  97         struct kvm_vmcb_info vmcb02;
  98         u64 hsave_msr;
  99         u64 vm_cr_msr;
 100         u64 vmcb12_gpa;
 101         u64 last_vmcb12_gpa;
 102
 103         /* These are the merged vectors */
 104         u32 *msrpm;
 105
 106         /* A VMRUN has started but has not yet been performed, so
 107          * we cannot inject a nested vmexit yet.  */
 108         bool nested_run_pending;
 109
 110         /* cache for control fields of the guest */
 111         struct vmcb_control_area ctl;
 112
 113         bool initialized;
 114 };
 115
 116 struct vcpu_svm {
 117         struct kvm_vcpu vcpu;
 118         /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */
 119         struct vmcb *vmcb;
 120         struct kvm_vmcb_info vmcb01;
 121         struct kvm_vmcb_info *current_vmcb;
 122         struct svm_cpu_data *svm_data;
 123         u32 asid;
 124         u32 sysenter_esp_hi;
 125         u32 sysenter_eip_hi;
 126         uint64_t tsc_aux;
 127
 128         u64 msr_decfg;
 129
 130         u64 next_rip;
 131
 132         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 133
 134         u64 spec_ctrl;
 135         /*
 136          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 137          * translated into the appropriate L2_CFG bits on the host to
 138          * perform speculative control.
 139          */
 140         u64 virt_spec_ctrl;
 141
 142         u32 *msrpm;
 143
 144         ulong nmi_iret_rip;
 145
 146         struct svm_nested_state nested;
 147
 148         bool nmi_singlestep;
 149         u64 nmi_singlestep_guest_rflags;
 150
 151         unsigned int3_injected;
 152         unsigned long int3_rip;
 153
 154         /* cached guest cpuid flags for faster access */
 155         bool nrips_enabled      : 1;
 156
 157         u32 ldr_reg;
 158         u32 dfr_reg;
 159         struct page *avic_backing_page;
 160         u64 *avic_physical_id_cache;
 161         bool avic_is_running;
 162
 163         /*
 164          * Per-vcpu list of struct amd_svm_iommu_ir:
 165          * This is used mainly to store interrupt remapping information used
 166          * when update the vcpu affinity. This avoids the need to scan for
 167          * IRTE and try to match ga_tag in the IOMMU driver.
 168          */
 169         struct list_head ir_list;
 170         spinlock_t ir_list_lock;
 171
 172         /* Save desired MSR intercept (read: pass-through) state */
 173         struct {
 174                 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
 175                 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
 176         } shadow_msr_intercept;
 177
 178         /* SEV-ES support */
 179         struct vmcb_save_area *vmsa;
 180         struct ghcb *ghcb;
 181         struct kvm_host_map ghcb_map;
 182         bool received_first_sipi;
 183
 184         /* SEV-ES scratch area support */
 185         void *ghcb_sa;
 186         u64 ghcb_sa_len;
 187         bool ghcb_sa_sync;
 188         bool ghcb_sa_free;
 189
 190         bool guest_state_loaded;
 191 };
 192
 193 struct svm_cpu_data {
 194         int cpu;
 195
 196         u64 asid_generation;
 197         u32 max_asid;
 198         u32 next_asid;
 199         u32 min_asid;
 200         struct kvm_ldttss_desc *tss_desc;
 201
 202         struct page *save_area;
 203         struct vmcb *current_vmcb;
 204
 205         /* index = sev_asid, value = vmcb pointer */
 206         struct vmcb **sev_vmcbs;
 207 };
 208
 209 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
 210
 211 void recalc_intercepts(struct vcpu_svm *svm);
 212
 213 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 214 {
 215         return container_of(kvm, struct kvm_svm, kvm);
 216 }
 217
 218 static inline bool sev_guest(struct kvm *kvm)
 219 {
 220 #ifdef CONFIG_KVM_AMD_SEV
 221         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 222
 223         return sev->active;
 224 #else
 225         return false;
 226 #endif
 227 }
 228
 229 static inline bool sev_es_guest(struct kvm *kvm)
 230 {
 231 #ifdef CONFIG_KVM_AMD_SEV
 232         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 233
 234         return sev_guest(kvm) && sev->es_active;
 235 #else
 236         return false;
 237 #endif
 238 }
 239
 240 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
 241 {
 242         vmcb->control.clean = 0;
 243 }
 244
 245 static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
 246 {
 247         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 248                                & ~VMCB_ALWAYS_DIRTY_MASK;
 249 }
 250
 251 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
 252 {
 253         vmcb->control.clean &= ~(1 << bit);
 254 }
 255
 256 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit)
 257 {
 258         return !test_bit(bit, (unsigned long *)&vmcb->control.clean);
 259 }
 260
 261 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 262 {
 263         return container_of(vcpu, struct vcpu_svm, vcpu);
 264 }
 265
 266 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
 267 {
 268         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 269         __set_bit(bit, (unsigned long *)&control->intercepts);
 270 }
 271
 272 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
 273 {
 274         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 275         __clear_bit(bit, (unsigned long *)&control->intercepts);
 276 }
 277
 278 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
 279 {
 280         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 281         return test_bit(bit, (unsigned long *)&control->intercepts);
 282 }
 283
 284 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 285 {
 286         struct vmcb *vmcb = svm->vmcb01.ptr;
 287
 288         if (!sev_es_guest(svm->vcpu.kvm)) {
 289                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
 290                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
 291                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
 292                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
 293                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
 294                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
 295                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
 296                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
 297                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
 298                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
 299                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
 300                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
 301                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
 302                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
 303         }
 304
 305         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
 306         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
 307
 308         recalc_intercepts(svm);
 309 }
 310
 311 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 312 {
 313         struct vmcb *vmcb = svm->vmcb01.ptr;
 314
 315         vmcb->control.intercepts[INTERCEPT_DR] = 0;
 316
 317         /* DR7 access must remain intercepted for an SEV-ES guest */
 318         if (sev_es_guest(svm->vcpu.kvm)) {
 319                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
 320                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
 321         }
 322
 323         recalc_intercepts(svm);
 324 }
 325
 326 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
 327 {
 328         struct vmcb *vmcb = svm->vmcb01.ptr;
 329
 330         WARN_ON_ONCE(bit >= 32);
 331         vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
 332
 333         recalc_intercepts(svm);
 334 }
 335
 336 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
 337 {
 338         struct vmcb *vmcb = svm->vmcb01.ptr;
 339
 340         WARN_ON_ONCE(bit >= 32);
 341         vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
 342
 343         recalc_intercepts(svm);
 344 }
 345
 346 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
 347 {
 348         struct vmcb *vmcb = svm->vmcb01.ptr;
 349
 350         vmcb_set_intercept(&vmcb->control, bit);
 351
 352         recalc_intercepts(svm);
 353 }
 354
 355 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
 356 {
 357         struct vmcb *vmcb = svm->vmcb01.ptr;
 358
 359         vmcb_clr_intercept(&vmcb->control, bit);
 360
 361         recalc_intercepts(svm);
 362 }
 363
 364 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
 365 {
 366         return vmcb_is_intercept(&svm->vmcb->control, bit);
 367 }
 368
 369 static inline bool vgif_enabled(struct vcpu_svm *svm)
 370 {
 371         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 372 }
 373
 374 static inline void enable_gif(struct vcpu_svm *svm)
 375 {
 376         if (vgif_enabled(svm))
 377                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 378         else
 379                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 380 }
 381
 382 static inline void disable_gif(struct vcpu_svm *svm)
 383 {
 384         if (vgif_enabled(svm))
 385                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 386         else
 387                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 388 }
 389
 390 static inline bool gif_set(struct vcpu_svm *svm)
 391 {
 392         if (vgif_enabled(svm))
 393                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 394         else
 395                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 396 }
 397
 398 /* svm.c */
 399 #define MSR_INVALID                             0xffffffffU
 400
 401 extern int sev;
 402 extern int sev_es;
 403 extern bool dump_invalid_vmcb;
 404
 405 u32 svm_msrpm_offset(u32 msr);
 406 u32 *svm_vcpu_alloc_msrpm(void);
 407 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm);
 408 void svm_vcpu_free_msrpm(u32 *msrpm);
 409
 410 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 411 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 412 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 413 void svm_flush_tlb(struct kvm_vcpu *vcpu);
 414 void disable_nmi_singlestep(struct vcpu_svm *svm);
 415 bool svm_smi_blocked(struct kvm_vcpu *vcpu);
 416 bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
 417 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
 418 void svm_set_gif(struct vcpu_svm *svm, bool value);
 419 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code);
 420 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 421                           int read, int write);
 422
 423 /* nested.c */
 424
 425 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
 426 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
 427 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
 428
 429 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
 430 {
 431         struct vcpu_svm *svm = to_svm(vcpu);
 432
 433         return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
 434 }
 435
 436 static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
 437 {
 438         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
 439 }
 440
 441 static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
 442 {
 443         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
 444 }
 445
 446 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
 447 {
 448         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
 449 }
 450
 451 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, u64 vmcb_gpa, struct vmcb *vmcb12);
 452 void svm_leave_nested(struct vcpu_svm *svm);
 453 void svm_free_nested(struct vcpu_svm *svm);
 454 int svm_allocate_nested(struct vcpu_svm *svm);
 455 int nested_svm_vmrun(struct kvm_vcpu *vcpu);
 456 void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
 457 int nested_svm_vmexit(struct vcpu_svm *svm);
 458
 459 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code)
 460 {
 461         svm->vmcb->control.exit_code   = exit_code;
 462         svm->vmcb->control.exit_info_1 = 0;
 463         svm->vmcb->control.exit_info_2 = 0;
 464         return nested_svm_vmexit(svm);
 465 }
 466
 467 int nested_svm_exit_handled(struct vcpu_svm *svm);
 468 int nested_svm_check_permissions(struct kvm_vcpu *vcpu);
 469 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 470                                bool has_error_code, u32 error_code);
 471 int nested_svm_exit_special(struct vcpu_svm *svm);
 472 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm);
 473 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm);
 474 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb);
 475
 476 extern struct kvm_x86_nested_ops svm_nested_ops;
 477
 478 /* avic.c */
 479
 480 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 481 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT                 31
 482 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 483
 484 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 485 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 486 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 487 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 488
 489 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 490
 491 extern int avic;
 492
 493 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 494 {
 495         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 496         vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
 497 }
 498
 499 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 500 {
 501         struct vcpu_svm *svm = to_svm(vcpu);
 502         u64 *entry = svm->avic_physical_id_cache;
 503
 504         if (!entry)
 505                 return false;
 506
 507         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 508 }
 509
 510 int avic_ga_log_notifier(u32 ga_tag);
 511 void avic_vm_destroy(struct kvm *kvm);
 512 int avic_vm_init(struct kvm *kvm);
 513 void avic_init_vmcb(struct vcpu_svm *svm);
 514 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
 515 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu);
 516 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu);
 517 int avic_init_vcpu(struct vcpu_svm *svm);
 518 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 519 void avic_vcpu_put(struct kvm_vcpu *vcpu);
 520 void avic_post_state_restore(struct kvm_vcpu *vcpu);
 521 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 522 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
 523 bool svm_check_apicv_inhibit_reasons(ulong bit);
 524 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
 525 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
 526 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
 527 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
 528 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
 529 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
 530 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
 531                        uint32_t guest_irq, bool set);
 532 void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
 533 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
 534
 535 /* sev.c */
 536
 537 #define GHCB_VERSION_MAX                1ULL
 538 #define GHCB_VERSION_MIN                1ULL
 539
 540 #define GHCB_MSR_INFO_POS               0
 541 #define GHCB_MSR_INFO_MASK              (BIT_ULL(12) - 1)
 542
 543 #define GHCB_MSR_SEV_INFO_RESP          0x001
 544 #define GHCB_MSR_SEV_INFO_REQ           0x002
 545 #define GHCB_MSR_VER_MAX_POS            48
 546 #define GHCB_MSR_VER_MAX_MASK           0xffff
 547 #define GHCB_MSR_VER_MIN_POS            32
 548 #define GHCB_MSR_VER_MIN_MASK           0xffff
 549 #define GHCB_MSR_CBIT_POS               24
 550 #define GHCB_MSR_CBIT_MASK              0xff
 551 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit)                            \
 552         ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) |   \
 553          (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) |   \
 554          (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) |        \
 555          GHCB_MSR_SEV_INFO_RESP)
 556
 557 #define GHCB_MSR_CPUID_REQ              0x004
 558 #define GHCB_MSR_CPUID_RESP             0x005
 559 #define GHCB_MSR_CPUID_FUNC_POS         32
 560 #define GHCB_MSR_CPUID_FUNC_MASK        0xffffffff
 561 #define GHCB_MSR_CPUID_VALUE_POS        32
 562 #define GHCB_MSR_CPUID_VALUE_MASK       0xffffffff
 563 #define GHCB_MSR_CPUID_REG_POS          30
 564 #define GHCB_MSR_CPUID_REG_MASK         0x3
 565
 566 #define GHCB_MSR_TERM_REQ               0x100
 567 #define GHCB_MSR_TERM_REASON_SET_POS    12
 568 #define GHCB_MSR_TERM_REASON_SET_MASK   0xf
 569 #define GHCB_MSR_TERM_REASON_POS        16
 570 #define GHCB_MSR_TERM_REASON_MASK       0xff
 571
 572 extern unsigned int max_sev_asid;
 573
 574 static inline bool svm_sev_enabled(void)
 575 {
 576         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 577 }
 578
 579 void sev_vm_destroy(struct kvm *kvm);
 580 int svm_mem_enc_op(struct kvm *kvm, void __user *argp);
 581 int svm_register_enc_region(struct kvm *kvm,
 582                             struct kvm_enc_region *range);
 583 int svm_unregister_enc_region(struct kvm *kvm,
 584                               struct kvm_enc_region *range);
 585 int svm_vm_copy_asid_from(struct kvm *kvm, unsigned int source_fd);
 586 void pre_sev_run(struct vcpu_svm *svm, int cpu);
 587 void __init sev_hardware_setup(void);
 588 void sev_hardware_teardown(void);
 589 void sev_free_vcpu(struct kvm_vcpu *vcpu);
 590 int sev_handle_vmgexit(struct kvm_vcpu *vcpu);
 591 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
 592 void sev_es_init_vmcb(struct vcpu_svm *svm);
 593 void sev_es_create_vcpu(struct vcpu_svm *svm);
 594 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
 595 void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu);
 596
 597 /* vmenter.S */
 598
 599 void __svm_sev_es_vcpu_run(unsigned long vmcb_pa);
 600 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
 601
 602 #endif