arch/x86/kvm/svm/svm.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * AMD SVM support
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *   Avi Kivity   <avi@qumranet.com>
  13  */
  14
  15 #ifndef __SVM_SVM_H
  16 #define __SVM_SVM_H
  17
  18 #include <linux/kvm_types.h>
  19 #include <linux/kvm_host.h>
  20 #include <linux/bits.h>
  21
  22 #include <asm/svm.h>
  23
  24 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
  25
  26 static const u32 host_save_user_msrs[] = {
  27         MSR_TSC_AUX,
  28 };
  29 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  30
  31 #define IOPM_SIZE PAGE_SIZE * 3
  32 #define MSRPM_SIZE PAGE_SIZE * 2
  33
  34 #define MAX_DIRECT_ACCESS_MSRS  20
  35 #define MSRPM_OFFSETS   16
  36 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  37 extern bool npt_enabled;
  38
  39 enum {
  40         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
  41                             pause filter count */
  42         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
  43         VMCB_ASID,       /* ASID */
  44         VMCB_INTR,       /* int_ctl, int_vector */
  45         VMCB_NPT,        /* npt_en, nCR3, gPAT */
  46         VMCB_CR,         /* CR0, CR3, CR4, EFER */
  47         VMCB_DR,         /* DR6, DR7 */
  48         VMCB_DT,         /* GDT, IDT */
  49         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
  50         VMCB_CR2,        /* CR2 only */
  51         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
  52         VMCB_AVIC,       /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
  53                           * AVIC PHYSICAL_TABLE pointer,
  54                           * AVIC LOGICAL_TABLE pointer
  55                           */
  56         VMCB_DIRTY_MAX,
  57 };
  58
  59 /* TPR and CR2 are always written before VMRUN */
  60 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
  61
  62 struct kvm_sev_info {
  63         bool active;            /* SEV enabled guest */
  64         bool es_active;         /* SEV-ES enabled guest */
  65         unsigned int asid;      /* ASID used for this guest */
  66         unsigned int handle;    /* SEV firmware handle */
  67         int fd;                 /* SEV device fd */
  68         unsigned long pages_locked; /* Number of pages locked */
  69         struct list_head regions_list;  /* List of registered regions */
  70         u64 ap_jump_table;      /* SEV-ES AP Jump Table address */
  71         struct kvm *enc_context_owner; /* Owner of copied encryption context */
  72 };
  73
  74 struct kvm_svm {
  75         struct kvm kvm;
  76
  77         /* Struct members for AVIC */
  78         u32 avic_vm_id;
  79         struct page *avic_logical_id_table_page;
  80         struct page *avic_physical_id_table_page;
  81         struct hlist_node hnode;
  82
  83         struct kvm_sev_info sev_info;
  84 };
  85
  86 struct kvm_vcpu;
  87
  88 struct kvm_vmcb_info {
  89         struct vmcb *ptr;
  90         unsigned long pa;
  91         int cpu;
  92         uint64_t asid_generation;
  93 };
  94
  95 struct svm_nested_state {
  96         struct kvm_vmcb_info vmcb02;
  97         u64 hsave_msr;
  98         u64 vm_cr_msr;
  99         u64 vmcb12_gpa;
 100         u64 last_vmcb12_gpa;
 101
 102         /* These are the merged vectors */
 103         u32 *msrpm;
 104
 105         /* A VMRUN has started but has not yet been performed, so
 106          * we cannot inject a nested vmexit yet.  */
 107         bool nested_run_pending;
 108
 109         /* cache for control fields of the guest */
 110         struct vmcb_control_area ctl;
 111
 112         bool initialized;
 113 };
 114
 115 struct vcpu_svm {
 116         struct kvm_vcpu vcpu;
 117         /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */
 118         struct vmcb *vmcb;
 119         struct kvm_vmcb_info vmcb01;
 120         struct kvm_vmcb_info *current_vmcb;
 121         struct svm_cpu_data *svm_data;
 122         u32 asid;
 123         u32 sysenter_esp_hi;
 124         u32 sysenter_eip_hi;
 125         uint64_t tsc_aux;
 126
 127         u64 msr_decfg;
 128
 129         u64 next_rip;
 130
 131         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 132
 133         u64 spec_ctrl;
 134         /*
 135          * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
 136          * translated into the appropriate L2_CFG bits on the host to
 137          * perform speculative control.
 138          */
 139         u64 virt_spec_ctrl;
 140
 141         u32 *msrpm;
 142
 143         ulong nmi_iret_rip;
 144
 145         struct svm_nested_state nested;
 146
 147         bool nmi_singlestep;
 148         u64 nmi_singlestep_guest_rflags;
 149
 150         unsigned int3_injected;
 151         unsigned long int3_rip;
 152
 153         /* cached guest cpuid flags for faster access */
 154         bool nrips_enabled      : 1;
 155
 156         u32 ldr_reg;
 157         u32 dfr_reg;
 158         struct page *avic_backing_page;
 159         u64 *avic_physical_id_cache;
 160         bool avic_is_running;
 161
 162         /*
 163          * Per-vcpu list of struct amd_svm_iommu_ir:
 164          * This is used mainly to store interrupt remapping information used
 165          * when update the vcpu affinity. This avoids the need to scan for
 166          * IRTE and try to match ga_tag in the IOMMU driver.
 167          */
 168         struct list_head ir_list;
 169         spinlock_t ir_list_lock;
 170
 171         /* Save desired MSR intercept (read: pass-through) state */
 172         struct {
 173                 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
 174                 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
 175         } shadow_msr_intercept;
 176
 177         /* SEV-ES support */
 178         struct vmcb_save_area *vmsa;
 179         struct ghcb *ghcb;
 180         struct kvm_host_map ghcb_map;
 181         bool received_first_sipi;
 182
 183         /* SEV-ES scratch area support */
 184         void *ghcb_sa;
 185         u64 ghcb_sa_len;
 186         bool ghcb_sa_sync;
 187         bool ghcb_sa_free;
 188
 189         bool guest_state_loaded;
 190 };
 191
 192 struct svm_cpu_data {
 193         int cpu;
 194
 195         u64 asid_generation;
 196         u32 max_asid;
 197         u32 next_asid;
 198         u32 min_asid;
 199         struct kvm_ldttss_desc *tss_desc;
 200
 201         struct page *save_area;
 202         struct vmcb *current_vmcb;
 203
 204         /* index = sev_asid, value = vmcb pointer */
 205         struct vmcb **sev_vmcbs;
 206 };
 207
 208 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data);
 209
 210 void recalc_intercepts(struct vcpu_svm *svm);
 211
 212 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
 213 {
 214         return container_of(kvm, struct kvm_svm, kvm);
 215 }
 216
 217 static inline bool sev_guest(struct kvm *kvm)
 218 {
 219 #ifdef CONFIG_KVM_AMD_SEV
 220         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 221
 222         return sev->active;
 223 #else
 224         return false;
 225 #endif
 226 }
 227
 228 static inline bool sev_es_guest(struct kvm *kvm)
 229 {
 230 #ifdef CONFIG_KVM_AMD_SEV
 231         struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
 232
 233         return sev_guest(kvm) && sev->es_active;
 234 #else
 235         return false;
 236 #endif
 237 }
 238
 239 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
 240 {
 241         vmcb->control.clean = 0;
 242 }
 243
 244 static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
 245 {
 246         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
 247                                & ~VMCB_ALWAYS_DIRTY_MASK;
 248 }
 249
 250 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
 251 {
 252         vmcb->control.clean &= ~(1 << bit);
 253 }
 254
 255 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit)
 256 {
 257         return !test_bit(bit, (unsigned long *)&vmcb->control.clean);
 258 }
 259
 260 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 261 {
 262         return container_of(vcpu, struct vcpu_svm, vcpu);
 263 }
 264
 265 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
 266 {
 267         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 268         __set_bit(bit, (unsigned long *)&control->intercepts);
 269 }
 270
 271 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
 272 {
 273         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 274         __clear_bit(bit, (unsigned long *)&control->intercepts);
 275 }
 276
 277 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
 278 {
 279         WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
 280         return test_bit(bit, (unsigned long *)&control->intercepts);
 281 }
 282
 283 static inline void set_dr_intercepts(struct vcpu_svm *svm)
 284 {
 285         struct vmcb *vmcb = svm->vmcb01.ptr;
 286
 287         if (!sev_es_guest(svm->vcpu.kvm)) {
 288                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
 289                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
 290                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
 291                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
 292                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
 293                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
 294                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
 295                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
 296                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
 297                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
 298                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
 299                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
 300                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
 301                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
 302         }
 303
 304         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
 305         vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
 306
 307         recalc_intercepts(svm);
 308 }
 309
 310 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
 311 {
 312         struct vmcb *vmcb = svm->vmcb01.ptr;
 313
 314         vmcb->control.intercepts[INTERCEPT_DR] = 0;
 315
 316         /* DR7 access must remain intercepted for an SEV-ES guest */
 317         if (sev_es_guest(svm->vcpu.kvm)) {
 318                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
 319                 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
 320         }
 321
 322         recalc_intercepts(svm);
 323 }
 324
 325 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
 326 {
 327         struct vmcb *vmcb = svm->vmcb01.ptr;
 328
 329         WARN_ON_ONCE(bit >= 32);
 330         vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
 331
 332         recalc_intercepts(svm);
 333 }
 334
 335 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
 336 {
 337         struct vmcb *vmcb = svm->vmcb01.ptr;
 338
 339         WARN_ON_ONCE(bit >= 32);
 340         vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
 341
 342         recalc_intercepts(svm);
 343 }
 344
 345 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
 346 {
 347         struct vmcb *vmcb = svm->vmcb01.ptr;
 348
 349         vmcb_set_intercept(&vmcb->control, bit);
 350
 351         recalc_intercepts(svm);
 352 }
 353
 354 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
 355 {
 356         struct vmcb *vmcb = svm->vmcb01.ptr;
 357
 358         vmcb_clr_intercept(&vmcb->control, bit);
 359
 360         recalc_intercepts(svm);
 361 }
 362
 363 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
 364 {
 365         return vmcb_is_intercept(&svm->vmcb->control, bit);
 366 }
 367
 368 static inline bool vgif_enabled(struct vcpu_svm *svm)
 369 {
 370         return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
 371 }
 372
 373 static inline void enable_gif(struct vcpu_svm *svm)
 374 {
 375         if (vgif_enabled(svm))
 376                 svm->vmcb->control.int_ctl |= V_GIF_MASK;
 377         else
 378                 svm->vcpu.arch.hflags |= HF_GIF_MASK;
 379 }
 380
 381 static inline void disable_gif(struct vcpu_svm *svm)
 382 {
 383         if (vgif_enabled(svm))
 384                 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
 385         else
 386                 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 387 }
 388
 389 static inline bool gif_set(struct vcpu_svm *svm)
 390 {
 391         if (vgif_enabled(svm))
 392                 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
 393         else
 394                 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 395 }
 396
 397 /* svm.c */
 398 #define MSR_INVALID                             0xffffffffU
 399
 400 extern int sev;
 401 extern int sev_es;
 402 extern bool dump_invalid_vmcb;
 403
 404 u32 svm_msrpm_offset(u32 msr);
 405 u32 *svm_vcpu_alloc_msrpm(void);
 406 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm);
 407 void svm_vcpu_free_msrpm(u32 *msrpm);
 408
 409 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 410 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 411 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 412 void svm_flush_tlb(struct kvm_vcpu *vcpu);
 413 void disable_nmi_singlestep(struct vcpu_svm *svm);
 414 bool svm_smi_blocked(struct kvm_vcpu *vcpu);
 415 bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
 416 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
 417 void svm_set_gif(struct vcpu_svm *svm, bool value);
 418 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code);
 419 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 420                           int read, int write);
 421
 422 /* nested.c */
 423
 424 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
 425 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
 426 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
 427
 428 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
 429 {
 430         struct vcpu_svm *svm = to_svm(vcpu);
 431
 432         return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
 433 }
 434
 435 static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
 436 {
 437         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
 438 }
 439
 440 static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
 441 {
 442         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
 443 }
 444
 445 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
 446 {
 447         return vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
 448 }
 449
 450 int enter_svm_guest_mode(struct kvm_vcpu *vcpu, u64 vmcb_gpa, struct vmcb *vmcb12);
 451 void svm_leave_nested(struct vcpu_svm *svm);
 452 void svm_free_nested(struct vcpu_svm *svm);
 453 int svm_allocate_nested(struct vcpu_svm *svm);
 454 int nested_svm_vmrun(struct kvm_vcpu *vcpu);
 455 void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb);
 456 int nested_svm_vmexit(struct vcpu_svm *svm);
 457
 458 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code)
 459 {
 460         svm->vmcb->control.exit_code   = exit_code;
 461         svm->vmcb->control.exit_info_1 = 0;
 462         svm->vmcb->control.exit_info_2 = 0;
 463         return nested_svm_vmexit(svm);
 464 }
 465
 466 int nested_svm_exit_handled(struct vcpu_svm *svm);
 467 int nested_svm_check_permissions(struct kvm_vcpu *vcpu);
 468 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 469                                bool has_error_code, u32 error_code);
 470 int nested_svm_exit_special(struct vcpu_svm *svm);
 471 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm);
 472 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm);
 473 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb);
 474
 475 extern struct kvm_x86_nested_ops svm_nested_ops;
 476
 477 /* avic.c */
 478
 479 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFF)
 480 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT                 31
 481 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK                (1 << 31)
 482
 483 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    (0xFFULL)
 484 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK        (0xFFFFFFFFFFULL << 12)
 485 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK          (1ULL << 62)
 486 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK               (1ULL << 63)
 487
 488 #define VMCB_AVIC_APIC_BAR_MASK         0xFFFFFFFFFF000ULL
 489
 490 extern int avic;
 491
 492 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
 493 {
 494         svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
 495         vmcb_mark_dirty(svm->vmcb, VMCB_AVIC);
 496 }
 497
 498 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
 499 {
 500         struct vcpu_svm *svm = to_svm(vcpu);
 501         u64 *entry = svm->avic_physical_id_cache;
 502
 503         if (!entry)
 504                 return false;
 505
 506         return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
 507 }
 508
 509 int avic_ga_log_notifier(u32 ga_tag);
 510 void avic_vm_destroy(struct kvm *kvm);
 511 int avic_vm_init(struct kvm *kvm);
 512 void avic_init_vmcb(struct vcpu_svm *svm);
 513 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate);
 514 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu);
 515 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu);
 516 int avic_init_vcpu(struct vcpu_svm *svm);
 517 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
 518 void avic_vcpu_put(struct kvm_vcpu *vcpu);
 519 void avic_post_state_restore(struct kvm_vcpu *vcpu);
 520 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 521 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
 522 bool svm_check_apicv_inhibit_reasons(ulong bit);
 523 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate);
 524 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
 525 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr);
 526 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr);
 527 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec);
 528 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu);
 529 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
 530                        uint32_t guest_irq, bool set);
 531 void svm_vcpu_blocking(struct kvm_vcpu *vcpu);
 532 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu);
 533
 534 /* sev.c */
 535
 536 #define GHCB_VERSION_MAX                1ULL
 537 #define GHCB_VERSION_MIN                1ULL
 538
 539 #define GHCB_MSR_INFO_POS               0
 540 #define GHCB_MSR_INFO_MASK              (BIT_ULL(12) - 1)
 541
 542 #define GHCB_MSR_SEV_INFO_RESP          0x001
 543 #define GHCB_MSR_SEV_INFO_REQ           0x002
 544 #define GHCB_MSR_VER_MAX_POS            48
 545 #define GHCB_MSR_VER_MAX_MASK           0xffff
 546 #define GHCB_MSR_VER_MIN_POS            32
 547 #define GHCB_MSR_VER_MIN_MASK           0xffff
 548 #define GHCB_MSR_CBIT_POS               24
 549 #define GHCB_MSR_CBIT_MASK              0xff
 550 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit)                            \
 551         ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) |   \
 552          (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) |   \
 553          (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) |        \
 554          GHCB_MSR_SEV_INFO_RESP)
 555
 556 #define GHCB_MSR_CPUID_REQ              0x004
 557 #define GHCB_MSR_CPUID_RESP             0x005
 558 #define GHCB_MSR_CPUID_FUNC_POS         32
 559 #define GHCB_MSR_CPUID_FUNC_MASK        0xffffffff
 560 #define GHCB_MSR_CPUID_VALUE_POS        32
 561 #define GHCB_MSR_CPUID_VALUE_MASK       0xffffffff
 562 #define GHCB_MSR_CPUID_REG_POS          30
 563 #define GHCB_MSR_CPUID_REG_MASK         0x3
 564
 565 #define GHCB_MSR_TERM_REQ               0x100
 566 #define GHCB_MSR_TERM_REASON_SET_POS    12
 567 #define GHCB_MSR_TERM_REASON_SET_MASK   0xf
 568 #define GHCB_MSR_TERM_REASON_POS        16
 569 #define GHCB_MSR_TERM_REASON_MASK       0xff
 570
 571 extern unsigned int max_sev_asid;
 572
 573 static inline bool svm_sev_enabled(void)
 574 {
 575         return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0;
 576 }
 577
 578 void sev_vm_destroy(struct kvm *kvm);
 579 int svm_mem_enc_op(struct kvm *kvm, void __user *argp);
 580 int svm_register_enc_region(struct kvm *kvm,
 581                             struct kvm_enc_region *range);
 582 int svm_unregister_enc_region(struct kvm *kvm,
 583                               struct kvm_enc_region *range);
 584 int svm_vm_copy_asid_from(struct kvm *kvm, unsigned int source_fd);
 585 void pre_sev_run(struct vcpu_svm *svm, int cpu);
 586 void __init sev_hardware_setup(void);
 587 void sev_hardware_teardown(void);
 588 void sev_free_vcpu(struct kvm_vcpu *vcpu);
 589 int sev_handle_vmgexit(struct kvm_vcpu *vcpu);
 590 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
 591 void sev_es_init_vmcb(struct vcpu_svm *svm);
 592 void sev_es_create_vcpu(struct vcpu_svm *svm);
 593 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
 594 void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu);
 595
 596 /* vmenter.S */
 597
 598 void __svm_sev_es_vcpu_run(unsigned long vmcb_pa);
 599 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
 600
 601 #endif