1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
15 #define pr_fmt(fmt) "SVM: " fmt
17 #include <linux/kvm_types.h>
18 #include <linux/hashtable.h>
19 #include <linux/amd-iommu.h>
20 #include <linux/kvm_host.h>
22 #include <asm/irq_remapping.h>
30 #define SVM_AVIC_DOORBELL 0xc001011b
32 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
35 * 0xff is broadcast, so the max index allowed for physical APIC ID
36 * table is 0xfe. APIC IDs above 0xff are reserved.
38 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
40 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
41 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
42 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
44 /* AVIC GATAG is encoded using VM and VCPU IDs */
45 #define AVIC_VCPU_ID_BITS 8
46 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
48 #define AVIC_VM_ID_BITS 24
49 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
50 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
52 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
53 (y & AVIC_VCPU_ID_MASK))
54 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
55 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
58 * This hash table is used to map VM_ID to a struct kvm_svm,
59 * when handling AMD IOMMU GALOG notification to schedule in
62 #define SVM_VM_DATA_HASH_BITS 8
63 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
64 static u32 next_vm_id = 0;
65 static bool next_vm_id_wrapped = 0;
66 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
69 * This is a wrapper of struct amd_iommu_ir_data.
71 struct amd_svm_iommu_ir {
72 struct list_head node; /* Used by SVM for per-vcpu ir_list */
73 void *data; /* Storing pointer to struct amd_ir_data */
76 enum avic_ipi_failure_cause {
77 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
78 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
79 AVIC_IPI_FAILURE_INVALID_TARGET,
80 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
84 * This function is called from IOMMU driver to notify
85 * SVM to schedule in a particular vCPU of a particular VM.
87 int avic_ga_log_notifier(u32 ga_tag)
90 struct kvm_svm *kvm_svm;
91 struct kvm_vcpu *vcpu = NULL;
92 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
93 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
95 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
96 trace_kvm_avic_ga_log(vm_id, vcpu_id);
98 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
99 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
100 if (kvm_svm->avic_vm_id != vm_id)
102 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
105 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
108 * At this point, the IOMMU should have already set the pending
109 * bit in the vAPIC backing page. So, we just need to schedule
113 kvm_vcpu_wake_up(vcpu);
118 void avic_vm_destroy(struct kvm *kvm)
121 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
126 if (kvm_svm->avic_logical_id_table_page)
127 __free_page(kvm_svm->avic_logical_id_table_page);
128 if (kvm_svm->avic_physical_id_table_page)
129 __free_page(kvm_svm->avic_physical_id_table_page);
131 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
132 hash_del(&kvm_svm->hnode);
133 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
136 int avic_vm_init(struct kvm *kvm)
140 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
149 /* Allocating physical APIC ID table (4KB) */
150 p_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
154 kvm_svm->avic_physical_id_table_page = p_page;
156 /* Allocating logical APIC ID table (4KB) */
157 l_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
161 kvm_svm->avic_logical_id_table_page = l_page;
163 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
165 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
166 if (vm_id == 0) { /* id is 1-based, zero is not okay */
167 next_vm_id_wrapped = 1;
170 /* Is it still in use? Only possible if wrapped at least once */
171 if (next_vm_id_wrapped) {
172 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
173 if (k2->avic_vm_id == vm_id)
177 kvm_svm->avic_vm_id = vm_id;
178 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
179 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
184 avic_vm_destroy(kvm);
188 void avic_init_vmcb(struct vcpu_svm *svm)
190 struct vmcb *vmcb = svm->vmcb;
191 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
192 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
193 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
194 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
196 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
197 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
198 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
199 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
200 if (kvm_apicv_activated(svm->vcpu.kvm))
201 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
203 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
206 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
209 u64 *avic_physical_id_table;
210 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
212 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
215 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
217 return &avic_physical_id_table[index];
222 * AVIC hardware walks the nested page table to check permissions,
223 * but does not use the SPA address specified in the leaf page
224 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
225 * field of the VMCB. Therefore, we set up the
226 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
228 static int avic_update_access_page(struct kvm *kvm, bool activate)
233 mutex_lock(&kvm->slots_lock);
235 * During kvm_destroy_vm(), kvm_pit_set_reinject() could trigger
236 * APICv mode change, which update APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
237 * memory region. So, we need to ensure that kvm->mm == current->mm.
239 if ((kvm->arch.apic_access_memslot_enabled == activate) ||
240 (kvm->mm != current->mm))
243 ret = __x86_set_memory_region(kvm,
244 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
245 APIC_DEFAULT_PHYS_BASE,
246 activate ? PAGE_SIZE : 0);
252 kvm->arch.apic_access_memslot_enabled = activate;
254 mutex_unlock(&kvm->slots_lock);
258 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
260 u64 *entry, new_entry;
261 int id = vcpu->vcpu_id;
262 struct vcpu_svm *svm = to_svm(vcpu);
264 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
267 if (!vcpu->arch.apic->regs)
270 if (kvm_apicv_activated(vcpu->kvm)) {
273 ret = avic_update_access_page(vcpu->kvm, true);
278 svm->avic_backing_page = virt_to_page(vcpu->arch.apic->regs);
280 /* Setting AVIC backing page address in the phy APIC ID table */
281 entry = avic_get_physical_id_entry(vcpu, id);
285 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
286 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
287 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
288 WRITE_ONCE(*entry, new_entry);
290 svm->avic_physical_id_cache = entry;
295 static void avic_kick_target_vcpus(struct kvm *kvm, struct kvm_lapic *source,
298 struct kvm_vcpu *vcpu;
301 kvm_for_each_vcpu(i, vcpu, kvm) {
302 bool m = kvm_apic_match_dest(vcpu, source,
303 icrl & APIC_SHORT_MASK,
304 GET_APIC_DEST_FIELD(icrh),
305 icrl & APIC_DEST_MASK);
307 if (m && !avic_vcpu_is_running(vcpu))
308 kvm_vcpu_wake_up(vcpu);
312 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu)
314 struct vcpu_svm *svm = to_svm(vcpu);
315 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
316 u32 icrl = svm->vmcb->control.exit_info_1;
317 u32 id = svm->vmcb->control.exit_info_2 >> 32;
318 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
319 struct kvm_lapic *apic = vcpu->arch.apic;
321 trace_kvm_avic_incomplete_ipi(vcpu->vcpu_id, icrh, icrl, id, index);
324 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
326 * AVIC hardware handles the generation of
327 * IPIs when the specified Message Type is Fixed
328 * (also known as fixed delivery mode) and
329 * the Trigger Mode is edge-triggered. The hardware
330 * also supports self and broadcast delivery modes
331 * specified via the Destination Shorthand(DSH)
332 * field of the ICRL. Logical and physical APIC ID
333 * formats are supported. All other IPI types cause
334 * a #VMEXIT, which needs to emulated.
336 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
337 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
339 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING:
341 * At this point, we expect that the AVIC HW has already
342 * set the appropriate IRR bits on the valid target
343 * vcpus. So, we just need to kick the appropriate vcpu.
345 avic_kick_target_vcpus(vcpu->kvm, apic, icrl, icrh);
347 case AVIC_IPI_FAILURE_INVALID_TARGET:
348 WARN_ONCE(1, "Invalid IPI target: index=%u, vcpu=%d, icr=%#0x:%#0x\n",
349 index, vcpu->vcpu_id, icrh, icrl);
351 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
352 WARN_ONCE(1, "Invalid backing page\n");
355 pr_err("Unknown IPI interception\n");
361 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
363 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
365 u32 *logical_apic_id_table;
366 int dlid = GET_APIC_LOGICAL_ID(ldr);
371 if (flat) { /* flat */
372 index = ffs(dlid) - 1;
375 } else { /* cluster */
376 int cluster = (dlid & 0xf0) >> 4;
377 int apic = ffs(dlid & 0x0f) - 1;
379 if ((apic < 0) || (apic > 7) ||
382 index = (cluster << 2) + apic;
385 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
387 return &logical_apic_id_table[index];
390 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
393 u32 *entry, new_entry;
395 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
396 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
400 new_entry = READ_ONCE(*entry);
401 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
402 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
403 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
404 WRITE_ONCE(*entry, new_entry);
409 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
411 struct vcpu_svm *svm = to_svm(vcpu);
412 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
413 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
416 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
419 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
422 struct vcpu_svm *svm = to_svm(vcpu);
423 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
424 u32 id = kvm_xapic_id(vcpu->arch.apic);
426 if (ldr == svm->ldr_reg)
429 avic_invalidate_logical_id_entry(vcpu);
432 ret = avic_ldr_write(vcpu, id, ldr);
440 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
443 struct vcpu_svm *svm = to_svm(vcpu);
444 u32 id = kvm_xapic_id(vcpu->arch.apic);
446 if (vcpu->vcpu_id == id)
449 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
450 new = avic_get_physical_id_entry(vcpu, id);
454 /* We need to move physical_id_entry to new offset */
457 to_svm(vcpu)->avic_physical_id_cache = new;
460 * Also update the guest physical APIC ID in the logical
461 * APIC ID table entry if already setup the LDR.
464 avic_handle_ldr_update(vcpu);
469 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
471 struct vcpu_svm *svm = to_svm(vcpu);
472 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
474 if (svm->dfr_reg == dfr)
477 avic_invalidate_logical_id_entry(vcpu);
481 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
483 struct kvm_lapic *apic = svm->vcpu.arch.apic;
484 u32 offset = svm->vmcb->control.exit_info_1 &
485 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
489 if (avic_handle_apic_id_update(&svm->vcpu))
493 if (avic_handle_ldr_update(&svm->vcpu))
497 avic_handle_dfr_update(&svm->vcpu);
503 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
508 static bool is_avic_unaccelerated_access_trap(u32 offset)
537 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu)
539 struct vcpu_svm *svm = to_svm(vcpu);
541 u32 offset = svm->vmcb->control.exit_info_1 &
542 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
543 u32 vector = svm->vmcb->control.exit_info_2 &
544 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
545 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
546 AVIC_UNACCEL_ACCESS_WRITE_MASK;
547 bool trap = is_avic_unaccelerated_access_trap(offset);
549 trace_kvm_avic_unaccelerated_access(vcpu->vcpu_id, offset,
550 trap, write, vector);
553 WARN_ONCE(!write, "svm: Handling trap read.\n");
554 ret = avic_unaccel_trap_write(svm);
557 ret = kvm_emulate_instruction(vcpu, 0);
563 int avic_init_vcpu(struct vcpu_svm *svm)
566 struct kvm_vcpu *vcpu = &svm->vcpu;
568 if (!enable_apicv || !irqchip_in_kernel(vcpu->kvm))
571 ret = avic_init_backing_page(vcpu);
575 INIT_LIST_HEAD(&svm->ir_list);
576 spin_lock_init(&svm->ir_list_lock);
577 svm->dfr_reg = APIC_DFR_FLAT;
582 void avic_post_state_restore(struct kvm_vcpu *vcpu)
584 if (avic_handle_apic_id_update(vcpu) != 0)
586 avic_handle_dfr_update(vcpu);
587 avic_handle_ldr_update(vcpu);
590 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate)
592 if (!enable_apicv || !lapic_in_kernel(vcpu))
595 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
596 kvm_request_apicv_update(vcpu->kvm, activate,
597 APICV_INHIBIT_REASON_IRQWIN);
598 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
601 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
606 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
610 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
614 static int svm_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate)
618 struct amd_svm_iommu_ir *ir;
619 struct vcpu_svm *svm = to_svm(vcpu);
621 if (!kvm_arch_has_assigned_device(vcpu->kvm))
625 * Here, we go through the per-vcpu ir_list to update all existing
626 * interrupt remapping table entry targeting this vcpu.
628 spin_lock_irqsave(&svm->ir_list_lock, flags);
630 if (list_empty(&svm->ir_list))
633 list_for_each_entry(ir, &svm->ir_list, node) {
635 ret = amd_iommu_activate_guest_mode(ir->data);
637 ret = amd_iommu_deactivate_guest_mode(ir->data);
642 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
646 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
648 struct vcpu_svm *svm = to_svm(vcpu);
649 struct vmcb *vmcb = svm->vmcb01.ptr;
650 bool activated = kvm_vcpu_apicv_active(vcpu);
657 * During AVIC temporary deactivation, guest could update
658 * APIC ID, DFR and LDR registers, which would not be trapped
659 * by avic_unaccelerated_access_interception(). In this case,
660 * we need to check and update the AVIC logical APIC ID table
661 * accordingly before re-activating.
663 avic_post_state_restore(vcpu);
664 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
666 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
668 vmcb_mark_dirty(vmcb, VMCB_AVIC);
670 svm_set_pi_irte_mode(vcpu, activated);
673 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
678 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
680 if (!vcpu->arch.apicv_active)
683 kvm_lapic_set_irr(vec, vcpu->arch.apic);
684 smp_mb__after_atomic();
686 if (avic_vcpu_is_running(vcpu)) {
687 int cpuid = vcpu->cpu;
689 if (cpuid != get_cpu())
690 wrmsrl(SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpuid));
693 kvm_vcpu_wake_up(vcpu);
698 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu)
703 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
706 struct amd_svm_iommu_ir *cur;
708 spin_lock_irqsave(&svm->ir_list_lock, flags);
709 list_for_each_entry(cur, &svm->ir_list, node) {
710 if (cur->data != pi->ir_data)
712 list_del(&cur->node);
716 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
719 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
723 struct amd_svm_iommu_ir *ir;
726 * In some cases, the existing irte is updated and re-set,
727 * so we need to check here if it's already been * added
730 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
731 struct kvm *kvm = svm->vcpu.kvm;
732 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
733 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
734 struct vcpu_svm *prev_svm;
741 prev_svm = to_svm(prev_vcpu);
742 svm_ir_list_del(prev_svm, pi);
746 * Allocating new amd_iommu_pi_data, which will get
747 * add to the per-vcpu ir_list.
749 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
754 ir->data = pi->ir_data;
756 spin_lock_irqsave(&svm->ir_list_lock, flags);
757 list_add(&ir->node, &svm->ir_list);
758 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
765 * The HW cannot support posting multicast/broadcast
766 * interrupts to a vCPU. So, we still use legacy interrupt
767 * remapping for these kind of interrupts.
769 * For lowest-priority interrupts, we only support
770 * those with single CPU as the destination, e.g. user
771 * configures the interrupts via /proc/irq or uses
772 * irqbalance to make the interrupts single-CPU.
775 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
776 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
778 struct kvm_lapic_irq irq;
779 struct kvm_vcpu *vcpu = NULL;
781 kvm_set_msi_irq(kvm, e, &irq);
783 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
784 !kvm_irq_is_postable(&irq)) {
785 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
786 __func__, irq.vector);
790 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
793 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
794 vcpu_info->vector = irq.vector;
800 * svm_update_pi_irte - set IRTE for Posted-Interrupts
803 * @host_irq: host irq of the interrupt
804 * @guest_irq: gsi of the interrupt
805 * @set: set or unset PI
806 * returns 0 on success, < 0 on failure
808 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
809 uint32_t guest_irq, bool set)
811 struct kvm_kernel_irq_routing_entry *e;
812 struct kvm_irq_routing_table *irq_rt;
813 int idx, ret = -EINVAL;
815 if (!kvm_arch_has_assigned_device(kvm) ||
816 !irq_remapping_cap(IRQ_POSTING_CAP))
819 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
820 __func__, host_irq, guest_irq, set);
822 idx = srcu_read_lock(&kvm->irq_srcu);
823 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
824 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
826 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
827 struct vcpu_data vcpu_info;
828 struct vcpu_svm *svm = NULL;
830 if (e->type != KVM_IRQ_ROUTING_MSI)
834 * Here, we setup with legacy mode in the following cases:
835 * 1. When cannot target interrupt to a specific vcpu.
836 * 2. Unsetting posted interrupt.
837 * 3. APIC virtualization is disabled for the vcpu.
838 * 4. IRQ has incompatible delivery mode (SMI, INIT, etc)
840 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
841 kvm_vcpu_apicv_active(&svm->vcpu)) {
842 struct amd_iommu_pi_data pi;
844 /* Try to enable guest_mode in IRTE */
845 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
847 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
849 pi.is_guest_mode = true;
850 pi.vcpu_data = &vcpu_info;
851 ret = irq_set_vcpu_affinity(host_irq, &pi);
854 * Here, we successfully setting up vcpu affinity in
855 * IOMMU guest mode. Now, we need to store the posted
856 * interrupt information in a per-vcpu ir_list so that
857 * we can reference to them directly when we update vcpu
858 * scheduling information in IOMMU irte.
860 if (!ret && pi.is_guest_mode)
861 svm_ir_list_add(svm, &pi);
863 /* Use legacy mode in IRTE */
864 struct amd_iommu_pi_data pi;
867 * Here, pi is used to:
868 * - Tell IOMMU to use legacy mode for this interrupt.
869 * - Retrieve ga_tag of prior interrupt remapping data.
872 pi.is_guest_mode = false;
873 ret = irq_set_vcpu_affinity(host_irq, &pi);
876 * Check if the posted interrupt was previously
877 * setup with the guest_mode by checking if the ga_tag
878 * was cached. If so, we need to clean up the per-vcpu
881 if (!ret && pi.prev_ga_tag) {
882 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
883 struct kvm_vcpu *vcpu;
885 vcpu = kvm_get_vcpu_by_id(kvm, id);
887 svm_ir_list_del(to_svm(vcpu), &pi);
892 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
893 e->gsi, vcpu_info.vector,
894 vcpu_info.pi_desc_addr, set);
898 pr_err("%s: failed to update PI IRTE\n", __func__);
905 srcu_read_unlock(&kvm->irq_srcu, idx);
909 bool svm_check_apicv_inhibit_reasons(ulong bit)
911 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
912 BIT(APICV_INHIBIT_REASON_HYPERV) |
913 BIT(APICV_INHIBIT_REASON_NESTED) |
914 BIT(APICV_INHIBIT_REASON_IRQWIN) |
915 BIT(APICV_INHIBIT_REASON_PIT_REINJ) |
916 BIT(APICV_INHIBIT_REASON_X2APIC);
918 return supported & BIT(bit);
921 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate)
923 avic_update_access_page(kvm, activate);
927 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
931 struct amd_svm_iommu_ir *ir;
932 struct vcpu_svm *svm = to_svm(vcpu);
934 if (!kvm_arch_has_assigned_device(vcpu->kvm))
938 * Here, we go through the per-vcpu ir_list to update all existing
939 * interrupt remapping table entry targeting this vcpu.
941 spin_lock_irqsave(&svm->ir_list_lock, flags);
943 if (list_empty(&svm->ir_list))
946 list_for_each_entry(ir, &svm->ir_list, node) {
947 ret = amd_iommu_update_ga(cpu, r, ir->data);
952 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
956 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
959 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
960 int h_physical_id = kvm_cpu_get_apicid(cpu);
961 struct vcpu_svm *svm = to_svm(vcpu);
963 if (!kvm_vcpu_apicv_active(vcpu))
967 * Since the host physical APIC id is 8 bits,
968 * we can support host APIC ID upto 255.
970 if (WARN_ON(h_physical_id > AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
973 entry = READ_ONCE(*(svm->avic_physical_id_cache));
974 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
976 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
977 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
979 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
980 if (svm->avic_is_running)
981 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
983 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
984 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
985 svm->avic_is_running);
988 void avic_vcpu_put(struct kvm_vcpu *vcpu)
991 struct vcpu_svm *svm = to_svm(vcpu);
993 if (!kvm_vcpu_apicv_active(vcpu))
996 entry = READ_ONCE(*(svm->avic_physical_id_cache));
997 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
998 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1000 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1001 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1005 * This function is called during VCPU halt/unhalt.
1007 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1009 struct vcpu_svm *svm = to_svm(vcpu);
1011 svm->avic_is_running = is_run;
1013 avic_vcpu_load(vcpu, vcpu->cpu);
1015 avic_vcpu_put(vcpu);
1018 void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1020 avic_set_running(vcpu, false);
1023 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1025 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
1026 kvm_vcpu_update_apicv(vcpu);
1027 avic_set_running(vcpu, true);