2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/spec-ctrl.h>
54 #include <asm/virtext.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id svm_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_SVM),
66 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
68 #define IOPM_ALLOC_ORDER 2
69 #define MSRPM_ALLOC_ORDER 1
71 #define SEG_TYPE_LDT 2
72 #define SEG_TYPE_BUSY_TSS16 3
74 #define SVM_FEATURE_NPT (1 << 0)
75 #define SVM_FEATURE_LBRV (1 << 1)
76 #define SVM_FEATURE_SVML (1 << 2)
77 #define SVM_FEATURE_NRIP (1 << 3)
78 #define SVM_FEATURE_TSC_RATE (1 << 4)
79 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
80 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
81 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
82 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
84 #define SVM_AVIC_DOORBELL 0xc001011b
86 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
87 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
88 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
92 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
93 #define TSC_RATIO_MIN 0x0000000000000001ULL
94 #define TSC_RATIO_MAX 0x000000ffffffffffULL
96 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
99 * 0xff is broadcast, so the max index allowed for physical APIC ID
100 * table is 0xfe. APIC IDs above 0xff are reserved.
102 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS 8
110 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
112 #define AVIC_VM_ID_BITS 24
113 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
116 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
121 static bool erratum_383_found __read_mostly;
123 static const u32 host_save_user_msrs[] = {
125 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
128 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
134 struct kvm_sev_info {
135 bool active; /* SEV enabled guest */
136 unsigned int asid; /* ASID used for this guest */
137 unsigned int handle; /* SEV firmware handle */
138 int fd; /* SEV device fd */
139 unsigned long pages_locked; /* Number of pages locked */
140 struct list_head regions_list; /* List of registered regions */
146 /* Struct members for AVIC */
149 struct page *avic_logical_id_table_page;
150 struct page *avic_physical_id_table_page;
151 struct hlist_node hnode;
153 struct kvm_sev_info sev_info;
158 struct nested_state {
164 /* These are the merged vectors */
167 /* gpa pointers to the real vectors */
171 /* A VMEXIT is required but not yet emulated */
174 /* cache for intercepts of the guest */
177 u32 intercept_exceptions;
180 /* Nested Paging related state */
184 #define MSRPM_OFFSETS 16
185 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
188 * Set osvw_len to higher value when updated Revision Guides
189 * are published and we know what the new status bits are
191 static uint64_t osvw_len = 4, osvw_status;
194 struct kvm_vcpu vcpu;
196 unsigned long vmcb_pa;
197 struct svm_cpu_data *svm_data;
198 uint64_t asid_generation;
199 uint64_t sysenter_esp;
200 uint64_t sysenter_eip;
207 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
221 struct nested_state nested;
224 u64 nmi_singlestep_guest_rflags;
226 unsigned int3_injected;
227 unsigned long int3_rip;
229 /* cached guest cpuid flags for faster access */
230 bool nrips_enabled : 1;
233 struct page *avic_backing_page;
234 u64 *avic_physical_id_cache;
235 bool avic_is_running;
238 * Per-vcpu list of struct amd_svm_iommu_ir:
239 * This is used mainly to store interrupt remapping information used
240 * when update the vcpu affinity. This avoids the need to scan for
241 * IRTE and try to match ga_tag in the IOMMU driver.
243 struct list_head ir_list;
244 spinlock_t ir_list_lock;
246 /* which host CPU was used for running this vcpu */
247 unsigned int last_cpu;
251 * This is a wrapper of struct amd_iommu_ir_data.
253 struct amd_svm_iommu_ir {
254 struct list_head node; /* Used by SVM for per-vcpu ir_list */
255 void *data; /* Storing pointer to struct amd_ir_data */
258 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
259 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
261 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
262 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
263 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
264 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
266 static DEFINE_PER_CPU(u64, current_tsc_ratio);
267 #define TSC_RATIO_DEFAULT 0x0100000000ULL
269 #define MSR_INVALID 0xffffffffU
271 static const struct svm_direct_access_msrs {
272 u32 index; /* Index of the MSR */
273 bool always; /* True if intercept is always on */
274 } direct_access_msrs[] = {
275 { .index = MSR_STAR, .always = true },
276 { .index = MSR_IA32_SYSENTER_CS, .always = true },
278 { .index = MSR_GS_BASE, .always = true },
279 { .index = MSR_FS_BASE, .always = true },
280 { .index = MSR_KERNEL_GS_BASE, .always = true },
281 { .index = MSR_LSTAR, .always = true },
282 { .index = MSR_CSTAR, .always = true },
283 { .index = MSR_SYSCALL_MASK, .always = true },
285 { .index = MSR_IA32_SPEC_CTRL, .always = false },
286 { .index = MSR_IA32_PRED_CMD, .always = false },
287 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
288 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
289 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
290 { .index = MSR_IA32_LASTINTTOIP, .always = false },
291 { .index = MSR_INVALID, .always = false },
294 /* enable NPT for AMD64 and X86 with PAE */
295 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
296 static bool npt_enabled = true;
298 static bool npt_enabled;
302 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
303 * pause_filter_count: On processors that support Pause filtering(indicated
304 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
305 * count value. On VMRUN this value is loaded into an internal counter.
306 * Each time a pause instruction is executed, this counter is decremented
307 * until it reaches zero at which time a #VMEXIT is generated if pause
308 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
309 * Intercept Filtering for more details.
310 * This also indicate if ple logic enabled.
312 * pause_filter_thresh: In addition, some processor families support advanced
313 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
314 * the amount of time a guest is allowed to execute in a pause loop.
315 * In this mode, a 16-bit pause filter threshold field is added in the
316 * VMCB. The threshold value is a cycle count that is used to reset the
317 * pause counter. As with simple pause filtering, VMRUN loads the pause
318 * count value from VMCB into an internal counter. Then, on each pause
319 * instruction the hardware checks the elapsed number of cycles since
320 * the most recent pause instruction against the pause filter threshold.
321 * If the elapsed cycle count is greater than the pause filter threshold,
322 * then the internal pause count is reloaded from the VMCB and execution
323 * continues. If the elapsed cycle count is less than the pause filter
324 * threshold, then the internal pause count is decremented. If the count
325 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
326 * triggered. If advanced pause filtering is supported and pause filter
327 * threshold field is set to zero, the filter will operate in the simpler,
331 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
332 module_param(pause_filter_thresh, ushort, 0444);
334 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
335 module_param(pause_filter_count, ushort, 0444);
337 /* Default doubles per-vcpu window every exit. */
338 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
339 module_param(pause_filter_count_grow, ushort, 0444);
341 /* Default resets per-vcpu window every exit to pause_filter_count. */
342 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
343 module_param(pause_filter_count_shrink, ushort, 0444);
345 /* Default is to compute the maximum so we can never overflow. */
346 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
347 module_param(pause_filter_count_max, ushort, 0444);
349 /* allow nested paging (virtualized MMU) for all guests */
350 static int npt = true;
351 module_param(npt, int, S_IRUGO);
353 /* allow nested virtualization in KVM/SVM */
354 static int nested = true;
355 module_param(nested, int, S_IRUGO);
357 /* enable / disable AVIC */
359 #ifdef CONFIG_X86_LOCAL_APIC
360 module_param(avic, int, S_IRUGO);
363 /* enable/disable Virtual VMLOAD VMSAVE */
364 static int vls = true;
365 module_param(vls, int, 0444);
367 /* enable/disable Virtual GIF */
368 static int vgif = true;
369 module_param(vgif, int, 0444);
371 /* enable/disable SEV support */
372 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
373 module_param(sev, int, 0444);
375 static u8 rsm_ins_bytes[] = "\x0f\xaa";
377 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
378 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
379 static void svm_complete_interrupts(struct vcpu_svm *svm);
381 static int nested_svm_exit_handled(struct vcpu_svm *svm);
382 static int nested_svm_intercept(struct vcpu_svm *svm);
383 static int nested_svm_vmexit(struct vcpu_svm *svm);
384 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
385 bool has_error_code, u32 error_code);
388 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
389 pause filter count */
390 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
391 VMCB_ASID, /* ASID */
392 VMCB_INTR, /* int_ctl, int_vector */
393 VMCB_NPT, /* npt_en, nCR3, gPAT */
394 VMCB_CR, /* CR0, CR3, CR4, EFER */
395 VMCB_DR, /* DR6, DR7 */
396 VMCB_DT, /* GDT, IDT */
397 VMCB_SEG, /* CS, DS, SS, ES, CPL */
398 VMCB_CR2, /* CR2 only */
399 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
400 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
401 * AVIC PHYSICAL_TABLE pointer,
402 * AVIC LOGICAL_TABLE pointer
407 /* TPR and CR2 are always written before VMRUN */
408 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
410 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
412 static unsigned int max_sev_asid;
413 static unsigned int min_sev_asid;
414 static unsigned long *sev_asid_bitmap;
415 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
418 struct list_head list;
419 unsigned long npages;
426 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
428 return container_of(kvm, struct kvm_svm, kvm);
431 static inline bool svm_sev_enabled(void)
436 static inline bool sev_guest(struct kvm *kvm)
438 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
443 static inline int sev_get_asid(struct kvm *kvm)
445 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
450 static inline void mark_all_dirty(struct vmcb *vmcb)
452 vmcb->control.clean = 0;
455 static inline void mark_all_clean(struct vmcb *vmcb)
457 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
458 & ~VMCB_ALWAYS_DIRTY_MASK;
461 static inline void mark_dirty(struct vmcb *vmcb, int bit)
463 vmcb->control.clean &= ~(1 << bit);
466 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
468 return container_of(vcpu, struct vcpu_svm, vcpu);
471 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
473 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
474 mark_dirty(svm->vmcb, VMCB_AVIC);
477 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
479 struct vcpu_svm *svm = to_svm(vcpu);
480 u64 *entry = svm->avic_physical_id_cache;
485 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
488 static void recalc_intercepts(struct vcpu_svm *svm)
490 struct vmcb_control_area *c, *h;
491 struct nested_state *g;
493 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
495 if (!is_guest_mode(&svm->vcpu))
498 c = &svm->vmcb->control;
499 h = &svm->nested.hsave->control;
502 c->intercept_cr = h->intercept_cr | g->intercept_cr;
503 c->intercept_dr = h->intercept_dr | g->intercept_dr;
504 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
505 c->intercept = h->intercept | g->intercept;
508 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
510 if (is_guest_mode(&svm->vcpu))
511 return svm->nested.hsave;
516 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
518 struct vmcb *vmcb = get_host_vmcb(svm);
520 vmcb->control.intercept_cr |= (1U << bit);
522 recalc_intercepts(svm);
525 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
527 struct vmcb *vmcb = get_host_vmcb(svm);
529 vmcb->control.intercept_cr &= ~(1U << bit);
531 recalc_intercepts(svm);
534 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
536 struct vmcb *vmcb = get_host_vmcb(svm);
538 return vmcb->control.intercept_cr & (1U << bit);
541 static inline void set_dr_intercepts(struct vcpu_svm *svm)
543 struct vmcb *vmcb = get_host_vmcb(svm);
545 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
546 | (1 << INTERCEPT_DR1_READ)
547 | (1 << INTERCEPT_DR2_READ)
548 | (1 << INTERCEPT_DR3_READ)
549 | (1 << INTERCEPT_DR4_READ)
550 | (1 << INTERCEPT_DR5_READ)
551 | (1 << INTERCEPT_DR6_READ)
552 | (1 << INTERCEPT_DR7_READ)
553 | (1 << INTERCEPT_DR0_WRITE)
554 | (1 << INTERCEPT_DR1_WRITE)
555 | (1 << INTERCEPT_DR2_WRITE)
556 | (1 << INTERCEPT_DR3_WRITE)
557 | (1 << INTERCEPT_DR4_WRITE)
558 | (1 << INTERCEPT_DR5_WRITE)
559 | (1 << INTERCEPT_DR6_WRITE)
560 | (1 << INTERCEPT_DR7_WRITE);
562 recalc_intercepts(svm);
565 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
567 struct vmcb *vmcb = get_host_vmcb(svm);
569 vmcb->control.intercept_dr = 0;
571 recalc_intercepts(svm);
574 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
576 struct vmcb *vmcb = get_host_vmcb(svm);
578 vmcb->control.intercept_exceptions |= (1U << bit);
580 recalc_intercepts(svm);
583 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
585 struct vmcb *vmcb = get_host_vmcb(svm);
587 vmcb->control.intercept_exceptions &= ~(1U << bit);
589 recalc_intercepts(svm);
592 static inline void set_intercept(struct vcpu_svm *svm, int bit)
594 struct vmcb *vmcb = get_host_vmcb(svm);
596 vmcb->control.intercept |= (1ULL << bit);
598 recalc_intercepts(svm);
601 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
603 struct vmcb *vmcb = get_host_vmcb(svm);
605 vmcb->control.intercept &= ~(1ULL << bit);
607 recalc_intercepts(svm);
610 static inline bool vgif_enabled(struct vcpu_svm *svm)
612 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
615 static inline void enable_gif(struct vcpu_svm *svm)
617 if (vgif_enabled(svm))
618 svm->vmcb->control.int_ctl |= V_GIF_MASK;
620 svm->vcpu.arch.hflags |= HF_GIF_MASK;
623 static inline void disable_gif(struct vcpu_svm *svm)
625 if (vgif_enabled(svm))
626 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
628 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
631 static inline bool gif_set(struct vcpu_svm *svm)
633 if (vgif_enabled(svm))
634 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
636 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
639 static unsigned long iopm_base;
641 struct kvm_ldttss_desc {
644 unsigned base1:8, type:5, dpl:2, p:1;
645 unsigned limit1:4, zero0:3, g:1, base2:8;
648 } __attribute__((packed));
650 struct svm_cpu_data {
657 struct kvm_ldttss_desc *tss_desc;
659 struct page *save_area;
660 struct vmcb *current_vmcb;
662 /* index = sev_asid, value = vmcb pointer */
663 struct vmcb **sev_vmcbs;
666 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
668 struct svm_init_data {
673 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
675 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
676 #define MSRS_RANGE_SIZE 2048
677 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
679 static u32 svm_msrpm_offset(u32 msr)
684 for (i = 0; i < NUM_MSR_MAPS; i++) {
685 if (msr < msrpm_ranges[i] ||
686 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
689 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
690 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
692 /* Now we have the u8 offset - but need the u32 offset */
696 /* MSR not in any range */
700 #define MAX_INST_SIZE 15
702 static inline void clgi(void)
704 asm volatile (__ex(SVM_CLGI));
707 static inline void stgi(void)
709 asm volatile (__ex(SVM_STGI));
712 static inline void invlpga(unsigned long addr, u32 asid)
714 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
717 static int get_npt_level(struct kvm_vcpu *vcpu)
720 return PT64_ROOT_4LEVEL;
722 return PT32E_ROOT_LEVEL;
726 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
728 vcpu->arch.efer = efer;
729 if (!npt_enabled && !(efer & EFER_LMA))
732 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
733 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
736 static int is_external_interrupt(u32 info)
738 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
739 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
742 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
744 struct vcpu_svm *svm = to_svm(vcpu);
747 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
748 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
752 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
754 struct vcpu_svm *svm = to_svm(vcpu);
757 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
759 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
763 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
765 struct vcpu_svm *svm = to_svm(vcpu);
767 if (svm->vmcb->control.next_rip != 0) {
768 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
769 svm->next_rip = svm->vmcb->control.next_rip;
772 if (!svm->next_rip) {
773 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
775 printk(KERN_DEBUG "%s: NOP\n", __func__);
778 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
779 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
780 __func__, kvm_rip_read(vcpu), svm->next_rip);
782 kvm_rip_write(vcpu, svm->next_rip);
783 svm_set_interrupt_shadow(vcpu, 0);
786 static void svm_queue_exception(struct kvm_vcpu *vcpu)
788 struct vcpu_svm *svm = to_svm(vcpu);
789 unsigned nr = vcpu->arch.exception.nr;
790 bool has_error_code = vcpu->arch.exception.has_error_code;
791 bool reinject = vcpu->arch.exception.injected;
792 u32 error_code = vcpu->arch.exception.error_code;
795 * If we are within a nested VM we'd better #VMEXIT and let the guest
796 * handle the exception
799 nested_svm_check_exception(svm, nr, has_error_code, error_code))
802 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
803 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
806 * For guest debugging where we have to reinject #BP if some
807 * INT3 is guest-owned:
808 * Emulate nRIP by moving RIP forward. Will fail if injection
809 * raises a fault that is not intercepted. Still better than
810 * failing in all cases.
812 skip_emulated_instruction(&svm->vcpu);
813 rip = kvm_rip_read(&svm->vcpu);
814 svm->int3_rip = rip + svm->vmcb->save.cs.base;
815 svm->int3_injected = rip - old_rip;
818 svm->vmcb->control.event_inj = nr
820 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
821 | SVM_EVTINJ_TYPE_EXEPT;
822 svm->vmcb->control.event_inj_err = error_code;
825 static void svm_init_erratum_383(void)
831 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
834 /* Use _safe variants to not break nested virtualization */
835 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
841 low = lower_32_bits(val);
842 high = upper_32_bits(val);
844 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
846 erratum_383_found = true;
849 static void svm_init_osvw(struct kvm_vcpu *vcpu)
852 * Guests should see errata 400 and 415 as fixed (assuming that
853 * HLT and IO instructions are intercepted).
855 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
856 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
859 * By increasing VCPU's osvw.length to 3 we are telling the guest that
860 * all osvw.status bits inside that length, including bit 0 (which is
861 * reserved for erratum 298), are valid. However, if host processor's
862 * osvw_len is 0 then osvw_status[0] carries no information. We need to
863 * be conservative here and therefore we tell the guest that erratum 298
864 * is present (because we really don't know).
866 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
867 vcpu->arch.osvw.status |= 1;
870 static int has_svm(void)
874 if (!cpu_has_svm(&msg)) {
875 printk(KERN_INFO "has_svm: %s\n", msg);
882 static void svm_hardware_disable(void)
884 /* Make sure we clean up behind us */
885 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
886 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
890 amd_pmu_disable_virt();
893 static int svm_hardware_enable(void)
896 struct svm_cpu_data *sd;
898 struct desc_struct *gdt;
899 int me = raw_smp_processor_id();
901 rdmsrl(MSR_EFER, efer);
902 if (efer & EFER_SVME)
906 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
909 sd = per_cpu(svm_data, me);
911 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
915 sd->asid_generation = 1;
916 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
917 sd->next_asid = sd->max_asid + 1;
918 sd->min_asid = max_sev_asid + 1;
920 gdt = get_current_gdt_rw();
921 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
923 wrmsrl(MSR_EFER, efer | EFER_SVME);
925 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
927 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
928 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
929 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
936 * Note that it is possible to have a system with mixed processor
937 * revisions and therefore different OSVW bits. If bits are not the same
938 * on different processors then choose the worst case (i.e. if erratum
939 * is present on one processor and not on another then assume that the
940 * erratum is present everywhere).
942 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
943 uint64_t len, status = 0;
946 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
948 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
952 osvw_status = osvw_len = 0;
956 osvw_status |= status;
957 osvw_status &= (1ULL << osvw_len) - 1;
960 osvw_status = osvw_len = 0;
962 svm_init_erratum_383();
964 amd_pmu_enable_virt();
969 static void svm_cpu_uninit(int cpu)
971 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
976 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
977 kfree(sd->sev_vmcbs);
978 __free_page(sd->save_area);
982 static int svm_cpu_init(int cpu)
984 struct svm_cpu_data *sd;
987 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
992 sd->save_area = alloc_page(GFP_KERNEL);
996 if (svm_sev_enabled()) {
998 sd->sev_vmcbs = kmalloc((max_sev_asid + 1) * sizeof(void *), GFP_KERNEL);
1003 per_cpu(svm_data, cpu) = sd;
1013 static bool valid_msr_intercept(u32 index)
1017 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
1018 if (direct_access_msrs[i].index == index)
1024 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
1031 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
1032 to_svm(vcpu)->msrpm;
1034 offset = svm_msrpm_offset(msr);
1035 bit_write = 2 * (msr & 0x0f) + 1;
1036 tmp = msrpm[offset];
1038 BUG_ON(offset == MSR_INVALID);
1040 return !!test_bit(bit_write, &tmp);
1043 static void set_msr_interception(u32 *msrpm, unsigned msr,
1044 int read, int write)
1046 u8 bit_read, bit_write;
1051 * If this warning triggers extend the direct_access_msrs list at the
1052 * beginning of the file
1054 WARN_ON(!valid_msr_intercept(msr));
1056 offset = svm_msrpm_offset(msr);
1057 bit_read = 2 * (msr & 0x0f);
1058 bit_write = 2 * (msr & 0x0f) + 1;
1059 tmp = msrpm[offset];
1061 BUG_ON(offset == MSR_INVALID);
1063 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
1064 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
1066 msrpm[offset] = tmp;
1069 static void svm_vcpu_init_msrpm(u32 *msrpm)
1073 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
1075 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1076 if (!direct_access_msrs[i].always)
1079 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
1083 static void add_msr_offset(u32 offset)
1087 for (i = 0; i < MSRPM_OFFSETS; ++i) {
1089 /* Offset already in list? */
1090 if (msrpm_offsets[i] == offset)
1093 /* Slot used by another offset? */
1094 if (msrpm_offsets[i] != MSR_INVALID)
1097 /* Add offset to list */
1098 msrpm_offsets[i] = offset;
1104 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1105 * increase MSRPM_OFFSETS in this case.
1110 static void init_msrpm_offsets(void)
1114 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
1116 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
1119 offset = svm_msrpm_offset(direct_access_msrs[i].index);
1120 BUG_ON(offset == MSR_INVALID);
1122 add_msr_offset(offset);
1126 static void svm_enable_lbrv(struct vcpu_svm *svm)
1128 u32 *msrpm = svm->msrpm;
1130 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1131 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1132 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1133 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1134 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1137 static void svm_disable_lbrv(struct vcpu_svm *svm)
1139 u32 *msrpm = svm->msrpm;
1141 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1142 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1143 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1144 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1145 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1148 static void disable_nmi_singlestep(struct vcpu_svm *svm)
1150 svm->nmi_singlestep = false;
1152 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1153 /* Clear our flags if they were not set by the guest */
1154 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1155 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1156 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1157 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1162 * This hash table is used to map VM_ID to a struct kvm_svm,
1163 * when handling AMD IOMMU GALOG notification to schedule in
1164 * a particular vCPU.
1166 #define SVM_VM_DATA_HASH_BITS 8
1167 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1168 static u32 next_vm_id = 0;
1169 static bool next_vm_id_wrapped = 0;
1170 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1173 * This function is called from IOMMU driver to notify
1174 * SVM to schedule in a particular vCPU of a particular VM.
1176 static int avic_ga_log_notifier(u32 ga_tag)
1178 unsigned long flags;
1179 struct kvm_svm *kvm_svm;
1180 struct kvm_vcpu *vcpu = NULL;
1181 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1182 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1184 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1186 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1187 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
1188 if (kvm_svm->avic_vm_id != vm_id)
1190 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
1193 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1196 * At this point, the IOMMU should have already set the pending
1197 * bit in the vAPIC backing page. So, we just need to schedule
1201 kvm_vcpu_wake_up(vcpu);
1206 static __init int sev_hardware_setup(void)
1208 struct sev_user_data_status *status;
1211 /* Maximum number of encrypted guests supported simultaneously */
1212 max_sev_asid = cpuid_ecx(0x8000001F);
1217 /* Minimum ASID value that should be used for SEV guest */
1218 min_sev_asid = cpuid_edx(0x8000001F);
1220 /* Initialize SEV ASID bitmap */
1221 sev_asid_bitmap = kcalloc(BITS_TO_LONGS(max_sev_asid),
1222 sizeof(unsigned long), GFP_KERNEL);
1223 if (!sev_asid_bitmap)
1226 status = kmalloc(sizeof(*status), GFP_KERNEL);
1231 * Check SEV platform status.
1233 * PLATFORM_STATUS can be called in any state, if we failed to query
1234 * the PLATFORM status then either PSP firmware does not support SEV
1235 * feature or SEV firmware is dead.
1237 rc = sev_platform_status(status, NULL);
1241 pr_info("SEV supported\n");
1248 static void grow_ple_window(struct kvm_vcpu *vcpu)
1250 struct vcpu_svm *svm = to_svm(vcpu);
1251 struct vmcb_control_area *control = &svm->vmcb->control;
1252 int old = control->pause_filter_count;
1254 control->pause_filter_count = __grow_ple_window(old,
1256 pause_filter_count_grow,
1257 pause_filter_count_max);
1259 if (control->pause_filter_count != old)
1260 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1262 trace_kvm_ple_window_grow(vcpu->vcpu_id,
1263 control->pause_filter_count, old);
1266 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1268 struct vcpu_svm *svm = to_svm(vcpu);
1269 struct vmcb_control_area *control = &svm->vmcb->control;
1270 int old = control->pause_filter_count;
1272 control->pause_filter_count =
1273 __shrink_ple_window(old,
1275 pause_filter_count_shrink,
1276 pause_filter_count);
1277 if (control->pause_filter_count != old)
1278 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1280 trace_kvm_ple_window_shrink(vcpu->vcpu_id,
1281 control->pause_filter_count, old);
1284 static __init int svm_hardware_setup(void)
1287 struct page *iopm_pages;
1291 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1296 iopm_va = page_address(iopm_pages);
1297 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1298 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1300 init_msrpm_offsets();
1302 if (boot_cpu_has(X86_FEATURE_NX))
1303 kvm_enable_efer_bits(EFER_NX);
1305 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1306 kvm_enable_efer_bits(EFER_FFXSR);
1308 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1309 kvm_has_tsc_control = true;
1310 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1311 kvm_tsc_scaling_ratio_frac_bits = 32;
1314 /* Check for pause filtering support */
1315 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1316 pause_filter_count = 0;
1317 pause_filter_thresh = 0;
1318 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
1319 pause_filter_thresh = 0;
1323 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1324 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1328 if (boot_cpu_has(X86_FEATURE_SEV) &&
1329 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
1330 r = sev_hardware_setup();
1338 for_each_possible_cpu(cpu) {
1339 r = svm_cpu_init(cpu);
1344 if (!boot_cpu_has(X86_FEATURE_NPT))
1345 npt_enabled = false;
1347 if (npt_enabled && !npt) {
1348 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1349 npt_enabled = false;
1353 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1360 !boot_cpu_has(X86_FEATURE_AVIC) ||
1361 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1364 pr_info("AVIC enabled\n");
1366 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1372 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1373 !IS_ENABLED(CONFIG_X86_64)) {
1376 pr_info("Virtual VMLOAD VMSAVE supported\n");
1381 if (!boot_cpu_has(X86_FEATURE_VGIF))
1384 pr_info("Virtual GIF supported\n");
1390 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1395 static __exit void svm_hardware_unsetup(void)
1399 if (svm_sev_enabled())
1400 kfree(sev_asid_bitmap);
1402 for_each_possible_cpu(cpu)
1403 svm_cpu_uninit(cpu);
1405 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1409 static void init_seg(struct vmcb_seg *seg)
1412 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1413 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1414 seg->limit = 0xffff;
1418 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1421 seg->attrib = SVM_SELECTOR_P_MASK | type;
1422 seg->limit = 0xffff;
1426 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
1428 struct vcpu_svm *svm = to_svm(vcpu);
1430 if (is_guest_mode(vcpu))
1431 return svm->nested.hsave->control.tsc_offset;
1433 return vcpu->arch.tsc_offset;
1436 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1438 struct vcpu_svm *svm = to_svm(vcpu);
1439 u64 g_tsc_offset = 0;
1441 if (is_guest_mode(vcpu)) {
1442 /* Write L1's TSC offset. */
1443 g_tsc_offset = svm->vmcb->control.tsc_offset -
1444 svm->nested.hsave->control.tsc_offset;
1445 svm->nested.hsave->control.tsc_offset = offset;
1447 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1448 svm->vmcb->control.tsc_offset,
1451 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1453 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1456 static void avic_init_vmcb(struct vcpu_svm *svm)
1458 struct vmcb *vmcb = svm->vmcb;
1459 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
1460 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1461 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
1462 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
1464 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1465 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1466 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1467 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1468 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1471 static void init_vmcb(struct vcpu_svm *svm)
1473 struct vmcb_control_area *control = &svm->vmcb->control;
1474 struct vmcb_save_area *save = &svm->vmcb->save;
1476 svm->vcpu.arch.hflags = 0;
1478 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1479 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1480 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1481 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1482 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1483 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1484 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1485 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1487 set_dr_intercepts(svm);
1489 set_exception_intercept(svm, PF_VECTOR);
1490 set_exception_intercept(svm, UD_VECTOR);
1491 set_exception_intercept(svm, MC_VECTOR);
1492 set_exception_intercept(svm, AC_VECTOR);
1493 set_exception_intercept(svm, DB_VECTOR);
1495 * Guest access to VMware backdoor ports could legitimately
1496 * trigger #GP because of TSS I/O permission bitmap.
1497 * We intercept those #GP and allow access to them anyway
1500 if (enable_vmware_backdoor)
1501 set_exception_intercept(svm, GP_VECTOR);
1503 set_intercept(svm, INTERCEPT_INTR);
1504 set_intercept(svm, INTERCEPT_NMI);
1505 set_intercept(svm, INTERCEPT_SMI);
1506 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1507 set_intercept(svm, INTERCEPT_RDPMC);
1508 set_intercept(svm, INTERCEPT_CPUID);
1509 set_intercept(svm, INTERCEPT_INVD);
1510 set_intercept(svm, INTERCEPT_INVLPG);
1511 set_intercept(svm, INTERCEPT_INVLPGA);
1512 set_intercept(svm, INTERCEPT_IOIO_PROT);
1513 set_intercept(svm, INTERCEPT_MSR_PROT);
1514 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1515 set_intercept(svm, INTERCEPT_SHUTDOWN);
1516 set_intercept(svm, INTERCEPT_VMRUN);
1517 set_intercept(svm, INTERCEPT_VMMCALL);
1518 set_intercept(svm, INTERCEPT_VMLOAD);
1519 set_intercept(svm, INTERCEPT_VMSAVE);
1520 set_intercept(svm, INTERCEPT_STGI);
1521 set_intercept(svm, INTERCEPT_CLGI);
1522 set_intercept(svm, INTERCEPT_SKINIT);
1523 set_intercept(svm, INTERCEPT_WBINVD);
1524 set_intercept(svm, INTERCEPT_XSETBV);
1525 set_intercept(svm, INTERCEPT_RSM);
1527 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1528 set_intercept(svm, INTERCEPT_MONITOR);
1529 set_intercept(svm, INTERCEPT_MWAIT);
1532 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1533 set_intercept(svm, INTERCEPT_HLT);
1535 control->iopm_base_pa = __sme_set(iopm_base);
1536 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1537 control->int_ctl = V_INTR_MASKING_MASK;
1539 init_seg(&save->es);
1540 init_seg(&save->ss);
1541 init_seg(&save->ds);
1542 init_seg(&save->fs);
1543 init_seg(&save->gs);
1545 save->cs.selector = 0xf000;
1546 save->cs.base = 0xffff0000;
1547 /* Executable/Readable Code Segment */
1548 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1549 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1550 save->cs.limit = 0xffff;
1552 save->gdtr.limit = 0xffff;
1553 save->idtr.limit = 0xffff;
1555 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1556 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1558 svm_set_efer(&svm->vcpu, 0);
1559 save->dr6 = 0xffff0ff0;
1560 kvm_set_rflags(&svm->vcpu, 2);
1561 save->rip = 0x0000fff0;
1562 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1565 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1566 * It also updates the guest-visible cr0 value.
1568 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1569 kvm_mmu_reset_context(&svm->vcpu);
1571 save->cr4 = X86_CR4_PAE;
1575 /* Setup VMCB for Nested Paging */
1576 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1577 clr_intercept(svm, INTERCEPT_INVLPG);
1578 clr_exception_intercept(svm, PF_VECTOR);
1579 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1580 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1581 save->g_pat = svm->vcpu.arch.pat;
1585 svm->asid_generation = 0;
1587 svm->nested.vmcb = 0;
1588 svm->vcpu.arch.hflags = 0;
1590 if (pause_filter_count) {
1591 control->pause_filter_count = pause_filter_count;
1592 if (pause_filter_thresh)
1593 control->pause_filter_thresh = pause_filter_thresh;
1594 set_intercept(svm, INTERCEPT_PAUSE);
1596 clr_intercept(svm, INTERCEPT_PAUSE);
1599 if (kvm_vcpu_apicv_active(&svm->vcpu))
1600 avic_init_vmcb(svm);
1603 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1604 * in VMCB and clear intercepts to avoid #VMEXIT.
1607 clr_intercept(svm, INTERCEPT_VMLOAD);
1608 clr_intercept(svm, INTERCEPT_VMSAVE);
1609 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1613 clr_intercept(svm, INTERCEPT_STGI);
1614 clr_intercept(svm, INTERCEPT_CLGI);
1615 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1618 if (sev_guest(svm->vcpu.kvm)) {
1619 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1620 clr_exception_intercept(svm, UD_VECTOR);
1623 mark_all_dirty(svm->vmcb);
1629 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1632 u64 *avic_physical_id_table;
1633 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
1635 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1638 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
1640 return &avic_physical_id_table[index];
1645 * AVIC hardware walks the nested page table to check permissions,
1646 * but does not use the SPA address specified in the leaf page
1647 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1648 * field of the VMCB. Therefore, we set up the
1649 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1651 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1653 struct kvm *kvm = vcpu->kvm;
1656 if (kvm->arch.apic_access_page_done)
1659 ret = x86_set_memory_region(kvm,
1660 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1661 APIC_DEFAULT_PHYS_BASE,
1666 kvm->arch.apic_access_page_done = true;
1670 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1673 u64 *entry, new_entry;
1674 int id = vcpu->vcpu_id;
1675 struct vcpu_svm *svm = to_svm(vcpu);
1677 ret = avic_init_access_page(vcpu);
1681 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1684 if (!svm->vcpu.arch.apic->regs)
1687 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1689 /* Setting AVIC backing page address in the phy APIC ID table */
1690 entry = avic_get_physical_id_entry(vcpu, id);
1694 new_entry = READ_ONCE(*entry);
1695 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1696 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1697 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1698 WRITE_ONCE(*entry, new_entry);
1700 svm->avic_physical_id_cache = entry;
1705 static void __sev_asid_free(int asid)
1707 struct svm_cpu_data *sd;
1711 clear_bit(pos, sev_asid_bitmap);
1713 for_each_possible_cpu(cpu) {
1714 sd = per_cpu(svm_data, cpu);
1715 sd->sev_vmcbs[pos] = NULL;
1719 static void sev_asid_free(struct kvm *kvm)
1721 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1723 __sev_asid_free(sev->asid);
1726 static void sev_unbind_asid(struct kvm *kvm, unsigned int handle)
1728 struct sev_data_decommission *decommission;
1729 struct sev_data_deactivate *data;
1734 data = kzalloc(sizeof(*data), GFP_KERNEL);
1738 /* deactivate handle */
1739 data->handle = handle;
1740 sev_guest_deactivate(data, NULL);
1742 wbinvd_on_all_cpus();
1743 sev_guest_df_flush(NULL);
1746 decommission = kzalloc(sizeof(*decommission), GFP_KERNEL);
1750 /* decommission handle */
1751 decommission->handle = handle;
1752 sev_guest_decommission(decommission, NULL);
1754 kfree(decommission);
1757 static struct page **sev_pin_memory(struct kvm *kvm, unsigned long uaddr,
1758 unsigned long ulen, unsigned long *n,
1761 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1762 unsigned long npages, npinned, size;
1763 unsigned long locked, lock_limit;
1764 struct page **pages;
1767 /* Calculate number of pages. */
1768 first = (uaddr & PAGE_MASK) >> PAGE_SHIFT;
1769 last = ((uaddr + ulen - 1) & PAGE_MASK) >> PAGE_SHIFT;
1770 npages = (last - first + 1);
1772 locked = sev->pages_locked + npages;
1773 lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
1774 if (locked > lock_limit && !capable(CAP_IPC_LOCK)) {
1775 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked, lock_limit);
1779 /* Avoid using vmalloc for smaller buffers. */
1780 size = npages * sizeof(struct page *);
1781 if (size > PAGE_SIZE)
1782 pages = vmalloc(size);
1784 pages = kmalloc(size, GFP_KERNEL);
1789 /* Pin the user virtual address. */
1790 npinned = get_user_pages_fast(uaddr, npages, write ? FOLL_WRITE : 0, pages);
1791 if (npinned != npages) {
1792 pr_err("SEV: Failure locking %lu pages.\n", npages);
1797 sev->pages_locked = locked;
1803 release_pages(pages, npinned);
1809 static void sev_unpin_memory(struct kvm *kvm, struct page **pages,
1810 unsigned long npages)
1812 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1814 release_pages(pages, npages);
1816 sev->pages_locked -= npages;
1819 static void sev_clflush_pages(struct page *pages[], unsigned long npages)
1821 uint8_t *page_virtual;
1824 if (npages == 0 || pages == NULL)
1827 for (i = 0; i < npages; i++) {
1828 page_virtual = kmap_atomic(pages[i]);
1829 clflush_cache_range(page_virtual, PAGE_SIZE);
1830 kunmap_atomic(page_virtual);
1834 static void __unregister_enc_region_locked(struct kvm *kvm,
1835 struct enc_region *region)
1838 * The guest may change the memory encryption attribute from C=0 -> C=1
1839 * or vice versa for this memory range. Lets make sure caches are
1840 * flushed to ensure that guest data gets written into memory with
1843 sev_clflush_pages(region->pages, region->npages);
1845 sev_unpin_memory(kvm, region->pages, region->npages);
1846 list_del(®ion->list);
1850 static struct kvm *svm_vm_alloc(void)
1852 struct kvm_svm *kvm_svm = kzalloc(sizeof(struct kvm_svm), GFP_KERNEL);
1853 return &kvm_svm->kvm;
1856 static void svm_vm_free(struct kvm *kvm)
1858 kfree(to_kvm_svm(kvm));
1861 static void sev_vm_destroy(struct kvm *kvm)
1863 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
1864 struct list_head *head = &sev->regions_list;
1865 struct list_head *pos, *q;
1867 if (!sev_guest(kvm))
1870 mutex_lock(&kvm->lock);
1873 * if userspace was terminated before unregistering the memory regions
1874 * then lets unpin all the registered memory.
1876 if (!list_empty(head)) {
1877 list_for_each_safe(pos, q, head) {
1878 __unregister_enc_region_locked(kvm,
1879 list_entry(pos, struct enc_region, list));
1883 mutex_unlock(&kvm->lock);
1885 sev_unbind_asid(kvm, sev->handle);
1889 static void avic_vm_destroy(struct kvm *kvm)
1891 unsigned long flags;
1892 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1897 if (kvm_svm->avic_logical_id_table_page)
1898 __free_page(kvm_svm->avic_logical_id_table_page);
1899 if (kvm_svm->avic_physical_id_table_page)
1900 __free_page(kvm_svm->avic_physical_id_table_page);
1902 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1903 hash_del(&kvm_svm->hnode);
1904 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1907 static void svm_vm_destroy(struct kvm *kvm)
1909 avic_vm_destroy(kvm);
1910 sev_vm_destroy(kvm);
1913 static int avic_vm_init(struct kvm *kvm)
1915 unsigned long flags;
1917 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
1919 struct page *p_page;
1920 struct page *l_page;
1926 /* Allocating physical APIC ID table (4KB) */
1927 p_page = alloc_page(GFP_KERNEL);
1931 kvm_svm->avic_physical_id_table_page = p_page;
1932 clear_page(page_address(p_page));
1934 /* Allocating logical APIC ID table (4KB) */
1935 l_page = alloc_page(GFP_KERNEL);
1939 kvm_svm->avic_logical_id_table_page = l_page;
1940 clear_page(page_address(l_page));
1942 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1944 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1945 if (vm_id == 0) { /* id is 1-based, zero is not okay */
1946 next_vm_id_wrapped = 1;
1949 /* Is it still in use? Only possible if wrapped at least once */
1950 if (next_vm_id_wrapped) {
1951 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
1952 if (k2->avic_vm_id == vm_id)
1956 kvm_svm->avic_vm_id = vm_id;
1957 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
1958 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1963 avic_vm_destroy(kvm);
1968 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1971 unsigned long flags;
1972 struct amd_svm_iommu_ir *ir;
1973 struct vcpu_svm *svm = to_svm(vcpu);
1975 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1979 * Here, we go through the per-vcpu ir_list to update all existing
1980 * interrupt remapping table entry targeting this vcpu.
1982 spin_lock_irqsave(&svm->ir_list_lock, flags);
1984 if (list_empty(&svm->ir_list))
1987 list_for_each_entry(ir, &svm->ir_list, node) {
1988 ret = amd_iommu_update_ga(cpu, r, ir->data);
1993 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1997 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2000 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2001 int h_physical_id = kvm_cpu_get_apicid(cpu);
2002 struct vcpu_svm *svm = to_svm(vcpu);
2004 if (!kvm_vcpu_apicv_active(vcpu))
2007 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
2010 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2011 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
2013 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
2014 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
2016 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2017 if (svm->avic_is_running)
2018 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2020 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2021 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
2022 svm->avic_is_running);
2025 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
2028 struct vcpu_svm *svm = to_svm(vcpu);
2030 if (!kvm_vcpu_apicv_active(vcpu))
2033 entry = READ_ONCE(*(svm->avic_physical_id_cache));
2034 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
2035 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
2037 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
2038 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
2042 * This function is called during VCPU halt/unhalt.
2044 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
2046 struct vcpu_svm *svm = to_svm(vcpu);
2048 svm->avic_is_running = is_run;
2050 avic_vcpu_load(vcpu, vcpu->cpu);
2052 avic_vcpu_put(vcpu);
2055 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
2057 struct vcpu_svm *svm = to_svm(vcpu);
2061 vcpu->arch.microcode_version = 0x01000065;
2065 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
2066 MSR_IA32_APICBASE_ENABLE;
2067 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
2068 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
2072 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
2073 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
2075 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
2076 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
2079 static int avic_init_vcpu(struct vcpu_svm *svm)
2083 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2086 ret = avic_init_backing_page(&svm->vcpu);
2090 INIT_LIST_HEAD(&svm->ir_list);
2091 spin_lock_init(&svm->ir_list_lock);
2096 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
2098 struct vcpu_svm *svm;
2100 struct page *msrpm_pages;
2101 struct page *hsave_page;
2102 struct page *nested_msrpm_pages;
2105 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2111 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
2116 page = alloc_page(GFP_KERNEL);
2120 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2124 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
2125 if (!nested_msrpm_pages)
2128 hsave_page = alloc_page(GFP_KERNEL);
2132 err = avic_init_vcpu(svm);
2136 /* We initialize this flag to true to make sure that the is_running
2137 * bit would be set the first time the vcpu is loaded.
2139 svm->avic_is_running = true;
2141 svm->nested.hsave = page_address(hsave_page);
2143 svm->msrpm = page_address(msrpm_pages);
2144 svm_vcpu_init_msrpm(svm->msrpm);
2146 svm->nested.msrpm = page_address(nested_msrpm_pages);
2147 svm_vcpu_init_msrpm(svm->nested.msrpm);
2149 svm->vmcb = page_address(page);
2150 clear_page(svm->vmcb);
2151 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
2152 svm->asid_generation = 0;
2155 svm_init_osvw(&svm->vcpu);
2160 __free_page(hsave_page);
2162 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
2164 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
2168 kvm_vcpu_uninit(&svm->vcpu);
2170 kmem_cache_free(kvm_vcpu_cache, svm);
2172 return ERR_PTR(err);
2175 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
2177 struct vcpu_svm *svm = to_svm(vcpu);
2179 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
2180 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
2181 __free_page(virt_to_page(svm->nested.hsave));
2182 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
2183 kvm_vcpu_uninit(vcpu);
2184 kmem_cache_free(kvm_vcpu_cache, svm);
2186 * The vmcb page can be recycled, causing a false negative in
2187 * svm_vcpu_load(). So do a full IBPB now.
2189 indirect_branch_prediction_barrier();
2192 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2194 struct vcpu_svm *svm = to_svm(vcpu);
2195 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2198 if (unlikely(cpu != vcpu->cpu)) {
2199 svm->asid_generation = 0;
2200 mark_all_dirty(svm->vmcb);
2203 #ifdef CONFIG_X86_64
2204 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
2206 savesegment(fs, svm->host.fs);
2207 savesegment(gs, svm->host.gs);
2208 svm->host.ldt = kvm_read_ldt();
2210 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2211 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2213 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
2214 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2215 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
2216 __this_cpu_write(current_tsc_ratio, tsc_ratio);
2217 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
2220 /* This assumes that the kernel never uses MSR_TSC_AUX */
2221 if (static_cpu_has(X86_FEATURE_RDTSCP))
2222 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2224 if (sd->current_vmcb != svm->vmcb) {
2225 sd->current_vmcb = svm->vmcb;
2226 indirect_branch_prediction_barrier();
2228 avic_vcpu_load(vcpu, cpu);
2231 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
2233 struct vcpu_svm *svm = to_svm(vcpu);
2236 avic_vcpu_put(vcpu);
2238 ++vcpu->stat.host_state_reload;
2239 kvm_load_ldt(svm->host.ldt);
2240 #ifdef CONFIG_X86_64
2241 loadsegment(fs, svm->host.fs);
2242 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
2243 load_gs_index(svm->host.gs);
2245 #ifdef CONFIG_X86_32_LAZY_GS
2246 loadsegment(gs, svm->host.gs);
2249 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
2250 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
2253 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
2255 avic_set_running(vcpu, false);
2258 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
2260 avic_set_running(vcpu, true);
2263 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
2265 struct vcpu_svm *svm = to_svm(vcpu);
2266 unsigned long rflags = svm->vmcb->save.rflags;
2268 if (svm->nmi_singlestep) {
2269 /* Hide our flags if they were not set by the guest */
2270 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
2271 rflags &= ~X86_EFLAGS_TF;
2272 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
2273 rflags &= ~X86_EFLAGS_RF;
2278 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2280 if (to_svm(vcpu)->nmi_singlestep)
2281 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2284 * Any change of EFLAGS.VM is accompanied by a reload of SS
2285 * (caused by either a task switch or an inter-privilege IRET),
2286 * so we do not need to update the CPL here.
2288 to_svm(vcpu)->vmcb->save.rflags = rflags;
2291 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2294 case VCPU_EXREG_PDPTR:
2295 BUG_ON(!npt_enabled);
2296 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
2303 static void svm_set_vintr(struct vcpu_svm *svm)
2305 set_intercept(svm, INTERCEPT_VINTR);
2308 static void svm_clear_vintr(struct vcpu_svm *svm)
2310 clr_intercept(svm, INTERCEPT_VINTR);
2313 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
2315 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2318 case VCPU_SREG_CS: return &save->cs;
2319 case VCPU_SREG_DS: return &save->ds;
2320 case VCPU_SREG_ES: return &save->es;
2321 case VCPU_SREG_FS: return &save->fs;
2322 case VCPU_SREG_GS: return &save->gs;
2323 case VCPU_SREG_SS: return &save->ss;
2324 case VCPU_SREG_TR: return &save->tr;
2325 case VCPU_SREG_LDTR: return &save->ldtr;
2331 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2333 struct vmcb_seg *s = svm_seg(vcpu, seg);
2338 static void svm_get_segment(struct kvm_vcpu *vcpu,
2339 struct kvm_segment *var, int seg)
2341 struct vmcb_seg *s = svm_seg(vcpu, seg);
2343 var->base = s->base;
2344 var->limit = s->limit;
2345 var->selector = s->selector;
2346 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
2347 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
2348 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
2349 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
2350 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
2351 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
2352 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
2355 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2356 * However, the SVM spec states that the G bit is not observed by the
2357 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2358 * So let's synthesize a legal G bit for all segments, this helps
2359 * running KVM nested. It also helps cross-vendor migration, because
2360 * Intel's vmentry has a check on the 'G' bit.
2362 var->g = s->limit > 0xfffff;
2365 * AMD's VMCB does not have an explicit unusable field, so emulate it
2366 * for cross vendor migration purposes by "not present"
2368 var->unusable = !var->present;
2373 * Work around a bug where the busy flag in the tr selector
2383 * The accessed bit must always be set in the segment
2384 * descriptor cache, although it can be cleared in the
2385 * descriptor, the cached bit always remains at 1. Since
2386 * Intel has a check on this, set it here to support
2387 * cross-vendor migration.
2394 * On AMD CPUs sometimes the DB bit in the segment
2395 * descriptor is left as 1, although the whole segment has
2396 * been made unusable. Clear it here to pass an Intel VMX
2397 * entry check when cross vendor migrating.
2401 /* This is symmetric with svm_set_segment() */
2402 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
2407 static int svm_get_cpl(struct kvm_vcpu *vcpu)
2409 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
2414 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2416 struct vcpu_svm *svm = to_svm(vcpu);
2418 dt->size = svm->vmcb->save.idtr.limit;
2419 dt->address = svm->vmcb->save.idtr.base;
2422 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2424 struct vcpu_svm *svm = to_svm(vcpu);
2426 svm->vmcb->save.idtr.limit = dt->size;
2427 svm->vmcb->save.idtr.base = dt->address ;
2428 mark_dirty(svm->vmcb, VMCB_DT);
2431 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2433 struct vcpu_svm *svm = to_svm(vcpu);
2435 dt->size = svm->vmcb->save.gdtr.limit;
2436 dt->address = svm->vmcb->save.gdtr.base;
2439 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2441 struct vcpu_svm *svm = to_svm(vcpu);
2443 svm->vmcb->save.gdtr.limit = dt->size;
2444 svm->vmcb->save.gdtr.base = dt->address ;
2445 mark_dirty(svm->vmcb, VMCB_DT);
2448 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2452 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
2456 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2460 static void update_cr0_intercept(struct vcpu_svm *svm)
2462 ulong gcr0 = svm->vcpu.arch.cr0;
2463 u64 *hcr0 = &svm->vmcb->save.cr0;
2465 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
2466 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
2468 mark_dirty(svm->vmcb, VMCB_CR);
2470 if (gcr0 == *hcr0) {
2471 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
2472 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2474 set_cr_intercept(svm, INTERCEPT_CR0_READ);
2475 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
2479 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2481 struct vcpu_svm *svm = to_svm(vcpu);
2483 #ifdef CONFIG_X86_64
2484 if (vcpu->arch.efer & EFER_LME) {
2485 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
2486 vcpu->arch.efer |= EFER_LMA;
2487 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2490 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2491 vcpu->arch.efer &= ~EFER_LMA;
2492 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2496 vcpu->arch.cr0 = cr0;
2499 cr0 |= X86_CR0_PG | X86_CR0_WP;
2502 * re-enable caching here because the QEMU bios
2503 * does not do it - this results in some delay at
2506 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2507 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2508 svm->vmcb->save.cr0 = cr0;
2509 mark_dirty(svm->vmcb, VMCB_CR);
2510 update_cr0_intercept(svm);
2513 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2515 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2516 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2518 if (cr4 & X86_CR4_VMXE)
2521 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2522 svm_flush_tlb(vcpu, true);
2524 vcpu->arch.cr4 = cr4;
2527 cr4 |= host_cr4_mce;
2528 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2529 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2533 static void svm_set_segment(struct kvm_vcpu *vcpu,
2534 struct kvm_segment *var, int seg)
2536 struct vcpu_svm *svm = to_svm(vcpu);
2537 struct vmcb_seg *s = svm_seg(vcpu, seg);
2539 s->base = var->base;
2540 s->limit = var->limit;
2541 s->selector = var->selector;
2542 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2543 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2544 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2545 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2546 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2547 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2548 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2549 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2552 * This is always accurate, except if SYSRET returned to a segment
2553 * with SS.DPL != 3. Intel does not have this quirk, and always
2554 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2555 * would entail passing the CPL to userspace and back.
2557 if (seg == VCPU_SREG_SS)
2558 /* This is symmetric with svm_get_segment() */
2559 svm->vmcb->save.cpl = (var->dpl & 3);
2561 mark_dirty(svm->vmcb, VMCB_SEG);
2564 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2566 struct vcpu_svm *svm = to_svm(vcpu);
2568 clr_exception_intercept(svm, BP_VECTOR);
2570 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2571 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2572 set_exception_intercept(svm, BP_VECTOR);
2574 vcpu->guest_debug = 0;
2577 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2579 if (sd->next_asid > sd->max_asid) {
2580 ++sd->asid_generation;
2581 sd->next_asid = sd->min_asid;
2582 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2585 svm->asid_generation = sd->asid_generation;
2586 svm->vmcb->control.asid = sd->next_asid++;
2588 mark_dirty(svm->vmcb, VMCB_ASID);
2591 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2593 return to_svm(vcpu)->vmcb->save.dr6;
2596 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2598 struct vcpu_svm *svm = to_svm(vcpu);
2600 svm->vmcb->save.dr6 = value;
2601 mark_dirty(svm->vmcb, VMCB_DR);
2604 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2606 struct vcpu_svm *svm = to_svm(vcpu);
2608 get_debugreg(vcpu->arch.db[0], 0);
2609 get_debugreg(vcpu->arch.db[1], 1);
2610 get_debugreg(vcpu->arch.db[2], 2);
2611 get_debugreg(vcpu->arch.db[3], 3);
2612 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2613 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2615 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2616 set_dr_intercepts(svm);
2619 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2621 struct vcpu_svm *svm = to_svm(vcpu);
2623 svm->vmcb->save.dr7 = value;
2624 mark_dirty(svm->vmcb, VMCB_DR);
2627 static int pf_interception(struct vcpu_svm *svm)
2629 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2630 u64 error_code = svm->vmcb->control.exit_info_1;
2632 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2633 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2634 svm->vmcb->control.insn_bytes : NULL,
2635 svm->vmcb->control.insn_len);
2638 static int npf_interception(struct vcpu_svm *svm)
2640 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
2641 u64 error_code = svm->vmcb->control.exit_info_1;
2643 trace_kvm_page_fault(fault_address, error_code);
2644 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
2645 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2646 svm->vmcb->control.insn_bytes : NULL,
2647 svm->vmcb->control.insn_len);
2650 static int db_interception(struct vcpu_svm *svm)
2652 struct kvm_run *kvm_run = svm->vcpu.run;
2654 if (!(svm->vcpu.guest_debug &
2655 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2656 !svm->nmi_singlestep) {
2657 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2661 if (svm->nmi_singlestep) {
2662 disable_nmi_singlestep(svm);
2665 if (svm->vcpu.guest_debug &
2666 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2667 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2668 kvm_run->debug.arch.pc =
2669 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2670 kvm_run->debug.arch.exception = DB_VECTOR;
2677 static int bp_interception(struct vcpu_svm *svm)
2679 struct kvm_run *kvm_run = svm->vcpu.run;
2681 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2682 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2683 kvm_run->debug.arch.exception = BP_VECTOR;
2687 static int ud_interception(struct vcpu_svm *svm)
2689 return handle_ud(&svm->vcpu);
2692 static int ac_interception(struct vcpu_svm *svm)
2694 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2698 static int gp_interception(struct vcpu_svm *svm)
2700 struct kvm_vcpu *vcpu = &svm->vcpu;
2701 u32 error_code = svm->vmcb->control.exit_info_1;
2704 WARN_ON_ONCE(!enable_vmware_backdoor);
2706 er = emulate_instruction(vcpu,
2707 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
2708 if (er == EMULATE_USER_EXIT)
2710 else if (er != EMULATE_DONE)
2711 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2715 static bool is_erratum_383(void)
2720 if (!erratum_383_found)
2723 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2727 /* Bit 62 may or may not be set for this mce */
2728 value &= ~(1ULL << 62);
2730 if (value != 0xb600000000010015ULL)
2733 /* Clear MCi_STATUS registers */
2734 for (i = 0; i < 6; ++i)
2735 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2737 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2741 value &= ~(1ULL << 2);
2742 low = lower_32_bits(value);
2743 high = upper_32_bits(value);
2745 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2748 /* Flush tlb to evict multi-match entries */
2754 static void svm_handle_mce(struct vcpu_svm *svm)
2756 if (is_erratum_383()) {
2758 * Erratum 383 triggered. Guest state is corrupt so kill the
2761 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2763 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2769 * On an #MC intercept the MCE handler is not called automatically in
2770 * the host. So do it by hand here.
2774 /* not sure if we ever come back to this point */
2779 static int mc_interception(struct vcpu_svm *svm)
2784 static int shutdown_interception(struct vcpu_svm *svm)
2786 struct kvm_run *kvm_run = svm->vcpu.run;
2789 * VMCB is undefined after a SHUTDOWN intercept
2790 * so reinitialize it.
2792 clear_page(svm->vmcb);
2795 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2799 static int io_interception(struct vcpu_svm *svm)
2801 struct kvm_vcpu *vcpu = &svm->vcpu;
2802 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2803 int size, in, string;
2806 ++svm->vcpu.stat.io_exits;
2807 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2808 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2810 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2812 port = io_info >> 16;
2813 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2814 svm->next_rip = svm->vmcb->control.exit_info_2;
2816 return kvm_fast_pio(&svm->vcpu, size, port, in);
2819 static int nmi_interception(struct vcpu_svm *svm)
2824 static int intr_interception(struct vcpu_svm *svm)
2826 ++svm->vcpu.stat.irq_exits;
2830 static int nop_on_interception(struct vcpu_svm *svm)
2835 static int halt_interception(struct vcpu_svm *svm)
2837 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2838 return kvm_emulate_halt(&svm->vcpu);
2841 static int vmmcall_interception(struct vcpu_svm *svm)
2843 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2844 return kvm_emulate_hypercall(&svm->vcpu);
2847 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2849 struct vcpu_svm *svm = to_svm(vcpu);
2851 return svm->nested.nested_cr3;
2854 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2856 struct vcpu_svm *svm = to_svm(vcpu);
2857 u64 cr3 = svm->nested.nested_cr3;
2861 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2862 offset_in_page(cr3) + index * 8, 8);
2868 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2871 struct vcpu_svm *svm = to_svm(vcpu);
2873 svm->vmcb->control.nested_cr3 = __sme_set(root);
2874 mark_dirty(svm->vmcb, VMCB_NPT);
2875 svm_flush_tlb(vcpu, true);
2878 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2879 struct x86_exception *fault)
2881 struct vcpu_svm *svm = to_svm(vcpu);
2883 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2885 * TODO: track the cause of the nested page fault, and
2886 * correctly fill in the high bits of exit_info_1.
2888 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2889 svm->vmcb->control.exit_code_hi = 0;
2890 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2891 svm->vmcb->control.exit_info_2 = fault->address;
2894 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2895 svm->vmcb->control.exit_info_1 |= fault->error_code;
2898 * The present bit is always zero for page structure faults on real
2901 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2902 svm->vmcb->control.exit_info_1 &= ~1;
2904 nested_svm_vmexit(svm);
2907 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2909 WARN_ON(mmu_is_nested(vcpu));
2910 kvm_init_shadow_mmu(vcpu);
2911 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2912 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2913 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2914 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2915 vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2916 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2917 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2920 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2922 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2925 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2927 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2928 !is_paging(&svm->vcpu)) {
2929 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2933 if (svm->vmcb->save.cpl) {
2934 kvm_inject_gp(&svm->vcpu, 0);
2941 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2942 bool has_error_code, u32 error_code)
2946 if (!is_guest_mode(&svm->vcpu))
2949 vmexit = nested_svm_intercept(svm);
2950 if (vmexit != NESTED_EXIT_DONE)
2953 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2954 svm->vmcb->control.exit_code_hi = 0;
2955 svm->vmcb->control.exit_info_1 = error_code;
2958 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2959 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2960 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2961 * written only when inject_pending_event runs (DR6 would written here
2962 * too). This should be conditional on a new capability---if the
2963 * capability is disabled, kvm_multiple_exception would write the
2964 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2966 if (svm->vcpu.arch.exception.nested_apf)
2967 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2969 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2971 svm->nested.exit_required = true;
2975 /* This function returns true if it is save to enable the irq window */
2976 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2978 if (!is_guest_mode(&svm->vcpu))
2981 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2984 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2988 * if vmexit was already requested (by intercepted exception
2989 * for instance) do not overwrite it with "external interrupt"
2992 if (svm->nested.exit_required)
2995 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2996 svm->vmcb->control.exit_info_1 = 0;
2997 svm->vmcb->control.exit_info_2 = 0;
2999 if (svm->nested.intercept & 1ULL) {
3001 * The #vmexit can't be emulated here directly because this
3002 * code path runs with irqs and preemption disabled. A
3003 * #vmexit emulation might sleep. Only signal request for
3006 svm->nested.exit_required = true;
3007 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
3014 /* This function returns true if it is save to enable the nmi window */
3015 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
3017 if (!is_guest_mode(&svm->vcpu))
3020 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
3023 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
3024 svm->nested.exit_required = true;
3029 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
3035 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
3036 if (is_error_page(page))
3044 kvm_inject_gp(&svm->vcpu, 0);
3049 static void nested_svm_unmap(struct page *page)
3052 kvm_release_page_dirty(page);
3055 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
3057 unsigned port, size, iopm_len;
3062 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
3063 return NESTED_EXIT_HOST;
3065 port = svm->vmcb->control.exit_info_1 >> 16;
3066 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
3067 SVM_IOIO_SIZE_SHIFT;
3068 gpa = svm->nested.vmcb_iopm + (port / 8);
3069 start_bit = port % 8;
3070 iopm_len = (start_bit + size > 8) ? 2 : 1;
3071 mask = (0xf >> (4 - size)) << start_bit;
3074 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
3075 return NESTED_EXIT_DONE;
3077 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3080 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
3082 u32 offset, msr, value;
3085 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3086 return NESTED_EXIT_HOST;
3088 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3089 offset = svm_msrpm_offset(msr);
3090 write = svm->vmcb->control.exit_info_1 & 1;
3091 mask = 1 << ((2 * (msr & 0xf)) + write);
3093 if (offset == MSR_INVALID)
3094 return NESTED_EXIT_DONE;
3096 /* Offset is in 32 bit units but need in 8 bit units */
3099 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
3100 return NESTED_EXIT_DONE;
3102 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
3105 /* DB exceptions for our internal use must not cause vmexit */
3106 static int nested_svm_intercept_db(struct vcpu_svm *svm)
3110 /* if we're not singlestepping, it's not ours */
3111 if (!svm->nmi_singlestep)
3112 return NESTED_EXIT_DONE;
3114 /* if it's not a singlestep exception, it's not ours */
3115 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
3116 return NESTED_EXIT_DONE;
3117 if (!(dr6 & DR6_BS))
3118 return NESTED_EXIT_DONE;
3120 /* if the guest is singlestepping, it should get the vmexit */
3121 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
3122 disable_nmi_singlestep(svm);
3123 return NESTED_EXIT_DONE;
3126 /* it's ours, the nested hypervisor must not see this one */
3127 return NESTED_EXIT_HOST;
3130 static int nested_svm_exit_special(struct vcpu_svm *svm)
3132 u32 exit_code = svm->vmcb->control.exit_code;
3134 switch (exit_code) {
3137 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
3138 return NESTED_EXIT_HOST;
3140 /* For now we are always handling NPFs when using them */
3142 return NESTED_EXIT_HOST;
3144 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
3145 /* When we're shadowing, trap PFs, but not async PF */
3146 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
3147 return NESTED_EXIT_HOST;
3153 return NESTED_EXIT_CONTINUE;
3157 * If this function returns true, this #vmexit was already handled
3159 static int nested_svm_intercept(struct vcpu_svm *svm)
3161 u32 exit_code = svm->vmcb->control.exit_code;
3162 int vmexit = NESTED_EXIT_HOST;
3164 switch (exit_code) {
3166 vmexit = nested_svm_exit_handled_msr(svm);
3169 vmexit = nested_svm_intercept_ioio(svm);
3171 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
3172 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
3173 if (svm->nested.intercept_cr & bit)
3174 vmexit = NESTED_EXIT_DONE;
3177 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
3178 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
3179 if (svm->nested.intercept_dr & bit)
3180 vmexit = NESTED_EXIT_DONE;
3183 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
3184 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
3185 if (svm->nested.intercept_exceptions & excp_bits) {
3186 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
3187 vmexit = nested_svm_intercept_db(svm);
3189 vmexit = NESTED_EXIT_DONE;
3191 /* async page fault always cause vmexit */
3192 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
3193 svm->vcpu.arch.exception.nested_apf != 0)
3194 vmexit = NESTED_EXIT_DONE;
3197 case SVM_EXIT_ERR: {
3198 vmexit = NESTED_EXIT_DONE;
3202 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
3203 if (svm->nested.intercept & exit_bits)
3204 vmexit = NESTED_EXIT_DONE;
3211 static int nested_svm_exit_handled(struct vcpu_svm *svm)
3215 vmexit = nested_svm_intercept(svm);
3217 if (vmexit == NESTED_EXIT_DONE)
3218 nested_svm_vmexit(svm);
3223 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
3225 struct vmcb_control_area *dst = &dst_vmcb->control;
3226 struct vmcb_control_area *from = &from_vmcb->control;
3228 dst->intercept_cr = from->intercept_cr;
3229 dst->intercept_dr = from->intercept_dr;
3230 dst->intercept_exceptions = from->intercept_exceptions;
3231 dst->intercept = from->intercept;
3232 dst->iopm_base_pa = from->iopm_base_pa;
3233 dst->msrpm_base_pa = from->msrpm_base_pa;
3234 dst->tsc_offset = from->tsc_offset;
3235 dst->asid = from->asid;
3236 dst->tlb_ctl = from->tlb_ctl;
3237 dst->int_ctl = from->int_ctl;
3238 dst->int_vector = from->int_vector;
3239 dst->int_state = from->int_state;
3240 dst->exit_code = from->exit_code;
3241 dst->exit_code_hi = from->exit_code_hi;
3242 dst->exit_info_1 = from->exit_info_1;
3243 dst->exit_info_2 = from->exit_info_2;
3244 dst->exit_int_info = from->exit_int_info;
3245 dst->exit_int_info_err = from->exit_int_info_err;
3246 dst->nested_ctl = from->nested_ctl;
3247 dst->event_inj = from->event_inj;
3248 dst->event_inj_err = from->event_inj_err;
3249 dst->nested_cr3 = from->nested_cr3;
3250 dst->virt_ext = from->virt_ext;
3253 static int nested_svm_vmexit(struct vcpu_svm *svm)
3255 struct vmcb *nested_vmcb;
3256 struct vmcb *hsave = svm->nested.hsave;
3257 struct vmcb *vmcb = svm->vmcb;
3260 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
3261 vmcb->control.exit_info_1,
3262 vmcb->control.exit_info_2,
3263 vmcb->control.exit_int_info,
3264 vmcb->control.exit_int_info_err,
3267 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
3271 /* Exit Guest-Mode */
3272 leave_guest_mode(&svm->vcpu);
3273 svm->nested.vmcb = 0;
3275 /* Give the current vmcb to the guest */
3278 nested_vmcb->save.es = vmcb->save.es;
3279 nested_vmcb->save.cs = vmcb->save.cs;
3280 nested_vmcb->save.ss = vmcb->save.ss;
3281 nested_vmcb->save.ds = vmcb->save.ds;
3282 nested_vmcb->save.gdtr = vmcb->save.gdtr;
3283 nested_vmcb->save.idtr = vmcb->save.idtr;
3284 nested_vmcb->save.efer = svm->vcpu.arch.efer;
3285 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
3286 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
3287 nested_vmcb->save.cr2 = vmcb->save.cr2;
3288 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
3289 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
3290 nested_vmcb->save.rip = vmcb->save.rip;
3291 nested_vmcb->save.rsp = vmcb->save.rsp;
3292 nested_vmcb->save.rax = vmcb->save.rax;
3293 nested_vmcb->save.dr7 = vmcb->save.dr7;
3294 nested_vmcb->save.dr6 = vmcb->save.dr6;
3295 nested_vmcb->save.cpl = vmcb->save.cpl;
3297 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
3298 nested_vmcb->control.int_vector = vmcb->control.int_vector;
3299 nested_vmcb->control.int_state = vmcb->control.int_state;
3300 nested_vmcb->control.exit_code = vmcb->control.exit_code;
3301 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
3302 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
3303 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
3304 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
3305 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
3307 if (svm->nrips_enabled)
3308 nested_vmcb->control.next_rip = vmcb->control.next_rip;
3311 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3312 * to make sure that we do not lose injected events. So check event_inj
3313 * here and copy it to exit_int_info if it is valid.
3314 * Exit_int_info and event_inj can't be both valid because the case
3315 * below only happens on a VMRUN instruction intercept which has
3316 * no valid exit_int_info set.
3318 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
3319 struct vmcb_control_area *nc = &nested_vmcb->control;
3321 nc->exit_int_info = vmcb->control.event_inj;
3322 nc->exit_int_info_err = vmcb->control.event_inj_err;
3325 nested_vmcb->control.tlb_ctl = 0;
3326 nested_vmcb->control.event_inj = 0;
3327 nested_vmcb->control.event_inj_err = 0;
3329 /* We always set V_INTR_MASKING and remember the old value in hflags */
3330 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
3331 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
3333 /* Restore the original control entries */
3334 copy_vmcb_control_area(vmcb, hsave);
3336 svm->vcpu.arch.tsc_offset = svm->vmcb->control.tsc_offset;
3337 kvm_clear_exception_queue(&svm->vcpu);
3338 kvm_clear_interrupt_queue(&svm->vcpu);
3340 svm->nested.nested_cr3 = 0;
3342 /* Restore selected save entries */
3343 svm->vmcb->save.es = hsave->save.es;
3344 svm->vmcb->save.cs = hsave->save.cs;
3345 svm->vmcb->save.ss = hsave->save.ss;
3346 svm->vmcb->save.ds = hsave->save.ds;
3347 svm->vmcb->save.gdtr = hsave->save.gdtr;
3348 svm->vmcb->save.idtr = hsave->save.idtr;
3349 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
3350 svm_set_efer(&svm->vcpu, hsave->save.efer);
3351 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
3352 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
3354 svm->vmcb->save.cr3 = hsave->save.cr3;
3355 svm->vcpu.arch.cr3 = hsave->save.cr3;
3357 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
3359 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
3360 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
3361 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
3362 svm->vmcb->save.dr7 = 0;
3363 svm->vmcb->save.cpl = 0;
3364 svm->vmcb->control.exit_int_info = 0;
3366 mark_all_dirty(svm->vmcb);
3368 nested_svm_unmap(page);
3370 nested_svm_uninit_mmu_context(&svm->vcpu);
3371 kvm_mmu_reset_context(&svm->vcpu);
3372 kvm_mmu_load(&svm->vcpu);
3377 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3380 * This function merges the msr permission bitmaps of kvm and the
3381 * nested vmcb. It is optimized in that it only merges the parts where
3382 * the kvm msr permission bitmap may contain zero bits
3386 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
3389 for (i = 0; i < MSRPM_OFFSETS; i++) {
3393 if (msrpm_offsets[i] == 0xffffffff)
3396 p = msrpm_offsets[i];
3397 offset = svm->nested.vmcb_msrpm + (p * 4);
3399 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
3402 svm->nested.msrpm[p] = svm->msrpm[p] | value;
3405 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
3410 static bool nested_vmcb_checks(struct vmcb *vmcb)
3412 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
3415 if (vmcb->control.asid == 0)
3418 if ((vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) &&
3425 static void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa,
3426 struct vmcb *nested_vmcb, struct page *page)
3428 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
3429 svm->vcpu.arch.hflags |= HF_HIF_MASK;
3431 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
3433 if (nested_vmcb->control.nested_ctl & SVM_NESTED_CTL_NP_ENABLE) {
3434 kvm_mmu_unload(&svm->vcpu);
3435 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
3436 nested_svm_init_mmu_context(&svm->vcpu);
3439 /* Load the nested guest state */
3440 svm->vmcb->save.es = nested_vmcb->save.es;
3441 svm->vmcb->save.cs = nested_vmcb->save.cs;
3442 svm->vmcb->save.ss = nested_vmcb->save.ss;
3443 svm->vmcb->save.ds = nested_vmcb->save.ds;
3444 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3445 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3446 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3447 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3448 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3449 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3451 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3452 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3454 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3456 /* Guest paging mode is active - reset mmu */
3457 kvm_mmu_reset_context(&svm->vcpu);
3459 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3460 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3461 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3462 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3464 /* In case we don't even reach vcpu_run, the fields are not updated */
3465 svm->vmcb->save.rax = nested_vmcb->save.rax;
3466 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3467 svm->vmcb->save.rip = nested_vmcb->save.rip;
3468 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3469 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3470 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3472 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3473 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3475 /* cache intercepts */
3476 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3477 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3478 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3479 svm->nested.intercept = nested_vmcb->control.intercept;
3481 svm_flush_tlb(&svm->vcpu, true);
3482 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3483 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3484 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3486 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3488 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3489 /* We only want the cr8 intercept bits of the guest */
3490 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3491 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3494 /* We don't want to see VMMCALLs from a nested guest */
3495 clr_intercept(svm, INTERCEPT_VMMCALL);
3497 svm->vcpu.arch.tsc_offset += nested_vmcb->control.tsc_offset;
3498 svm->vmcb->control.tsc_offset = svm->vcpu.arch.tsc_offset;
3500 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3501 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3502 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3503 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3504 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3506 nested_svm_unmap(page);
3508 /* Enter Guest-Mode */
3509 enter_guest_mode(&svm->vcpu);
3512 * Merge guest and host intercepts - must be called with vcpu in
3513 * guest-mode to take affect here
3515 recalc_intercepts(svm);
3517 svm->nested.vmcb = vmcb_gpa;
3521 mark_all_dirty(svm->vmcb);
3524 static bool nested_svm_vmrun(struct vcpu_svm *svm)
3526 struct vmcb *nested_vmcb;
3527 struct vmcb *hsave = svm->nested.hsave;
3528 struct vmcb *vmcb = svm->vmcb;
3532 vmcb_gpa = svm->vmcb->save.rax;
3534 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3538 if (!nested_vmcb_checks(nested_vmcb)) {
3539 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
3540 nested_vmcb->control.exit_code_hi = 0;
3541 nested_vmcb->control.exit_info_1 = 0;
3542 nested_vmcb->control.exit_info_2 = 0;
3544 nested_svm_unmap(page);
3549 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
3550 nested_vmcb->save.rip,
3551 nested_vmcb->control.int_ctl,
3552 nested_vmcb->control.event_inj,
3553 nested_vmcb->control.nested_ctl);
3555 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
3556 nested_vmcb->control.intercept_cr >> 16,
3557 nested_vmcb->control.intercept_exceptions,
3558 nested_vmcb->control.intercept);
3560 /* Clear internal status */
3561 kvm_clear_exception_queue(&svm->vcpu);
3562 kvm_clear_interrupt_queue(&svm->vcpu);
3565 * Save the old vmcb, so we don't need to pick what we save, but can
3566 * restore everything when a VMEXIT occurs
3568 hsave->save.es = vmcb->save.es;
3569 hsave->save.cs = vmcb->save.cs;
3570 hsave->save.ss = vmcb->save.ss;
3571 hsave->save.ds = vmcb->save.ds;
3572 hsave->save.gdtr = vmcb->save.gdtr;
3573 hsave->save.idtr = vmcb->save.idtr;
3574 hsave->save.efer = svm->vcpu.arch.efer;
3575 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
3576 hsave->save.cr4 = svm->vcpu.arch.cr4;
3577 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
3578 hsave->save.rip = kvm_rip_read(&svm->vcpu);
3579 hsave->save.rsp = vmcb->save.rsp;
3580 hsave->save.rax = vmcb->save.rax;
3582 hsave->save.cr3 = vmcb->save.cr3;
3584 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
3586 copy_vmcb_control_area(hsave, vmcb);
3588 enter_svm_guest_mode(svm, vmcb_gpa, nested_vmcb, page);
3593 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3595 to_vmcb->save.fs = from_vmcb->save.fs;
3596 to_vmcb->save.gs = from_vmcb->save.gs;
3597 to_vmcb->save.tr = from_vmcb->save.tr;
3598 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3599 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3600 to_vmcb->save.star = from_vmcb->save.star;
3601 to_vmcb->save.lstar = from_vmcb->save.lstar;
3602 to_vmcb->save.cstar = from_vmcb->save.cstar;
3603 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3604 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3605 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3606 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3609 static int vmload_interception(struct vcpu_svm *svm)
3611 struct vmcb *nested_vmcb;
3615 if (nested_svm_check_permissions(svm))
3618 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3622 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3623 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3625 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3626 nested_svm_unmap(page);
3631 static int vmsave_interception(struct vcpu_svm *svm)
3633 struct vmcb *nested_vmcb;
3637 if (nested_svm_check_permissions(svm))
3640 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3644 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3645 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3647 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3648 nested_svm_unmap(page);
3653 static int vmrun_interception(struct vcpu_svm *svm)
3655 if (nested_svm_check_permissions(svm))
3658 /* Save rip after vmrun instruction */
3659 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3661 if (!nested_svm_vmrun(svm))
3664 if (!nested_svm_vmrun_msrpm(svm))
3671 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3672 svm->vmcb->control.exit_code_hi = 0;
3673 svm->vmcb->control.exit_info_1 = 0;
3674 svm->vmcb->control.exit_info_2 = 0;
3676 nested_svm_vmexit(svm);
3681 static int stgi_interception(struct vcpu_svm *svm)
3685 if (nested_svm_check_permissions(svm))
3689 * If VGIF is enabled, the STGI intercept is only added to
3690 * detect the opening of the SMI/NMI window; remove it now.
3692 if (vgif_enabled(svm))
3693 clr_intercept(svm, INTERCEPT_STGI);
3695 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3696 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3697 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3704 static int clgi_interception(struct vcpu_svm *svm)
3708 if (nested_svm_check_permissions(svm))
3711 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3712 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3716 /* After a CLGI no interrupts should come */
3717 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3718 svm_clear_vintr(svm);
3719 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3720 mark_dirty(svm->vmcb, VMCB_INTR);
3726 static int invlpga_interception(struct vcpu_svm *svm)
3728 struct kvm_vcpu *vcpu = &svm->vcpu;
3730 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3731 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3733 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3734 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3736 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3737 return kvm_skip_emulated_instruction(&svm->vcpu);
3740 static int skinit_interception(struct vcpu_svm *svm)
3742 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3744 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3748 static int wbinvd_interception(struct vcpu_svm *svm)
3750 return kvm_emulate_wbinvd(&svm->vcpu);
3753 static int xsetbv_interception(struct vcpu_svm *svm)
3755 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3756 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3758 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3759 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3760 return kvm_skip_emulated_instruction(&svm->vcpu);
3766 static int task_switch_interception(struct vcpu_svm *svm)
3770 int int_type = svm->vmcb->control.exit_int_info &
3771 SVM_EXITINTINFO_TYPE_MASK;
3772 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3774 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3776 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3777 bool has_error_code = false;
3780 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3782 if (svm->vmcb->control.exit_info_2 &
3783 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3784 reason = TASK_SWITCH_IRET;
3785 else if (svm->vmcb->control.exit_info_2 &
3786 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3787 reason = TASK_SWITCH_JMP;
3789 reason = TASK_SWITCH_GATE;
3791 reason = TASK_SWITCH_CALL;
3793 if (reason == TASK_SWITCH_GATE) {
3795 case SVM_EXITINTINFO_TYPE_NMI:
3796 svm->vcpu.arch.nmi_injected = false;
3798 case SVM_EXITINTINFO_TYPE_EXEPT:
3799 if (svm->vmcb->control.exit_info_2 &
3800 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3801 has_error_code = true;
3803 (u32)svm->vmcb->control.exit_info_2;
3805 kvm_clear_exception_queue(&svm->vcpu);
3807 case SVM_EXITINTINFO_TYPE_INTR:
3808 kvm_clear_interrupt_queue(&svm->vcpu);
3815 if (reason != TASK_SWITCH_GATE ||
3816 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3817 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3818 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3819 skip_emulated_instruction(&svm->vcpu);
3821 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3824 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3825 has_error_code, error_code) == EMULATE_FAIL) {
3826 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3827 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3828 svm->vcpu.run->internal.ndata = 0;
3834 static int cpuid_interception(struct vcpu_svm *svm)
3836 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3837 return kvm_emulate_cpuid(&svm->vcpu);
3840 static int iret_interception(struct vcpu_svm *svm)
3842 ++svm->vcpu.stat.nmi_window_exits;
3843 clr_intercept(svm, INTERCEPT_IRET);
3844 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3845 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3846 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3850 static int invlpg_interception(struct vcpu_svm *svm)
3852 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3853 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3855 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3856 return kvm_skip_emulated_instruction(&svm->vcpu);
3859 static int emulate_on_interception(struct vcpu_svm *svm)
3861 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3864 static int rsm_interception(struct vcpu_svm *svm)
3866 return x86_emulate_instruction(&svm->vcpu, 0, 0,
3867 rsm_ins_bytes, 2) == EMULATE_DONE;
3870 static int rdpmc_interception(struct vcpu_svm *svm)
3874 if (!static_cpu_has(X86_FEATURE_NRIPS))
3875 return emulate_on_interception(svm);
3877 err = kvm_rdpmc(&svm->vcpu);
3878 return kvm_complete_insn_gp(&svm->vcpu, err);
3881 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3884 unsigned long cr0 = svm->vcpu.arch.cr0;
3888 intercept = svm->nested.intercept;
3890 if (!is_guest_mode(&svm->vcpu) ||
3891 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3894 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3895 val &= ~SVM_CR0_SELECTIVE_MASK;
3898 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3899 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3905 #define CR_VALID (1ULL << 63)
3907 static int cr_interception(struct vcpu_svm *svm)
3913 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3914 return emulate_on_interception(svm);
3916 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3917 return emulate_on_interception(svm);
3919 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3920 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3921 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3923 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3926 if (cr >= 16) { /* mov to cr */
3928 val = kvm_register_read(&svm->vcpu, reg);
3931 if (!check_selective_cr0_intercepted(svm, val))
3932 err = kvm_set_cr0(&svm->vcpu, val);
3938 err = kvm_set_cr3(&svm->vcpu, val);
3941 err = kvm_set_cr4(&svm->vcpu, val);
3944 err = kvm_set_cr8(&svm->vcpu, val);
3947 WARN(1, "unhandled write to CR%d", cr);
3948 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3951 } else { /* mov from cr */
3954 val = kvm_read_cr0(&svm->vcpu);
3957 val = svm->vcpu.arch.cr2;
3960 val = kvm_read_cr3(&svm->vcpu);
3963 val = kvm_read_cr4(&svm->vcpu);
3966 val = kvm_get_cr8(&svm->vcpu);
3969 WARN(1, "unhandled read from CR%d", cr);
3970 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3973 kvm_register_write(&svm->vcpu, reg, val);
3975 return kvm_complete_insn_gp(&svm->vcpu, err);
3978 static int dr_interception(struct vcpu_svm *svm)
3983 if (svm->vcpu.guest_debug == 0) {
3985 * No more DR vmexits; force a reload of the debug registers
3986 * and reenter on this instruction. The next vmexit will
3987 * retrieve the full state of the debug registers.
3989 clr_dr_intercepts(svm);
3990 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3994 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3995 return emulate_on_interception(svm);
3997 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3998 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
4000 if (dr >= 16) { /* mov to DRn */
4001 if (!kvm_require_dr(&svm->vcpu, dr - 16))
4003 val = kvm_register_read(&svm->vcpu, reg);
4004 kvm_set_dr(&svm->vcpu, dr - 16, val);
4006 if (!kvm_require_dr(&svm->vcpu, dr))
4008 kvm_get_dr(&svm->vcpu, dr, &val);
4009 kvm_register_write(&svm->vcpu, reg, val);
4012 return kvm_skip_emulated_instruction(&svm->vcpu);
4015 static int cr8_write_interception(struct vcpu_svm *svm)
4017 struct kvm_run *kvm_run = svm->vcpu.run;
4020 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
4021 /* instruction emulation calls kvm_set_cr8() */
4022 r = cr_interception(svm);
4023 if (lapic_in_kernel(&svm->vcpu))
4025 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
4027 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
4031 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
4035 switch (msr->index) {
4036 case MSR_F10H_DECFG:
4037 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
4038 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
4047 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4049 struct vcpu_svm *svm = to_svm(vcpu);
4051 switch (msr_info->index) {
4053 msr_info->data = svm->vmcb->save.star;
4055 #ifdef CONFIG_X86_64
4057 msr_info->data = svm->vmcb->save.lstar;
4060 msr_info->data = svm->vmcb->save.cstar;
4062 case MSR_KERNEL_GS_BASE:
4063 msr_info->data = svm->vmcb->save.kernel_gs_base;
4065 case MSR_SYSCALL_MASK:
4066 msr_info->data = svm->vmcb->save.sfmask;
4069 case MSR_IA32_SYSENTER_CS:
4070 msr_info->data = svm->vmcb->save.sysenter_cs;
4072 case MSR_IA32_SYSENTER_EIP:
4073 msr_info->data = svm->sysenter_eip;
4075 case MSR_IA32_SYSENTER_ESP:
4076 msr_info->data = svm->sysenter_esp;
4079 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4081 msr_info->data = svm->tsc_aux;
4084 * Nobody will change the following 5 values in the VMCB so we can
4085 * safely return them on rdmsr. They will always be 0 until LBRV is
4088 case MSR_IA32_DEBUGCTLMSR:
4089 msr_info->data = svm->vmcb->save.dbgctl;
4091 case MSR_IA32_LASTBRANCHFROMIP:
4092 msr_info->data = svm->vmcb->save.br_from;
4094 case MSR_IA32_LASTBRANCHTOIP:
4095 msr_info->data = svm->vmcb->save.br_to;
4097 case MSR_IA32_LASTINTFROMIP:
4098 msr_info->data = svm->vmcb->save.last_excp_from;
4100 case MSR_IA32_LASTINTTOIP:
4101 msr_info->data = svm->vmcb->save.last_excp_to;
4103 case MSR_VM_HSAVE_PA:
4104 msr_info->data = svm->nested.hsave_msr;
4107 msr_info->data = svm->nested.vm_cr_msr;
4109 case MSR_IA32_SPEC_CTRL:
4110 if (!msr_info->host_initiated &&
4111 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
4114 msr_info->data = svm->spec_ctrl;
4116 case MSR_F15H_IC_CFG: {
4120 family = guest_cpuid_family(vcpu);
4121 model = guest_cpuid_model(vcpu);
4123 if (family < 0 || model < 0)
4124 return kvm_get_msr_common(vcpu, msr_info);
4128 if (family == 0x15 &&
4129 (model >= 0x2 && model < 0x20))
4130 msr_info->data = 0x1E;
4133 case MSR_F10H_DECFG:
4134 msr_info->data = svm->msr_decfg;
4137 return kvm_get_msr_common(vcpu, msr_info);
4142 static int rdmsr_interception(struct vcpu_svm *svm)
4144 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4145 struct msr_data msr_info;
4147 msr_info.index = ecx;
4148 msr_info.host_initiated = false;
4149 if (svm_get_msr(&svm->vcpu, &msr_info)) {
4150 trace_kvm_msr_read_ex(ecx);
4151 kvm_inject_gp(&svm->vcpu, 0);
4154 trace_kvm_msr_read(ecx, msr_info.data);
4156 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
4157 msr_info.data & 0xffffffff);
4158 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
4159 msr_info.data >> 32);
4160 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4161 return kvm_skip_emulated_instruction(&svm->vcpu);
4165 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
4167 struct vcpu_svm *svm = to_svm(vcpu);
4168 int svm_dis, chg_mask;
4170 if (data & ~SVM_VM_CR_VALID_MASK)
4173 chg_mask = SVM_VM_CR_VALID_MASK;
4175 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
4176 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
4178 svm->nested.vm_cr_msr &= ~chg_mask;
4179 svm->nested.vm_cr_msr |= (data & chg_mask);
4181 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
4183 /* check for svm_disable while efer.svme is set */
4184 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
4190 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
4192 struct vcpu_svm *svm = to_svm(vcpu);
4194 u32 ecx = msr->index;
4195 u64 data = msr->data;
4197 case MSR_IA32_CR_PAT:
4198 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
4200 vcpu->arch.pat = data;
4201 svm->vmcb->save.g_pat = data;
4202 mark_dirty(svm->vmcb, VMCB_NPT);
4204 case MSR_IA32_SPEC_CTRL:
4205 if (!msr->host_initiated &&
4206 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
4209 /* The STIBP bit doesn't fault even if it's not advertised */
4210 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP))
4213 svm->spec_ctrl = data;
4220 * When it's written (to non-zero) for the first time, pass
4224 * The handling of the MSR bitmap for L2 guests is done in
4225 * nested_svm_vmrun_msrpm.
4226 * We update the L1 MSR bit as well since it will end up
4227 * touching the MSR anyway now.
4229 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
4231 case MSR_IA32_PRED_CMD:
4232 if (!msr->host_initiated &&
4233 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
4236 if (data & ~PRED_CMD_IBPB)
4242 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
4243 if (is_guest_mode(vcpu))
4245 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
4248 svm->vmcb->save.star = data;
4250 #ifdef CONFIG_X86_64
4252 svm->vmcb->save.lstar = data;
4255 svm->vmcb->save.cstar = data;
4257 case MSR_KERNEL_GS_BASE:
4258 svm->vmcb->save.kernel_gs_base = data;
4260 case MSR_SYSCALL_MASK:
4261 svm->vmcb->save.sfmask = data;
4264 case MSR_IA32_SYSENTER_CS:
4265 svm->vmcb->save.sysenter_cs = data;
4267 case MSR_IA32_SYSENTER_EIP:
4268 svm->sysenter_eip = data;
4269 svm->vmcb->save.sysenter_eip = data;
4271 case MSR_IA32_SYSENTER_ESP:
4272 svm->sysenter_esp = data;
4273 svm->vmcb->save.sysenter_esp = data;
4276 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
4280 * This is rare, so we update the MSR here instead of using
4281 * direct_access_msrs. Doing that would require a rdmsr in
4284 svm->tsc_aux = data;
4285 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
4287 case MSR_IA32_DEBUGCTLMSR:
4288 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
4289 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4293 if (data & DEBUGCTL_RESERVED_BITS)
4296 svm->vmcb->save.dbgctl = data;
4297 mark_dirty(svm->vmcb, VMCB_LBR);
4298 if (data & (1ULL<<0))
4299 svm_enable_lbrv(svm);
4301 svm_disable_lbrv(svm);
4303 case MSR_VM_HSAVE_PA:
4304 svm->nested.hsave_msr = data;
4307 return svm_set_vm_cr(vcpu, data);
4309 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
4311 case MSR_F10H_DECFG: {
4312 struct kvm_msr_entry msr_entry;
4314 msr_entry.index = msr->index;
4315 if (svm_get_msr_feature(&msr_entry))
4318 /* Check the supported bits */
4319 if (data & ~msr_entry.data)
4322 /* Don't allow the guest to change a bit, #GP */
4323 if (!msr->host_initiated && (data ^ msr_entry.data))
4326 svm->msr_decfg = data;
4329 case MSR_IA32_APICBASE:
4330 if (kvm_vcpu_apicv_active(vcpu))
4331 avic_update_vapic_bar(to_svm(vcpu), data);
4332 /* Follow through */
4334 return kvm_set_msr_common(vcpu, msr);
4339 static int wrmsr_interception(struct vcpu_svm *svm)
4341 struct msr_data msr;
4342 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
4343 u64 data = kvm_read_edx_eax(&svm->vcpu);
4347 msr.host_initiated = false;
4349 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
4350 if (kvm_set_msr(&svm->vcpu, &msr)) {
4351 trace_kvm_msr_write_ex(ecx, data);
4352 kvm_inject_gp(&svm->vcpu, 0);
4355 trace_kvm_msr_write(ecx, data);
4356 return kvm_skip_emulated_instruction(&svm->vcpu);
4360 static int msr_interception(struct vcpu_svm *svm)
4362 if (svm->vmcb->control.exit_info_1)
4363 return wrmsr_interception(svm);
4365 return rdmsr_interception(svm);
4368 static int interrupt_window_interception(struct vcpu_svm *svm)
4370 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4371 svm_clear_vintr(svm);
4372 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
4373 mark_dirty(svm->vmcb, VMCB_INTR);
4374 ++svm->vcpu.stat.irq_window_exits;
4378 static int pause_interception(struct vcpu_svm *svm)
4380 struct kvm_vcpu *vcpu = &svm->vcpu;
4381 bool in_kernel = (svm_get_cpl(vcpu) == 0);
4383 if (pause_filter_thresh)
4384 grow_ple_window(vcpu);
4386 kvm_vcpu_on_spin(vcpu, in_kernel);
4390 static int nop_interception(struct vcpu_svm *svm)
4392 return kvm_skip_emulated_instruction(&(svm->vcpu));
4395 static int monitor_interception(struct vcpu_svm *svm)
4397 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
4398 return nop_interception(svm);
4401 static int mwait_interception(struct vcpu_svm *svm)
4403 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4404 return nop_interception(svm);
4407 enum avic_ipi_failure_cause {
4408 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
4409 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
4410 AVIC_IPI_FAILURE_INVALID_TARGET,
4411 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
4414 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
4416 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
4417 u32 icrl = svm->vmcb->control.exit_info_1;
4418 u32 id = svm->vmcb->control.exit_info_2 >> 32;
4419 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
4420 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4422 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
4425 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
4427 * AVIC hardware handles the generation of
4428 * IPIs when the specified Message Type is Fixed
4429 * (also known as fixed delivery mode) and
4430 * the Trigger Mode is edge-triggered. The hardware
4431 * also supports self and broadcast delivery modes
4432 * specified via the Destination Shorthand(DSH)
4433 * field of the ICRL. Logical and physical APIC ID
4434 * formats are supported. All other IPI types cause
4435 * a #VMEXIT, which needs to emulated.
4437 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
4438 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
4440 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
4442 struct kvm_vcpu *vcpu;
4443 struct kvm *kvm = svm->vcpu.kvm;
4444 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4447 * At this point, we expect that the AVIC HW has already
4448 * set the appropriate IRR bits on the valid target
4449 * vcpus. So, we just need to kick the appropriate vcpu.
4451 kvm_for_each_vcpu(i, vcpu, kvm) {
4452 bool m = kvm_apic_match_dest(vcpu, apic,
4453 icrl & KVM_APIC_SHORT_MASK,
4454 GET_APIC_DEST_FIELD(icrh),
4455 icrl & KVM_APIC_DEST_MASK);
4457 if (m && !avic_vcpu_is_running(vcpu))
4458 kvm_vcpu_wake_up(vcpu);
4462 case AVIC_IPI_FAILURE_INVALID_TARGET:
4464 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
4465 WARN_ONCE(1, "Invalid backing page\n");
4468 pr_err("Unknown IPI interception\n");
4474 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
4476 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4478 u32 *logical_apic_id_table;
4479 int dlid = GET_APIC_LOGICAL_ID(ldr);
4484 if (flat) { /* flat */
4485 index = ffs(dlid) - 1;
4488 } else { /* cluster */
4489 int cluster = (dlid & 0xf0) >> 4;
4490 int apic = ffs(dlid & 0x0f) - 1;
4492 if ((apic < 0) || (apic > 7) ||
4495 index = (cluster << 2) + apic;
4498 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
4500 return &logical_apic_id_table[index];
4503 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
4507 u32 *entry, new_entry;
4509 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
4510 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
4514 new_entry = READ_ONCE(*entry);
4515 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
4516 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
4518 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4520 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
4521 WRITE_ONCE(*entry, new_entry);
4526 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
4529 struct vcpu_svm *svm = to_svm(vcpu);
4530 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
4535 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
4536 if (ret && svm->ldr_reg) {
4537 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
4545 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
4548 struct vcpu_svm *svm = to_svm(vcpu);
4549 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
4550 u32 id = (apic_id_reg >> 24) & 0xff;
4552 if (vcpu->vcpu_id == id)
4555 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
4556 new = avic_get_physical_id_entry(vcpu, id);
4560 /* We need to move physical_id_entry to new offset */
4563 to_svm(vcpu)->avic_physical_id_cache = new;
4566 * Also update the guest physical APIC ID in the logical
4567 * APIC ID table entry if already setup the LDR.
4570 avic_handle_ldr_update(vcpu);
4575 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
4577 struct vcpu_svm *svm = to_svm(vcpu);
4578 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
4579 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
4580 u32 mod = (dfr >> 28) & 0xf;
4583 * We assume that all local APICs are using the same type.
4584 * If this changes, we need to flush the AVIC logical
4587 if (kvm_svm->ldr_mode == mod)
4590 clear_page(page_address(kvm_svm->avic_logical_id_table_page));
4591 kvm_svm->ldr_mode = mod;
4594 avic_handle_ldr_update(vcpu);
4598 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
4600 struct kvm_lapic *apic = svm->vcpu.arch.apic;
4601 u32 offset = svm->vmcb->control.exit_info_1 &
4602 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4606 if (avic_handle_apic_id_update(&svm->vcpu))
4610 if (avic_handle_ldr_update(&svm->vcpu))
4614 avic_handle_dfr_update(&svm->vcpu);
4620 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4625 static bool is_avic_unaccelerated_access_trap(u32 offset)
4654 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4657 u32 offset = svm->vmcb->control.exit_info_1 &
4658 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4659 u32 vector = svm->vmcb->control.exit_info_2 &
4660 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4661 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4662 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4663 bool trap = is_avic_unaccelerated_access_trap(offset);
4665 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4666 trap, write, vector);
4669 WARN_ONCE(!write, "svm: Handling trap read.\n");
4670 ret = avic_unaccel_trap_write(svm);
4672 /* Handling Fault */
4673 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4679 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4680 [SVM_EXIT_READ_CR0] = cr_interception,
4681 [SVM_EXIT_READ_CR3] = cr_interception,
4682 [SVM_EXIT_READ_CR4] = cr_interception,
4683 [SVM_EXIT_READ_CR8] = cr_interception,
4684 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4685 [SVM_EXIT_WRITE_CR0] = cr_interception,
4686 [SVM_EXIT_WRITE_CR3] = cr_interception,
4687 [SVM_EXIT_WRITE_CR4] = cr_interception,
4688 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4689 [SVM_EXIT_READ_DR0] = dr_interception,
4690 [SVM_EXIT_READ_DR1] = dr_interception,
4691 [SVM_EXIT_READ_DR2] = dr_interception,
4692 [SVM_EXIT_READ_DR3] = dr_interception,
4693 [SVM_EXIT_READ_DR4] = dr_interception,
4694 [SVM_EXIT_READ_DR5] = dr_interception,
4695 [SVM_EXIT_READ_DR6] = dr_interception,
4696 [SVM_EXIT_READ_DR7] = dr_interception,
4697 [SVM_EXIT_WRITE_DR0] = dr_interception,
4698 [SVM_EXIT_WRITE_DR1] = dr_interception,
4699 [SVM_EXIT_WRITE_DR2] = dr_interception,
4700 [SVM_EXIT_WRITE_DR3] = dr_interception,
4701 [SVM_EXIT_WRITE_DR4] = dr_interception,
4702 [SVM_EXIT_WRITE_DR5] = dr_interception,
4703 [SVM_EXIT_WRITE_DR6] = dr_interception,
4704 [SVM_EXIT_WRITE_DR7] = dr_interception,
4705 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4706 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4707 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4708 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4709 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4710 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4711 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
4712 [SVM_EXIT_INTR] = intr_interception,
4713 [SVM_EXIT_NMI] = nmi_interception,
4714 [SVM_EXIT_SMI] = nop_on_interception,
4715 [SVM_EXIT_INIT] = nop_on_interception,
4716 [SVM_EXIT_VINTR] = interrupt_window_interception,
4717 [SVM_EXIT_RDPMC] = rdpmc_interception,
4718 [SVM_EXIT_CPUID] = cpuid_interception,
4719 [SVM_EXIT_IRET] = iret_interception,
4720 [SVM_EXIT_INVD] = emulate_on_interception,
4721 [SVM_EXIT_PAUSE] = pause_interception,
4722 [SVM_EXIT_HLT] = halt_interception,
4723 [SVM_EXIT_INVLPG] = invlpg_interception,
4724 [SVM_EXIT_INVLPGA] = invlpga_interception,
4725 [SVM_EXIT_IOIO] = io_interception,
4726 [SVM_EXIT_MSR] = msr_interception,
4727 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4728 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4729 [SVM_EXIT_VMRUN] = vmrun_interception,
4730 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4731 [SVM_EXIT_VMLOAD] = vmload_interception,
4732 [SVM_EXIT_VMSAVE] = vmsave_interception,
4733 [SVM_EXIT_STGI] = stgi_interception,
4734 [SVM_EXIT_CLGI] = clgi_interception,
4735 [SVM_EXIT_SKINIT] = skinit_interception,
4736 [SVM_EXIT_WBINVD] = wbinvd_interception,
4737 [SVM_EXIT_MONITOR] = monitor_interception,
4738 [SVM_EXIT_MWAIT] = mwait_interception,
4739 [SVM_EXIT_XSETBV] = xsetbv_interception,
4740 [SVM_EXIT_NPF] = npf_interception,
4741 [SVM_EXIT_RSM] = rsm_interception,
4742 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4743 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4746 static void dump_vmcb(struct kvm_vcpu *vcpu)
4748 struct vcpu_svm *svm = to_svm(vcpu);
4749 struct vmcb_control_area *control = &svm->vmcb->control;
4750 struct vmcb_save_area *save = &svm->vmcb->save;
4752 pr_err("VMCB Control Area:\n");
4753 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4754 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4755 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4756 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4757 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4758 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4759 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4760 pr_err("%-20s%d\n", "pause filter threshold:",
4761 control->pause_filter_thresh);
4762 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4763 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4764 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4765 pr_err("%-20s%d\n", "asid:", control->asid);
4766 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4767 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4768 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4769 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4770 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4771 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4772 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4773 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4774 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4775 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4776 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4777 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4778 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4779 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4780 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4781 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4782 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4783 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4784 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4785 pr_err("VMCB State Save Area:\n");
4786 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4788 save->es.selector, save->es.attrib,
4789 save->es.limit, save->es.base);
4790 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4792 save->cs.selector, save->cs.attrib,
4793 save->cs.limit, save->cs.base);
4794 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4796 save->ss.selector, save->ss.attrib,
4797 save->ss.limit, save->ss.base);
4798 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4800 save->ds.selector, save->ds.attrib,
4801 save->ds.limit, save->ds.base);
4802 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4804 save->fs.selector, save->fs.attrib,
4805 save->fs.limit, save->fs.base);
4806 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4808 save->gs.selector, save->gs.attrib,
4809 save->gs.limit, save->gs.base);
4810 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4812 save->gdtr.selector, save->gdtr.attrib,
4813 save->gdtr.limit, save->gdtr.base);
4814 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4816 save->ldtr.selector, save->ldtr.attrib,
4817 save->ldtr.limit, save->ldtr.base);
4818 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4820 save->idtr.selector, save->idtr.attrib,
4821 save->idtr.limit, save->idtr.base);
4822 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4824 save->tr.selector, save->tr.attrib,
4825 save->tr.limit, save->tr.base);
4826 pr_err("cpl: %d efer: %016llx\n",
4827 save->cpl, save->efer);
4828 pr_err("%-15s %016llx %-13s %016llx\n",
4829 "cr0:", save->cr0, "cr2:", save->cr2);
4830 pr_err("%-15s %016llx %-13s %016llx\n",
4831 "cr3:", save->cr3, "cr4:", save->cr4);
4832 pr_err("%-15s %016llx %-13s %016llx\n",
4833 "dr6:", save->dr6, "dr7:", save->dr7);
4834 pr_err("%-15s %016llx %-13s %016llx\n",
4835 "rip:", save->rip, "rflags:", save->rflags);
4836 pr_err("%-15s %016llx %-13s %016llx\n",
4837 "rsp:", save->rsp, "rax:", save->rax);
4838 pr_err("%-15s %016llx %-13s %016llx\n",
4839 "star:", save->star, "lstar:", save->lstar);
4840 pr_err("%-15s %016llx %-13s %016llx\n",
4841 "cstar:", save->cstar, "sfmask:", save->sfmask);
4842 pr_err("%-15s %016llx %-13s %016llx\n",
4843 "kernel_gs_base:", save->kernel_gs_base,
4844 "sysenter_cs:", save->sysenter_cs);
4845 pr_err("%-15s %016llx %-13s %016llx\n",
4846 "sysenter_esp:", save->sysenter_esp,
4847 "sysenter_eip:", save->sysenter_eip);
4848 pr_err("%-15s %016llx %-13s %016llx\n",
4849 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4850 pr_err("%-15s %016llx %-13s %016llx\n",
4851 "br_from:", save->br_from, "br_to:", save->br_to);
4852 pr_err("%-15s %016llx %-13s %016llx\n",
4853 "excp_from:", save->last_excp_from,
4854 "excp_to:", save->last_excp_to);
4857 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4859 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4861 *info1 = control->exit_info_1;
4862 *info2 = control->exit_info_2;
4865 static int handle_exit(struct kvm_vcpu *vcpu)
4867 struct vcpu_svm *svm = to_svm(vcpu);
4868 struct kvm_run *kvm_run = vcpu->run;
4869 u32 exit_code = svm->vmcb->control.exit_code;
4871 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4873 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4874 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4876 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4878 if (unlikely(svm->nested.exit_required)) {
4879 nested_svm_vmexit(svm);
4880 svm->nested.exit_required = false;
4885 if (is_guest_mode(vcpu)) {
4888 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4889 svm->vmcb->control.exit_info_1,
4890 svm->vmcb->control.exit_info_2,
4891 svm->vmcb->control.exit_int_info,
4892 svm->vmcb->control.exit_int_info_err,
4895 vmexit = nested_svm_exit_special(svm);
4897 if (vmexit == NESTED_EXIT_CONTINUE)
4898 vmexit = nested_svm_exit_handled(svm);
4900 if (vmexit == NESTED_EXIT_DONE)
4904 svm_complete_interrupts(svm);
4906 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4907 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4908 kvm_run->fail_entry.hardware_entry_failure_reason
4909 = svm->vmcb->control.exit_code;
4910 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4915 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4916 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4917 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4918 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4919 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4921 __func__, svm->vmcb->control.exit_int_info,
4924 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4925 || !svm_exit_handlers[exit_code]) {
4926 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4927 kvm_queue_exception(vcpu, UD_VECTOR);
4931 return svm_exit_handlers[exit_code](svm);
4934 static void reload_tss(struct kvm_vcpu *vcpu)
4936 int cpu = raw_smp_processor_id();
4938 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4939 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4943 static void pre_sev_run(struct vcpu_svm *svm, int cpu)
4945 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4946 int asid = sev_get_asid(svm->vcpu.kvm);
4948 /* Assign the asid allocated with this SEV guest */
4949 svm->vmcb->control.asid = asid;
4954 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4955 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4957 if (sd->sev_vmcbs[asid] == svm->vmcb &&
4958 svm->last_cpu == cpu)
4961 svm->last_cpu = cpu;
4962 sd->sev_vmcbs[asid] = svm->vmcb;
4963 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4964 mark_dirty(svm->vmcb, VMCB_ASID);
4967 static void pre_svm_run(struct vcpu_svm *svm)
4969 int cpu = raw_smp_processor_id();
4971 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4973 if (sev_guest(svm->vcpu.kvm))
4974 return pre_sev_run(svm, cpu);
4976 /* FIXME: handle wraparound of asid_generation */
4977 if (svm->asid_generation != sd->asid_generation)
4981 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4983 struct vcpu_svm *svm = to_svm(vcpu);
4985 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4986 vcpu->arch.hflags |= HF_NMI_MASK;
4987 set_intercept(svm, INTERCEPT_IRET);
4988 ++vcpu->stat.nmi_injections;
4991 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4993 struct vmcb_control_area *control;
4995 /* The following fields are ignored when AVIC is enabled */
4996 control = &svm->vmcb->control;
4997 control->int_vector = irq;
4998 control->int_ctl &= ~V_INTR_PRIO_MASK;
4999 control->int_ctl |= V_IRQ_MASK |
5000 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
5001 mark_dirty(svm->vmcb, VMCB_INTR);
5004 static void svm_set_irq(struct kvm_vcpu *vcpu)
5006 struct vcpu_svm *svm = to_svm(vcpu);
5008 BUG_ON(!(gif_set(svm)));
5010 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
5011 ++vcpu->stat.irq_injections;
5013 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
5014 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
5017 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
5019 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
5022 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5024 struct vcpu_svm *svm = to_svm(vcpu);
5026 if (svm_nested_virtualize_tpr(vcpu) ||
5027 kvm_vcpu_apicv_active(vcpu))
5030 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5036 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
5039 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
5044 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
5046 return avic && irqchip_split(vcpu->kvm);
5049 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5053 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5057 /* Note: Currently only used by Hyper-V. */
5058 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5060 struct vcpu_svm *svm = to_svm(vcpu);
5061 struct vmcb *vmcb = svm->vmcb;
5063 if (!kvm_vcpu_apicv_active(&svm->vcpu))
5066 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
5067 mark_dirty(vmcb, VMCB_INTR);
5070 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5075 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
5077 kvm_lapic_set_irr(vec, vcpu->arch.apic);
5078 smp_mb__after_atomic();
5080 if (avic_vcpu_is_running(vcpu))
5081 wrmsrl(SVM_AVIC_DOORBELL,
5082 kvm_cpu_get_apicid(vcpu->cpu));
5084 kvm_vcpu_wake_up(vcpu);
5087 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5089 unsigned long flags;
5090 struct amd_svm_iommu_ir *cur;
5092 spin_lock_irqsave(&svm->ir_list_lock, flags);
5093 list_for_each_entry(cur, &svm->ir_list, node) {
5094 if (cur->data != pi->ir_data)
5096 list_del(&cur->node);
5100 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5103 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
5106 unsigned long flags;
5107 struct amd_svm_iommu_ir *ir;
5110 * In some cases, the existing irte is updaed and re-set,
5111 * so we need to check here if it's already been * added
5114 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
5115 struct kvm *kvm = svm->vcpu.kvm;
5116 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
5117 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
5118 struct vcpu_svm *prev_svm;
5125 prev_svm = to_svm(prev_vcpu);
5126 svm_ir_list_del(prev_svm, pi);
5130 * Allocating new amd_iommu_pi_data, which will get
5131 * add to the per-vcpu ir_list.
5133 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
5138 ir->data = pi->ir_data;
5140 spin_lock_irqsave(&svm->ir_list_lock, flags);
5141 list_add(&ir->node, &svm->ir_list);
5142 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
5149 * The HW cannot support posting multicast/broadcast
5150 * interrupts to a vCPU. So, we still use legacy interrupt
5151 * remapping for these kind of interrupts.
5153 * For lowest-priority interrupts, we only support
5154 * those with single CPU as the destination, e.g. user
5155 * configures the interrupts via /proc/irq or uses
5156 * irqbalance to make the interrupts single-CPU.
5159 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
5160 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
5162 struct kvm_lapic_irq irq;
5163 struct kvm_vcpu *vcpu = NULL;
5165 kvm_set_msi_irq(kvm, e, &irq);
5167 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
5168 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5169 __func__, irq.vector);
5173 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
5175 *svm = to_svm(vcpu);
5176 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
5177 vcpu_info->vector = irq.vector;
5183 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5186 * @host_irq: host irq of the interrupt
5187 * @guest_irq: gsi of the interrupt
5188 * @set: set or unset PI
5189 * returns 0 on success, < 0 on failure
5191 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
5192 uint32_t guest_irq, bool set)
5194 struct kvm_kernel_irq_routing_entry *e;
5195 struct kvm_irq_routing_table *irq_rt;
5196 int idx, ret = -EINVAL;
5198 if (!kvm_arch_has_assigned_device(kvm) ||
5199 !irq_remapping_cap(IRQ_POSTING_CAP))
5202 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5203 __func__, host_irq, guest_irq, set);
5205 idx = srcu_read_lock(&kvm->irq_srcu);
5206 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
5207 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
5209 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
5210 struct vcpu_data vcpu_info;
5211 struct vcpu_svm *svm = NULL;
5213 if (e->type != KVM_IRQ_ROUTING_MSI)
5217 * Here, we setup with legacy mode in the following cases:
5218 * 1. When cannot target interrupt to a specific vcpu.
5219 * 2. Unsetting posted interrupt.
5220 * 3. APIC virtialization is disabled for the vcpu.
5222 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
5223 kvm_vcpu_apicv_active(&svm->vcpu)) {
5224 struct amd_iommu_pi_data pi;
5226 /* Try to enable guest_mode in IRTE */
5227 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
5229 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
5231 pi.is_guest_mode = true;
5232 pi.vcpu_data = &vcpu_info;
5233 ret = irq_set_vcpu_affinity(host_irq, &pi);
5236 * Here, we successfully setting up vcpu affinity in
5237 * IOMMU guest mode. Now, we need to store the posted
5238 * interrupt information in a per-vcpu ir_list so that
5239 * we can reference to them directly when we update vcpu
5240 * scheduling information in IOMMU irte.
5242 if (!ret && pi.is_guest_mode)
5243 svm_ir_list_add(svm, &pi);
5245 /* Use legacy mode in IRTE */
5246 struct amd_iommu_pi_data pi;
5249 * Here, pi is used to:
5250 * - Tell IOMMU to use legacy mode for this interrupt.
5251 * - Retrieve ga_tag of prior interrupt remapping data.
5253 pi.is_guest_mode = false;
5254 ret = irq_set_vcpu_affinity(host_irq, &pi);
5257 * Check if the posted interrupt was previously
5258 * setup with the guest_mode by checking if the ga_tag
5259 * was cached. If so, we need to clean up the per-vcpu
5262 if (!ret && pi.prev_ga_tag) {
5263 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
5264 struct kvm_vcpu *vcpu;
5266 vcpu = kvm_get_vcpu_by_id(kvm, id);
5268 svm_ir_list_del(to_svm(vcpu), &pi);
5273 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
5274 e->gsi, vcpu_info.vector,
5275 vcpu_info.pi_desc_addr, set);
5279 pr_err("%s: failed to update PI IRTE\n", __func__);
5286 srcu_read_unlock(&kvm->irq_srcu, idx);
5290 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
5292 struct vcpu_svm *svm = to_svm(vcpu);
5293 struct vmcb *vmcb = svm->vmcb;
5295 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
5296 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
5297 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
5302 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
5304 struct vcpu_svm *svm = to_svm(vcpu);
5306 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
5309 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5311 struct vcpu_svm *svm = to_svm(vcpu);
5314 svm->vcpu.arch.hflags |= HF_NMI_MASK;
5315 set_intercept(svm, INTERCEPT_IRET);
5317 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
5318 clr_intercept(svm, INTERCEPT_IRET);
5322 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
5324 struct vcpu_svm *svm = to_svm(vcpu);
5325 struct vmcb *vmcb = svm->vmcb;
5328 if (!gif_set(svm) ||
5329 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
5332 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
5334 if (is_guest_mode(vcpu))
5335 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
5340 static void enable_irq_window(struct kvm_vcpu *vcpu)
5342 struct vcpu_svm *svm = to_svm(vcpu);
5344 if (kvm_vcpu_apicv_active(vcpu))
5348 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5349 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5350 * get that intercept, this function will be called again though and
5351 * we'll get the vintr intercept. However, if the vGIF feature is
5352 * enabled, the STGI interception will not occur. Enable the irq
5353 * window under the assumption that the hardware will set the GIF.
5355 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
5357 svm_inject_irq(svm, 0x0);
5361 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5363 struct vcpu_svm *svm = to_svm(vcpu);
5365 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
5367 return; /* IRET will cause a vm exit */
5369 if (!gif_set(svm)) {
5370 if (vgif_enabled(svm))
5371 set_intercept(svm, INTERCEPT_STGI);
5372 return; /* STGI will cause a vm exit */
5375 if (svm->nested.exit_required)
5376 return; /* we're not going to run the guest yet */
5379 * Something prevents NMI from been injected. Single step over possible
5380 * problem (IRET or exception injection or interrupt shadow)
5382 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
5383 svm->nmi_singlestep = true;
5384 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
5387 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
5392 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
5397 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
5399 struct vcpu_svm *svm = to_svm(vcpu);
5401 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
5402 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
5404 svm->asid_generation--;
5407 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
5411 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
5413 struct vcpu_svm *svm = to_svm(vcpu);
5415 if (svm_nested_virtualize_tpr(vcpu))
5418 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
5419 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
5420 kvm_set_cr8(vcpu, cr8);
5424 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
5426 struct vcpu_svm *svm = to_svm(vcpu);
5429 if (svm_nested_virtualize_tpr(vcpu) ||
5430 kvm_vcpu_apicv_active(vcpu))
5433 cr8 = kvm_get_cr8(vcpu);
5434 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
5435 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
5438 static void svm_complete_interrupts(struct vcpu_svm *svm)
5442 u32 exitintinfo = svm->vmcb->control.exit_int_info;
5443 unsigned int3_injected = svm->int3_injected;
5445 svm->int3_injected = 0;
5448 * If we've made progress since setting HF_IRET_MASK, we've
5449 * executed an IRET and can allow NMI injection.
5451 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
5452 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
5453 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
5454 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5457 svm->vcpu.arch.nmi_injected = false;
5458 kvm_clear_exception_queue(&svm->vcpu);
5459 kvm_clear_interrupt_queue(&svm->vcpu);
5461 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
5464 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
5466 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
5467 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
5470 case SVM_EXITINTINFO_TYPE_NMI:
5471 svm->vcpu.arch.nmi_injected = true;
5473 case SVM_EXITINTINFO_TYPE_EXEPT:
5475 * In case of software exceptions, do not reinject the vector,
5476 * but re-execute the instruction instead. Rewind RIP first
5477 * if we emulated INT3 before.
5479 if (kvm_exception_is_soft(vector)) {
5480 if (vector == BP_VECTOR && int3_injected &&
5481 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
5482 kvm_rip_write(&svm->vcpu,
5483 kvm_rip_read(&svm->vcpu) -
5487 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
5488 u32 err = svm->vmcb->control.exit_int_info_err;
5489 kvm_requeue_exception_e(&svm->vcpu, vector, err);
5492 kvm_requeue_exception(&svm->vcpu, vector);
5494 case SVM_EXITINTINFO_TYPE_INTR:
5495 kvm_queue_interrupt(&svm->vcpu, vector, false);
5502 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
5504 struct vcpu_svm *svm = to_svm(vcpu);
5505 struct vmcb_control_area *control = &svm->vmcb->control;
5507 control->exit_int_info = control->event_inj;
5508 control->exit_int_info_err = control->event_inj_err;
5509 control->event_inj = 0;
5510 svm_complete_interrupts(svm);
5513 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
5515 struct vcpu_svm *svm = to_svm(vcpu);
5517 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
5518 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
5519 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
5522 * A vmexit emulation is required before the vcpu can be executed
5525 if (unlikely(svm->nested.exit_required))
5529 * Disable singlestep if we're injecting an interrupt/exception.
5530 * We don't want our modified rflags to be pushed on the stack where
5531 * we might not be able to easily reset them if we disabled NMI
5534 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
5536 * Event injection happens before external interrupts cause a
5537 * vmexit and interrupts are disabled here, so smp_send_reschedule
5538 * is enough to force an immediate vmexit.
5540 disable_nmi_singlestep(svm);
5541 smp_send_reschedule(vcpu->cpu);
5546 sync_lapic_to_cr8(vcpu);
5548 svm->vmcb->save.cr2 = vcpu->arch.cr2;
5555 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5556 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5557 * is no need to worry about the conditional branch over the wrmsr
5558 * being speculatively taken.
5560 x86_spec_ctrl_set_guest(svm->spec_ctrl);
5563 "push %%" _ASM_BP "; \n\t"
5564 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
5565 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
5566 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
5567 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
5568 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
5569 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
5570 #ifdef CONFIG_X86_64
5571 "mov %c[r8](%[svm]), %%r8 \n\t"
5572 "mov %c[r9](%[svm]), %%r9 \n\t"
5573 "mov %c[r10](%[svm]), %%r10 \n\t"
5574 "mov %c[r11](%[svm]), %%r11 \n\t"
5575 "mov %c[r12](%[svm]), %%r12 \n\t"
5576 "mov %c[r13](%[svm]), %%r13 \n\t"
5577 "mov %c[r14](%[svm]), %%r14 \n\t"
5578 "mov %c[r15](%[svm]), %%r15 \n\t"
5581 /* Enter guest mode */
5582 "push %%" _ASM_AX " \n\t"
5583 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
5584 __ex(SVM_VMLOAD) "\n\t"
5585 __ex(SVM_VMRUN) "\n\t"
5586 __ex(SVM_VMSAVE) "\n\t"
5587 "pop %%" _ASM_AX " \n\t"
5589 /* Save guest registers, load host registers */
5590 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
5591 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
5592 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
5593 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
5594 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
5595 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
5596 #ifdef CONFIG_X86_64
5597 "mov %%r8, %c[r8](%[svm]) \n\t"
5598 "mov %%r9, %c[r9](%[svm]) \n\t"
5599 "mov %%r10, %c[r10](%[svm]) \n\t"
5600 "mov %%r11, %c[r11](%[svm]) \n\t"
5601 "mov %%r12, %c[r12](%[svm]) \n\t"
5602 "mov %%r13, %c[r13](%[svm]) \n\t"
5603 "mov %%r14, %c[r14](%[svm]) \n\t"
5604 "mov %%r15, %c[r15](%[svm]) \n\t"
5607 * Clear host registers marked as clobbered to prevent
5610 "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
5611 "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
5612 "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
5613 "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
5614 "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
5615 #ifdef CONFIG_X86_64
5616 "xor %%r8, %%r8 \n\t"
5617 "xor %%r9, %%r9 \n\t"
5618 "xor %%r10, %%r10 \n\t"
5619 "xor %%r11, %%r11 \n\t"
5620 "xor %%r12, %%r12 \n\t"
5621 "xor %%r13, %%r13 \n\t"
5622 "xor %%r14, %%r14 \n\t"
5623 "xor %%r15, %%r15 \n\t"
5628 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
5629 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
5630 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
5631 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
5632 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
5633 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
5634 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
5635 #ifdef CONFIG_X86_64
5636 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
5637 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
5638 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
5639 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
5640 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
5641 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
5642 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
5643 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
5646 #ifdef CONFIG_X86_64
5647 , "rbx", "rcx", "rdx", "rsi", "rdi"
5648 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5650 , "ebx", "ecx", "edx", "esi", "edi"
5654 /* Eliminate branch target predictions from guest mode */
5657 #ifdef CONFIG_X86_64
5658 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
5660 loadsegment(fs, svm->host.fs);
5661 #ifndef CONFIG_X86_32_LAZY_GS
5662 loadsegment(gs, svm->host.gs);
5667 * We do not use IBRS in the kernel. If this vCPU has used the
5668 * SPEC_CTRL MSR it may have left it on; save the value and
5669 * turn it off. This is much more efficient than blindly adding
5670 * it to the atomic save/restore list. Especially as the former
5671 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5673 * For non-nested case:
5674 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5678 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5681 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
5682 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
5684 x86_spec_ctrl_restore_host(svm->spec_ctrl);
5688 local_irq_disable();
5690 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5691 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5692 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5693 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5695 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5696 kvm_before_interrupt(&svm->vcpu);
5700 /* Any pending NMI will happen here */
5702 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5703 kvm_after_interrupt(&svm->vcpu);
5705 sync_cr8_to_lapic(vcpu);
5709 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5711 /* if exit due to PF check for async PF */
5712 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5713 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5716 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5717 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5721 * We need to handle MC intercepts here before the vcpu has a chance to
5722 * change the physical cpu
5724 if (unlikely(svm->vmcb->control.exit_code ==
5725 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5726 svm_handle_mce(svm);
5728 mark_all_clean(svm->vmcb);
5730 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5732 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5734 struct vcpu_svm *svm = to_svm(vcpu);
5736 svm->vmcb->save.cr3 = __sme_set(root);
5737 mark_dirty(svm->vmcb, VMCB_CR);
5738 svm_flush_tlb(vcpu, true);
5741 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5743 struct vcpu_svm *svm = to_svm(vcpu);
5745 svm->vmcb->control.nested_cr3 = __sme_set(root);
5746 mark_dirty(svm->vmcb, VMCB_NPT);
5748 /* Also sync guest cr3 here in case we live migrate */
5749 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5750 mark_dirty(svm->vmcb, VMCB_CR);
5752 svm_flush_tlb(vcpu, true);
5755 static int is_disabled(void)
5759 rdmsrl(MSR_VM_CR, vm_cr);
5760 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5767 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5770 * Patch in the VMMCALL instruction:
5772 hypercall[0] = 0x0f;
5773 hypercall[1] = 0x01;
5774 hypercall[2] = 0xd9;
5777 static void svm_check_processor_compat(void *rtn)
5782 static bool svm_cpu_has_accelerated_tpr(void)
5787 static bool svm_has_high_real_mode_segbase(void)
5792 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5797 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5799 struct vcpu_svm *svm = to_svm(vcpu);
5801 /* Update nrips enabled cache */
5802 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5804 if (!kvm_vcpu_apicv_active(vcpu))
5807 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5810 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5815 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5819 entry->ecx |= (1 << 2); /* Set SVM bit */
5822 entry->eax = 1; /* SVM revision 1 */
5823 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5824 ASID emulation to nested SVM */
5825 entry->ecx = 0; /* Reserved */
5826 entry->edx = 0; /* Per default do not support any
5827 additional features */
5829 /* Support next_rip if host supports it */
5830 if (boot_cpu_has(X86_FEATURE_NRIPS))
5831 entry->edx |= SVM_FEATURE_NRIP;
5833 /* Support NPT for the guest if enabled */
5835 entry->edx |= SVM_FEATURE_NPT;
5839 /* Support memory encryption cpuid if host supports it */
5840 if (boot_cpu_has(X86_FEATURE_SEV))
5841 cpuid(0x8000001f, &entry->eax, &entry->ebx,
5842 &entry->ecx, &entry->edx);
5847 static int svm_get_lpage_level(void)
5849 return PT_PDPE_LEVEL;
5852 static bool svm_rdtscp_supported(void)
5854 return boot_cpu_has(X86_FEATURE_RDTSCP);
5857 static bool svm_invpcid_supported(void)
5862 static bool svm_mpx_supported(void)
5867 static bool svm_xsaves_supported(void)
5872 static bool svm_umip_emulated(void)
5877 static bool svm_has_wbinvd_exit(void)
5882 #define PRE_EX(exit) { .exit_code = (exit), \
5883 .stage = X86_ICPT_PRE_EXCEPT, }
5884 #define POST_EX(exit) { .exit_code = (exit), \
5885 .stage = X86_ICPT_POST_EXCEPT, }
5886 #define POST_MEM(exit) { .exit_code = (exit), \
5887 .stage = X86_ICPT_POST_MEMACCESS, }
5889 static const struct __x86_intercept {
5891 enum x86_intercept_stage stage;
5892 } x86_intercept_map[] = {
5893 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5894 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5895 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5896 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5897 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5898 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5899 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5900 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5901 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5902 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5903 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5904 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5905 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5906 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5907 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5908 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5909 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5910 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5911 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5912 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5913 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5914 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5915 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5916 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5917 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5918 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5919 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5920 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5921 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5922 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5923 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5924 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5925 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5926 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5927 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5928 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5929 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5930 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5931 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5932 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5933 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5934 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5935 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5936 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5937 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5938 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5945 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5946 struct x86_instruction_info *info,
5947 enum x86_intercept_stage stage)
5949 struct vcpu_svm *svm = to_svm(vcpu);
5950 int vmexit, ret = X86EMUL_CONTINUE;
5951 struct __x86_intercept icpt_info;
5952 struct vmcb *vmcb = svm->vmcb;
5954 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5957 icpt_info = x86_intercept_map[info->intercept];
5959 if (stage != icpt_info.stage)
5962 switch (icpt_info.exit_code) {
5963 case SVM_EXIT_READ_CR0:
5964 if (info->intercept == x86_intercept_cr_read)
5965 icpt_info.exit_code += info->modrm_reg;
5967 case SVM_EXIT_WRITE_CR0: {
5968 unsigned long cr0, val;
5971 if (info->intercept == x86_intercept_cr_write)
5972 icpt_info.exit_code += info->modrm_reg;
5974 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5975 info->intercept == x86_intercept_clts)
5978 intercept = svm->nested.intercept;
5980 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5983 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5984 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5986 if (info->intercept == x86_intercept_lmsw) {
5989 /* lmsw can't clear PE - catch this here */
5990 if (cr0 & X86_CR0_PE)
5995 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5999 case SVM_EXIT_READ_DR0:
6000 case SVM_EXIT_WRITE_DR0:
6001 icpt_info.exit_code += info->modrm_reg;
6004 if (info->intercept == x86_intercept_wrmsr)
6005 vmcb->control.exit_info_1 = 1;
6007 vmcb->control.exit_info_1 = 0;
6009 case SVM_EXIT_PAUSE:
6011 * We get this for NOP only, but pause
6012 * is rep not, check this here
6014 if (info->rep_prefix != REPE_PREFIX)
6017 case SVM_EXIT_IOIO: {
6021 if (info->intercept == x86_intercept_in ||
6022 info->intercept == x86_intercept_ins) {
6023 exit_info = ((info->src_val & 0xffff) << 16) |
6025 bytes = info->dst_bytes;
6027 exit_info = (info->dst_val & 0xffff) << 16;
6028 bytes = info->src_bytes;
6031 if (info->intercept == x86_intercept_outs ||
6032 info->intercept == x86_intercept_ins)
6033 exit_info |= SVM_IOIO_STR_MASK;
6035 if (info->rep_prefix)
6036 exit_info |= SVM_IOIO_REP_MASK;
6038 bytes = min(bytes, 4u);
6040 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
6042 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
6044 vmcb->control.exit_info_1 = exit_info;
6045 vmcb->control.exit_info_2 = info->next_rip;
6053 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6054 if (static_cpu_has(X86_FEATURE_NRIPS))
6055 vmcb->control.next_rip = info->next_rip;
6056 vmcb->control.exit_code = icpt_info.exit_code;
6057 vmexit = nested_svm_exit_handled(svm);
6059 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
6066 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
6070 * We must have an instruction with interrupts enabled, so
6071 * the timer interrupt isn't delayed by the interrupt shadow.
6074 local_irq_disable();
6077 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
6079 if (pause_filter_thresh)
6080 shrink_ple_window(vcpu);
6083 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
6085 if (avic_handle_apic_id_update(vcpu) != 0)
6087 if (avic_handle_dfr_update(vcpu) != 0)
6089 avic_handle_ldr_update(vcpu);
6092 static void svm_setup_mce(struct kvm_vcpu *vcpu)
6094 /* [63:9] are reserved. */
6095 vcpu->arch.mcg_cap &= 0x1ff;
6098 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
6100 struct vcpu_svm *svm = to_svm(vcpu);
6102 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6106 if (is_guest_mode(&svm->vcpu) &&
6107 svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
6108 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6109 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
6110 svm->nested.exit_required = true;
6117 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
6119 struct vcpu_svm *svm = to_svm(vcpu);
6122 if (is_guest_mode(vcpu)) {
6123 /* FED8h - SVM Guest */
6124 put_smstate(u64, smstate, 0x7ed8, 1);
6125 /* FEE0h - SVM Guest VMCB Physical Address */
6126 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
6128 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
6129 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
6130 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
6132 ret = nested_svm_vmexit(svm);
6139 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
6141 struct vcpu_svm *svm = to_svm(vcpu);
6142 struct vmcb *nested_vmcb;
6150 ret = kvm_vcpu_read_guest(vcpu, smbase + 0xfed8, &svm_state_save,
6151 sizeof(svm_state_save));
6155 if (svm_state_save.guest) {
6156 vcpu->arch.hflags &= ~HF_SMM_MASK;
6157 nested_vmcb = nested_svm_map(svm, svm_state_save.vmcb, &page);
6159 enter_svm_guest_mode(svm, svm_state_save.vmcb, nested_vmcb, page);
6162 vcpu->arch.hflags |= HF_SMM_MASK;
6167 static int enable_smi_window(struct kvm_vcpu *vcpu)
6169 struct vcpu_svm *svm = to_svm(vcpu);
6171 if (!gif_set(svm)) {
6172 if (vgif_enabled(svm))
6173 set_intercept(svm, INTERCEPT_STGI);
6174 /* STGI will cause a vm exit */
6180 static int sev_asid_new(void)
6185 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6187 pos = find_next_zero_bit(sev_asid_bitmap, max_sev_asid, min_sev_asid - 1);
6188 if (pos >= max_sev_asid)
6191 set_bit(pos, sev_asid_bitmap);
6195 static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp)
6197 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6201 asid = sev_asid_new();
6205 ret = sev_platform_init(&argp->error);
6211 INIT_LIST_HEAD(&sev->regions_list);
6216 __sev_asid_free(asid);
6220 static int sev_bind_asid(struct kvm *kvm, unsigned int handle, int *error)
6222 struct sev_data_activate *data;
6223 int asid = sev_get_asid(kvm);
6226 wbinvd_on_all_cpus();
6228 ret = sev_guest_df_flush(error);
6232 data = kzalloc(sizeof(*data), GFP_KERNEL);
6236 /* activate ASID on the given handle */
6237 data->handle = handle;
6239 ret = sev_guest_activate(data, error);
6245 static int __sev_issue_cmd(int fd, int id, void *data, int *error)
6254 ret = sev_issue_cmd_external_user(f.file, id, data, error);
6260 static int sev_issue_cmd(struct kvm *kvm, int id, void *data, int *error)
6262 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6264 return __sev_issue_cmd(sev->fd, id, data, error);
6267 static int sev_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp)
6269 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6270 struct sev_data_launch_start *start;
6271 struct kvm_sev_launch_start params;
6272 void *dh_blob, *session_blob;
6273 int *error = &argp->error;
6276 if (!sev_guest(kvm))
6279 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6282 start = kzalloc(sizeof(*start), GFP_KERNEL);
6287 if (params.dh_uaddr) {
6288 dh_blob = psp_copy_user_blob(params.dh_uaddr, params.dh_len);
6289 if (IS_ERR(dh_blob)) {
6290 ret = PTR_ERR(dh_blob);
6294 start->dh_cert_address = __sme_set(__pa(dh_blob));
6295 start->dh_cert_len = params.dh_len;
6298 session_blob = NULL;
6299 if (params.session_uaddr) {
6300 session_blob = psp_copy_user_blob(params.session_uaddr, params.session_len);
6301 if (IS_ERR(session_blob)) {
6302 ret = PTR_ERR(session_blob);
6306 start->session_address = __sme_set(__pa(session_blob));
6307 start->session_len = params.session_len;
6310 start->handle = params.handle;
6311 start->policy = params.policy;
6313 /* create memory encryption context */
6314 ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_LAUNCH_START, start, error);
6316 goto e_free_session;
6318 /* Bind ASID to this guest */
6319 ret = sev_bind_asid(kvm, start->handle, error);
6321 goto e_free_session;
6323 /* return handle to userspace */
6324 params.handle = start->handle;
6325 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params))) {
6326 sev_unbind_asid(kvm, start->handle);
6328 goto e_free_session;
6331 sev->handle = start->handle;
6332 sev->fd = argp->sev_fd;
6335 kfree(session_blob);
6343 static int get_num_contig_pages(int idx, struct page **inpages,
6344 unsigned long npages)
6346 unsigned long paddr, next_paddr;
6347 int i = idx + 1, pages = 1;
6349 /* find the number of contiguous pages starting from idx */
6350 paddr = __sme_page_pa(inpages[idx]);
6351 while (i < npages) {
6352 next_paddr = __sme_page_pa(inpages[i++]);
6353 if ((paddr + PAGE_SIZE) == next_paddr) {
6364 static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp)
6366 unsigned long vaddr, vaddr_end, next_vaddr, npages, size;
6367 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6368 struct kvm_sev_launch_update_data params;
6369 struct sev_data_launch_update_data *data;
6370 struct page **inpages;
6373 if (!sev_guest(kvm))
6376 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6379 data = kzalloc(sizeof(*data), GFP_KERNEL);
6383 vaddr = params.uaddr;
6385 vaddr_end = vaddr + size;
6387 /* Lock the user memory. */
6388 inpages = sev_pin_memory(kvm, vaddr, size, &npages, 1);
6395 * The LAUNCH_UPDATE command will perform in-place encryption of the
6396 * memory content (i.e it will write the same memory region with C=1).
6397 * It's possible that the cache may contain the data with C=0, i.e.,
6398 * unencrypted so invalidate it first.
6400 sev_clflush_pages(inpages, npages);
6402 for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i += pages) {
6406 * If the user buffer is not page-aligned, calculate the offset
6409 offset = vaddr & (PAGE_SIZE - 1);
6411 /* Calculate the number of pages that can be encrypted in one go. */
6412 pages = get_num_contig_pages(i, inpages, npages);
6414 len = min_t(size_t, ((pages * PAGE_SIZE) - offset), size);
6416 data->handle = sev->handle;
6418 data->address = __sme_page_pa(inpages[i]) + offset;
6419 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_DATA, data, &argp->error);
6424 next_vaddr = vaddr + len;
6428 /* content of memory is updated, mark pages dirty */
6429 for (i = 0; i < npages; i++) {
6430 set_page_dirty_lock(inpages[i]);
6431 mark_page_accessed(inpages[i]);
6433 /* unlock the user pages */
6434 sev_unpin_memory(kvm, inpages, npages);
6440 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
6442 void __user *measure = (void __user *)(uintptr_t)argp->data;
6443 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6444 struct sev_data_launch_measure *data;
6445 struct kvm_sev_launch_measure params;
6446 void __user *p = NULL;
6450 if (!sev_guest(kvm))
6453 if (copy_from_user(¶ms, measure, sizeof(params)))
6456 data = kzalloc(sizeof(*data), GFP_KERNEL);
6460 /* User wants to query the blob length */
6464 p = (void __user *)(uintptr_t)params.uaddr;
6466 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
6472 blob = kmalloc(params.len, GFP_KERNEL);
6476 data->address = __psp_pa(blob);
6477 data->len = params.len;
6481 data->handle = sev->handle;
6482 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_MEASURE, data, &argp->error);
6485 * If we query the session length, FW responded with expected data.
6494 if (copy_to_user(p, blob, params.len))
6499 params.len = data->len;
6500 if (copy_to_user(measure, ¶ms, sizeof(params)))
6509 static int sev_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp)
6511 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6512 struct sev_data_launch_finish *data;
6515 if (!sev_guest(kvm))
6518 data = kzalloc(sizeof(*data), GFP_KERNEL);
6522 data->handle = sev->handle;
6523 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_FINISH, data, &argp->error);
6529 static int sev_guest_status(struct kvm *kvm, struct kvm_sev_cmd *argp)
6531 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6532 struct kvm_sev_guest_status params;
6533 struct sev_data_guest_status *data;
6536 if (!sev_guest(kvm))
6539 data = kzalloc(sizeof(*data), GFP_KERNEL);
6543 data->handle = sev->handle;
6544 ret = sev_issue_cmd(kvm, SEV_CMD_GUEST_STATUS, data, &argp->error);
6548 params.policy = data->policy;
6549 params.state = data->state;
6550 params.handle = data->handle;
6552 if (copy_to_user((void __user *)(uintptr_t)argp->data, ¶ms, sizeof(params)))
6559 static int __sev_issue_dbg_cmd(struct kvm *kvm, unsigned long src,
6560 unsigned long dst, int size,
6561 int *error, bool enc)
6563 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6564 struct sev_data_dbg *data;
6567 data = kzalloc(sizeof(*data), GFP_KERNEL);
6571 data->handle = sev->handle;
6572 data->dst_addr = dst;
6573 data->src_addr = src;
6576 ret = sev_issue_cmd(kvm,
6577 enc ? SEV_CMD_DBG_ENCRYPT : SEV_CMD_DBG_DECRYPT,
6583 static int __sev_dbg_decrypt(struct kvm *kvm, unsigned long src_paddr,
6584 unsigned long dst_paddr, int sz, int *err)
6589 * Its safe to read more than we are asked, caller should ensure that
6590 * destination has enough space.
6592 src_paddr = round_down(src_paddr, 16);
6593 offset = src_paddr & 15;
6594 sz = round_up(sz + offset, 16);
6596 return __sev_issue_dbg_cmd(kvm, src_paddr, dst_paddr, sz, err, false);
6599 static int __sev_dbg_decrypt_user(struct kvm *kvm, unsigned long paddr,
6600 unsigned long __user dst_uaddr,
6601 unsigned long dst_paddr,
6604 struct page *tpage = NULL;
6607 /* if inputs are not 16-byte then use intermediate buffer */
6608 if (!IS_ALIGNED(dst_paddr, 16) ||
6609 !IS_ALIGNED(paddr, 16) ||
6610 !IS_ALIGNED(size, 16)) {
6611 tpage = (void *)alloc_page(GFP_KERNEL);
6615 dst_paddr = __sme_page_pa(tpage);
6618 ret = __sev_dbg_decrypt(kvm, paddr, dst_paddr, size, err);
6623 offset = paddr & 15;
6624 if (copy_to_user((void __user *)(uintptr_t)dst_uaddr,
6625 page_address(tpage) + offset, size))
6636 static int __sev_dbg_encrypt_user(struct kvm *kvm, unsigned long paddr,
6637 unsigned long __user vaddr,
6638 unsigned long dst_paddr,
6639 unsigned long __user dst_vaddr,
6640 int size, int *error)
6642 struct page *src_tpage = NULL;
6643 struct page *dst_tpage = NULL;
6644 int ret, len = size;
6646 /* If source buffer is not aligned then use an intermediate buffer */
6647 if (!IS_ALIGNED(vaddr, 16)) {
6648 src_tpage = alloc_page(GFP_KERNEL);
6652 if (copy_from_user(page_address(src_tpage),
6653 (void __user *)(uintptr_t)vaddr, size)) {
6654 __free_page(src_tpage);
6658 paddr = __sme_page_pa(src_tpage);
6662 * If destination buffer or length is not aligned then do read-modify-write:
6663 * - decrypt destination in an intermediate buffer
6664 * - copy the source buffer in an intermediate buffer
6665 * - use the intermediate buffer as source buffer
6667 if (!IS_ALIGNED(dst_vaddr, 16) || !IS_ALIGNED(size, 16)) {
6670 dst_tpage = alloc_page(GFP_KERNEL);
6676 ret = __sev_dbg_decrypt(kvm, dst_paddr,
6677 __sme_page_pa(dst_tpage), size, error);
6682 * If source is kernel buffer then use memcpy() otherwise
6685 dst_offset = dst_paddr & 15;
6688 memcpy(page_address(dst_tpage) + dst_offset,
6689 page_address(src_tpage), size);
6691 if (copy_from_user(page_address(dst_tpage) + dst_offset,
6692 (void __user *)(uintptr_t)vaddr, size)) {
6698 paddr = __sme_page_pa(dst_tpage);
6699 dst_paddr = round_down(dst_paddr, 16);
6700 len = round_up(size, 16);
6703 ret = __sev_issue_dbg_cmd(kvm, paddr, dst_paddr, len, error, true);
6707 __free_page(src_tpage);
6709 __free_page(dst_tpage);
6713 static int sev_dbg_crypt(struct kvm *kvm, struct kvm_sev_cmd *argp, bool dec)
6715 unsigned long vaddr, vaddr_end, next_vaddr;
6716 unsigned long dst_vaddr, dst_vaddr_end;
6717 struct page **src_p, **dst_p;
6718 struct kvm_sev_dbg debug;
6722 if (!sev_guest(kvm))
6725 if (copy_from_user(&debug, (void __user *)(uintptr_t)argp->data, sizeof(debug)))
6728 vaddr = debug.src_uaddr;
6730 vaddr_end = vaddr + size;
6731 dst_vaddr = debug.dst_uaddr;
6732 dst_vaddr_end = dst_vaddr + size;
6734 for (; vaddr < vaddr_end; vaddr = next_vaddr) {
6735 int len, s_off, d_off;
6737 /* lock userspace source and destination page */
6738 src_p = sev_pin_memory(kvm, vaddr & PAGE_MASK, PAGE_SIZE, &n, 0);
6742 dst_p = sev_pin_memory(kvm, dst_vaddr & PAGE_MASK, PAGE_SIZE, &n, 1);
6744 sev_unpin_memory(kvm, src_p, n);
6749 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6750 * memory content (i.e it will write the same memory region with C=1).
6751 * It's possible that the cache may contain the data with C=0, i.e.,
6752 * unencrypted so invalidate it first.
6754 sev_clflush_pages(src_p, 1);
6755 sev_clflush_pages(dst_p, 1);
6758 * Since user buffer may not be page aligned, calculate the
6759 * offset within the page.
6761 s_off = vaddr & ~PAGE_MASK;
6762 d_off = dst_vaddr & ~PAGE_MASK;
6763 len = min_t(size_t, (PAGE_SIZE - s_off), size);
6766 ret = __sev_dbg_decrypt_user(kvm,
6767 __sme_page_pa(src_p[0]) + s_off,
6769 __sme_page_pa(dst_p[0]) + d_off,
6772 ret = __sev_dbg_encrypt_user(kvm,
6773 __sme_page_pa(src_p[0]) + s_off,
6775 __sme_page_pa(dst_p[0]) + d_off,
6779 sev_unpin_memory(kvm, src_p, 1);
6780 sev_unpin_memory(kvm, dst_p, 1);
6785 next_vaddr = vaddr + len;
6786 dst_vaddr = dst_vaddr + len;
6793 static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
6795 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6796 struct sev_data_launch_secret *data;
6797 struct kvm_sev_launch_secret params;
6798 struct page **pages;
6803 if (!sev_guest(kvm))
6806 if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params)))
6809 pages = sev_pin_memory(kvm, params.guest_uaddr, params.guest_len, &n, 1);
6814 * The secret must be copied into contiguous memory region, lets verify
6815 * that userspace memory pages are contiguous before we issue command.
6817 if (get_num_contig_pages(0, pages, n) != n) {
6819 goto e_unpin_memory;
6823 data = kzalloc(sizeof(*data), GFP_KERNEL);
6825 goto e_unpin_memory;
6827 offset = params.guest_uaddr & (PAGE_SIZE - 1);
6828 data->guest_address = __sme_page_pa(pages[0]) + offset;
6829 data->guest_len = params.guest_len;
6831 blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
6833 ret = PTR_ERR(blob);
6837 data->trans_address = __psp_pa(blob);
6838 data->trans_len = params.trans_len;
6840 hdr = psp_copy_user_blob(params.hdr_uaddr, params.hdr_len);
6845 data->hdr_address = __psp_pa(hdr);
6846 data->hdr_len = params.hdr_len;
6848 data->handle = sev->handle;
6849 ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
6858 sev_unpin_memory(kvm, pages, n);
6862 static int svm_mem_enc_op(struct kvm *kvm, void __user *argp)
6864 struct kvm_sev_cmd sev_cmd;
6867 if (!svm_sev_enabled())
6870 if (copy_from_user(&sev_cmd, argp, sizeof(struct kvm_sev_cmd)))
6873 mutex_lock(&kvm->lock);
6875 switch (sev_cmd.id) {
6877 r = sev_guest_init(kvm, &sev_cmd);
6879 case KVM_SEV_LAUNCH_START:
6880 r = sev_launch_start(kvm, &sev_cmd);
6882 case KVM_SEV_LAUNCH_UPDATE_DATA:
6883 r = sev_launch_update_data(kvm, &sev_cmd);
6885 case KVM_SEV_LAUNCH_MEASURE:
6886 r = sev_launch_measure(kvm, &sev_cmd);
6888 case KVM_SEV_LAUNCH_FINISH:
6889 r = sev_launch_finish(kvm, &sev_cmd);
6891 case KVM_SEV_GUEST_STATUS:
6892 r = sev_guest_status(kvm, &sev_cmd);
6894 case KVM_SEV_DBG_DECRYPT:
6895 r = sev_dbg_crypt(kvm, &sev_cmd, true);
6897 case KVM_SEV_DBG_ENCRYPT:
6898 r = sev_dbg_crypt(kvm, &sev_cmd, false);
6900 case KVM_SEV_LAUNCH_SECRET:
6901 r = sev_launch_secret(kvm, &sev_cmd);
6908 if (copy_to_user(argp, &sev_cmd, sizeof(struct kvm_sev_cmd)))
6912 mutex_unlock(&kvm->lock);
6916 static int svm_register_enc_region(struct kvm *kvm,
6917 struct kvm_enc_region *range)
6919 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6920 struct enc_region *region;
6923 if (!sev_guest(kvm))
6926 region = kzalloc(sizeof(*region), GFP_KERNEL);
6930 region->pages = sev_pin_memory(kvm, range->addr, range->size, ®ion->npages, 1);
6931 if (!region->pages) {
6937 * The guest may change the memory encryption attribute from C=0 -> C=1
6938 * or vice versa for this memory range. Lets make sure caches are
6939 * flushed to ensure that guest data gets written into memory with
6942 sev_clflush_pages(region->pages, region->npages);
6944 region->uaddr = range->addr;
6945 region->size = range->size;
6947 mutex_lock(&kvm->lock);
6948 list_add_tail(®ion->list, &sev->regions_list);
6949 mutex_unlock(&kvm->lock);
6958 static struct enc_region *
6959 find_enc_region(struct kvm *kvm, struct kvm_enc_region *range)
6961 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
6962 struct list_head *head = &sev->regions_list;
6963 struct enc_region *i;
6965 list_for_each_entry(i, head, list) {
6966 if (i->uaddr == range->addr &&
6967 i->size == range->size)
6975 static int svm_unregister_enc_region(struct kvm *kvm,
6976 struct kvm_enc_region *range)
6978 struct enc_region *region;
6981 mutex_lock(&kvm->lock);
6983 if (!sev_guest(kvm)) {
6988 region = find_enc_region(kvm, range);
6994 __unregister_enc_region_locked(kvm, region);
6996 mutex_unlock(&kvm->lock);
7000 mutex_unlock(&kvm->lock);
7004 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
7005 .cpu_has_kvm_support = has_svm,
7006 .disabled_by_bios = is_disabled,
7007 .hardware_setup = svm_hardware_setup,
7008 .hardware_unsetup = svm_hardware_unsetup,
7009 .check_processor_compatibility = svm_check_processor_compat,
7010 .hardware_enable = svm_hardware_enable,
7011 .hardware_disable = svm_hardware_disable,
7012 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
7013 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
7015 .vcpu_create = svm_create_vcpu,
7016 .vcpu_free = svm_free_vcpu,
7017 .vcpu_reset = svm_vcpu_reset,
7019 .vm_alloc = svm_vm_alloc,
7020 .vm_free = svm_vm_free,
7021 .vm_init = avic_vm_init,
7022 .vm_destroy = svm_vm_destroy,
7024 .prepare_guest_switch = svm_prepare_guest_switch,
7025 .vcpu_load = svm_vcpu_load,
7026 .vcpu_put = svm_vcpu_put,
7027 .vcpu_blocking = svm_vcpu_blocking,
7028 .vcpu_unblocking = svm_vcpu_unblocking,
7030 .update_bp_intercept = update_bp_intercept,
7031 .get_msr_feature = svm_get_msr_feature,
7032 .get_msr = svm_get_msr,
7033 .set_msr = svm_set_msr,
7034 .get_segment_base = svm_get_segment_base,
7035 .get_segment = svm_get_segment,
7036 .set_segment = svm_set_segment,
7037 .get_cpl = svm_get_cpl,
7038 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
7039 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
7040 .decache_cr3 = svm_decache_cr3,
7041 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
7042 .set_cr0 = svm_set_cr0,
7043 .set_cr3 = svm_set_cr3,
7044 .set_cr4 = svm_set_cr4,
7045 .set_efer = svm_set_efer,
7046 .get_idt = svm_get_idt,
7047 .set_idt = svm_set_idt,
7048 .get_gdt = svm_get_gdt,
7049 .set_gdt = svm_set_gdt,
7050 .get_dr6 = svm_get_dr6,
7051 .set_dr6 = svm_set_dr6,
7052 .set_dr7 = svm_set_dr7,
7053 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
7054 .cache_reg = svm_cache_reg,
7055 .get_rflags = svm_get_rflags,
7056 .set_rflags = svm_set_rflags,
7058 .tlb_flush = svm_flush_tlb,
7060 .run = svm_vcpu_run,
7061 .handle_exit = handle_exit,
7062 .skip_emulated_instruction = skip_emulated_instruction,
7063 .set_interrupt_shadow = svm_set_interrupt_shadow,
7064 .get_interrupt_shadow = svm_get_interrupt_shadow,
7065 .patch_hypercall = svm_patch_hypercall,
7066 .set_irq = svm_set_irq,
7067 .set_nmi = svm_inject_nmi,
7068 .queue_exception = svm_queue_exception,
7069 .cancel_injection = svm_cancel_injection,
7070 .interrupt_allowed = svm_interrupt_allowed,
7071 .nmi_allowed = svm_nmi_allowed,
7072 .get_nmi_mask = svm_get_nmi_mask,
7073 .set_nmi_mask = svm_set_nmi_mask,
7074 .enable_nmi_window = enable_nmi_window,
7075 .enable_irq_window = enable_irq_window,
7076 .update_cr8_intercept = update_cr8_intercept,
7077 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
7078 .get_enable_apicv = svm_get_enable_apicv,
7079 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
7080 .load_eoi_exitmap = svm_load_eoi_exitmap,
7081 .hwapic_irr_update = svm_hwapic_irr_update,
7082 .hwapic_isr_update = svm_hwapic_isr_update,
7083 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
7084 .apicv_post_state_restore = avic_post_state_restore,
7086 .set_tss_addr = svm_set_tss_addr,
7087 .set_identity_map_addr = svm_set_identity_map_addr,
7088 .get_tdp_level = get_npt_level,
7089 .get_mt_mask = svm_get_mt_mask,
7091 .get_exit_info = svm_get_exit_info,
7093 .get_lpage_level = svm_get_lpage_level,
7095 .cpuid_update = svm_cpuid_update,
7097 .rdtscp_supported = svm_rdtscp_supported,
7098 .invpcid_supported = svm_invpcid_supported,
7099 .mpx_supported = svm_mpx_supported,
7100 .xsaves_supported = svm_xsaves_supported,
7101 .umip_emulated = svm_umip_emulated,
7103 .set_supported_cpuid = svm_set_supported_cpuid,
7105 .has_wbinvd_exit = svm_has_wbinvd_exit,
7107 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
7108 .write_tsc_offset = svm_write_tsc_offset,
7110 .set_tdp_cr3 = set_tdp_cr3,
7112 .check_intercept = svm_check_intercept,
7113 .handle_external_intr = svm_handle_external_intr,
7115 .sched_in = svm_sched_in,
7117 .pmu_ops = &amd_pmu_ops,
7118 .deliver_posted_interrupt = svm_deliver_avic_intr,
7119 .update_pi_irte = svm_update_pi_irte,
7120 .setup_mce = svm_setup_mce,
7122 .smi_allowed = svm_smi_allowed,
7123 .pre_enter_smm = svm_pre_enter_smm,
7124 .pre_leave_smm = svm_pre_leave_smm,
7125 .enable_smi_window = enable_smi_window,
7127 .mem_enc_op = svm_mem_enc_op,
7128 .mem_enc_reg_region = svm_register_enc_region,
7129 .mem_enc_unreg_region = svm_unregister_enc_region,
7132 static int __init svm_init(void)
7134 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
7135 __alignof__(struct vcpu_svm), THIS_MODULE);
7138 static void __exit svm_exit(void)
7143 module_init(svm_init)
7144 module_exit(svm_exit)