1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine -- Performance Monitoring Unit support
5 * Copyright 2015 Red Hat, Inc. and/or its affiliates.
8 * Avi Kivity <avi@redhat.com>
9 * Gleb Natapov <gleb@redhat.com>
10 * Wei Huang <wei@redhat.com>
13 #include <linux/types.h>
14 #include <linux/kvm_host.h>
15 #include <linux/perf_event.h>
16 #include <linux/bsearch.h>
17 #include <linux/sort.h>
18 #include <asm/perf_event.h>
24 /* This is enough to filter the vast majority of currently defined events. */
25 #define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300
28 * - Each perf counter is defined as "struct kvm_pmc";
29 * - There are two types of perf counters: general purpose (gp) and fixed.
30 * gp counters are stored in gp_counters[] and fixed counters are stored
31 * in fixed_counters[] respectively. Both of them are part of "struct
33 * - pmu.c understands the difference between gp counters and fixed counters.
34 * However AMD doesn't support fixed-counters;
35 * - There are three types of index to access perf counters (PMC):
36 * 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
37 * has MSR_K7_PERFCTRn.
38 * 2. MSR Index (named idx): This normally is used by RDPMC instruction.
39 * For instance AMD RDPMC instruction uses 0000_0003h in ECX to access
40 * C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
41 * that it also supports fixed counters. idx can be used to as index to
42 * gp and fixed counters.
43 * 3. Global PMC Index (named pmc): pmc is an index specific to PMU
44 * code. Each pmc, stored in kvm_pmc.idx field, is unique across
45 * all perf counters (both gp and fixed). The mapping relationship
46 * between pmc and perf counters is as the following:
47 * * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
48 * [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
49 * * AMD: [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters
52 static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
54 struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
55 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
57 kvm_pmu_deliver_pmi(vcpu);
60 static inline void __kvm_perf_overflow(struct kvm_pmc *pmc, bool in_pmi)
62 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
64 /* Ignore counters that have been reprogrammed already. */
65 if (test_and_set_bit(pmc->idx, pmu->reprogram_pmi))
68 __set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
69 kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
75 * Inject PMI. If vcpu was in a guest mode during NMI PMI
76 * can be ejected on a guest mode re-entry. Otherwise we can't
77 * be sure that vcpu wasn't executing hlt instruction at the
78 * time of vmexit and is not going to re-enter guest mode until
79 * woken up. So we should wake it, but this is impossible from
80 * NMI context. Do it from irq work instead.
82 if (in_pmi && !kvm_handling_nmi_from_guest(pmc->vcpu))
83 irq_work_queue(&pmc_to_pmu(pmc)->irq_work);
85 kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
88 static void kvm_perf_overflow(struct perf_event *perf_event,
89 struct perf_sample_data *data,
92 struct kvm_pmc *pmc = perf_event->overflow_handler_context;
94 __kvm_perf_overflow(pmc, true);
97 static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
98 u64 config, bool exclude_user,
99 bool exclude_kernel, bool intr,
100 bool in_tx, bool in_tx_cp)
102 struct perf_event *event;
103 struct perf_event_attr attr = {
105 .size = sizeof(attr),
107 .exclude_idle = true,
109 .exclude_user = exclude_user,
110 .exclude_kernel = exclude_kernel,
114 if (type == PERF_TYPE_HARDWARE && config >= PERF_COUNT_HW_MAX)
117 attr.sample_period = get_sample_period(pmc, pmc->counter);
120 attr.config |= HSW_IN_TX;
123 * HSW_IN_TX_CHECKPOINTED is not supported with nonzero
124 * period. Just clear the sample period so at least
125 * allocating the counter doesn't fail.
127 attr.sample_period = 0;
128 attr.config |= HSW_IN_TX_CHECKPOINTED;
131 event = perf_event_create_kernel_counter(&attr, -1, current,
132 kvm_perf_overflow, pmc);
134 pr_debug_ratelimited("kvm_pmu: event creation failed %ld for pmc->idx = %d\n",
135 PTR_ERR(event), pmc->idx);
139 pmc->perf_event = event;
140 pmc_to_pmu(pmc)->event_count++;
141 clear_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
142 pmc->is_paused = false;
146 static void pmc_pause_counter(struct kvm_pmc *pmc)
148 u64 counter = pmc->counter;
150 if (!pmc->perf_event || pmc->is_paused)
153 /* update counter, reset event value to avoid redundant accumulation */
154 counter += perf_event_pause(pmc->perf_event, true);
155 pmc->counter = counter & pmc_bitmask(pmc);
156 pmc->is_paused = true;
159 static bool pmc_resume_counter(struct kvm_pmc *pmc)
161 if (!pmc->perf_event)
164 /* recalibrate sample period and check if it's accepted by perf core */
165 if (perf_event_period(pmc->perf_event,
166 get_sample_period(pmc, pmc->counter)))
169 /* reuse perf_event to serve as pmc_reprogram_counter() does*/
170 perf_event_enable(pmc->perf_event);
171 pmc->is_paused = false;
173 clear_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->reprogram_pmi);
177 static int cmp_u64(const void *a, const void *b)
179 return *(__u64 *)a - *(__u64 *)b;
182 void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
185 u32 type = PERF_TYPE_RAW;
186 struct kvm *kvm = pmc->vcpu->kvm;
187 struct kvm_pmu_event_filter *filter;
188 bool allow_event = true;
190 if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
191 printk_once("kvm pmu: pin control bit is ignored\n");
193 pmc->eventsel = eventsel;
195 pmc_pause_counter(pmc);
197 if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc))
200 filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
202 __u64 key = eventsel & AMD64_RAW_EVENT_MASK_NB;
204 if (bsearch(&key, filter->events, filter->nevents,
205 sizeof(__u64), cmp_u64))
206 allow_event = filter->action == KVM_PMU_EVENT_ALLOW;
208 allow_event = filter->action == KVM_PMU_EVENT_DENY;
213 if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
214 ARCH_PERFMON_EVENTSEL_INV |
215 ARCH_PERFMON_EVENTSEL_CMASK |
217 HSW_IN_TX_CHECKPOINTED))) {
218 config = kvm_x86_ops.pmu_ops->pmc_perf_hw_id(pmc);
219 if (config != PERF_COUNT_HW_MAX)
220 type = PERF_TYPE_HARDWARE;
223 if (type == PERF_TYPE_RAW)
224 config = eventsel & AMD64_RAW_EVENT_MASK;
226 if (pmc->current_config == eventsel && pmc_resume_counter(pmc))
229 pmc_release_perf_event(pmc);
231 pmc->current_config = eventsel;
232 pmc_reprogram_counter(pmc, type, config,
233 !(eventsel & ARCH_PERFMON_EVENTSEL_USR),
234 !(eventsel & ARCH_PERFMON_EVENTSEL_OS),
235 eventsel & ARCH_PERFMON_EVENTSEL_INT,
236 (eventsel & HSW_IN_TX),
237 (eventsel & HSW_IN_TX_CHECKPOINTED));
239 EXPORT_SYMBOL_GPL(reprogram_gp_counter);
241 void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
243 unsigned en_field = ctrl & 0x3;
244 bool pmi = ctrl & 0x8;
245 struct kvm_pmu_event_filter *filter;
246 struct kvm *kvm = pmc->vcpu->kvm;
248 pmc_pause_counter(pmc);
250 if (!en_field || !pmc_is_enabled(pmc))
253 filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
255 if (filter->action == KVM_PMU_EVENT_DENY &&
256 test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
258 if (filter->action == KVM_PMU_EVENT_ALLOW &&
259 !test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
263 if (pmc->current_config == (u64)ctrl && pmc_resume_counter(pmc))
266 pmc_release_perf_event(pmc);
268 pmc->current_config = (u64)ctrl;
269 pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
270 kvm_x86_ops.pmu_ops->pmc_perf_hw_id(pmc),
271 !(en_field & 0x2), /* exclude user */
272 !(en_field & 0x1), /* exclude kernel */
275 EXPORT_SYMBOL_GPL(reprogram_fixed_counter);
277 void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
279 struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, pmc_idx);
285 reprogram_gp_counter(pmc, pmc->eventsel);
287 int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
288 u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);
290 reprogram_fixed_counter(pmc, ctrl, idx);
293 EXPORT_SYMBOL_GPL(reprogram_counter);
295 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
297 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
300 for_each_set_bit(bit, pmu->reprogram_pmi, X86_PMC_IDX_MAX) {
301 struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, bit);
303 if (unlikely(!pmc || !pmc->perf_event)) {
304 clear_bit(bit, pmu->reprogram_pmi);
308 reprogram_counter(pmu, bit);
312 * Unused perf_events are only released if the corresponding MSRs
313 * weren't accessed during the last vCPU time slice. kvm_arch_sched_in
314 * triggers KVM_REQ_PMU if cleanup is needed.
316 if (unlikely(pmu->need_cleanup))
317 kvm_pmu_cleanup(vcpu);
320 /* check if idx is a valid index to access PMU */
321 bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
323 return kvm_x86_ops.pmu_ops->is_valid_rdpmc_ecx(vcpu, idx);
326 bool is_vmware_backdoor_pmc(u32 pmc_idx)
329 case VMWARE_BACKDOOR_PMC_HOST_TSC:
330 case VMWARE_BACKDOOR_PMC_REAL_TIME:
331 case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
337 static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
342 case VMWARE_BACKDOOR_PMC_HOST_TSC:
345 case VMWARE_BACKDOOR_PMC_REAL_TIME:
346 ctr_val = ktime_get_boottime_ns();
348 case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
349 ctr_val = ktime_get_boottime_ns() +
350 vcpu->kvm->arch.kvmclock_offset;
360 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
362 bool fast_mode = idx & (1u << 31);
363 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
365 u64 mask = fast_mode ? ~0u : ~0ull;
370 if (is_vmware_backdoor_pmc(idx))
371 return kvm_pmu_rdpmc_vmware(vcpu, idx, data);
373 pmc = kvm_x86_ops.pmu_ops->rdpmc_ecx_to_pmc(vcpu, idx, &mask);
377 if (!(kvm_read_cr4(vcpu) & X86_CR4_PCE) &&
378 (static_call(kvm_x86_get_cpl)(vcpu) != 0) &&
379 (kvm_read_cr0(vcpu) & X86_CR0_PE))
382 *data = pmc_read_counter(pmc) & mask;
386 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
388 if (lapic_in_kernel(vcpu)) {
389 if (kvm_x86_ops.pmu_ops->deliver_pmi)
390 kvm_x86_ops.pmu_ops->deliver_pmi(vcpu);
391 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
395 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
397 return kvm_x86_ops.pmu_ops->msr_idx_to_pmc(vcpu, msr) ||
398 kvm_x86_ops.pmu_ops->is_valid_msr(vcpu, msr);
401 static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr)
403 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
404 struct kvm_pmc *pmc = kvm_x86_ops.pmu_ops->msr_idx_to_pmc(vcpu, msr);
407 __set_bit(pmc->idx, pmu->pmc_in_use);
410 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
412 return kvm_x86_ops.pmu_ops->get_msr(vcpu, msr_info);
415 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
417 kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
418 return kvm_x86_ops.pmu_ops->set_msr(vcpu, msr_info);
421 /* refresh PMU settings. This function generally is called when underlying
422 * settings are changed (such as changes of PMU CPUID by guest VMs), which
423 * should rarely happen.
425 void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
427 kvm_x86_ops.pmu_ops->refresh(vcpu);
430 void kvm_pmu_reset(struct kvm_vcpu *vcpu)
432 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
434 irq_work_sync(&pmu->irq_work);
435 kvm_x86_ops.pmu_ops->reset(vcpu);
438 void kvm_pmu_init(struct kvm_vcpu *vcpu)
440 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
442 memset(pmu, 0, sizeof(*pmu));
443 kvm_x86_ops.pmu_ops->init(vcpu);
444 init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn);
445 pmu->event_count = 0;
446 pmu->need_cleanup = false;
447 kvm_pmu_refresh(vcpu);
450 static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
452 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
454 if (pmc_is_fixed(pmc))
455 return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
456 pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
458 return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
461 /* Release perf_events for vPMCs that have been unused for a full time slice. */
462 void kvm_pmu_cleanup(struct kvm_vcpu *vcpu)
464 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
465 struct kvm_pmc *pmc = NULL;
466 DECLARE_BITMAP(bitmask, X86_PMC_IDX_MAX);
469 pmu->need_cleanup = false;
471 bitmap_andnot(bitmask, pmu->all_valid_pmc_idx,
472 pmu->pmc_in_use, X86_PMC_IDX_MAX);
474 for_each_set_bit(i, bitmask, X86_PMC_IDX_MAX) {
475 pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, i);
477 if (pmc && pmc->perf_event && !pmc_speculative_in_use(pmc))
478 pmc_stop_counter(pmc);
481 if (kvm_x86_ops.pmu_ops->cleanup)
482 kvm_x86_ops.pmu_ops->cleanup(vcpu);
484 bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX);
487 void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
492 static void kvm_pmu_incr_counter(struct kvm_pmc *pmc)
494 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
497 prev_count = pmc->counter;
498 pmc->counter = (pmc->counter + 1) & pmc_bitmask(pmc);
500 reprogram_counter(pmu, pmc->idx);
501 if (pmc->counter < prev_count)
502 __kvm_perf_overflow(pmc, false);
505 static inline bool eventsel_match_perf_hw_id(struct kvm_pmc *pmc,
506 unsigned int perf_hw_id)
508 u64 old_eventsel = pmc->eventsel;
511 pmc->eventsel &= (ARCH_PERFMON_EVENTSEL_EVENT | ARCH_PERFMON_EVENTSEL_UMASK);
512 config = kvm_x86_ops.pmu_ops->pmc_perf_hw_id(pmc);
513 pmc->eventsel = old_eventsel;
514 return config == perf_hw_id;
517 static inline bool cpl_is_matched(struct kvm_pmc *pmc)
519 bool select_os, select_user;
520 u64 config = pmc->current_config;
522 if (pmc_is_gp(pmc)) {
523 select_os = config & ARCH_PERFMON_EVENTSEL_OS;
524 select_user = config & ARCH_PERFMON_EVENTSEL_USR;
526 select_os = config & 0x1;
527 select_user = config & 0x2;
530 return (static_call(kvm_x86_get_cpl)(pmc->vcpu) == 0) ? select_os : select_user;
533 void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id)
535 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
539 for_each_set_bit(i, pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX) {
540 pmc = kvm_x86_ops.pmu_ops->pmc_idx_to_pmc(pmu, i);
542 if (!pmc || !pmc_is_enabled(pmc) || !pmc_speculative_in_use(pmc))
545 /* Ignore checks for edge detect, pin control, invert and CMASK bits */
546 if (eventsel_match_perf_hw_id(pmc, perf_hw_id) && cpl_is_matched(pmc))
547 kvm_pmu_incr_counter(pmc);
550 EXPORT_SYMBOL_GPL(kvm_pmu_trigger_event);
552 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp)
554 struct kvm_pmu_event_filter tmp, *filter;
558 if (copy_from_user(&tmp, argp, sizeof(tmp)))
561 if (tmp.action != KVM_PMU_EVENT_ALLOW &&
562 tmp.action != KVM_PMU_EVENT_DENY)
568 if (tmp.nevents > KVM_PMU_EVENT_FILTER_MAX_EVENTS)
571 size = struct_size(filter, events, tmp.nevents);
572 filter = kmalloc(size, GFP_KERNEL_ACCOUNT);
577 if (copy_from_user(filter, argp, size))
580 /* Ensure nevents can't be changed between the user copies. */
584 * Sort the in-kernel list so that we can search it with bsearch.
586 sort(&filter->events, filter->nevents, sizeof(__u64), cmp_u64, NULL);
588 mutex_lock(&kvm->lock);
589 filter = rcu_replace_pointer(kvm->arch.pmu_event_filter, filter,
590 mutex_is_locked(&kvm->lock));
591 mutex_unlock(&kvm->lock);
593 synchronize_srcu_expedited(&kvm->srcu);