1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
52 #include <asm/kvm_page_track.h>
55 extern bool itlb_multihit_kvm_mitigation;
57 static int __read_mostly nx_huge_pages = -1;
58 #ifdef CONFIG_PREEMPT_RT
59 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
60 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
62 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
65 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
66 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops nx_huge_pages_ops = {
69 .set = set_nx_huge_pages,
70 .get = param_get_bool,
73 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
74 .set = set_nx_huge_pages_recovery_ratio,
75 .get = param_get_uint,
78 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
79 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
80 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
81 &nx_huge_pages_recovery_ratio, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
84 static bool __read_mostly force_flush_and_sync_on_reuse;
85 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
88 * When setting this variable to true it enables Two-Dimensional-Paging
89 * where the hardware walks 2 page tables:
90 * 1. the guest-virtual to guest-physical
91 * 2. while doing 1. it walks guest-physical to host-physical
92 * If the hardware supports that we don't need to do shadow paging.
94 bool tdp_enabled = false;
96 static int max_huge_page_level __read_mostly;
97 static int max_tdp_level __read_mostly;
100 AUDIT_PRE_PAGE_FAULT,
101 AUDIT_POST_PAGE_FAULT,
103 AUDIT_POST_PTE_WRITE,
110 module_param(dbg, bool, 0644);
113 #define PTE_PREFETCH_NUM 8
115 #define PT32_LEVEL_BITS 10
117 #define PT32_LEVEL_SHIFT(level) \
118 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
120 #define PT32_LVL_OFFSET_MASK(level) \
121 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
122 * PT32_LEVEL_BITS))) - 1))
124 #define PT32_INDEX(address, level)\
125 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #include <trace/events/kvm.h>
137 /* make pte_list_desc fit well in cache line */
138 #define PTE_LIST_EXT 3
140 struct pte_list_desc {
141 u64 *sptes[PTE_LIST_EXT];
142 struct pte_list_desc *more;
145 struct kvm_shadow_walk_iterator {
153 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
154 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
156 shadow_walk_okay(&(_walker)); \
157 shadow_walk_next(&(_walker)))
159 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
160 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
161 shadow_walk_okay(&(_walker)); \
162 shadow_walk_next(&(_walker)))
164 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
165 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
166 shadow_walk_okay(&(_walker)) && \
167 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
168 __shadow_walk_next(&(_walker), spte))
170 static struct kmem_cache *pte_list_desc_cache;
171 struct kmem_cache *mmu_page_header_cache;
172 static struct percpu_counter kvm_total_used_mmu_pages;
174 static void mmu_spte_set(u64 *sptep, u64 spte);
175 static union kvm_mmu_page_role
176 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
178 #define CREATE_TRACE_POINTS
179 #include "mmutrace.h"
182 static inline bool kvm_available_flush_tlb_with_range(void)
184 return kvm_x86_ops.tlb_remote_flush_with_range;
187 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
188 struct kvm_tlb_range *range)
192 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
193 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
196 kvm_flush_remote_tlbs(kvm);
199 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
200 u64 start_gfn, u64 pages)
202 struct kvm_tlb_range range;
204 range.start_gfn = start_gfn;
207 kvm_flush_remote_tlbs_with_range(kvm, &range);
210 bool is_nx_huge_page_enabled(void)
212 return READ_ONCE(nx_huge_pages);
215 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
218 u64 mask = make_mmio_spte(vcpu, gfn, access);
220 trace_mark_mmio_spte(sptep, gfn, mask);
221 mmu_spte_set(sptep, mask);
224 static gfn_t get_mmio_spte_gfn(u64 spte)
226 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
228 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
229 & shadow_nonpresent_or_rsvd_mask;
231 return gpa >> PAGE_SHIFT;
234 static unsigned get_mmio_spte_access(u64 spte)
236 return spte & shadow_mmio_access_mask;
239 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
240 kvm_pfn_t pfn, unsigned int access)
242 if (unlikely(is_noslot_pfn(pfn))) {
243 mark_mmio_spte(vcpu, sptep, gfn, access);
250 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
252 u64 kvm_gen, spte_gen, gen;
254 gen = kvm_vcpu_memslots(vcpu)->generation;
255 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
258 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
259 spte_gen = get_mmio_spte_generation(spte);
261 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
262 return likely(kvm_gen == spte_gen);
265 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
266 struct x86_exception *exception)
268 /* Check if guest physical address doesn't exceed guest maximum */
269 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
270 exception->error_code |= PFERR_RSVD_MASK;
277 static int is_cpuid_PSE36(void)
282 static int is_nx(struct kvm_vcpu *vcpu)
284 return vcpu->arch.efer & EFER_NX;
287 static gfn_t pse36_gfn_delta(u32 gpte)
289 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
291 return (gpte & PT32_DIR_PSE36_MASK) << shift;
295 static void __set_spte(u64 *sptep, u64 spte)
297 WRITE_ONCE(*sptep, spte);
300 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
302 WRITE_ONCE(*sptep, spte);
305 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
307 return xchg(sptep, spte);
310 static u64 __get_spte_lockless(u64 *sptep)
312 return READ_ONCE(*sptep);
323 static void count_spte_clear(u64 *sptep, u64 spte)
325 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
327 if (is_shadow_present_pte(spte))
330 /* Ensure the spte is completely set before we increase the count */
332 sp->clear_spte_count++;
335 static void __set_spte(u64 *sptep, u64 spte)
337 union split_spte *ssptep, sspte;
339 ssptep = (union split_spte *)sptep;
340 sspte = (union split_spte)spte;
342 ssptep->spte_high = sspte.spte_high;
345 * If we map the spte from nonpresent to present, We should store
346 * the high bits firstly, then set present bit, so cpu can not
347 * fetch this spte while we are setting the spte.
351 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
354 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
356 union split_spte *ssptep, sspte;
358 ssptep = (union split_spte *)sptep;
359 sspte = (union split_spte)spte;
361 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
364 * If we map the spte from present to nonpresent, we should clear
365 * present bit firstly to avoid vcpu fetch the old high bits.
369 ssptep->spte_high = sspte.spte_high;
370 count_spte_clear(sptep, spte);
373 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
375 union split_spte *ssptep, sspte, orig;
377 ssptep = (union split_spte *)sptep;
378 sspte = (union split_spte)spte;
380 /* xchg acts as a barrier before the setting of the high bits */
381 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
382 orig.spte_high = ssptep->spte_high;
383 ssptep->spte_high = sspte.spte_high;
384 count_spte_clear(sptep, spte);
390 * The idea using the light way get the spte on x86_32 guest is from
391 * gup_get_pte (mm/gup.c).
393 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
394 * coalesces them and we are running out of the MMU lock. Therefore
395 * we need to protect against in-progress updates of the spte.
397 * Reading the spte while an update is in progress may get the old value
398 * for the high part of the spte. The race is fine for a present->non-present
399 * change (because the high part of the spte is ignored for non-present spte),
400 * but for a present->present change we must reread the spte.
402 * All such changes are done in two steps (present->non-present and
403 * non-present->present), hence it is enough to count the number of
404 * present->non-present updates: if it changed while reading the spte,
405 * we might have hit the race. This is done using clear_spte_count.
407 static u64 __get_spte_lockless(u64 *sptep)
409 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
410 union split_spte spte, *orig = (union split_spte *)sptep;
414 count = sp->clear_spte_count;
417 spte.spte_low = orig->spte_low;
420 spte.spte_high = orig->spte_high;
423 if (unlikely(spte.spte_low != orig->spte_low ||
424 count != sp->clear_spte_count))
431 static bool spte_has_volatile_bits(u64 spte)
433 if (!is_shadow_present_pte(spte))
437 * Always atomically update spte if it can be updated
438 * out of mmu-lock, it can ensure dirty bit is not lost,
439 * also, it can help us to get a stable is_writable_pte()
440 * to ensure tlb flush is not missed.
442 if (spte_can_locklessly_be_made_writable(spte) ||
443 is_access_track_spte(spte))
446 if (spte_ad_enabled(spte)) {
447 if ((spte & shadow_accessed_mask) == 0 ||
448 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
455 /* Rules for using mmu_spte_set:
456 * Set the sptep from nonpresent to present.
457 * Note: the sptep being assigned *must* be either not present
458 * or in a state where the hardware will not attempt to update
461 static void mmu_spte_set(u64 *sptep, u64 new_spte)
463 WARN_ON(is_shadow_present_pte(*sptep));
464 __set_spte(sptep, new_spte);
468 * Update the SPTE (excluding the PFN), but do not track changes in its
469 * accessed/dirty status.
471 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
473 u64 old_spte = *sptep;
475 WARN_ON(!is_shadow_present_pte(new_spte));
477 if (!is_shadow_present_pte(old_spte)) {
478 mmu_spte_set(sptep, new_spte);
482 if (!spte_has_volatile_bits(old_spte))
483 __update_clear_spte_fast(sptep, new_spte);
485 old_spte = __update_clear_spte_slow(sptep, new_spte);
487 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
492 /* Rules for using mmu_spte_update:
493 * Update the state bits, it means the mapped pfn is not changed.
495 * Whenever we overwrite a writable spte with a read-only one we
496 * should flush remote TLBs. Otherwise rmap_write_protect
497 * will find a read-only spte, even though the writable spte
498 * might be cached on a CPU's TLB, the return value indicates this
501 * Returns true if the TLB needs to be flushed
503 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
506 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
508 if (!is_shadow_present_pte(old_spte))
512 * For the spte updated out of mmu-lock is safe, since
513 * we always atomically update it, see the comments in
514 * spte_has_volatile_bits().
516 if (spte_can_locklessly_be_made_writable(old_spte) &&
517 !is_writable_pte(new_spte))
521 * Flush TLB when accessed/dirty states are changed in the page tables,
522 * to guarantee consistency between TLB and page tables.
525 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
527 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
530 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
532 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
539 * Rules for using mmu_spte_clear_track_bits:
540 * It sets the sptep from present to nonpresent, and track the
541 * state bits, it is used to clear the last level sptep.
542 * Returns non-zero if the PTE was previously valid.
544 static int mmu_spte_clear_track_bits(u64 *sptep)
547 u64 old_spte = *sptep;
549 if (!spte_has_volatile_bits(old_spte))
550 __update_clear_spte_fast(sptep, 0ull);
552 old_spte = __update_clear_spte_slow(sptep, 0ull);
554 if (!is_shadow_present_pte(old_spte))
557 pfn = spte_to_pfn(old_spte);
560 * KVM does not hold the refcount of the page used by
561 * kvm mmu, before reclaiming the page, we should
562 * unmap it from mmu first.
564 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
566 if (is_accessed_spte(old_spte))
567 kvm_set_pfn_accessed(pfn);
569 if (is_dirty_spte(old_spte))
570 kvm_set_pfn_dirty(pfn);
576 * Rules for using mmu_spte_clear_no_track:
577 * Directly clear spte without caring the state bits of sptep,
578 * it is used to set the upper level spte.
580 static void mmu_spte_clear_no_track(u64 *sptep)
582 __update_clear_spte_fast(sptep, 0ull);
585 static u64 mmu_spte_get_lockless(u64 *sptep)
587 return __get_spte_lockless(sptep);
590 /* Restore an acc-track PTE back to a regular PTE */
591 static u64 restore_acc_track_spte(u64 spte)
594 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
595 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
597 WARN_ON_ONCE(spte_ad_enabled(spte));
598 WARN_ON_ONCE(!is_access_track_spte(spte));
600 new_spte &= ~shadow_acc_track_mask;
601 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
602 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
603 new_spte |= saved_bits;
608 /* Returns the Accessed status of the PTE and resets it at the same time. */
609 static bool mmu_spte_age(u64 *sptep)
611 u64 spte = mmu_spte_get_lockless(sptep);
613 if (!is_accessed_spte(spte))
616 if (spte_ad_enabled(spte)) {
617 clear_bit((ffs(shadow_accessed_mask) - 1),
618 (unsigned long *)sptep);
621 * Capture the dirty status of the page, so that it doesn't get
622 * lost when the SPTE is marked for access tracking.
624 if (is_writable_pte(spte))
625 kvm_set_pfn_dirty(spte_to_pfn(spte));
627 spte = mark_spte_for_access_track(spte);
628 mmu_spte_update_no_track(sptep, spte);
634 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
637 * Prevent page table teardown by making any free-er wait during
638 * kvm_flush_remote_tlbs() IPI to all active vcpus.
643 * Make sure a following spte read is not reordered ahead of the write
646 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
649 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
652 * Make sure the write to vcpu->mode is not reordered in front of
653 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
654 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
656 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
660 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
664 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
665 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
666 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
669 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
670 PT64_ROOT_MAX_LEVEL);
673 if (maybe_indirect) {
674 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
675 PT64_ROOT_MAX_LEVEL);
679 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
680 PT64_ROOT_MAX_LEVEL);
683 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
685 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
686 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
687 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
688 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
691 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
693 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
696 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
698 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
701 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
703 if (!sp->role.direct)
704 return sp->gfns[index];
706 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
709 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
711 if (!sp->role.direct) {
712 sp->gfns[index] = gfn;
716 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
717 pr_err_ratelimited("gfn mismatch under direct page %llx "
718 "(expected %llx, got %llx)\n",
720 kvm_mmu_page_get_gfn(sp, index), gfn);
724 * Return the pointer to the large page information for a given gfn,
725 * handling slots that are not large page aligned.
727 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
728 struct kvm_memory_slot *slot,
733 idx = gfn_to_index(gfn, slot->base_gfn, level);
734 return &slot->arch.lpage_info[level - 2][idx];
737 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
738 gfn_t gfn, int count)
740 struct kvm_lpage_info *linfo;
743 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
744 linfo = lpage_info_slot(gfn, slot, i);
745 linfo->disallow_lpage += count;
746 WARN_ON(linfo->disallow_lpage < 0);
750 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
752 update_gfn_disallow_lpage_count(slot, gfn, 1);
755 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
757 update_gfn_disallow_lpage_count(slot, gfn, -1);
760 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
762 struct kvm_memslots *slots;
763 struct kvm_memory_slot *slot;
766 kvm->arch.indirect_shadow_pages++;
768 slots = kvm_memslots_for_spte_role(kvm, sp->role);
769 slot = __gfn_to_memslot(slots, gfn);
771 /* the non-leaf shadow pages are keeping readonly. */
772 if (sp->role.level > PG_LEVEL_4K)
773 return kvm_slot_page_track_add_page(kvm, slot, gfn,
774 KVM_PAGE_TRACK_WRITE);
776 kvm_mmu_gfn_disallow_lpage(slot, gfn);
779 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
781 if (sp->lpage_disallowed)
784 ++kvm->stat.nx_lpage_splits;
785 list_add_tail(&sp->lpage_disallowed_link,
786 &kvm->arch.lpage_disallowed_mmu_pages);
787 sp->lpage_disallowed = true;
790 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
792 struct kvm_memslots *slots;
793 struct kvm_memory_slot *slot;
796 kvm->arch.indirect_shadow_pages--;
798 slots = kvm_memslots_for_spte_role(kvm, sp->role);
799 slot = __gfn_to_memslot(slots, gfn);
800 if (sp->role.level > PG_LEVEL_4K)
801 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
802 KVM_PAGE_TRACK_WRITE);
804 kvm_mmu_gfn_allow_lpage(slot, gfn);
807 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
809 --kvm->stat.nx_lpage_splits;
810 sp->lpage_disallowed = false;
811 list_del(&sp->lpage_disallowed_link);
814 static struct kvm_memory_slot *
815 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
818 struct kvm_memory_slot *slot;
820 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
821 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
823 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
830 * About rmap_head encoding:
832 * If the bit zero of rmap_head->val is clear, then it points to the only spte
833 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
834 * pte_list_desc containing more mappings.
838 * Returns the number of pointers in the rmap chain, not counting the new one.
840 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
841 struct kvm_rmap_head *rmap_head)
843 struct pte_list_desc *desc;
846 if (!rmap_head->val) {
847 rmap_printk("%p %llx 0->1\n", spte, *spte);
848 rmap_head->val = (unsigned long)spte;
849 } else if (!(rmap_head->val & 1)) {
850 rmap_printk("%p %llx 1->many\n", spte, *spte);
851 desc = mmu_alloc_pte_list_desc(vcpu);
852 desc->sptes[0] = (u64 *)rmap_head->val;
853 desc->sptes[1] = spte;
854 rmap_head->val = (unsigned long)desc | 1;
857 rmap_printk("%p %llx many->many\n", spte, *spte);
858 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
859 while (desc->sptes[PTE_LIST_EXT-1]) {
860 count += PTE_LIST_EXT;
863 desc->more = mmu_alloc_pte_list_desc(vcpu);
869 for (i = 0; desc->sptes[i]; ++i)
871 desc->sptes[i] = spte;
877 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
878 struct pte_list_desc *desc, int i,
879 struct pte_list_desc *prev_desc)
883 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
885 desc->sptes[i] = desc->sptes[j];
886 desc->sptes[j] = NULL;
889 if (!prev_desc && !desc->more)
893 prev_desc->more = desc->more;
895 rmap_head->val = (unsigned long)desc->more | 1;
896 mmu_free_pte_list_desc(desc);
899 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
901 struct pte_list_desc *desc;
902 struct pte_list_desc *prev_desc;
905 if (!rmap_head->val) {
906 pr_err("%s: %p 0->BUG\n", __func__, spte);
908 } else if (!(rmap_head->val & 1)) {
909 rmap_printk("%p 1->0\n", spte);
910 if ((u64 *)rmap_head->val != spte) {
911 pr_err("%s: %p 1->BUG\n", __func__, spte);
916 rmap_printk("%p many->many\n", spte);
917 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
920 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
921 if (desc->sptes[i] == spte) {
922 pte_list_desc_remove_entry(rmap_head,
930 pr_err("%s: %p many->many\n", __func__, spte);
935 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
937 mmu_spte_clear_track_bits(sptep);
938 __pte_list_remove(sptep, rmap_head);
941 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
942 struct kvm_memory_slot *slot)
946 idx = gfn_to_index(gfn, slot->base_gfn, level);
947 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
950 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
951 struct kvm_mmu_page *sp)
953 struct kvm_memslots *slots;
954 struct kvm_memory_slot *slot;
956 slots = kvm_memslots_for_spte_role(kvm, sp->role);
957 slot = __gfn_to_memslot(slots, gfn);
958 return __gfn_to_rmap(gfn, sp->role.level, slot);
961 static bool rmap_can_add(struct kvm_vcpu *vcpu)
963 struct kvm_mmu_memory_cache *mc;
965 mc = &vcpu->arch.mmu_pte_list_desc_cache;
966 return kvm_mmu_memory_cache_nr_free_objects(mc);
969 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
971 struct kvm_mmu_page *sp;
972 struct kvm_rmap_head *rmap_head;
974 sp = sptep_to_sp(spte);
975 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
976 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
977 return pte_list_add(vcpu, spte, rmap_head);
980 static void rmap_remove(struct kvm *kvm, u64 *spte)
982 struct kvm_mmu_page *sp;
984 struct kvm_rmap_head *rmap_head;
986 sp = sptep_to_sp(spte);
987 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
988 rmap_head = gfn_to_rmap(kvm, gfn, sp);
989 __pte_list_remove(spte, rmap_head);
993 * Used by the following functions to iterate through the sptes linked by a
994 * rmap. All fields are private and not assumed to be used outside.
996 struct rmap_iterator {
998 struct pte_list_desc *desc; /* holds the sptep if not NULL */
999 int pos; /* index of the sptep */
1003 * Iteration must be started by this function. This should also be used after
1004 * removing/dropping sptes from the rmap link because in such cases the
1005 * information in the iterator may not be valid.
1007 * Returns sptep if found, NULL otherwise.
1009 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1010 struct rmap_iterator *iter)
1014 if (!rmap_head->val)
1017 if (!(rmap_head->val & 1)) {
1019 sptep = (u64 *)rmap_head->val;
1023 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1025 sptep = iter->desc->sptes[iter->pos];
1027 BUG_ON(!is_shadow_present_pte(*sptep));
1032 * Must be used with a valid iterator: e.g. after rmap_get_first().
1034 * Returns sptep if found, NULL otherwise.
1036 static u64 *rmap_get_next(struct rmap_iterator *iter)
1041 if (iter->pos < PTE_LIST_EXT - 1) {
1043 sptep = iter->desc->sptes[iter->pos];
1048 iter->desc = iter->desc->more;
1052 /* desc->sptes[0] cannot be NULL */
1053 sptep = iter->desc->sptes[iter->pos];
1060 BUG_ON(!is_shadow_present_pte(*sptep));
1064 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1065 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1066 _spte_; _spte_ = rmap_get_next(_iter_))
1068 static void drop_spte(struct kvm *kvm, u64 *sptep)
1070 if (mmu_spte_clear_track_bits(sptep))
1071 rmap_remove(kvm, sptep);
1075 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1077 if (is_large_pte(*sptep)) {
1078 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1079 drop_spte(kvm, sptep);
1087 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1089 if (__drop_large_spte(vcpu->kvm, sptep)) {
1090 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1092 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1093 KVM_PAGES_PER_HPAGE(sp->role.level));
1098 * Write-protect on the specified @sptep, @pt_protect indicates whether
1099 * spte write-protection is caused by protecting shadow page table.
1101 * Note: write protection is difference between dirty logging and spte
1103 * - for dirty logging, the spte can be set to writable at anytime if
1104 * its dirty bitmap is properly set.
1105 * - for spte protection, the spte can be writable only after unsync-ing
1108 * Return true if tlb need be flushed.
1110 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1114 if (!is_writable_pte(spte) &&
1115 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1118 rmap_printk("spte %p %llx\n", sptep, *sptep);
1121 spte &= ~SPTE_MMU_WRITEABLE;
1122 spte = spte & ~PT_WRITABLE_MASK;
1124 return mmu_spte_update(sptep, spte);
1127 static bool __rmap_write_protect(struct kvm *kvm,
1128 struct kvm_rmap_head *rmap_head,
1132 struct rmap_iterator iter;
1135 for_each_rmap_spte(rmap_head, &iter, sptep)
1136 flush |= spte_write_protect(sptep, pt_protect);
1141 static bool spte_clear_dirty(u64 *sptep)
1145 rmap_printk("spte %p %llx\n", sptep, *sptep);
1147 MMU_WARN_ON(!spte_ad_enabled(spte));
1148 spte &= ~shadow_dirty_mask;
1149 return mmu_spte_update(sptep, spte);
1152 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1154 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1155 (unsigned long *)sptep);
1156 if (was_writable && !spte_ad_enabled(*sptep))
1157 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1159 return was_writable;
1163 * Gets the GFN ready for another round of dirty logging by clearing the
1164 * - D bit on ad-enabled SPTEs, and
1165 * - W bit on ad-disabled SPTEs.
1166 * Returns true iff any D or W bits were cleared.
1168 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1169 struct kvm_memory_slot *slot)
1172 struct rmap_iterator iter;
1175 for_each_rmap_spte(rmap_head, &iter, sptep)
1176 if (spte_ad_need_write_protect(*sptep))
1177 flush |= spte_wrprot_for_clear_dirty(sptep);
1179 flush |= spte_clear_dirty(sptep);
1185 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1186 * @kvm: kvm instance
1187 * @slot: slot to protect
1188 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1189 * @mask: indicates which pages we should protect
1191 * Used when we do not need to care about huge page mappings: e.g. during dirty
1192 * logging we do not have any such mappings.
1194 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1195 struct kvm_memory_slot *slot,
1196 gfn_t gfn_offset, unsigned long mask)
1198 struct kvm_rmap_head *rmap_head;
1200 if (is_tdp_mmu_enabled(kvm))
1201 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1202 slot->base_gfn + gfn_offset, mask, true);
1204 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1206 __rmap_write_protect(kvm, rmap_head, false);
1208 /* clear the first set bit */
1214 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1215 * protect the page if the D-bit isn't supported.
1216 * @kvm: kvm instance
1217 * @slot: slot to clear D-bit
1218 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1219 * @mask: indicates which pages we should clear D-bit
1221 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1223 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1224 struct kvm_memory_slot *slot,
1225 gfn_t gfn_offset, unsigned long mask)
1227 struct kvm_rmap_head *rmap_head;
1229 if (is_tdp_mmu_enabled(kvm))
1230 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1231 slot->base_gfn + gfn_offset, mask, false);
1233 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1235 __rmap_clear_dirty(kvm, rmap_head, slot);
1237 /* clear the first set bit */
1243 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1246 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1247 * enable dirty logging for them.
1249 * Used when we do not need to care about huge page mappings: e.g. during dirty
1250 * logging we do not have any such mappings.
1252 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1253 struct kvm_memory_slot *slot,
1254 gfn_t gfn_offset, unsigned long mask)
1256 if (kvm_x86_ops.cpu_dirty_log_size)
1257 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1259 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1262 int kvm_cpu_dirty_log_size(void)
1264 return kvm_x86_ops.cpu_dirty_log_size;
1267 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1268 struct kvm_memory_slot *slot, u64 gfn)
1270 struct kvm_rmap_head *rmap_head;
1272 bool write_protected = false;
1274 for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1275 rmap_head = __gfn_to_rmap(gfn, i, slot);
1276 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1279 if (is_tdp_mmu_enabled(kvm))
1281 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn);
1283 return write_protected;
1286 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1288 struct kvm_memory_slot *slot;
1290 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1291 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1294 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1295 struct kvm_memory_slot *slot)
1298 struct rmap_iterator iter;
1301 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1302 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1304 pte_list_remove(rmap_head, sptep);
1311 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1312 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1315 return kvm_zap_rmapp(kvm, rmap_head, slot);
1318 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1319 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1323 struct rmap_iterator iter;
1326 pte_t *ptep = (pte_t *)data;
1329 WARN_ON(pte_huge(*ptep));
1330 new_pfn = pte_pfn(*ptep);
1333 for_each_rmap_spte(rmap_head, &iter, sptep) {
1334 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1335 sptep, *sptep, gfn, level);
1339 if (pte_write(*ptep)) {
1340 pte_list_remove(rmap_head, sptep);
1343 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1346 mmu_spte_clear_track_bits(sptep);
1347 mmu_spte_set(sptep, new_spte);
1351 if (need_flush && kvm_available_flush_tlb_with_range()) {
1352 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1359 struct slot_rmap_walk_iterator {
1361 struct kvm_memory_slot *slot;
1367 /* output fields. */
1369 struct kvm_rmap_head *rmap;
1372 /* private field. */
1373 struct kvm_rmap_head *end_rmap;
1377 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1379 iterator->level = level;
1380 iterator->gfn = iterator->start_gfn;
1381 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1382 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1387 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1388 struct kvm_memory_slot *slot, int start_level,
1389 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1391 iterator->slot = slot;
1392 iterator->start_level = start_level;
1393 iterator->end_level = end_level;
1394 iterator->start_gfn = start_gfn;
1395 iterator->end_gfn = end_gfn;
1397 rmap_walk_init_level(iterator, iterator->start_level);
1400 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1402 return !!iterator->rmap;
1405 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1407 if (++iterator->rmap <= iterator->end_rmap) {
1408 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1412 if (++iterator->level > iterator->end_level) {
1413 iterator->rmap = NULL;
1417 rmap_walk_init_level(iterator, iterator->level);
1420 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1421 _start_gfn, _end_gfn, _iter_) \
1422 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1423 _end_level_, _start_gfn, _end_gfn); \
1424 slot_rmap_walk_okay(_iter_); \
1425 slot_rmap_walk_next(_iter_))
1427 static __always_inline int
1428 kvm_handle_hva_range(struct kvm *kvm,
1429 unsigned long start,
1432 int (*handler)(struct kvm *kvm,
1433 struct kvm_rmap_head *rmap_head,
1434 struct kvm_memory_slot *slot,
1437 unsigned long data))
1439 struct kvm_memslots *slots;
1440 struct kvm_memory_slot *memslot;
1441 struct slot_rmap_walk_iterator iterator;
1445 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1446 slots = __kvm_memslots(kvm, i);
1447 kvm_for_each_memslot(memslot, slots) {
1448 unsigned long hva_start, hva_end;
1449 gfn_t gfn_start, gfn_end;
1451 hva_start = max(start, memslot->userspace_addr);
1452 hva_end = min(end, memslot->userspace_addr +
1453 (memslot->npages << PAGE_SHIFT));
1454 if (hva_start >= hva_end)
1457 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1458 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1460 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1461 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1463 for_each_slot_rmap_range(memslot, PG_LEVEL_4K,
1464 KVM_MAX_HUGEPAGE_LEVEL,
1465 gfn_start, gfn_end - 1,
1467 ret |= handler(kvm, iterator.rmap, memslot,
1468 iterator.gfn, iterator.level, data);
1475 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1477 int (*handler)(struct kvm *kvm,
1478 struct kvm_rmap_head *rmap_head,
1479 struct kvm_memory_slot *slot,
1480 gfn_t gfn, int level,
1481 unsigned long data))
1483 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1486 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
1491 r = kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1493 if (is_tdp_mmu_enabled(kvm))
1494 r |= kvm_tdp_mmu_zap_hva_range(kvm, start, end);
1499 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1503 r = kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1505 if (is_tdp_mmu_enabled(kvm))
1506 r |= kvm_tdp_mmu_set_spte_hva(kvm, hva, &pte);
1511 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1512 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1516 struct rmap_iterator iter;
1519 for_each_rmap_spte(rmap_head, &iter, sptep)
1520 young |= mmu_spte_age(sptep);
1522 trace_kvm_age_page(gfn, level, slot, young);
1526 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1527 struct kvm_memory_slot *slot, gfn_t gfn,
1528 int level, unsigned long data)
1531 struct rmap_iterator iter;
1533 for_each_rmap_spte(rmap_head, &iter, sptep)
1534 if (is_accessed_spte(*sptep))
1539 #define RMAP_RECYCLE_THRESHOLD 1000
1541 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1543 struct kvm_rmap_head *rmap_head;
1544 struct kvm_mmu_page *sp;
1546 sp = sptep_to_sp(spte);
1548 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1550 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1551 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1552 KVM_PAGES_PER_HPAGE(sp->role.level));
1555 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1559 young = kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1560 if (is_tdp_mmu_enabled(kvm))
1561 young |= kvm_tdp_mmu_age_hva_range(kvm, start, end);
1566 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1570 young = kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1571 if (is_tdp_mmu_enabled(kvm))
1572 young |= kvm_tdp_mmu_test_age_hva(kvm, hva);
1578 static int is_empty_shadow_page(u64 *spt)
1583 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1584 if (is_shadow_present_pte(*pos)) {
1585 printk(KERN_ERR "%s: %p %llx\n", __func__,
1594 * This value is the sum of all of the kvm instances's
1595 * kvm->arch.n_used_mmu_pages values. We need a global,
1596 * aggregate version in order to make the slab shrinker
1599 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1601 kvm->arch.n_used_mmu_pages += nr;
1602 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1605 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1607 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1608 hlist_del(&sp->hash_link);
1609 list_del(&sp->link);
1610 free_page((unsigned long)sp->spt);
1611 if (!sp->role.direct)
1612 free_page((unsigned long)sp->gfns);
1613 kmem_cache_free(mmu_page_header_cache, sp);
1616 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1618 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1621 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1622 struct kvm_mmu_page *sp, u64 *parent_pte)
1627 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1630 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1633 __pte_list_remove(parent_pte, &sp->parent_ptes);
1636 static void drop_parent_pte(struct kvm_mmu_page *sp,
1639 mmu_page_remove_parent_pte(sp, parent_pte);
1640 mmu_spte_clear_no_track(parent_pte);
1643 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1645 struct kvm_mmu_page *sp;
1647 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1648 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1650 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1651 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1654 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1655 * depends on valid pages being added to the head of the list. See
1656 * comments in kvm_zap_obsolete_pages().
1658 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1659 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1660 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1664 static void mark_unsync(u64 *spte);
1665 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1668 struct rmap_iterator iter;
1670 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1675 static void mark_unsync(u64 *spte)
1677 struct kvm_mmu_page *sp;
1680 sp = sptep_to_sp(spte);
1681 index = spte - sp->spt;
1682 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1684 if (sp->unsync_children++)
1686 kvm_mmu_mark_parents_unsync(sp);
1689 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1690 struct kvm_mmu_page *sp)
1695 #define KVM_PAGE_ARRAY_NR 16
1697 struct kvm_mmu_pages {
1698 struct mmu_page_and_offset {
1699 struct kvm_mmu_page *sp;
1701 } page[KVM_PAGE_ARRAY_NR];
1705 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1711 for (i=0; i < pvec->nr; i++)
1712 if (pvec->page[i].sp == sp)
1715 pvec->page[pvec->nr].sp = sp;
1716 pvec->page[pvec->nr].idx = idx;
1718 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1721 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1723 --sp->unsync_children;
1724 WARN_ON((int)sp->unsync_children < 0);
1725 __clear_bit(idx, sp->unsync_child_bitmap);
1728 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1729 struct kvm_mmu_pages *pvec)
1731 int i, ret, nr_unsync_leaf = 0;
1733 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1734 struct kvm_mmu_page *child;
1735 u64 ent = sp->spt[i];
1737 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1738 clear_unsync_child_bit(sp, i);
1742 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1744 if (child->unsync_children) {
1745 if (mmu_pages_add(pvec, child, i))
1748 ret = __mmu_unsync_walk(child, pvec);
1750 clear_unsync_child_bit(sp, i);
1752 } else if (ret > 0) {
1753 nr_unsync_leaf += ret;
1756 } else if (child->unsync) {
1758 if (mmu_pages_add(pvec, child, i))
1761 clear_unsync_child_bit(sp, i);
1764 return nr_unsync_leaf;
1767 #define INVALID_INDEX (-1)
1769 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1770 struct kvm_mmu_pages *pvec)
1773 if (!sp->unsync_children)
1776 mmu_pages_add(pvec, sp, INVALID_INDEX);
1777 return __mmu_unsync_walk(sp, pvec);
1780 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1782 WARN_ON(!sp->unsync);
1783 trace_kvm_mmu_sync_page(sp);
1785 --kvm->stat.mmu_unsync;
1788 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1789 struct list_head *invalid_list);
1790 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1791 struct list_head *invalid_list);
1793 #define for_each_valid_sp(_kvm, _sp, _list) \
1794 hlist_for_each_entry(_sp, _list, hash_link) \
1795 if (is_obsolete_sp((_kvm), (_sp))) { \
1798 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1799 for_each_valid_sp(_kvm, _sp, \
1800 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1801 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1803 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
1805 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
1808 /* @sp->gfn should be write-protected at the call site */
1809 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1810 struct list_head *invalid_list)
1812 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
1813 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1814 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1821 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1822 struct list_head *invalid_list,
1825 if (!remote_flush && list_empty(invalid_list))
1828 if (!list_empty(invalid_list))
1829 kvm_mmu_commit_zap_page(kvm, invalid_list);
1831 kvm_flush_remote_tlbs(kvm);
1835 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1836 struct list_head *invalid_list,
1837 bool remote_flush, bool local_flush)
1839 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1843 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1846 #ifdef CONFIG_KVM_MMU_AUDIT
1847 #include "mmu_audit.c"
1849 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1850 static void mmu_audit_disable(void) { }
1853 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1855 return sp->role.invalid ||
1856 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1859 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1860 struct list_head *invalid_list)
1862 kvm_unlink_unsync_page(vcpu->kvm, sp);
1863 return __kvm_sync_page(vcpu, sp, invalid_list);
1866 /* @gfn should be write-protected at the call site */
1867 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1868 struct list_head *invalid_list)
1870 struct kvm_mmu_page *s;
1873 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1877 WARN_ON(s->role.level != PG_LEVEL_4K);
1878 ret |= kvm_sync_page(vcpu, s, invalid_list);
1884 struct mmu_page_path {
1885 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1886 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1889 #define for_each_sp(pvec, sp, parents, i) \
1890 for (i = mmu_pages_first(&pvec, &parents); \
1891 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1892 i = mmu_pages_next(&pvec, &parents, i))
1894 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1895 struct mmu_page_path *parents,
1900 for (n = i+1; n < pvec->nr; n++) {
1901 struct kvm_mmu_page *sp = pvec->page[n].sp;
1902 unsigned idx = pvec->page[n].idx;
1903 int level = sp->role.level;
1905 parents->idx[level-1] = idx;
1906 if (level == PG_LEVEL_4K)
1909 parents->parent[level-2] = sp;
1915 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1916 struct mmu_page_path *parents)
1918 struct kvm_mmu_page *sp;
1924 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1926 sp = pvec->page[0].sp;
1927 level = sp->role.level;
1928 WARN_ON(level == PG_LEVEL_4K);
1930 parents->parent[level-2] = sp;
1932 /* Also set up a sentinel. Further entries in pvec are all
1933 * children of sp, so this element is never overwritten.
1935 parents->parent[level-1] = NULL;
1936 return mmu_pages_next(pvec, parents, 0);
1939 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1941 struct kvm_mmu_page *sp;
1942 unsigned int level = 0;
1945 unsigned int idx = parents->idx[level];
1946 sp = parents->parent[level];
1950 WARN_ON(idx == INVALID_INDEX);
1951 clear_unsync_child_bit(sp, idx);
1953 } while (!sp->unsync_children);
1956 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1957 struct kvm_mmu_page *parent)
1960 struct kvm_mmu_page *sp;
1961 struct mmu_page_path parents;
1962 struct kvm_mmu_pages pages;
1963 LIST_HEAD(invalid_list);
1966 while (mmu_unsync_walk(parent, &pages)) {
1967 bool protected = false;
1969 for_each_sp(pages, sp, parents, i)
1970 protected |= rmap_write_protect(vcpu, sp->gfn);
1973 kvm_flush_remote_tlbs(vcpu->kvm);
1977 for_each_sp(pages, sp, parents, i) {
1978 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1979 mmu_pages_clear_parents(&parents);
1981 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
1982 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1983 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
1988 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1991 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1993 atomic_set(&sp->write_flooding_count, 0);
1996 static void clear_sp_write_flooding_count(u64 *spte)
1998 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2001 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2006 unsigned int access)
2008 bool direct_mmu = vcpu->arch.mmu->direct_map;
2009 union kvm_mmu_page_role role;
2010 struct hlist_head *sp_list;
2012 struct kvm_mmu_page *sp;
2013 bool need_sync = false;
2016 LIST_HEAD(invalid_list);
2018 role = vcpu->arch.mmu->mmu_role.base;
2020 role.direct = direct;
2022 role.gpte_is_8_bytes = true;
2023 role.access = access;
2024 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2025 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2026 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2027 role.quadrant = quadrant;
2030 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2031 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2032 if (sp->gfn != gfn) {
2037 if (!need_sync && sp->unsync)
2040 if (sp->role.word != role.word)
2044 goto trace_get_page;
2047 /* The page is good, but __kvm_sync_page might still end
2048 * up zapping it. If so, break in order to rebuild it.
2050 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2053 WARN_ON(!list_empty(&invalid_list));
2054 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2057 if (sp->unsync_children)
2058 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2060 __clear_sp_write_flooding_count(sp);
2063 trace_kvm_mmu_get_page(sp, false);
2067 ++vcpu->kvm->stat.mmu_cache_miss;
2069 sp = kvm_mmu_alloc_page(vcpu, direct);
2073 hlist_add_head(&sp->hash_link, sp_list);
2076 * we should do write protection before syncing pages
2077 * otherwise the content of the synced shadow page may
2078 * be inconsistent with guest page table.
2080 account_shadowed(vcpu->kvm, sp);
2081 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2082 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2084 if (level > PG_LEVEL_4K && need_sync)
2085 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2087 trace_kvm_mmu_get_page(sp, true);
2089 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2091 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2092 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2096 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2097 struct kvm_vcpu *vcpu, hpa_t root,
2100 iterator->addr = addr;
2101 iterator->shadow_addr = root;
2102 iterator->level = vcpu->arch.mmu->shadow_root_level;
2104 if (iterator->level == PT64_ROOT_4LEVEL &&
2105 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2106 !vcpu->arch.mmu->direct_map)
2109 if (iterator->level == PT32E_ROOT_LEVEL) {
2111 * prev_root is currently only used for 64-bit hosts. So only
2112 * the active root_hpa is valid here.
2114 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2116 iterator->shadow_addr
2117 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2118 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2120 if (!iterator->shadow_addr)
2121 iterator->level = 0;
2125 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2126 struct kvm_vcpu *vcpu, u64 addr)
2128 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2132 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2134 if (iterator->level < PG_LEVEL_4K)
2137 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2138 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2142 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2145 if (is_last_spte(spte, iterator->level)) {
2146 iterator->level = 0;
2150 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2154 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2156 __shadow_walk_next(iterator, *iterator->sptep);
2159 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2160 struct kvm_mmu_page *sp)
2164 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2166 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2168 mmu_spte_set(sptep, spte);
2170 mmu_page_add_parent_pte(vcpu, sp, sptep);
2172 if (sp->unsync_children || sp->unsync)
2176 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2177 unsigned direct_access)
2179 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2180 struct kvm_mmu_page *child;
2183 * For the direct sp, if the guest pte's dirty bit
2184 * changed form clean to dirty, it will corrupt the
2185 * sp's access: allow writable in the read-only sp,
2186 * so we should update the spte at this point to get
2187 * a new sp with the correct access.
2189 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2190 if (child->role.access == direct_access)
2193 drop_parent_pte(child, sptep);
2194 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2198 /* Returns the number of zapped non-leaf child shadow pages. */
2199 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2200 u64 *spte, struct list_head *invalid_list)
2203 struct kvm_mmu_page *child;
2206 if (is_shadow_present_pte(pte)) {
2207 if (is_last_spte(pte, sp->role.level)) {
2208 drop_spte(kvm, spte);
2209 if (is_large_pte(pte))
2212 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2213 drop_parent_pte(child, spte);
2216 * Recursively zap nested TDP SPs, parentless SPs are
2217 * unlikely to be used again in the near future. This
2218 * avoids retaining a large number of stale nested SPs.
2220 if (tdp_enabled && invalid_list &&
2221 child->role.guest_mode && !child->parent_ptes.val)
2222 return kvm_mmu_prepare_zap_page(kvm, child,
2225 } else if (is_mmio_spte(pte)) {
2226 mmu_spte_clear_no_track(spte);
2231 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2232 struct kvm_mmu_page *sp,
2233 struct list_head *invalid_list)
2238 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2239 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2244 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2247 struct rmap_iterator iter;
2249 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2250 drop_parent_pte(sp, sptep);
2253 static int mmu_zap_unsync_children(struct kvm *kvm,
2254 struct kvm_mmu_page *parent,
2255 struct list_head *invalid_list)
2258 struct mmu_page_path parents;
2259 struct kvm_mmu_pages pages;
2261 if (parent->role.level == PG_LEVEL_4K)
2264 while (mmu_unsync_walk(parent, &pages)) {
2265 struct kvm_mmu_page *sp;
2267 for_each_sp(pages, sp, parents, i) {
2268 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2269 mmu_pages_clear_parents(&parents);
2277 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2278 struct kvm_mmu_page *sp,
2279 struct list_head *invalid_list,
2284 trace_kvm_mmu_prepare_zap_page(sp);
2285 ++kvm->stat.mmu_shadow_zapped;
2286 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2287 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2288 kvm_mmu_unlink_parents(kvm, sp);
2290 /* Zapping children means active_mmu_pages has become unstable. */
2291 list_unstable = *nr_zapped;
2293 if (!sp->role.invalid && !sp->role.direct)
2294 unaccount_shadowed(kvm, sp);
2297 kvm_unlink_unsync_page(kvm, sp);
2298 if (!sp->root_count) {
2303 * Already invalid pages (previously active roots) are not on
2304 * the active page list. See list_del() in the "else" case of
2307 if (sp->role.invalid)
2308 list_add(&sp->link, invalid_list);
2310 list_move(&sp->link, invalid_list);
2311 kvm_mod_used_mmu_pages(kvm, -1);
2314 * Remove the active root from the active page list, the root
2315 * will be explicitly freed when the root_count hits zero.
2317 list_del(&sp->link);
2320 * Obsolete pages cannot be used on any vCPUs, see the comment
2321 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2322 * treats invalid shadow pages as being obsolete.
2324 if (!is_obsolete_sp(kvm, sp))
2325 kvm_reload_remote_mmus(kvm);
2328 if (sp->lpage_disallowed)
2329 unaccount_huge_nx_page(kvm, sp);
2331 sp->role.invalid = 1;
2332 return list_unstable;
2335 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2336 struct list_head *invalid_list)
2340 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2344 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2345 struct list_head *invalid_list)
2347 struct kvm_mmu_page *sp, *nsp;
2349 if (list_empty(invalid_list))
2353 * We need to make sure everyone sees our modifications to
2354 * the page tables and see changes to vcpu->mode here. The barrier
2355 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2356 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2358 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2359 * guest mode and/or lockless shadow page table walks.
2361 kvm_flush_remote_tlbs(kvm);
2363 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2364 WARN_ON(!sp->role.invalid || sp->root_count);
2365 kvm_mmu_free_page(sp);
2369 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2370 unsigned long nr_to_zap)
2372 unsigned long total_zapped = 0;
2373 struct kvm_mmu_page *sp, *tmp;
2374 LIST_HEAD(invalid_list);
2378 if (list_empty(&kvm->arch.active_mmu_pages))
2382 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2384 * Don't zap active root pages, the page itself can't be freed
2385 * and zapping it will just force vCPUs to realloc and reload.
2390 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2392 total_zapped += nr_zapped;
2393 if (total_zapped >= nr_to_zap)
2400 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2402 kvm->stat.mmu_recycled += total_zapped;
2403 return total_zapped;
2406 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2408 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2409 return kvm->arch.n_max_mmu_pages -
2410 kvm->arch.n_used_mmu_pages;
2415 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2417 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2419 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2422 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2424 if (!kvm_mmu_available_pages(vcpu->kvm))
2430 * Changing the number of mmu pages allocated to the vm
2431 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2433 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2435 write_lock(&kvm->mmu_lock);
2437 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2438 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2441 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2444 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2446 write_unlock(&kvm->mmu_lock);
2449 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2451 struct kvm_mmu_page *sp;
2452 LIST_HEAD(invalid_list);
2455 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2457 write_lock(&kvm->mmu_lock);
2458 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2459 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2462 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2464 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2465 write_unlock(&kvm->mmu_lock);
2470 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2475 if (vcpu->arch.mmu->direct_map)
2478 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2480 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2485 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2487 trace_kvm_mmu_unsync_page(sp);
2488 ++vcpu->kvm->stat.mmu_unsync;
2491 kvm_mmu_mark_parents_unsync(sp);
2494 bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2497 struct kvm_mmu_page *sp;
2499 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2502 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2509 WARN_ON(sp->role.level != PG_LEVEL_4K);
2510 kvm_unsync_page(vcpu, sp);
2514 * We need to ensure that the marking of unsync pages is visible
2515 * before the SPTE is updated to allow writes because
2516 * kvm_mmu_sync_roots() checks the unsync flags without holding
2517 * the MMU lock and so can race with this. If the SPTE was updated
2518 * before the page had been marked as unsync-ed, something like the
2519 * following could happen:
2522 * ---------------------------------------------------------------------
2523 * 1.2 Host updates SPTE
2525 * 2.1 Guest writes a GPTE for GVA X.
2526 * (GPTE being in the guest page table shadowed
2527 * by the SP from CPU 1.)
2528 * This reads SPTE during the page table walk.
2529 * Since SPTE.W is read as 1, there is no
2532 * 2.2 Guest issues TLB flush.
2533 * That causes a VM Exit.
2535 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2536 * Since it is false, so it just returns.
2538 * 2.4 Guest accesses GVA X.
2539 * Since the mapping in the SP was not updated,
2540 * so the old mapping for GVA X incorrectly
2544 * (sp->unsync = true)
2546 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2547 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2548 * pairs with this write barrier.
2555 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2556 unsigned int pte_access, int level,
2557 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2558 bool can_unsync, bool host_writable)
2561 struct kvm_mmu_page *sp;
2564 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2567 sp = sptep_to_sp(sptep);
2569 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2570 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2572 if (spte & PT_WRITABLE_MASK)
2573 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2576 ret |= SET_SPTE_SPURIOUS;
2577 else if (mmu_spte_update(sptep, spte))
2578 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2582 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2583 unsigned int pte_access, bool write_fault, int level,
2584 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2587 int was_rmapped = 0;
2590 int ret = RET_PF_FIXED;
2593 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2594 *sptep, write_fault, gfn);
2596 if (is_shadow_present_pte(*sptep)) {
2598 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2599 * the parent of the now unreachable PTE.
2601 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2602 struct kvm_mmu_page *child;
2605 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2606 drop_parent_pte(child, sptep);
2608 } else if (pfn != spte_to_pfn(*sptep)) {
2609 pgprintk("hfn old %llx new %llx\n",
2610 spte_to_pfn(*sptep), pfn);
2611 drop_spte(vcpu->kvm, sptep);
2617 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2618 speculative, true, host_writable);
2619 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2621 ret = RET_PF_EMULATE;
2622 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2625 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2626 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2627 KVM_PAGES_PER_HPAGE(level));
2629 if (unlikely(is_mmio_spte(*sptep)))
2630 ret = RET_PF_EMULATE;
2633 * The fault is fully spurious if and only if the new SPTE and old SPTE
2634 * are identical, and emulation is not required.
2636 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2637 WARN_ON_ONCE(!was_rmapped);
2638 return RET_PF_SPURIOUS;
2641 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2642 trace_kvm_mmu_set_spte(level, gfn, sptep);
2643 if (!was_rmapped && is_large_pte(*sptep))
2644 ++vcpu->kvm->stat.lpages;
2646 if (is_shadow_present_pte(*sptep)) {
2648 rmap_count = rmap_add(vcpu, sptep, gfn);
2649 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2650 rmap_recycle(vcpu, sptep, gfn);
2657 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2660 struct kvm_memory_slot *slot;
2662 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2664 return KVM_PFN_ERR_FAULT;
2666 return gfn_to_pfn_memslot_atomic(slot, gfn);
2669 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2670 struct kvm_mmu_page *sp,
2671 u64 *start, u64 *end)
2673 struct page *pages[PTE_PREFETCH_NUM];
2674 struct kvm_memory_slot *slot;
2675 unsigned int access = sp->role.access;
2679 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2680 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2684 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2688 for (i = 0; i < ret; i++, gfn++, start++) {
2689 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2690 page_to_pfn(pages[i]), true, true);
2697 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2698 struct kvm_mmu_page *sp, u64 *sptep)
2700 u64 *spte, *start = NULL;
2703 WARN_ON(!sp->role.direct);
2705 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2708 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2709 if (is_shadow_present_pte(*spte) || spte == sptep) {
2712 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2720 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2722 struct kvm_mmu_page *sp;
2724 sp = sptep_to_sp(sptep);
2727 * Without accessed bits, there's no way to distinguish between
2728 * actually accessed translations and prefetched, so disable pte
2729 * prefetch if accessed bits aren't available.
2731 if (sp_ad_disabled(sp))
2734 if (sp->role.level > PG_LEVEL_4K)
2738 * If addresses are being invalidated, skip prefetching to avoid
2739 * accidentally prefetching those addresses.
2741 if (unlikely(vcpu->kvm->mmu_notifier_count))
2744 __direct_pte_prefetch(vcpu, sp, sptep);
2747 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2748 struct kvm_memory_slot *slot)
2754 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2758 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2759 * is not solely for performance, it's also necessary to avoid the
2760 * "writable" check in __gfn_to_hva_many(), which will always fail on
2761 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2762 * page fault steps have already verified the guest isn't writing a
2763 * read-only memslot.
2765 hva = __gfn_to_hva_memslot(slot, gfn);
2767 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2774 int kvm_mmu_max_mapping_level(struct kvm *kvm, struct kvm_memory_slot *slot,
2775 gfn_t gfn, kvm_pfn_t pfn, int max_level)
2777 struct kvm_lpage_info *linfo;
2779 max_level = min(max_level, max_huge_page_level);
2780 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2781 linfo = lpage_info_slot(gfn, slot, max_level);
2782 if (!linfo->disallow_lpage)
2786 if (max_level == PG_LEVEL_4K)
2789 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2792 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2793 int max_level, kvm_pfn_t *pfnp,
2794 bool huge_page_disallowed, int *req_level)
2796 struct kvm_memory_slot *slot;
2797 kvm_pfn_t pfn = *pfnp;
2801 *req_level = PG_LEVEL_4K;
2803 if (unlikely(max_level == PG_LEVEL_4K))
2806 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2809 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2813 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2814 if (level == PG_LEVEL_4K)
2817 *req_level = level = min(level, max_level);
2820 * Enforce the iTLB multihit workaround after capturing the requested
2821 * level, which will be used to do precise, accurate accounting.
2823 if (huge_page_disallowed)
2827 * mmu_notifier_retry() was successful and mmu_lock is held, so
2828 * the pmd can't be split from under us.
2830 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2831 VM_BUG_ON((gfn & mask) != (pfn & mask));
2832 *pfnp = pfn & ~mask;
2837 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2838 kvm_pfn_t *pfnp, int *goal_levelp)
2840 int level = *goal_levelp;
2842 if (cur_level == level && level > PG_LEVEL_4K &&
2843 is_shadow_present_pte(spte) &&
2844 !is_large_pte(spte)) {
2846 * A small SPTE exists for this pfn, but FNAME(fetch)
2847 * and __direct_map would like to create a large PTE
2848 * instead: just force them to go down another level,
2849 * patching back for them into pfn the next 9 bits of
2852 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2853 KVM_PAGES_PER_HPAGE(level - 1);
2854 *pfnp |= gfn & page_mask;
2859 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2860 int map_writable, int max_level, kvm_pfn_t pfn,
2861 bool prefault, bool is_tdp)
2863 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2864 bool write = error_code & PFERR_WRITE_MASK;
2865 bool exec = error_code & PFERR_FETCH_MASK;
2866 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2867 struct kvm_shadow_walk_iterator it;
2868 struct kvm_mmu_page *sp;
2869 int level, req_level, ret;
2870 gfn_t gfn = gpa >> PAGE_SHIFT;
2871 gfn_t base_gfn = gfn;
2873 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
2874 return RET_PF_RETRY;
2876 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2877 huge_page_disallowed, &req_level);
2879 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2880 for_each_shadow_entry(vcpu, gpa, it) {
2882 * We cannot overwrite existing page tables with an NX
2883 * large page, as the leaf could be executable.
2885 if (nx_huge_page_workaround_enabled)
2886 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2889 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2890 if (it.level == level)
2893 drop_large_spte(vcpu, it.sptep);
2894 if (!is_shadow_present_pte(*it.sptep)) {
2895 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2896 it.level - 1, true, ACC_ALL);
2898 link_shadow_page(vcpu, it.sptep, sp);
2899 if (is_tdp && huge_page_disallowed &&
2900 req_level >= it.level)
2901 account_huge_nx_page(vcpu->kvm, sp);
2905 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2906 write, level, base_gfn, pfn, prefault,
2908 if (ret == RET_PF_SPURIOUS)
2911 direct_pte_prefetch(vcpu, it.sptep);
2912 ++vcpu->stat.pf_fixed;
2916 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2918 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2921 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2924 * Do not cache the mmio info caused by writing the readonly gfn
2925 * into the spte otherwise read access on readonly gfn also can
2926 * caused mmio page fault and treat it as mmio access.
2928 if (pfn == KVM_PFN_ERR_RO_FAULT)
2929 return RET_PF_EMULATE;
2931 if (pfn == KVM_PFN_ERR_HWPOISON) {
2932 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2933 return RET_PF_RETRY;
2939 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2940 kvm_pfn_t pfn, unsigned int access,
2943 /* The pfn is invalid, report the error! */
2944 if (unlikely(is_error_pfn(pfn))) {
2945 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2949 if (unlikely(is_noslot_pfn(pfn)))
2950 vcpu_cache_mmio_info(vcpu, gva, gfn,
2951 access & shadow_mmio_access_mask);
2956 static bool page_fault_can_be_fast(u32 error_code)
2959 * Do not fix the mmio spte with invalid generation number which
2960 * need to be updated by slow page fault path.
2962 if (unlikely(error_code & PFERR_RSVD_MASK))
2965 /* See if the page fault is due to an NX violation */
2966 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2967 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2971 * #PF can be fast if:
2972 * 1. The shadow page table entry is not present, which could mean that
2973 * the fault is potentially caused by access tracking (if enabled).
2974 * 2. The shadow page table entry is present and the fault
2975 * is caused by write-protect, that means we just need change the W
2976 * bit of the spte which can be done out of mmu-lock.
2978 * However, if access tracking is disabled we know that a non-present
2979 * page must be a genuine page fault where we have to create a new SPTE.
2980 * So, if access tracking is disabled, we return true only for write
2981 * accesses to a present page.
2984 return shadow_acc_track_mask != 0 ||
2985 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
2986 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
2990 * Returns true if the SPTE was fixed successfully. Otherwise,
2991 * someone else modified the SPTE from its original value.
2994 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2995 u64 *sptep, u64 old_spte, u64 new_spte)
2999 WARN_ON(!sp->role.direct);
3002 * Theoretically we could also set dirty bit (and flush TLB) here in
3003 * order to eliminate unnecessary PML logging. See comments in
3004 * set_spte. But fast_page_fault is very unlikely to happen with PML
3005 * enabled, so we do not do this. This might result in the same GPA
3006 * to be logged in PML buffer again when the write really happens, and
3007 * eventually to be called by mark_page_dirty twice. But it's also no
3008 * harm. This also avoids the TLB flush needed after setting dirty bit
3009 * so non-PML cases won't be impacted.
3011 * Compare with set_spte where instead shadow_dirty_mask is set.
3013 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3016 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3018 * The gfn of direct spte is stable since it is
3019 * calculated by sp->gfn.
3021 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3022 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3028 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3030 if (fault_err_code & PFERR_FETCH_MASK)
3031 return is_executable_pte(spte);
3033 if (fault_err_code & PFERR_WRITE_MASK)
3034 return is_writable_pte(spte);
3036 /* Fault was on Read access */
3037 return spte & PT_PRESENT_MASK;
3041 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3043 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3046 struct kvm_shadow_walk_iterator iterator;
3047 struct kvm_mmu_page *sp;
3048 int ret = RET_PF_INVALID;
3050 uint retry_count = 0;
3052 if (!page_fault_can_be_fast(error_code))
3055 walk_shadow_page_lockless_begin(vcpu);
3060 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3061 if (!is_shadow_present_pte(spte))
3064 sp = sptep_to_sp(iterator.sptep);
3065 if (!is_last_spte(spte, sp->role.level))
3069 * Check whether the memory access that caused the fault would
3070 * still cause it if it were to be performed right now. If not,
3071 * then this is a spurious fault caused by TLB lazily flushed,
3072 * or some other CPU has already fixed the PTE after the
3073 * current CPU took the fault.
3075 * Need not check the access of upper level table entries since
3076 * they are always ACC_ALL.
3078 if (is_access_allowed(error_code, spte)) {
3079 ret = RET_PF_SPURIOUS;
3085 if (is_access_track_spte(spte))
3086 new_spte = restore_acc_track_spte(new_spte);
3089 * Currently, to simplify the code, write-protection can
3090 * be removed in the fast path only if the SPTE was
3091 * write-protected for dirty-logging or access tracking.
3093 if ((error_code & PFERR_WRITE_MASK) &&
3094 spte_can_locklessly_be_made_writable(spte)) {
3095 new_spte |= PT_WRITABLE_MASK;
3098 * Do not fix write-permission on the large spte. Since
3099 * we only dirty the first page into the dirty-bitmap in
3100 * fast_pf_fix_direct_spte(), other pages are missed
3101 * if its slot has dirty logging enabled.
3103 * Instead, we let the slow page fault path create a
3104 * normal spte to fix the access.
3106 * See the comments in kvm_arch_commit_memory_region().
3108 if (sp->role.level > PG_LEVEL_4K)
3112 /* Verify that the fault can be handled in the fast path */
3113 if (new_spte == spte ||
3114 !is_access_allowed(error_code, new_spte))
3118 * Currently, fast page fault only works for direct mapping
3119 * since the gfn is not stable for indirect shadow page. See
3120 * Documentation/virt/kvm/locking.rst to get more detail.
3122 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3128 if (++retry_count > 4) {
3129 printk_once(KERN_WARNING
3130 "kvm: Fast #PF retrying more than 4 times.\n");
3136 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3138 walk_shadow_page_lockless_end(vcpu);
3143 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3144 struct list_head *invalid_list)
3146 struct kvm_mmu_page *sp;
3148 if (!VALID_PAGE(*root_hpa))
3151 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3153 if (kvm_mmu_put_root(kvm, sp)) {
3154 if (is_tdp_mmu_page(sp))
3155 kvm_tdp_mmu_free_root(kvm, sp);
3156 else if (sp->role.invalid)
3157 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3160 *root_hpa = INVALID_PAGE;
3163 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3164 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3165 ulong roots_to_free)
3167 struct kvm *kvm = vcpu->kvm;
3169 LIST_HEAD(invalid_list);
3170 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3172 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3174 /* Before acquiring the MMU lock, see if we need to do any real work. */
3175 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3176 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3177 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3178 VALID_PAGE(mmu->prev_roots[i].hpa))
3181 if (i == KVM_MMU_NUM_PREV_ROOTS)
3185 write_lock(&kvm->mmu_lock);
3187 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3188 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3189 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3192 if (free_active_root) {
3193 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3194 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3195 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3197 for (i = 0; i < 4; ++i)
3198 if (mmu->pae_root[i] != 0)
3199 mmu_free_root_page(kvm,
3202 mmu->root_hpa = INVALID_PAGE;
3207 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3208 write_unlock(&kvm->mmu_lock);
3210 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3212 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3216 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3217 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3224 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3225 u8 level, bool direct)
3227 struct kvm_mmu_page *sp;
3229 write_lock(&vcpu->kvm->mmu_lock);
3231 if (make_mmu_pages_available(vcpu)) {
3232 write_unlock(&vcpu->kvm->mmu_lock);
3233 return INVALID_PAGE;
3235 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3238 write_unlock(&vcpu->kvm->mmu_lock);
3239 return __pa(sp->spt);
3242 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3244 u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level;
3248 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3249 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3251 if (!VALID_PAGE(root))
3253 vcpu->arch.mmu->root_hpa = root;
3254 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3255 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level,
3258 if (!VALID_PAGE(root))
3260 vcpu->arch.mmu->root_hpa = root;
3261 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3262 for (i = 0; i < 4; ++i) {
3263 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3265 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3266 i << 30, PT32_ROOT_LEVEL, true);
3267 if (!VALID_PAGE(root))
3269 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3271 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3275 /* root_pgd is ignored for direct MMUs. */
3276 vcpu->arch.mmu->root_pgd = 0;
3281 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3284 gfn_t root_gfn, root_pgd;
3288 root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu);
3289 root_gfn = root_pgd >> PAGE_SHIFT;
3291 if (mmu_check_root(vcpu, root_gfn))
3295 * Do we shadow a long mode page table? If so we need to
3296 * write-protect the guests page table root.
3298 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3299 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa));
3301 root = mmu_alloc_root(vcpu, root_gfn, 0,
3302 vcpu->arch.mmu->shadow_root_level, false);
3303 if (!VALID_PAGE(root))
3305 vcpu->arch.mmu->root_hpa = root;
3310 * We shadow a 32 bit page table. This may be a legacy 2-level
3311 * or a PAE 3-level page table. In either case we need to be aware that
3312 * the shadow page table may be a PAE or a long mode page table.
3314 pm_mask = PT_PRESENT_MASK;
3315 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3316 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3318 for (i = 0; i < 4; ++i) {
3319 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3320 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3321 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3322 if (!(pdptr & PT_PRESENT_MASK)) {
3323 vcpu->arch.mmu->pae_root[i] = 0;
3326 root_gfn = pdptr >> PAGE_SHIFT;
3327 if (mmu_check_root(vcpu, root_gfn))
3331 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3332 PT32_ROOT_LEVEL, false);
3333 if (!VALID_PAGE(root))
3335 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3337 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3340 * If we shadow a 32 bit page table with a long mode page
3341 * table we enter this path.
3343 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3344 if (vcpu->arch.mmu->lm_root == NULL) {
3346 * The additional page necessary for this is only
3347 * allocated on demand.
3352 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3353 if (lm_root == NULL)
3356 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3358 vcpu->arch.mmu->lm_root = lm_root;
3361 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3365 vcpu->arch.mmu->root_pgd = root_pgd;
3370 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3372 if (vcpu->arch.mmu->direct_map)
3373 return mmu_alloc_direct_roots(vcpu);
3375 return mmu_alloc_shadow_roots(vcpu);
3378 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3381 struct kvm_mmu_page *sp;
3383 if (vcpu->arch.mmu->direct_map)
3386 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3389 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3391 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3392 hpa_t root = vcpu->arch.mmu->root_hpa;
3393 sp = to_shadow_page(root);
3396 * Even if another CPU was marking the SP as unsync-ed
3397 * simultaneously, any guest page table changes are not
3398 * guaranteed to be visible anyway until this VCPU issues a TLB
3399 * flush strictly after those changes are made. We only need to
3400 * ensure that the other CPU sets these flags before any actual
3401 * changes to the page tables are made. The comments in
3402 * mmu_need_write_protect() describe what could go wrong if this
3403 * requirement isn't satisfied.
3405 if (!smp_load_acquire(&sp->unsync) &&
3406 !smp_load_acquire(&sp->unsync_children))
3409 write_lock(&vcpu->kvm->mmu_lock);
3410 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3412 mmu_sync_children(vcpu, sp);
3414 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3415 write_unlock(&vcpu->kvm->mmu_lock);
3419 write_lock(&vcpu->kvm->mmu_lock);
3420 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3422 for (i = 0; i < 4; ++i) {
3423 hpa_t root = vcpu->arch.mmu->pae_root[i];
3425 if (root && VALID_PAGE(root)) {
3426 root &= PT64_BASE_ADDR_MASK;
3427 sp = to_shadow_page(root);
3428 mmu_sync_children(vcpu, sp);
3432 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3433 write_unlock(&vcpu->kvm->mmu_lock);
3436 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3437 u32 access, struct x86_exception *exception)
3440 exception->error_code = 0;
3444 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3446 struct x86_exception *exception)
3449 exception->error_code = 0;
3450 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3454 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3456 int bit7 = (pte >> 7) & 1;
3458 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3461 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3463 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3466 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3469 * A nested guest cannot use the MMIO cache if it is using nested
3470 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3472 if (mmu_is_nested(vcpu))
3476 return vcpu_match_mmio_gpa(vcpu, addr);
3478 return vcpu_match_mmio_gva(vcpu, addr);
3482 * Return the level of the lowest level SPTE added to sptes.
3483 * That SPTE may be non-present.
3485 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3487 struct kvm_shadow_walk_iterator iterator;
3491 walk_shadow_page_lockless_begin(vcpu);
3493 for (shadow_walk_init(&iterator, vcpu, addr),
3494 *root_level = iterator.level;
3495 shadow_walk_okay(&iterator);
3496 __shadow_walk_next(&iterator, spte)) {
3497 leaf = iterator.level;
3498 spte = mmu_spte_get_lockless(iterator.sptep);
3502 if (!is_shadow_present_pte(spte))
3506 walk_shadow_page_lockless_end(vcpu);
3511 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3512 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3514 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3515 struct rsvd_bits_validate *rsvd_check;
3516 int root, leaf, level;
3517 bool reserved = false;
3519 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) {
3524 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3525 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3527 leaf = get_walk(vcpu, addr, sptes, &root);
3529 if (unlikely(leaf < 0)) {
3534 *sptep = sptes[leaf];
3537 * Skip reserved bits checks on the terminal leaf if it's not a valid
3538 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3539 * design, always have reserved bits set. The purpose of the checks is
3540 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3542 if (!is_shadow_present_pte(sptes[leaf]))
3545 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3547 for (level = root; level >= leaf; level--)
3549 * Use a bitwise-OR instead of a logical-OR to aggregate the
3550 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3551 * adding a Jcc in the loop.
3553 reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) |
3554 __is_rsvd_bits_set(rsvd_check, sptes[level], level);
3557 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3559 for (level = root; level >= leaf; level--)
3560 pr_err("------ spte 0x%llx level %d.\n",
3561 sptes[level], level);
3567 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3572 if (mmio_info_in_cache(vcpu, addr, direct))
3573 return RET_PF_EMULATE;
3575 reserved = get_mmio_spte(vcpu, addr, &spte);
3576 if (WARN_ON(reserved))
3579 if (is_mmio_spte(spte)) {
3580 gfn_t gfn = get_mmio_spte_gfn(spte);
3581 unsigned int access = get_mmio_spte_access(spte);
3583 if (!check_mmio_spte(vcpu, spte))
3584 return RET_PF_INVALID;
3589 trace_handle_mmio_page_fault(addr, gfn, access);
3590 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3591 return RET_PF_EMULATE;
3595 * If the page table is zapped by other cpus, let CPU fault again on
3598 return RET_PF_RETRY;
3601 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3602 u32 error_code, gfn_t gfn)
3604 if (unlikely(error_code & PFERR_RSVD_MASK))
3607 if (!(error_code & PFERR_PRESENT_MASK) ||
3608 !(error_code & PFERR_WRITE_MASK))
3612 * guest is writing the page which is write tracked which can
3613 * not be fixed by page fault handler.
3615 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3621 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3623 struct kvm_shadow_walk_iterator iterator;
3626 walk_shadow_page_lockless_begin(vcpu);
3627 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3628 clear_sp_write_flooding_count(iterator.sptep);
3629 if (!is_shadow_present_pte(spte))
3632 walk_shadow_page_lockless_end(vcpu);
3635 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3638 struct kvm_arch_async_pf arch;
3640 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3642 arch.direct_map = vcpu->arch.mmu->direct_map;
3643 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3645 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3646 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3649 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3650 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3651 bool write, bool *writable)
3653 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3656 /* Don't expose private memslots to L2. */
3657 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3658 *pfn = KVM_PFN_NOSLOT;
3664 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3665 write, writable, hva);
3667 return false; /* *pfn has correct page already */
3669 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3670 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3671 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3672 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3673 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3675 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3679 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3680 write, writable, hva);
3684 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3685 bool prefault, int max_level, bool is_tdp)
3687 bool write = error_code & PFERR_WRITE_MASK;
3690 gfn_t gfn = gpa >> PAGE_SHIFT;
3691 unsigned long mmu_seq;
3696 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3697 return RET_PF_EMULATE;
3699 if (!is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) {
3700 r = fast_page_fault(vcpu, gpa, error_code);
3701 if (r != RET_PF_INVALID)
3705 r = mmu_topup_memory_caches(vcpu, false);
3709 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3712 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3713 write, &map_writable))
3714 return RET_PF_RETRY;
3716 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3721 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3722 read_lock(&vcpu->kvm->mmu_lock);
3724 write_lock(&vcpu->kvm->mmu_lock);
3726 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
3728 r = make_mmu_pages_available(vcpu);
3732 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3733 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3736 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3740 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3741 read_unlock(&vcpu->kvm->mmu_lock);
3743 write_unlock(&vcpu->kvm->mmu_lock);
3744 kvm_release_pfn_clean(pfn);
3748 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3749 u32 error_code, bool prefault)
3751 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3753 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3754 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3755 PG_LEVEL_2M, false);
3758 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3759 u64 fault_address, char *insn, int insn_len)
3762 u32 flags = vcpu->arch.apf.host_apf_flags;
3764 #ifndef CONFIG_X86_64
3765 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3766 if (WARN_ON_ONCE(fault_address >> 32))
3770 vcpu->arch.l1tf_flush_l1d = true;
3772 trace_kvm_page_fault(fault_address, error_code);
3774 if (kvm_event_needs_reinjection(vcpu))
3775 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3776 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3778 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3779 vcpu->arch.apf.host_apf_flags = 0;
3780 local_irq_disable();
3781 kvm_async_pf_task_wait_schedule(fault_address);
3784 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3789 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3791 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3796 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3797 max_level > PG_LEVEL_4K;
3799 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3800 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3802 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3806 return direct_page_fault(vcpu, gpa, error_code, prefault,
3810 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3811 struct kvm_mmu *context)
3813 context->page_fault = nonpaging_page_fault;
3814 context->gva_to_gpa = nonpaging_gva_to_gpa;
3815 context->sync_page = nonpaging_sync_page;
3816 context->invlpg = NULL;
3817 context->root_level = 0;
3818 context->shadow_root_level = PT32E_ROOT_LEVEL;
3819 context->direct_map = true;
3820 context->nx = false;
3823 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3824 union kvm_mmu_page_role role)
3826 return (role.direct || pgd == root->pgd) &&
3827 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3828 role.word == to_shadow_page(root->hpa)->role.word;
3832 * Find out if a previously cached root matching the new pgd/role is available.
3833 * The current root is also inserted into the cache.
3834 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3836 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3837 * false is returned. This root should now be freed by the caller.
3839 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3840 union kvm_mmu_page_role new_role)
3843 struct kvm_mmu_root_info root;
3844 struct kvm_mmu *mmu = vcpu->arch.mmu;
3846 root.pgd = mmu->root_pgd;
3847 root.hpa = mmu->root_hpa;
3849 if (is_root_usable(&root, new_pgd, new_role))
3852 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3853 swap(root, mmu->prev_roots[i]);
3855 if (is_root_usable(&root, new_pgd, new_role))
3859 mmu->root_hpa = root.hpa;
3860 mmu->root_pgd = root.pgd;
3862 return i < KVM_MMU_NUM_PREV_ROOTS;
3865 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3866 union kvm_mmu_page_role new_role)
3868 struct kvm_mmu *mmu = vcpu->arch.mmu;
3871 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3872 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3873 * later if necessary.
3875 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3876 mmu->root_level >= PT64_ROOT_4LEVEL)
3877 return cached_root_available(vcpu, new_pgd, new_role);
3882 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3883 union kvm_mmu_page_role new_role,
3884 bool skip_tlb_flush, bool skip_mmu_sync)
3886 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
3887 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
3892 * It's possible that the cached previous root page is obsolete because
3893 * of a change in the MMU generation number. However, changing the
3894 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3895 * free the root set here and allocate a new one.
3897 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
3899 if (!skip_mmu_sync || force_flush_and_sync_on_reuse)
3900 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
3901 if (!skip_tlb_flush || force_flush_and_sync_on_reuse)
3902 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3905 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3906 * switching to a new CR3, that GVA->GPA mapping may no longer be
3907 * valid. So clear any cached MMIO info even when we don't need to sync
3908 * the shadow page tables.
3910 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3913 * If this is a direct root page, it doesn't have a write flooding
3914 * count. Otherwise, clear the write flooding count.
3916 if (!new_role.direct)
3917 __clear_sp_write_flooding_count(
3918 to_shadow_page(vcpu->arch.mmu->root_hpa));
3921 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
3924 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu),
3925 skip_tlb_flush, skip_mmu_sync);
3927 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
3929 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3931 return kvm_read_cr3(vcpu);
3934 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3935 unsigned int access, int *nr_present)
3937 if (unlikely(is_mmio_spte(*sptep))) {
3938 if (gfn != get_mmio_spte_gfn(*sptep)) {
3939 mmu_spte_clear_no_track(sptep);
3944 mark_mmio_spte(vcpu, sptep, gfn, access);
3951 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3952 unsigned level, unsigned gpte)
3955 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3956 * If it is clear, there are no large pages at this level, so clear
3957 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3959 gpte &= level - mmu->last_nonleaf_level;
3962 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
3963 * iff level <= PG_LEVEL_4K, which for our purpose means
3964 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
3966 gpte |= level - PG_LEVEL_4K - 1;
3968 return gpte & PT_PAGE_SIZE_MASK;
3971 #define PTTYPE_EPT 18 /* arbitrary */
3972 #define PTTYPE PTTYPE_EPT
3973 #include "paging_tmpl.h"
3977 #include "paging_tmpl.h"
3981 #include "paging_tmpl.h"
3985 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3986 struct rsvd_bits_validate *rsvd_check,
3987 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
3990 u64 gbpages_bit_rsvd = 0;
3991 u64 nonleaf_bit8_rsvd = 0;
3994 rsvd_check->bad_mt_xwr = 0;
3997 gbpages_bit_rsvd = rsvd_bits(7, 7);
3999 if (level == PT32E_ROOT_LEVEL)
4000 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4002 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4004 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4006 high_bits_rsvd |= rsvd_bits(63, 63);
4009 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4010 * leaf entries) on AMD CPUs only.
4013 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4016 case PT32_ROOT_LEVEL:
4017 /* no rsvd bits for 2 level 4K page table entries */
4018 rsvd_check->rsvd_bits_mask[0][1] = 0;
4019 rsvd_check->rsvd_bits_mask[0][0] = 0;
4020 rsvd_check->rsvd_bits_mask[1][0] =
4021 rsvd_check->rsvd_bits_mask[0][0];
4024 rsvd_check->rsvd_bits_mask[1][1] = 0;
4028 if (is_cpuid_PSE36())
4029 /* 36bits PSE 4MB page */
4030 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4032 /* 32 bits PSE 4MB page */
4033 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4035 case PT32E_ROOT_LEVEL:
4036 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4039 rsvd_bits(1, 2); /* PDPTE */
4040 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4041 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4042 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4043 rsvd_bits(13, 20); /* large page */
4044 rsvd_check->rsvd_bits_mask[1][0] =
4045 rsvd_check->rsvd_bits_mask[0][0];
4047 case PT64_ROOT_5LEVEL:
4048 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4051 rsvd_check->rsvd_bits_mask[1][4] =
4052 rsvd_check->rsvd_bits_mask[0][4];
4054 case PT64_ROOT_4LEVEL:
4055 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4058 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4060 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4061 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4062 rsvd_check->rsvd_bits_mask[1][3] =
4063 rsvd_check->rsvd_bits_mask[0][3];
4064 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4067 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4068 rsvd_bits(13, 20); /* large page */
4069 rsvd_check->rsvd_bits_mask[1][0] =
4070 rsvd_check->rsvd_bits_mask[0][0];
4075 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4076 struct kvm_mmu *context)
4078 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4079 vcpu->arch.reserved_gpa_bits,
4080 context->root_level, context->nx,
4081 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4083 guest_cpuid_is_amd_or_hygon(vcpu));
4087 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4088 u64 pa_bits_rsvd, bool execonly)
4090 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4093 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4094 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4095 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4096 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4097 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4100 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4101 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4102 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4103 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4104 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4106 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4107 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4108 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4109 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4110 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4112 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4113 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4115 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4118 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4119 struct kvm_mmu *context, bool execonly)
4121 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4122 vcpu->arch.reserved_gpa_bits, execonly);
4125 static inline u64 reserved_hpa_bits(void)
4127 return rsvd_bits(shadow_phys_bits, 63);
4131 * the page table on host is the shadow page table for the page
4132 * table in guest or amd nested guest, its mmu features completely
4133 * follow the features in guest.
4136 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4138 bool uses_nx = context->nx ||
4139 context->mmu_role.base.smep_andnot_wp;
4140 struct rsvd_bits_validate *shadow_zero_check;
4144 * Passing "true" to the last argument is okay; it adds a check
4145 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4147 shadow_zero_check = &context->shadow_zero_check;
4148 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4149 reserved_hpa_bits(),
4150 context->shadow_root_level, uses_nx,
4151 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4152 is_pse(vcpu), true);
4154 if (!shadow_me_mask)
4157 for (i = context->shadow_root_level; --i >= 0;) {
4158 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4159 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4163 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4165 static inline bool boot_cpu_is_amd(void)
4167 WARN_ON_ONCE(!tdp_enabled);
4168 return shadow_x_mask == 0;
4172 * the direct page table on host, use as much mmu features as
4173 * possible, however, kvm currently does not do execution-protection.
4176 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4177 struct kvm_mmu *context)
4179 struct rsvd_bits_validate *shadow_zero_check;
4182 shadow_zero_check = &context->shadow_zero_check;
4184 if (boot_cpu_is_amd())
4185 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4186 reserved_hpa_bits(),
4187 context->shadow_root_level, false,
4188 boot_cpu_has(X86_FEATURE_GBPAGES),
4191 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4192 reserved_hpa_bits(), false);
4194 if (!shadow_me_mask)
4197 for (i = context->shadow_root_level; --i >= 0;) {
4198 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4199 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4204 * as the comments in reset_shadow_zero_bits_mask() except it
4205 * is the shadow page table for intel nested guest.
4208 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4209 struct kvm_mmu *context, bool execonly)
4211 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4212 reserved_hpa_bits(), execonly);
4215 #define BYTE_MASK(access) \
4216 ((1 & (access) ? 2 : 0) | \
4217 (2 & (access) ? 4 : 0) | \
4218 (3 & (access) ? 8 : 0) | \
4219 (4 & (access) ? 16 : 0) | \
4220 (5 & (access) ? 32 : 0) | \
4221 (6 & (access) ? 64 : 0) | \
4222 (7 & (access) ? 128 : 0))
4225 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4226 struct kvm_mmu *mmu, bool ept)
4230 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4231 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4232 const u8 u = BYTE_MASK(ACC_USER_MASK);
4234 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4235 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4236 bool cr0_wp = is_write_protection(vcpu);
4238 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4239 unsigned pfec = byte << 1;
4242 * Each "*f" variable has a 1 bit for each UWX value
4243 * that causes a fault with the given PFEC.
4246 /* Faults from writes to non-writable pages */
4247 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4248 /* Faults from user mode accesses to supervisor pages */
4249 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4250 /* Faults from fetches of non-executable pages*/
4251 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4252 /* Faults from kernel mode fetches of user pages */
4254 /* Faults from kernel mode accesses of user pages */
4258 /* Faults from kernel mode accesses to user pages */
4259 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4261 /* Not really needed: !nx will cause pte.nx to fault */
4265 /* Allow supervisor writes if !cr0.wp */
4267 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4269 /* Disallow supervisor fetches of user code if cr4.smep */
4271 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4274 * SMAP:kernel-mode data accesses from user-mode
4275 * mappings should fault. A fault is considered
4276 * as a SMAP violation if all of the following
4277 * conditions are true:
4278 * - X86_CR4_SMAP is set in CR4
4279 * - A user page is accessed
4280 * - The access is not a fetch
4281 * - Page fault in kernel mode
4282 * - if CPL = 3 or X86_EFLAGS_AC is clear
4284 * Here, we cover the first three conditions.
4285 * The fourth is computed dynamically in permission_fault();
4286 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4287 * *not* subject to SMAP restrictions.
4290 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4293 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4298 * PKU is an additional mechanism by which the paging controls access to
4299 * user-mode addresses based on the value in the PKRU register. Protection
4300 * key violations are reported through a bit in the page fault error code.
4301 * Unlike other bits of the error code, the PK bit is not known at the
4302 * call site of e.g. gva_to_gpa; it must be computed directly in
4303 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4304 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4306 * In particular the following conditions come from the error code, the
4307 * page tables and the machine state:
4308 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4309 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4310 * - PK is always zero if U=0 in the page tables
4311 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4313 * The PKRU bitmask caches the result of these four conditions. The error
4314 * code (minus the P bit) and the page table's U bit form an index into the
4315 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4316 * with the two bits of the PKRU register corresponding to the protection key.
4317 * For the first three conditions above the bits will be 00, thus masking
4318 * away both AD and WD. For all reads or if the last condition holds, WD
4319 * only will be masked away.
4321 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4332 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4333 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4338 wp = is_write_protection(vcpu);
4340 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4341 unsigned pfec, pkey_bits;
4342 bool check_pkey, check_write, ff, uf, wf, pte_user;
4345 ff = pfec & PFERR_FETCH_MASK;
4346 uf = pfec & PFERR_USER_MASK;
4347 wf = pfec & PFERR_WRITE_MASK;
4349 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4350 pte_user = pfec & PFERR_RSVD_MASK;
4353 * Only need to check the access which is not an
4354 * instruction fetch and is to a user page.
4356 check_pkey = (!ff && pte_user);
4358 * write access is controlled by PKRU if it is a
4359 * user access or CR0.WP = 1.
4361 check_write = check_pkey && wf && (uf || wp);
4363 /* PKRU.AD stops both read and write access. */
4364 pkey_bits = !!check_pkey;
4365 /* PKRU.WD stops write access. */
4366 pkey_bits |= (!!check_write) << 1;
4368 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4372 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4374 unsigned root_level = mmu->root_level;
4376 mmu->last_nonleaf_level = root_level;
4377 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4378 mmu->last_nonleaf_level++;
4381 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4382 struct kvm_mmu *context,
4385 context->nx = is_nx(vcpu);
4386 context->root_level = level;
4388 reset_rsvds_bits_mask(vcpu, context);
4389 update_permission_bitmask(vcpu, context, false);
4390 update_pkru_bitmask(vcpu, context, false);
4391 update_last_nonleaf_level(vcpu, context);
4393 MMU_WARN_ON(!is_pae(vcpu));
4394 context->page_fault = paging64_page_fault;
4395 context->gva_to_gpa = paging64_gva_to_gpa;
4396 context->sync_page = paging64_sync_page;
4397 context->invlpg = paging64_invlpg;
4398 context->shadow_root_level = level;
4399 context->direct_map = false;
4402 static void paging64_init_context(struct kvm_vcpu *vcpu,
4403 struct kvm_mmu *context)
4405 int root_level = is_la57_mode(vcpu) ?
4406 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4408 paging64_init_context_common(vcpu, context, root_level);
4411 static void paging32_init_context(struct kvm_vcpu *vcpu,
4412 struct kvm_mmu *context)
4414 context->nx = false;
4415 context->root_level = PT32_ROOT_LEVEL;
4417 reset_rsvds_bits_mask(vcpu, context);
4418 update_permission_bitmask(vcpu, context, false);
4419 update_pkru_bitmask(vcpu, context, false);
4420 update_last_nonleaf_level(vcpu, context);
4422 context->page_fault = paging32_page_fault;
4423 context->gva_to_gpa = paging32_gva_to_gpa;
4424 context->sync_page = paging32_sync_page;
4425 context->invlpg = paging32_invlpg;
4426 context->shadow_root_level = PT32E_ROOT_LEVEL;
4427 context->direct_map = false;
4430 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4431 struct kvm_mmu *context)
4433 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4436 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4438 union kvm_mmu_extended_role ext = {0};
4440 ext.cr0_pg = !!is_paging(vcpu);
4441 ext.cr4_pae = !!is_pae(vcpu);
4442 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4443 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4444 ext.cr4_pse = !!is_pse(vcpu);
4445 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4446 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4453 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4456 union kvm_mmu_role role = {0};
4458 role.base.access = ACC_ALL;
4459 role.base.nxe = !!is_nx(vcpu);
4460 role.base.cr0_wp = is_write_protection(vcpu);
4461 role.base.smm = is_smm(vcpu);
4462 role.base.guest_mode = is_guest_mode(vcpu);
4467 role.ext = kvm_calc_mmu_role_ext(vcpu);
4472 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4474 /* Use 5-level TDP if and only if it's useful/necessary. */
4475 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4478 return max_tdp_level;
4481 static union kvm_mmu_role
4482 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4484 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4486 role.base.ad_disabled = (shadow_accessed_mask == 0);
4487 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4488 role.base.direct = true;
4489 role.base.gpte_is_8_bytes = true;
4494 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4496 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4497 union kvm_mmu_role new_role =
4498 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4500 if (new_role.as_u64 == context->mmu_role.as_u64)
4503 context->mmu_role.as_u64 = new_role.as_u64;
4504 context->page_fault = kvm_tdp_page_fault;
4505 context->sync_page = nonpaging_sync_page;
4506 context->invlpg = NULL;
4507 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4508 context->direct_map = true;
4509 context->get_guest_pgd = get_cr3;
4510 context->get_pdptr = kvm_pdptr_read;
4511 context->inject_page_fault = kvm_inject_page_fault;
4513 if (!is_paging(vcpu)) {
4514 context->nx = false;
4515 context->gva_to_gpa = nonpaging_gva_to_gpa;
4516 context->root_level = 0;
4517 } else if (is_long_mode(vcpu)) {
4518 context->nx = is_nx(vcpu);
4519 context->root_level = is_la57_mode(vcpu) ?
4520 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4521 reset_rsvds_bits_mask(vcpu, context);
4522 context->gva_to_gpa = paging64_gva_to_gpa;
4523 } else if (is_pae(vcpu)) {
4524 context->nx = is_nx(vcpu);
4525 context->root_level = PT32E_ROOT_LEVEL;
4526 reset_rsvds_bits_mask(vcpu, context);
4527 context->gva_to_gpa = paging64_gva_to_gpa;
4529 context->nx = false;
4530 context->root_level = PT32_ROOT_LEVEL;
4531 reset_rsvds_bits_mask(vcpu, context);
4532 context->gva_to_gpa = paging32_gva_to_gpa;
4535 update_permission_bitmask(vcpu, context, false);
4536 update_pkru_bitmask(vcpu, context, false);
4537 update_last_nonleaf_level(vcpu, context);
4538 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4541 static union kvm_mmu_role
4542 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4544 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4546 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4547 !is_write_protection(vcpu);
4548 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4549 !is_write_protection(vcpu);
4550 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4555 static union kvm_mmu_role
4556 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4558 union kvm_mmu_role role =
4559 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4561 role.base.direct = !is_paging(vcpu);
4563 if (!is_long_mode(vcpu))
4564 role.base.level = PT32E_ROOT_LEVEL;
4565 else if (is_la57_mode(vcpu))
4566 role.base.level = PT64_ROOT_5LEVEL;
4568 role.base.level = PT64_ROOT_4LEVEL;
4573 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4574 u32 cr0, u32 cr4, u32 efer,
4575 union kvm_mmu_role new_role)
4577 if (!(cr0 & X86_CR0_PG))
4578 nonpaging_init_context(vcpu, context);
4579 else if (efer & EFER_LMA)
4580 paging64_init_context(vcpu, context);
4581 else if (cr4 & X86_CR4_PAE)
4582 paging32E_init_context(vcpu, context);
4584 paging32_init_context(vcpu, context);
4586 context->mmu_role.as_u64 = new_role.as_u64;
4587 reset_shadow_zero_bits_mask(vcpu, context);
4590 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4592 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4593 union kvm_mmu_role new_role =
4594 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4596 if (new_role.as_u64 != context->mmu_role.as_u64)
4597 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4600 static union kvm_mmu_role
4601 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4603 union kvm_mmu_role role =
4604 kvm_calc_shadow_root_page_role_common(vcpu, false);
4606 role.base.direct = false;
4607 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4612 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
4615 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4616 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4618 context->shadow_root_level = new_role.base.level;
4620 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false);
4622 if (new_role.as_u64 != context->mmu_role.as_u64)
4623 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4625 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4627 static union kvm_mmu_role
4628 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4629 bool execonly, u8 level)
4631 union kvm_mmu_role role = {0};
4633 /* SMM flag is inherited from root_mmu */
4634 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4636 role.base.level = level;
4637 role.base.gpte_is_8_bytes = true;
4638 role.base.direct = false;
4639 role.base.ad_disabled = !accessed_dirty;
4640 role.base.guest_mode = true;
4641 role.base.access = ACC_ALL;
4644 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4645 * SMAP variation to denote shadow EPT entries.
4647 role.base.cr0_wp = true;
4648 role.base.smap_andnot_wp = true;
4650 role.ext = kvm_calc_mmu_role_ext(vcpu);
4651 role.ext.execonly = execonly;
4656 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4657 bool accessed_dirty, gpa_t new_eptp)
4659 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4660 u8 level = vmx_eptp_page_walk_level(new_eptp);
4661 union kvm_mmu_role new_role =
4662 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4665 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true);
4667 if (new_role.as_u64 == context->mmu_role.as_u64)
4670 context->shadow_root_level = level;
4673 context->ept_ad = accessed_dirty;
4674 context->page_fault = ept_page_fault;
4675 context->gva_to_gpa = ept_gva_to_gpa;
4676 context->sync_page = ept_sync_page;
4677 context->invlpg = ept_invlpg;
4678 context->root_level = level;
4679 context->direct_map = false;
4680 context->mmu_role.as_u64 = new_role.as_u64;
4682 update_permission_bitmask(vcpu, context, true);
4683 update_pkru_bitmask(vcpu, context, true);
4684 update_last_nonleaf_level(vcpu, context);
4685 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4686 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4688 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4690 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4692 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4694 kvm_init_shadow_mmu(vcpu,
4695 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
4696 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
4699 context->get_guest_pgd = get_cr3;
4700 context->get_pdptr = kvm_pdptr_read;
4701 context->inject_page_fault = kvm_inject_page_fault;
4704 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4706 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
4707 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4709 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4712 g_context->mmu_role.as_u64 = new_role.as_u64;
4713 g_context->get_guest_pgd = get_cr3;
4714 g_context->get_pdptr = kvm_pdptr_read;
4715 g_context->inject_page_fault = kvm_inject_page_fault;
4718 * L2 page tables are never shadowed, so there is no need to sync
4721 g_context->invlpg = NULL;
4724 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4725 * L1's nested page tables (e.g. EPT12). The nested translation
4726 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4727 * L2's page tables as the first level of translation and L1's
4728 * nested page tables as the second level of translation. Basically
4729 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4731 if (!is_paging(vcpu)) {
4732 g_context->nx = false;
4733 g_context->root_level = 0;
4734 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4735 } else if (is_long_mode(vcpu)) {
4736 g_context->nx = is_nx(vcpu);
4737 g_context->root_level = is_la57_mode(vcpu) ?
4738 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4739 reset_rsvds_bits_mask(vcpu, g_context);
4740 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4741 } else if (is_pae(vcpu)) {
4742 g_context->nx = is_nx(vcpu);
4743 g_context->root_level = PT32E_ROOT_LEVEL;
4744 reset_rsvds_bits_mask(vcpu, g_context);
4745 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4747 g_context->nx = false;
4748 g_context->root_level = PT32_ROOT_LEVEL;
4749 reset_rsvds_bits_mask(vcpu, g_context);
4750 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4753 update_permission_bitmask(vcpu, g_context, false);
4754 update_pkru_bitmask(vcpu, g_context, false);
4755 update_last_nonleaf_level(vcpu, g_context);
4758 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
4763 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
4765 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
4766 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
4769 if (mmu_is_nested(vcpu))
4770 init_kvm_nested_mmu(vcpu);
4771 else if (tdp_enabled)
4772 init_kvm_tdp_mmu(vcpu);
4774 init_kvm_softmmu(vcpu);
4776 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4778 static union kvm_mmu_page_role
4779 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4781 union kvm_mmu_role role;
4784 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4786 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4791 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4793 kvm_mmu_unload(vcpu);
4794 kvm_init_mmu(vcpu, true);
4796 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4798 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4802 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4805 r = mmu_alloc_roots(vcpu);
4806 kvm_mmu_sync_roots(vcpu);
4809 kvm_mmu_load_pgd(vcpu);
4810 static_call(kvm_x86_tlb_flush_current)(vcpu);
4814 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4816 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4818 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4819 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4820 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4821 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4823 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4825 static bool need_remote_flush(u64 old, u64 new)
4827 if (!is_shadow_present_pte(old))
4829 if (!is_shadow_present_pte(new))
4831 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4833 old ^= shadow_nx_mask;
4834 new ^= shadow_nx_mask;
4835 return (old & ~new & PT64_PERM_MASK) != 0;
4838 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4845 * Assume that the pte write on a page table of the same type
4846 * as the current vcpu paging mode since we update the sptes only
4847 * when they have the same mode.
4849 if (is_pae(vcpu) && *bytes == 4) {
4850 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4855 if (*bytes == 4 || *bytes == 8) {
4856 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
4865 * If we're seeing too many writes to a page, it may no longer be a page table,
4866 * or we may be forking, in which case it is better to unmap the page.
4868 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4871 * Skip write-flooding detected for the sp whose level is 1, because
4872 * it can become unsync, then the guest page is not write-protected.
4874 if (sp->role.level == PG_LEVEL_4K)
4877 atomic_inc(&sp->write_flooding_count);
4878 return atomic_read(&sp->write_flooding_count) >= 3;
4882 * Misaligned accesses are too much trouble to fix up; also, they usually
4883 * indicate a page is not used as a page table.
4885 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4888 unsigned offset, pte_size, misaligned;
4890 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4891 gpa, bytes, sp->role.word);
4893 offset = offset_in_page(gpa);
4894 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
4897 * Sometimes, the OS only writes the last one bytes to update status
4898 * bits, for example, in linux, andb instruction is used in clear_bit().
4900 if (!(offset & (pte_size - 1)) && bytes == 1)
4903 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4904 misaligned |= bytes < 4;
4909 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4911 unsigned page_offset, quadrant;
4915 page_offset = offset_in_page(gpa);
4916 level = sp->role.level;
4918 if (!sp->role.gpte_is_8_bytes) {
4919 page_offset <<= 1; /* 32->64 */
4921 * A 32-bit pde maps 4MB while the shadow pdes map
4922 * only 2MB. So we need to double the offset again
4923 * and zap two pdes instead of one.
4925 if (level == PT32_ROOT_LEVEL) {
4926 page_offset &= ~7; /* kill rounding error */
4930 quadrant = page_offset >> PAGE_SHIFT;
4931 page_offset &= ~PAGE_MASK;
4932 if (quadrant != sp->role.quadrant)
4936 spte = &sp->spt[page_offset / sizeof(*spte)];
4940 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4941 const u8 *new, int bytes,
4942 struct kvm_page_track_notifier_node *node)
4944 gfn_t gfn = gpa >> PAGE_SHIFT;
4945 struct kvm_mmu_page *sp;
4946 LIST_HEAD(invalid_list);
4947 u64 entry, gentry, *spte;
4949 bool remote_flush, local_flush;
4952 * If we don't have indirect shadow pages, it means no page is
4953 * write-protected, so we can exit simply.
4955 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4958 remote_flush = local_flush = false;
4960 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4963 * No need to care whether allocation memory is successful
4964 * or not since pte prefetch is skiped if it does not have
4965 * enough objects in the cache.
4967 mmu_topup_memory_caches(vcpu, true);
4969 write_lock(&vcpu->kvm->mmu_lock);
4971 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
4973 ++vcpu->kvm->stat.mmu_pte_write;
4974 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4976 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4977 if (detect_write_misaligned(sp, gpa, bytes) ||
4978 detect_write_flooding(sp)) {
4979 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4980 ++vcpu->kvm->stat.mmu_flooded;
4984 spte = get_written_sptes(sp, gpa, &npte);
4991 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
4992 if (gentry && sp->role.level != PG_LEVEL_4K)
4993 ++vcpu->kvm->stat.mmu_pde_zapped;
4994 if (need_remote_flush(entry, *spte))
4995 remote_flush = true;
4999 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5000 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5001 write_unlock(&vcpu->kvm->mmu_lock);
5004 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5005 void *insn, int insn_len)
5007 int r, emulation_type = EMULTYPE_PF;
5008 bool direct = vcpu->arch.mmu->direct_map;
5010 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5011 return RET_PF_RETRY;
5014 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5015 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5016 if (r == RET_PF_EMULATE)
5020 if (r == RET_PF_INVALID) {
5021 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5022 lower_32_bits(error_code), false);
5023 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5029 if (r != RET_PF_EMULATE)
5033 * Before emulating the instruction, check if the error code
5034 * was due to a RO violation while translating the guest page.
5035 * This can occur when using nested virtualization with nested
5036 * paging in both guests. If true, we simply unprotect the page
5037 * and resume the guest.
5039 if (vcpu->arch.mmu->direct_map &&
5040 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5041 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5046 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5047 * optimistically try to just unprotect the page and let the processor
5048 * re-execute the instruction that caused the page fault. Do not allow
5049 * retrying MMIO emulation, as it's not only pointless but could also
5050 * cause us to enter an infinite loop because the processor will keep
5051 * faulting on the non-existent MMIO address. Retrying an instruction
5052 * from a nested guest is also pointless and dangerous as we are only
5053 * explicitly shadowing L1's page tables, i.e. unprotecting something
5054 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5056 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5057 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5059 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5062 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5064 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5065 gva_t gva, hpa_t root_hpa)
5069 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5070 if (mmu != &vcpu->arch.guest_mmu) {
5071 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5072 if (is_noncanonical_address(gva, vcpu))
5075 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5081 if (root_hpa == INVALID_PAGE) {
5082 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5085 * INVLPG is required to invalidate any global mappings for the VA,
5086 * irrespective of PCID. Since it would take us roughly similar amount
5087 * of work to determine whether any of the prev_root mappings of the VA
5088 * is marked global, or to just sync it blindly, so we might as well
5089 * just always sync it.
5091 * Mappings not reachable via the current cr3 or the prev_roots will be
5092 * synced when switching to that cr3, so nothing needs to be done here
5095 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5096 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5097 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5099 mmu->invlpg(vcpu, gva, root_hpa);
5103 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5105 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5106 ++vcpu->stat.invlpg;
5108 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5111 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5113 struct kvm_mmu *mmu = vcpu->arch.mmu;
5114 bool tlb_flush = false;
5117 if (pcid == kvm_get_active_pcid(vcpu)) {
5118 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5122 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5123 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5124 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5125 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5131 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5133 ++vcpu->stat.invlpg;
5136 * Mappings not reachable via the current cr3 or the prev_roots will be
5137 * synced when switching to that cr3, so nothing needs to be done here
5142 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5143 int tdp_huge_page_level)
5145 tdp_enabled = enable_tdp;
5146 max_tdp_level = tdp_max_root_level;
5149 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5150 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5151 * the kernel is not. But, KVM never creates a page size greater than
5152 * what is used by the kernel for any given HVA, i.e. the kernel's
5153 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5156 max_huge_page_level = tdp_huge_page_level;
5157 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5158 max_huge_page_level = PG_LEVEL_1G;
5160 max_huge_page_level = PG_LEVEL_2M;
5162 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5164 /* The return value indicates if tlb flush on all vcpus is needed. */
5165 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head,
5166 struct kvm_memory_slot *slot);
5168 /* The caller should hold mmu-lock before calling this function. */
5169 static __always_inline bool
5170 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5171 slot_level_handler fn, int start_level, int end_level,
5172 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5174 struct slot_rmap_walk_iterator iterator;
5177 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5178 end_gfn, &iterator) {
5180 flush |= fn(kvm, iterator.rmap, memslot);
5182 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5183 if (flush && lock_flush_tlb) {
5184 kvm_flush_remote_tlbs_with_address(kvm,
5186 iterator.gfn - start_gfn + 1);
5189 cond_resched_rwlock_write(&kvm->mmu_lock);
5193 if (flush && lock_flush_tlb) {
5194 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5195 end_gfn - start_gfn + 1);
5202 static __always_inline bool
5203 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5204 slot_level_handler fn, int start_level, int end_level,
5205 bool lock_flush_tlb)
5207 return slot_handle_level_range(kvm, memslot, fn, start_level,
5208 end_level, memslot->base_gfn,
5209 memslot->base_gfn + memslot->npages - 1,
5213 static __always_inline bool
5214 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5215 slot_level_handler fn, bool lock_flush_tlb)
5217 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5218 PG_LEVEL_4K, lock_flush_tlb);
5221 static void free_mmu_pages(struct kvm_mmu *mmu)
5223 free_page((unsigned long)mmu->pae_root);
5224 free_page((unsigned long)mmu->lm_root);
5227 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5232 mmu->root_hpa = INVALID_PAGE;
5234 mmu->translate_gpa = translate_gpa;
5235 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5236 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5239 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5240 * while the PDP table is a per-vCPU construct that's allocated at MMU
5241 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5242 * x86_64. Therefore we need to allocate the PDP table in the first
5243 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5244 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5245 * skip allocating the PDP table.
5247 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5250 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5254 mmu->pae_root = page_address(page);
5255 for (i = 0; i < 4; ++i)
5256 mmu->pae_root[i] = INVALID_PAGE;
5261 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5265 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5266 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5268 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5269 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5271 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5273 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5274 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5276 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5278 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5282 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5284 goto fail_allocate_root;
5288 free_mmu_pages(&vcpu->arch.guest_mmu);
5292 #define BATCH_ZAP_PAGES 10
5293 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5295 struct kvm_mmu_page *sp, *node;
5296 int nr_zapped, batch = 0;
5299 list_for_each_entry_safe_reverse(sp, node,
5300 &kvm->arch.active_mmu_pages, link) {
5302 * No obsolete valid page exists before a newly created page
5303 * since active_mmu_pages is a FIFO list.
5305 if (!is_obsolete_sp(kvm, sp))
5309 * Invalid pages should never land back on the list of active
5310 * pages. Skip the bogus page, otherwise we'll get stuck in an
5311 * infinite loop if the page gets put back on the list (again).
5313 if (WARN_ON(sp->role.invalid))
5317 * No need to flush the TLB since we're only zapping shadow
5318 * pages with an obsolete generation number and all vCPUS have
5319 * loaded a new root, i.e. the shadow pages being zapped cannot
5320 * be in active use by the guest.
5322 if (batch >= BATCH_ZAP_PAGES &&
5323 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5328 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5329 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5336 * Trigger a remote TLB flush before freeing the page tables to ensure
5337 * KVM is not in the middle of a lockless shadow page table walk, which
5338 * may reference the pages.
5340 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5344 * Fast invalidate all shadow pages and use lock-break technique
5345 * to zap obsolete pages.
5347 * It's required when memslot is being deleted or VM is being
5348 * destroyed, in these cases, we should ensure that KVM MMU does
5349 * not use any resource of the being-deleted slot or all slots
5350 * after calling the function.
5352 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5354 lockdep_assert_held(&kvm->slots_lock);
5356 write_lock(&kvm->mmu_lock);
5357 trace_kvm_mmu_zap_all_fast(kvm);
5360 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5361 * held for the entire duration of zapping obsolete pages, it's
5362 * impossible for there to be multiple invalid generations associated
5363 * with *valid* shadow pages at any given time, i.e. there is exactly
5364 * one valid generation and (at most) one invalid generation.
5366 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5369 * Notify all vcpus to reload its shadow page table and flush TLB.
5370 * Then all vcpus will switch to new shadow page table with the new
5373 * Note: we need to do this under the protection of mmu_lock,
5374 * otherwise, vcpu would purge shadow page but miss tlb flush.
5376 kvm_reload_remote_mmus(kvm);
5378 kvm_zap_obsolete_pages(kvm);
5380 if (is_tdp_mmu_enabled(kvm))
5381 kvm_tdp_mmu_zap_all(kvm);
5383 write_unlock(&kvm->mmu_lock);
5386 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5388 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5391 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5392 struct kvm_memory_slot *slot,
5393 struct kvm_page_track_notifier_node *node)
5395 kvm_mmu_zap_all_fast(kvm);
5398 void kvm_mmu_init_vm(struct kvm *kvm)
5400 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5402 kvm_mmu_init_tdp_mmu(kvm);
5404 node->track_write = kvm_mmu_pte_write;
5405 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5406 kvm_page_track_register_notifier(kvm, node);
5409 void kvm_mmu_uninit_vm(struct kvm *kvm)
5411 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5413 kvm_page_track_unregister_notifier(kvm, node);
5415 kvm_mmu_uninit_tdp_mmu(kvm);
5418 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5420 struct kvm_memslots *slots;
5421 struct kvm_memory_slot *memslot;
5425 write_lock(&kvm->mmu_lock);
5426 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5427 slots = __kvm_memslots(kvm, i);
5428 kvm_for_each_memslot(memslot, slots) {
5431 start = max(gfn_start, memslot->base_gfn);
5432 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5436 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5438 KVM_MAX_HUGEPAGE_LEVEL,
5439 start, end - 1, true);
5443 if (is_tdp_mmu_enabled(kvm)) {
5444 flush = kvm_tdp_mmu_zap_gfn_range(kvm, gfn_start, gfn_end);
5446 kvm_flush_remote_tlbs(kvm);
5449 write_unlock(&kvm->mmu_lock);
5452 static bool slot_rmap_write_protect(struct kvm *kvm,
5453 struct kvm_rmap_head *rmap_head,
5454 struct kvm_memory_slot *slot)
5456 return __rmap_write_protect(kvm, rmap_head, false);
5459 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5460 struct kvm_memory_slot *memslot,
5465 write_lock(&kvm->mmu_lock);
5466 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5467 start_level, KVM_MAX_HUGEPAGE_LEVEL, false);
5468 if (is_tdp_mmu_enabled(kvm))
5469 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, PG_LEVEL_4K);
5470 write_unlock(&kvm->mmu_lock);
5473 * We can flush all the TLBs out of the mmu lock without TLB
5474 * corruption since we just change the spte from writable to
5475 * readonly so that we only need to care the case of changing
5476 * spte from present to present (changing the spte from present
5477 * to nonpresent will flush all the TLBs immediately), in other
5478 * words, the only case we care is mmu_spte_update() where we
5479 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5480 * instead of PT_WRITABLE_MASK, that means it does not depend
5481 * on PT_WRITABLE_MASK anymore.
5484 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5487 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5488 struct kvm_rmap_head *rmap_head,
5489 struct kvm_memory_slot *slot)
5492 struct rmap_iterator iter;
5493 int need_tlb_flush = 0;
5495 struct kvm_mmu_page *sp;
5498 for_each_rmap_spte(rmap_head, &iter, sptep) {
5499 sp = sptep_to_sp(sptep);
5500 pfn = spte_to_pfn(*sptep);
5503 * We cannot do huge page mapping for indirect shadow pages,
5504 * which are found on the last rmap (level = 1) when not using
5505 * tdp; such shadow pages are synced with the page table in
5506 * the guest, and the guest page table is using 4K page size
5507 * mapping if the indirect sp has level = 1.
5509 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5510 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5511 pfn, PG_LEVEL_NUM)) {
5512 pte_list_remove(rmap_head, sptep);
5514 if (kvm_available_flush_tlb_with_range())
5515 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5516 KVM_PAGES_PER_HPAGE(sp->role.level));
5524 return need_tlb_flush;
5527 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5528 const struct kvm_memory_slot *memslot)
5530 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5531 struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot;
5533 write_lock(&kvm->mmu_lock);
5534 slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5536 if (is_tdp_mmu_enabled(kvm))
5537 kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot);
5538 write_unlock(&kvm->mmu_lock);
5541 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5542 struct kvm_memory_slot *memslot)
5545 * All current use cases for flushing the TLBs for a specific memslot
5546 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5547 * The interaction between the various operations on memslot must be
5548 * serialized by slots_locks to ensure the TLB flush from one operation
5549 * is observed by any other operation on the same memslot.
5551 lockdep_assert_held(&kvm->slots_lock);
5552 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5556 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5557 struct kvm_memory_slot *memslot)
5561 write_lock(&kvm->mmu_lock);
5562 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5563 if (is_tdp_mmu_enabled(kvm))
5564 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5565 write_unlock(&kvm->mmu_lock);
5568 * It's also safe to flush TLBs out of mmu lock here as currently this
5569 * function is only used for dirty logging, in which case flushing TLB
5570 * out of mmu lock also guarantees no dirty pages will be lost in
5574 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5577 void kvm_mmu_zap_all(struct kvm *kvm)
5579 struct kvm_mmu_page *sp, *node;
5580 LIST_HEAD(invalid_list);
5583 write_lock(&kvm->mmu_lock);
5585 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5586 if (WARN_ON(sp->role.invalid))
5588 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5590 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5594 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5596 if (is_tdp_mmu_enabled(kvm))
5597 kvm_tdp_mmu_zap_all(kvm);
5599 write_unlock(&kvm->mmu_lock);
5602 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5604 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5606 gen &= MMIO_SPTE_GEN_MASK;
5609 * Generation numbers are incremented in multiples of the number of
5610 * address spaces in order to provide unique generations across all
5611 * address spaces. Strip what is effectively the address space
5612 * modifier prior to checking for a wrap of the MMIO generation so
5613 * that a wrap in any address space is detected.
5615 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5618 * The very rare case: if the MMIO generation number has wrapped,
5619 * zap all shadow pages.
5621 if (unlikely(gen == 0)) {
5622 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5623 kvm_mmu_zap_all_fast(kvm);
5627 static unsigned long
5628 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5631 int nr_to_scan = sc->nr_to_scan;
5632 unsigned long freed = 0;
5634 mutex_lock(&kvm_lock);
5636 list_for_each_entry(kvm, &vm_list, vm_list) {
5638 LIST_HEAD(invalid_list);
5641 * Never scan more than sc->nr_to_scan VM instances.
5642 * Will not hit this condition practically since we do not try
5643 * to shrink more than one VM and it is very unlikely to see
5644 * !n_used_mmu_pages so many times.
5649 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5650 * here. We may skip a VM instance errorneosly, but we do not
5651 * want to shrink a VM that only started to populate its MMU
5654 if (!kvm->arch.n_used_mmu_pages &&
5655 !kvm_has_zapped_obsolete_pages(kvm))
5658 idx = srcu_read_lock(&kvm->srcu);
5659 write_lock(&kvm->mmu_lock);
5661 if (kvm_has_zapped_obsolete_pages(kvm)) {
5662 kvm_mmu_commit_zap_page(kvm,
5663 &kvm->arch.zapped_obsolete_pages);
5667 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5670 write_unlock(&kvm->mmu_lock);
5671 srcu_read_unlock(&kvm->srcu, idx);
5674 * unfair on small ones
5675 * per-vm shrinkers cry out
5676 * sadness comes quickly
5678 list_move_tail(&kvm->vm_list, &vm_list);
5682 mutex_unlock(&kvm_lock);
5686 static unsigned long
5687 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5689 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5692 static struct shrinker mmu_shrinker = {
5693 .count_objects = mmu_shrink_count,
5694 .scan_objects = mmu_shrink_scan,
5695 .seeks = DEFAULT_SEEKS * 10,
5698 static void mmu_destroy_caches(void)
5700 kmem_cache_destroy(pte_list_desc_cache);
5701 kmem_cache_destroy(mmu_page_header_cache);
5704 static void kvm_set_mmio_spte_mask(void)
5709 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
5710 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
5711 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
5712 * 52-bit physical addresses then there are no reserved PA bits in the
5713 * PTEs and so the reserved PA approach must be disabled.
5715 if (shadow_phys_bits < 52)
5716 mask = BIT_ULL(51) | PT_PRESENT_MASK;
5720 kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK);
5723 static bool get_nx_auto_mode(void)
5725 /* Return true when CPU has the bug, and mitigations are ON */
5726 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5729 static void __set_nx_huge_pages(bool val)
5731 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5734 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5736 bool old_val = nx_huge_pages;
5739 /* In "auto" mode deploy workaround only if CPU has the bug. */
5740 if (sysfs_streq(val, "off"))
5742 else if (sysfs_streq(val, "force"))
5744 else if (sysfs_streq(val, "auto"))
5745 new_val = get_nx_auto_mode();
5746 else if (strtobool(val, &new_val) < 0)
5749 __set_nx_huge_pages(new_val);
5751 if (new_val != old_val) {
5754 mutex_lock(&kvm_lock);
5756 list_for_each_entry(kvm, &vm_list, vm_list) {
5757 mutex_lock(&kvm->slots_lock);
5758 kvm_mmu_zap_all_fast(kvm);
5759 mutex_unlock(&kvm->slots_lock);
5761 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5763 mutex_unlock(&kvm_lock);
5769 int kvm_mmu_module_init(void)
5773 if (nx_huge_pages == -1)
5774 __set_nx_huge_pages(get_nx_auto_mode());
5777 * MMU roles use union aliasing which is, generally speaking, an
5778 * undefined behavior. However, we supposedly know how compilers behave
5779 * and the current status quo is unlikely to change. Guardians below are
5780 * supposed to let us know if the assumption becomes false.
5782 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5783 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5784 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5786 kvm_mmu_reset_all_pte_masks();
5788 kvm_set_mmio_spte_mask();
5790 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5791 sizeof(struct pte_list_desc),
5792 0, SLAB_ACCOUNT, NULL);
5793 if (!pte_list_desc_cache)
5796 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5797 sizeof(struct kvm_mmu_page),
5798 0, SLAB_ACCOUNT, NULL);
5799 if (!mmu_page_header_cache)
5802 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5805 ret = register_shrinker(&mmu_shrinker);
5812 mmu_destroy_caches();
5817 * Calculate mmu pages needed for kvm.
5819 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
5821 unsigned long nr_mmu_pages;
5822 unsigned long nr_pages = 0;
5823 struct kvm_memslots *slots;
5824 struct kvm_memory_slot *memslot;
5827 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5828 slots = __kvm_memslots(kvm, i);
5830 kvm_for_each_memslot(memslot, slots)
5831 nr_pages += memslot->npages;
5834 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5835 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
5837 return nr_mmu_pages;
5840 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5842 kvm_mmu_unload(vcpu);
5843 free_mmu_pages(&vcpu->arch.root_mmu);
5844 free_mmu_pages(&vcpu->arch.guest_mmu);
5845 mmu_free_memory_caches(vcpu);
5848 void kvm_mmu_module_exit(void)
5850 mmu_destroy_caches();
5851 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5852 unregister_shrinker(&mmu_shrinker);
5853 mmu_audit_disable();
5856 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
5858 unsigned int old_val;
5861 old_val = nx_huge_pages_recovery_ratio;
5862 err = param_set_uint(val, kp);
5866 if (READ_ONCE(nx_huge_pages) &&
5867 !old_val && nx_huge_pages_recovery_ratio) {
5870 mutex_lock(&kvm_lock);
5872 list_for_each_entry(kvm, &vm_list, vm_list)
5873 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5875 mutex_unlock(&kvm_lock);
5881 static void kvm_recover_nx_lpages(struct kvm *kvm)
5884 struct kvm_mmu_page *sp;
5886 LIST_HEAD(invalid_list);
5890 rcu_idx = srcu_read_lock(&kvm->srcu);
5891 write_lock(&kvm->mmu_lock);
5893 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
5894 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
5895 for ( ; to_zap; --to_zap) {
5896 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
5900 * We use a separate list instead of just using active_mmu_pages
5901 * because the number of lpage_disallowed pages is expected to
5902 * be relatively small compared to the total.
5904 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
5905 struct kvm_mmu_page,
5906 lpage_disallowed_link);
5907 WARN_ON_ONCE(!sp->lpage_disallowed);
5908 if (is_tdp_mmu_page(sp)) {
5909 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
5911 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
5912 WARN_ON_ONCE(sp->lpage_disallowed);
5915 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5916 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
5917 cond_resched_rwlock_write(&kvm->mmu_lock);
5921 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
5923 write_unlock(&kvm->mmu_lock);
5924 srcu_read_unlock(&kvm->srcu, rcu_idx);
5927 static long get_nx_lpage_recovery_timeout(u64 start_time)
5929 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
5930 ? start_time + 60 * HZ - get_jiffies_64()
5931 : MAX_SCHEDULE_TIMEOUT;
5934 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
5937 long remaining_time;
5940 start_time = get_jiffies_64();
5941 remaining_time = get_nx_lpage_recovery_timeout(start_time);
5943 set_current_state(TASK_INTERRUPTIBLE);
5944 while (!kthread_should_stop() && remaining_time > 0) {
5945 schedule_timeout(remaining_time);
5946 remaining_time = get_nx_lpage_recovery_timeout(start_time);
5947 set_current_state(TASK_INTERRUPTIBLE);
5950 set_current_state(TASK_RUNNING);
5952 if (kthread_should_stop())
5955 kvm_recover_nx_lpages(kvm);
5959 int kvm_mmu_post_init_vm(struct kvm *kvm)
5963 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
5964 "kvm-nx-lpage-recovery",
5965 &kvm->arch.nx_lpage_recovery_thread);
5967 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
5972 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
5974 if (kvm->arch.nx_lpage_recovery_thread)
5975 kthread_stop(kvm->arch.nx_lpage_recovery_thread);