1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
52 #include <asm/kvm_page_track.h>
55 extern bool itlb_multihit_kvm_mitigation;
57 static int __read_mostly nx_huge_pages = -1;
58 #ifdef CONFIG_PREEMPT_RT
59 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
60 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
62 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
65 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
66 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops nx_huge_pages_ops = {
69 .set = set_nx_huge_pages,
70 .get = param_get_bool,
73 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
74 .set = set_nx_huge_pages_recovery_ratio,
75 .get = param_get_uint,
78 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
79 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
80 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
81 &nx_huge_pages_recovery_ratio, 0644);
82 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
84 static bool __read_mostly force_flush_and_sync_on_reuse;
85 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
88 * When setting this variable to true it enables Two-Dimensional-Paging
89 * where the hardware walks 2 page tables:
90 * 1. the guest-virtual to guest-physical
91 * 2. while doing 1. it walks guest-physical to host-physical
92 * If the hardware supports that we don't need to do shadow paging.
94 bool tdp_enabled = false;
96 static int max_huge_page_level __read_mostly;
97 static int max_tdp_level __read_mostly;
100 AUDIT_PRE_PAGE_FAULT,
101 AUDIT_POST_PAGE_FAULT,
103 AUDIT_POST_PTE_WRITE,
110 module_param(dbg, bool, 0644);
113 #define PTE_PREFETCH_NUM 8
115 #define PT32_LEVEL_BITS 10
117 #define PT32_LEVEL_SHIFT(level) \
118 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
120 #define PT32_LVL_OFFSET_MASK(level) \
121 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
122 * PT32_LEVEL_BITS))) - 1))
124 #define PT32_INDEX(address, level)\
125 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #include <trace/events/kvm.h>
137 /* make pte_list_desc fit well in cache line */
138 #define PTE_LIST_EXT 3
140 struct pte_list_desc {
141 u64 *sptes[PTE_LIST_EXT];
142 struct pte_list_desc *more;
145 struct kvm_shadow_walk_iterator {
153 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
154 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
156 shadow_walk_okay(&(_walker)); \
157 shadow_walk_next(&(_walker)))
159 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
160 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
161 shadow_walk_okay(&(_walker)); \
162 shadow_walk_next(&(_walker)))
164 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
165 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
166 shadow_walk_okay(&(_walker)) && \
167 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
168 __shadow_walk_next(&(_walker), spte))
170 static struct kmem_cache *pte_list_desc_cache;
171 struct kmem_cache *mmu_page_header_cache;
172 static struct percpu_counter kvm_total_used_mmu_pages;
174 static void mmu_spte_set(u64 *sptep, u64 spte);
175 static union kvm_mmu_page_role
176 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
178 #define CREATE_TRACE_POINTS
179 #include "mmutrace.h"
182 static inline bool kvm_available_flush_tlb_with_range(void)
184 return kvm_x86_ops.tlb_remote_flush_with_range;
187 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
188 struct kvm_tlb_range *range)
192 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
193 ret = kvm_x86_ops.tlb_remote_flush_with_range(kvm, range);
196 kvm_flush_remote_tlbs(kvm);
199 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
200 u64 start_gfn, u64 pages)
202 struct kvm_tlb_range range;
204 range.start_gfn = start_gfn;
207 kvm_flush_remote_tlbs_with_range(kvm, &range);
210 bool is_nx_huge_page_enabled(void)
212 return READ_ONCE(nx_huge_pages);
215 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
218 u64 mask = make_mmio_spte(vcpu, gfn, access);
220 trace_mark_mmio_spte(sptep, gfn, mask);
221 mmu_spte_set(sptep, mask);
224 static gfn_t get_mmio_spte_gfn(u64 spte)
226 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
228 gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
229 & shadow_nonpresent_or_rsvd_mask;
231 return gpa >> PAGE_SHIFT;
234 static unsigned get_mmio_spte_access(u64 spte)
236 return spte & shadow_mmio_access_mask;
239 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
240 kvm_pfn_t pfn, unsigned int access)
242 if (unlikely(is_noslot_pfn(pfn))) {
243 mark_mmio_spte(vcpu, sptep, gfn, access);
250 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
252 u64 kvm_gen, spte_gen, gen;
254 gen = kvm_vcpu_memslots(vcpu)->generation;
255 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
258 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
259 spte_gen = get_mmio_spte_generation(spte);
261 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
262 return likely(kvm_gen == spte_gen);
265 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
266 struct x86_exception *exception)
268 /* Check if guest physical address doesn't exceed guest maximum */
269 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
270 exception->error_code |= PFERR_RSVD_MASK;
277 static int is_cpuid_PSE36(void)
282 static int is_nx(struct kvm_vcpu *vcpu)
284 return vcpu->arch.efer & EFER_NX;
287 static gfn_t pse36_gfn_delta(u32 gpte)
289 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
291 return (gpte & PT32_DIR_PSE36_MASK) << shift;
295 static void __set_spte(u64 *sptep, u64 spte)
297 WRITE_ONCE(*sptep, spte);
300 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
302 WRITE_ONCE(*sptep, spte);
305 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
307 return xchg(sptep, spte);
310 static u64 __get_spte_lockless(u64 *sptep)
312 return READ_ONCE(*sptep);
323 static void count_spte_clear(u64 *sptep, u64 spte)
325 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
327 if (is_shadow_present_pte(spte))
330 /* Ensure the spte is completely set before we increase the count */
332 sp->clear_spte_count++;
335 static void __set_spte(u64 *sptep, u64 spte)
337 union split_spte *ssptep, sspte;
339 ssptep = (union split_spte *)sptep;
340 sspte = (union split_spte)spte;
342 ssptep->spte_high = sspte.spte_high;
345 * If we map the spte from nonpresent to present, We should store
346 * the high bits firstly, then set present bit, so cpu can not
347 * fetch this spte while we are setting the spte.
351 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
354 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
356 union split_spte *ssptep, sspte;
358 ssptep = (union split_spte *)sptep;
359 sspte = (union split_spte)spte;
361 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
364 * If we map the spte from present to nonpresent, we should clear
365 * present bit firstly to avoid vcpu fetch the old high bits.
369 ssptep->spte_high = sspte.spte_high;
370 count_spte_clear(sptep, spte);
373 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
375 union split_spte *ssptep, sspte, orig;
377 ssptep = (union split_spte *)sptep;
378 sspte = (union split_spte)spte;
380 /* xchg acts as a barrier before the setting of the high bits */
381 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
382 orig.spte_high = ssptep->spte_high;
383 ssptep->spte_high = sspte.spte_high;
384 count_spte_clear(sptep, spte);
390 * The idea using the light way get the spte on x86_32 guest is from
391 * gup_get_pte (mm/gup.c).
393 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
394 * coalesces them and we are running out of the MMU lock. Therefore
395 * we need to protect against in-progress updates of the spte.
397 * Reading the spte while an update is in progress may get the old value
398 * for the high part of the spte. The race is fine for a present->non-present
399 * change (because the high part of the spte is ignored for non-present spte),
400 * but for a present->present change we must reread the spte.
402 * All such changes are done in two steps (present->non-present and
403 * non-present->present), hence it is enough to count the number of
404 * present->non-present updates: if it changed while reading the spte,
405 * we might have hit the race. This is done using clear_spte_count.
407 static u64 __get_spte_lockless(u64 *sptep)
409 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
410 union split_spte spte, *orig = (union split_spte *)sptep;
414 count = sp->clear_spte_count;
417 spte.spte_low = orig->spte_low;
420 spte.spte_high = orig->spte_high;
423 if (unlikely(spte.spte_low != orig->spte_low ||
424 count != sp->clear_spte_count))
431 static bool spte_has_volatile_bits(u64 spte)
433 if (!is_shadow_present_pte(spte))
437 * Always atomically update spte if it can be updated
438 * out of mmu-lock, it can ensure dirty bit is not lost,
439 * also, it can help us to get a stable is_writable_pte()
440 * to ensure tlb flush is not missed.
442 if (spte_can_locklessly_be_made_writable(spte) ||
443 is_access_track_spte(spte))
446 if (spte_ad_enabled(spte)) {
447 if ((spte & shadow_accessed_mask) == 0 ||
448 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
455 /* Rules for using mmu_spte_set:
456 * Set the sptep from nonpresent to present.
457 * Note: the sptep being assigned *must* be either not present
458 * or in a state where the hardware will not attempt to update
461 static void mmu_spte_set(u64 *sptep, u64 new_spte)
463 WARN_ON(is_shadow_present_pte(*sptep));
464 __set_spte(sptep, new_spte);
468 * Update the SPTE (excluding the PFN), but do not track changes in its
469 * accessed/dirty status.
471 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
473 u64 old_spte = *sptep;
475 WARN_ON(!is_shadow_present_pte(new_spte));
477 if (!is_shadow_present_pte(old_spte)) {
478 mmu_spte_set(sptep, new_spte);
482 if (!spte_has_volatile_bits(old_spte))
483 __update_clear_spte_fast(sptep, new_spte);
485 old_spte = __update_clear_spte_slow(sptep, new_spte);
487 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
492 /* Rules for using mmu_spte_update:
493 * Update the state bits, it means the mapped pfn is not changed.
495 * Whenever we overwrite a writable spte with a read-only one we
496 * should flush remote TLBs. Otherwise rmap_write_protect
497 * will find a read-only spte, even though the writable spte
498 * might be cached on a CPU's TLB, the return value indicates this
501 * Returns true if the TLB needs to be flushed
503 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
506 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
508 if (!is_shadow_present_pte(old_spte))
512 * For the spte updated out of mmu-lock is safe, since
513 * we always atomically update it, see the comments in
514 * spte_has_volatile_bits().
516 if (spte_can_locklessly_be_made_writable(old_spte) &&
517 !is_writable_pte(new_spte))
521 * Flush TLB when accessed/dirty states are changed in the page tables,
522 * to guarantee consistency between TLB and page tables.
525 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
527 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
530 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
532 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
539 * Rules for using mmu_spte_clear_track_bits:
540 * It sets the sptep from present to nonpresent, and track the
541 * state bits, it is used to clear the last level sptep.
542 * Returns non-zero if the PTE was previously valid.
544 static int mmu_spte_clear_track_bits(u64 *sptep)
547 u64 old_spte = *sptep;
549 if (!spte_has_volatile_bits(old_spte))
550 __update_clear_spte_fast(sptep, 0ull);
552 old_spte = __update_clear_spte_slow(sptep, 0ull);
554 if (!is_shadow_present_pte(old_spte))
557 pfn = spte_to_pfn(old_spte);
560 * KVM does not hold the refcount of the page used by
561 * kvm mmu, before reclaiming the page, we should
562 * unmap it from mmu first.
564 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
566 if (is_accessed_spte(old_spte))
567 kvm_set_pfn_accessed(pfn);
569 if (is_dirty_spte(old_spte))
570 kvm_set_pfn_dirty(pfn);
576 * Rules for using mmu_spte_clear_no_track:
577 * Directly clear spte without caring the state bits of sptep,
578 * it is used to set the upper level spte.
580 static void mmu_spte_clear_no_track(u64 *sptep)
582 __update_clear_spte_fast(sptep, 0ull);
585 static u64 mmu_spte_get_lockless(u64 *sptep)
587 return __get_spte_lockless(sptep);
590 /* Restore an acc-track PTE back to a regular PTE */
591 static u64 restore_acc_track_spte(u64 spte)
594 u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift)
595 & shadow_acc_track_saved_bits_mask;
597 WARN_ON_ONCE(spte_ad_enabled(spte));
598 WARN_ON_ONCE(!is_access_track_spte(spte));
600 new_spte &= ~shadow_acc_track_mask;
601 new_spte &= ~(shadow_acc_track_saved_bits_mask <<
602 shadow_acc_track_saved_bits_shift);
603 new_spte |= saved_bits;
608 /* Returns the Accessed status of the PTE and resets it at the same time. */
609 static bool mmu_spte_age(u64 *sptep)
611 u64 spte = mmu_spte_get_lockless(sptep);
613 if (!is_accessed_spte(spte))
616 if (spte_ad_enabled(spte)) {
617 clear_bit((ffs(shadow_accessed_mask) - 1),
618 (unsigned long *)sptep);
621 * Capture the dirty status of the page, so that it doesn't get
622 * lost when the SPTE is marked for access tracking.
624 if (is_writable_pte(spte))
625 kvm_set_pfn_dirty(spte_to_pfn(spte));
627 spte = mark_spte_for_access_track(spte);
628 mmu_spte_update_no_track(sptep, spte);
634 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
637 * Prevent page table teardown by making any free-er wait during
638 * kvm_flush_remote_tlbs() IPI to all active vcpus.
643 * Make sure a following spte read is not reordered ahead of the write
646 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
649 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
652 * Make sure the write to vcpu->mode is not reordered in front of
653 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
654 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
656 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
660 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
664 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
665 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
666 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
669 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
670 PT64_ROOT_MAX_LEVEL);
673 if (maybe_indirect) {
674 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
675 PT64_ROOT_MAX_LEVEL);
679 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
680 PT64_ROOT_MAX_LEVEL);
683 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
685 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
686 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
687 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
688 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
691 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
693 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
696 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
698 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
701 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
703 if (!sp->role.direct)
704 return sp->gfns[index];
706 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
709 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
711 if (!sp->role.direct) {
712 sp->gfns[index] = gfn;
716 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
717 pr_err_ratelimited("gfn mismatch under direct page %llx "
718 "(expected %llx, got %llx)\n",
720 kvm_mmu_page_get_gfn(sp, index), gfn);
724 * Return the pointer to the large page information for a given gfn,
725 * handling slots that are not large page aligned.
727 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
728 struct kvm_memory_slot *slot,
733 idx = gfn_to_index(gfn, slot->base_gfn, level);
734 return &slot->arch.lpage_info[level - 2][idx];
737 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
738 gfn_t gfn, int count)
740 struct kvm_lpage_info *linfo;
743 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
744 linfo = lpage_info_slot(gfn, slot, i);
745 linfo->disallow_lpage += count;
746 WARN_ON(linfo->disallow_lpage < 0);
750 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
752 update_gfn_disallow_lpage_count(slot, gfn, 1);
755 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
757 update_gfn_disallow_lpage_count(slot, gfn, -1);
760 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
762 struct kvm_memslots *slots;
763 struct kvm_memory_slot *slot;
766 kvm->arch.indirect_shadow_pages++;
768 slots = kvm_memslots_for_spte_role(kvm, sp->role);
769 slot = __gfn_to_memslot(slots, gfn);
771 /* the non-leaf shadow pages are keeping readonly. */
772 if (sp->role.level > PG_LEVEL_4K)
773 return kvm_slot_page_track_add_page(kvm, slot, gfn,
774 KVM_PAGE_TRACK_WRITE);
776 kvm_mmu_gfn_disallow_lpage(slot, gfn);
779 static void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
781 if (sp->lpage_disallowed)
784 ++kvm->stat.nx_lpage_splits;
785 list_add_tail(&sp->lpage_disallowed_link,
786 &kvm->arch.lpage_disallowed_mmu_pages);
787 sp->lpage_disallowed = true;
790 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
792 struct kvm_memslots *slots;
793 struct kvm_memory_slot *slot;
796 kvm->arch.indirect_shadow_pages--;
798 slots = kvm_memslots_for_spte_role(kvm, sp->role);
799 slot = __gfn_to_memslot(slots, gfn);
800 if (sp->role.level > PG_LEVEL_4K)
801 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
802 KVM_PAGE_TRACK_WRITE);
804 kvm_mmu_gfn_allow_lpage(slot, gfn);
807 static void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
809 --kvm->stat.nx_lpage_splits;
810 sp->lpage_disallowed = false;
811 list_del(&sp->lpage_disallowed_link);
814 static struct kvm_memory_slot *
815 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
818 struct kvm_memory_slot *slot;
820 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
821 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
823 if (no_dirty_log && slot->dirty_bitmap)
830 * About rmap_head encoding:
832 * If the bit zero of rmap_head->val is clear, then it points to the only spte
833 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
834 * pte_list_desc containing more mappings.
838 * Returns the number of pointers in the rmap chain, not counting the new one.
840 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
841 struct kvm_rmap_head *rmap_head)
843 struct pte_list_desc *desc;
846 if (!rmap_head->val) {
847 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
848 rmap_head->val = (unsigned long)spte;
849 } else if (!(rmap_head->val & 1)) {
850 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
851 desc = mmu_alloc_pte_list_desc(vcpu);
852 desc->sptes[0] = (u64 *)rmap_head->val;
853 desc->sptes[1] = spte;
854 rmap_head->val = (unsigned long)desc | 1;
857 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
858 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
859 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
861 count += PTE_LIST_EXT;
863 if (desc->sptes[PTE_LIST_EXT-1]) {
864 desc->more = mmu_alloc_pte_list_desc(vcpu);
867 for (i = 0; desc->sptes[i]; ++i)
869 desc->sptes[i] = spte;
875 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
876 struct pte_list_desc *desc, int i,
877 struct pte_list_desc *prev_desc)
881 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
883 desc->sptes[i] = desc->sptes[j];
884 desc->sptes[j] = NULL;
887 if (!prev_desc && !desc->more)
891 prev_desc->more = desc->more;
893 rmap_head->val = (unsigned long)desc->more | 1;
894 mmu_free_pte_list_desc(desc);
897 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
899 struct pte_list_desc *desc;
900 struct pte_list_desc *prev_desc;
903 if (!rmap_head->val) {
904 pr_err("%s: %p 0->BUG\n", __func__, spte);
906 } else if (!(rmap_head->val & 1)) {
907 rmap_printk("%s: %p 1->0\n", __func__, spte);
908 if ((u64 *)rmap_head->val != spte) {
909 pr_err("%s: %p 1->BUG\n", __func__, spte);
914 rmap_printk("%s: %p many->many\n", __func__, spte);
915 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
918 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
919 if (desc->sptes[i] == spte) {
920 pte_list_desc_remove_entry(rmap_head,
928 pr_err("%s: %p many->many\n", __func__, spte);
933 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
935 mmu_spte_clear_track_bits(sptep);
936 __pte_list_remove(sptep, rmap_head);
939 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
940 struct kvm_memory_slot *slot)
944 idx = gfn_to_index(gfn, slot->base_gfn, level);
945 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
948 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
949 struct kvm_mmu_page *sp)
951 struct kvm_memslots *slots;
952 struct kvm_memory_slot *slot;
954 slots = kvm_memslots_for_spte_role(kvm, sp->role);
955 slot = __gfn_to_memslot(slots, gfn);
956 return __gfn_to_rmap(gfn, sp->role.level, slot);
959 static bool rmap_can_add(struct kvm_vcpu *vcpu)
961 struct kvm_mmu_memory_cache *mc;
963 mc = &vcpu->arch.mmu_pte_list_desc_cache;
964 return kvm_mmu_memory_cache_nr_free_objects(mc);
967 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
969 struct kvm_mmu_page *sp;
970 struct kvm_rmap_head *rmap_head;
972 sp = sptep_to_sp(spte);
973 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
974 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
975 return pte_list_add(vcpu, spte, rmap_head);
978 static void rmap_remove(struct kvm *kvm, u64 *spte)
980 struct kvm_mmu_page *sp;
982 struct kvm_rmap_head *rmap_head;
984 sp = sptep_to_sp(spte);
985 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
986 rmap_head = gfn_to_rmap(kvm, gfn, sp);
987 __pte_list_remove(spte, rmap_head);
991 * Used by the following functions to iterate through the sptes linked by a
992 * rmap. All fields are private and not assumed to be used outside.
994 struct rmap_iterator {
996 struct pte_list_desc *desc; /* holds the sptep if not NULL */
997 int pos; /* index of the sptep */
1001 * Iteration must be started by this function. This should also be used after
1002 * removing/dropping sptes from the rmap link because in such cases the
1003 * information in the iterator may not be valid.
1005 * Returns sptep if found, NULL otherwise.
1007 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1008 struct rmap_iterator *iter)
1012 if (!rmap_head->val)
1015 if (!(rmap_head->val & 1)) {
1017 sptep = (u64 *)rmap_head->val;
1021 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1023 sptep = iter->desc->sptes[iter->pos];
1025 BUG_ON(!is_shadow_present_pte(*sptep));
1030 * Must be used with a valid iterator: e.g. after rmap_get_first().
1032 * Returns sptep if found, NULL otherwise.
1034 static u64 *rmap_get_next(struct rmap_iterator *iter)
1039 if (iter->pos < PTE_LIST_EXT - 1) {
1041 sptep = iter->desc->sptes[iter->pos];
1046 iter->desc = iter->desc->more;
1050 /* desc->sptes[0] cannot be NULL */
1051 sptep = iter->desc->sptes[iter->pos];
1058 BUG_ON(!is_shadow_present_pte(*sptep));
1062 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1063 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1064 _spte_; _spte_ = rmap_get_next(_iter_))
1066 static void drop_spte(struct kvm *kvm, u64 *sptep)
1068 if (mmu_spte_clear_track_bits(sptep))
1069 rmap_remove(kvm, sptep);
1073 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1075 if (is_large_pte(*sptep)) {
1076 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1077 drop_spte(kvm, sptep);
1085 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1087 if (__drop_large_spte(vcpu->kvm, sptep)) {
1088 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1090 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1091 KVM_PAGES_PER_HPAGE(sp->role.level));
1096 * Write-protect on the specified @sptep, @pt_protect indicates whether
1097 * spte write-protection is caused by protecting shadow page table.
1099 * Note: write protection is difference between dirty logging and spte
1101 * - for dirty logging, the spte can be set to writable at anytime if
1102 * its dirty bitmap is properly set.
1103 * - for spte protection, the spte can be writable only after unsync-ing
1106 * Return true if tlb need be flushed.
1108 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1112 if (!is_writable_pte(spte) &&
1113 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1116 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1119 spte &= ~SPTE_MMU_WRITEABLE;
1120 spte = spte & ~PT_WRITABLE_MASK;
1122 return mmu_spte_update(sptep, spte);
1125 static bool __rmap_write_protect(struct kvm *kvm,
1126 struct kvm_rmap_head *rmap_head,
1130 struct rmap_iterator iter;
1133 for_each_rmap_spte(rmap_head, &iter, sptep)
1134 flush |= spte_write_protect(sptep, pt_protect);
1139 static bool spte_clear_dirty(u64 *sptep)
1143 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1145 MMU_WARN_ON(!spte_ad_enabled(spte));
1146 spte &= ~shadow_dirty_mask;
1147 return mmu_spte_update(sptep, spte);
1150 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1152 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1153 (unsigned long *)sptep);
1154 if (was_writable && !spte_ad_enabled(*sptep))
1155 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1157 return was_writable;
1161 * Gets the GFN ready for another round of dirty logging by clearing the
1162 * - D bit on ad-enabled SPTEs, and
1163 * - W bit on ad-disabled SPTEs.
1164 * Returns true iff any D or W bits were cleared.
1166 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1169 struct rmap_iterator iter;
1172 for_each_rmap_spte(rmap_head, &iter, sptep)
1173 if (spte_ad_need_write_protect(*sptep))
1174 flush |= spte_wrprot_for_clear_dirty(sptep);
1176 flush |= spte_clear_dirty(sptep);
1181 static bool spte_set_dirty(u64 *sptep)
1185 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1188 * Similar to the !kvm_x86_ops.slot_disable_log_dirty case,
1189 * do not bother adding back write access to pages marked
1190 * SPTE_AD_WRPROT_ONLY_MASK.
1192 spte |= shadow_dirty_mask;
1194 return mmu_spte_update(sptep, spte);
1197 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1200 struct rmap_iterator iter;
1203 for_each_rmap_spte(rmap_head, &iter, sptep)
1204 if (spte_ad_enabled(*sptep))
1205 flush |= spte_set_dirty(sptep);
1211 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1212 * @kvm: kvm instance
1213 * @slot: slot to protect
1214 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1215 * @mask: indicates which pages we should protect
1217 * Used when we do not need to care about huge page mappings: e.g. during dirty
1218 * logging we do not have any such mappings.
1220 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1221 struct kvm_memory_slot *slot,
1222 gfn_t gfn_offset, unsigned long mask)
1224 struct kvm_rmap_head *rmap_head;
1227 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1229 __rmap_write_protect(kvm, rmap_head, false);
1231 /* clear the first set bit */
1237 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1238 * protect the page if the D-bit isn't supported.
1239 * @kvm: kvm instance
1240 * @slot: slot to clear D-bit
1241 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1242 * @mask: indicates which pages we should clear D-bit
1244 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1246 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1247 struct kvm_memory_slot *slot,
1248 gfn_t gfn_offset, unsigned long mask)
1250 struct kvm_rmap_head *rmap_head;
1253 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1255 __rmap_clear_dirty(kvm, rmap_head);
1257 /* clear the first set bit */
1261 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1264 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1267 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1268 * enable dirty logging for them.
1270 * Used when we do not need to care about huge page mappings: e.g. during dirty
1271 * logging we do not have any such mappings.
1273 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1274 struct kvm_memory_slot *slot,
1275 gfn_t gfn_offset, unsigned long mask)
1277 if (kvm_x86_ops.enable_log_dirty_pt_masked)
1278 kvm_x86_ops.enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1281 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1284 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1285 struct kvm_memory_slot *slot, u64 gfn)
1287 struct kvm_rmap_head *rmap_head;
1289 bool write_protected = false;
1291 for (i = PG_LEVEL_4K; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1292 rmap_head = __gfn_to_rmap(gfn, i, slot);
1293 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1296 return write_protected;
1299 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1301 struct kvm_memory_slot *slot;
1303 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1304 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1307 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1310 struct rmap_iterator iter;
1313 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1314 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1316 pte_list_remove(rmap_head, sptep);
1323 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1324 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1327 return kvm_zap_rmapp(kvm, rmap_head);
1330 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1331 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1335 struct rmap_iterator iter;
1338 pte_t *ptep = (pte_t *)data;
1341 WARN_ON(pte_huge(*ptep));
1342 new_pfn = pte_pfn(*ptep);
1345 for_each_rmap_spte(rmap_head, &iter, sptep) {
1346 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1347 sptep, *sptep, gfn, level);
1351 if (pte_write(*ptep)) {
1352 pte_list_remove(rmap_head, sptep);
1355 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1358 mmu_spte_clear_track_bits(sptep);
1359 mmu_spte_set(sptep, new_spte);
1363 if (need_flush && kvm_available_flush_tlb_with_range()) {
1364 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1371 struct slot_rmap_walk_iterator {
1373 struct kvm_memory_slot *slot;
1379 /* output fields. */
1381 struct kvm_rmap_head *rmap;
1384 /* private field. */
1385 struct kvm_rmap_head *end_rmap;
1389 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1391 iterator->level = level;
1392 iterator->gfn = iterator->start_gfn;
1393 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1394 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1399 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1400 struct kvm_memory_slot *slot, int start_level,
1401 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1403 iterator->slot = slot;
1404 iterator->start_level = start_level;
1405 iterator->end_level = end_level;
1406 iterator->start_gfn = start_gfn;
1407 iterator->end_gfn = end_gfn;
1409 rmap_walk_init_level(iterator, iterator->start_level);
1412 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1414 return !!iterator->rmap;
1417 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1419 if (++iterator->rmap <= iterator->end_rmap) {
1420 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1424 if (++iterator->level > iterator->end_level) {
1425 iterator->rmap = NULL;
1429 rmap_walk_init_level(iterator, iterator->level);
1432 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1433 _start_gfn, _end_gfn, _iter_) \
1434 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1435 _end_level_, _start_gfn, _end_gfn); \
1436 slot_rmap_walk_okay(_iter_); \
1437 slot_rmap_walk_next(_iter_))
1439 static int kvm_handle_hva_range(struct kvm *kvm,
1440 unsigned long start,
1443 int (*handler)(struct kvm *kvm,
1444 struct kvm_rmap_head *rmap_head,
1445 struct kvm_memory_slot *slot,
1448 unsigned long data))
1450 struct kvm_memslots *slots;
1451 struct kvm_memory_slot *memslot;
1452 struct slot_rmap_walk_iterator iterator;
1456 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1457 slots = __kvm_memslots(kvm, i);
1458 kvm_for_each_memslot(memslot, slots) {
1459 unsigned long hva_start, hva_end;
1460 gfn_t gfn_start, gfn_end;
1462 hva_start = max(start, memslot->userspace_addr);
1463 hva_end = min(end, memslot->userspace_addr +
1464 (memslot->npages << PAGE_SHIFT));
1465 if (hva_start >= hva_end)
1468 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1469 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1471 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1472 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1474 for_each_slot_rmap_range(memslot, PG_LEVEL_4K,
1475 KVM_MAX_HUGEPAGE_LEVEL,
1476 gfn_start, gfn_end - 1,
1478 ret |= handler(kvm, iterator.rmap, memslot,
1479 iterator.gfn, iterator.level, data);
1486 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1488 int (*handler)(struct kvm *kvm,
1489 struct kvm_rmap_head *rmap_head,
1490 struct kvm_memory_slot *slot,
1491 gfn_t gfn, int level,
1492 unsigned long data))
1494 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1497 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
1502 r = kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1504 if (kvm->arch.tdp_mmu_enabled)
1505 r |= kvm_tdp_mmu_zap_hva_range(kvm, start, end);
1510 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1512 return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1515 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1516 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1520 struct rmap_iterator iter;
1523 for_each_rmap_spte(rmap_head, &iter, sptep)
1524 young |= mmu_spte_age(sptep);
1526 trace_kvm_age_page(gfn, level, slot, young);
1530 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1531 struct kvm_memory_slot *slot, gfn_t gfn,
1532 int level, unsigned long data)
1535 struct rmap_iterator iter;
1537 for_each_rmap_spte(rmap_head, &iter, sptep)
1538 if (is_accessed_spte(*sptep))
1543 #define RMAP_RECYCLE_THRESHOLD 1000
1545 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1547 struct kvm_rmap_head *rmap_head;
1548 struct kvm_mmu_page *sp;
1550 sp = sptep_to_sp(spte);
1552 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1554 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1555 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1556 KVM_PAGES_PER_HPAGE(sp->role.level));
1559 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1561 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1564 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1566 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1570 static int is_empty_shadow_page(u64 *spt)
1575 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1576 if (is_shadow_present_pte(*pos)) {
1577 printk(KERN_ERR "%s: %p %llx\n", __func__,
1586 * This value is the sum of all of the kvm instances's
1587 * kvm->arch.n_used_mmu_pages values. We need a global,
1588 * aggregate version in order to make the slab shrinker
1591 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1593 kvm->arch.n_used_mmu_pages += nr;
1594 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1597 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1599 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1600 hlist_del(&sp->hash_link);
1601 list_del(&sp->link);
1602 free_page((unsigned long)sp->spt);
1603 if (!sp->role.direct)
1604 free_page((unsigned long)sp->gfns);
1605 kmem_cache_free(mmu_page_header_cache, sp);
1608 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1610 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1613 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1614 struct kvm_mmu_page *sp, u64 *parent_pte)
1619 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1622 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1625 __pte_list_remove(parent_pte, &sp->parent_ptes);
1628 static void drop_parent_pte(struct kvm_mmu_page *sp,
1631 mmu_page_remove_parent_pte(sp, parent_pte);
1632 mmu_spte_clear_no_track(parent_pte);
1635 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1637 struct kvm_mmu_page *sp;
1639 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1640 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1642 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1643 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1646 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1647 * depends on valid pages being added to the head of the list. See
1648 * comments in kvm_zap_obsolete_pages().
1650 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1651 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1652 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1656 static void mark_unsync(u64 *spte);
1657 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1660 struct rmap_iterator iter;
1662 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1667 static void mark_unsync(u64 *spte)
1669 struct kvm_mmu_page *sp;
1672 sp = sptep_to_sp(spte);
1673 index = spte - sp->spt;
1674 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1676 if (sp->unsync_children++)
1678 kvm_mmu_mark_parents_unsync(sp);
1681 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1682 struct kvm_mmu_page *sp)
1687 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1688 struct kvm_mmu_page *sp, u64 *spte,
1694 #define KVM_PAGE_ARRAY_NR 16
1696 struct kvm_mmu_pages {
1697 struct mmu_page_and_offset {
1698 struct kvm_mmu_page *sp;
1700 } page[KVM_PAGE_ARRAY_NR];
1704 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1710 for (i=0; i < pvec->nr; i++)
1711 if (pvec->page[i].sp == sp)
1714 pvec->page[pvec->nr].sp = sp;
1715 pvec->page[pvec->nr].idx = idx;
1717 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1720 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1722 --sp->unsync_children;
1723 WARN_ON((int)sp->unsync_children < 0);
1724 __clear_bit(idx, sp->unsync_child_bitmap);
1727 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1728 struct kvm_mmu_pages *pvec)
1730 int i, ret, nr_unsync_leaf = 0;
1732 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1733 struct kvm_mmu_page *child;
1734 u64 ent = sp->spt[i];
1736 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1737 clear_unsync_child_bit(sp, i);
1741 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1743 if (child->unsync_children) {
1744 if (mmu_pages_add(pvec, child, i))
1747 ret = __mmu_unsync_walk(child, pvec);
1749 clear_unsync_child_bit(sp, i);
1751 } else if (ret > 0) {
1752 nr_unsync_leaf += ret;
1755 } else if (child->unsync) {
1757 if (mmu_pages_add(pvec, child, i))
1760 clear_unsync_child_bit(sp, i);
1763 return nr_unsync_leaf;
1766 #define INVALID_INDEX (-1)
1768 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1769 struct kvm_mmu_pages *pvec)
1772 if (!sp->unsync_children)
1775 mmu_pages_add(pvec, sp, INVALID_INDEX);
1776 return __mmu_unsync_walk(sp, pvec);
1779 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1781 WARN_ON(!sp->unsync);
1782 trace_kvm_mmu_sync_page(sp);
1784 --kvm->stat.mmu_unsync;
1787 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1788 struct list_head *invalid_list);
1789 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1790 struct list_head *invalid_list);
1792 #define for_each_valid_sp(_kvm, _sp, _list) \
1793 hlist_for_each_entry(_sp, _list, hash_link) \
1794 if (is_obsolete_sp((_kvm), (_sp))) { \
1797 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1798 for_each_valid_sp(_kvm, _sp, \
1799 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1800 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1802 static inline bool is_ept_sp(struct kvm_mmu_page *sp)
1804 return sp->role.cr0_wp && sp->role.smap_andnot_wp;
1807 /* @sp->gfn should be write-protected at the call site */
1808 static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1809 struct list_head *invalid_list)
1811 if ((!is_ept_sp(sp) && sp->role.gpte_is_8_bytes != !!is_pae(vcpu)) ||
1812 vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1813 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1820 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1821 struct list_head *invalid_list,
1824 if (!remote_flush && list_empty(invalid_list))
1827 if (!list_empty(invalid_list))
1828 kvm_mmu_commit_zap_page(kvm, invalid_list);
1830 kvm_flush_remote_tlbs(kvm);
1834 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1835 struct list_head *invalid_list,
1836 bool remote_flush, bool local_flush)
1838 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1842 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1845 #ifdef CONFIG_KVM_MMU_AUDIT
1846 #include "mmu_audit.c"
1848 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1849 static void mmu_audit_disable(void) { }
1852 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1854 return sp->role.invalid ||
1855 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1858 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1859 struct list_head *invalid_list)
1861 kvm_unlink_unsync_page(vcpu->kvm, sp);
1862 return __kvm_sync_page(vcpu, sp, invalid_list);
1865 /* @gfn should be write-protected at the call site */
1866 static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn,
1867 struct list_head *invalid_list)
1869 struct kvm_mmu_page *s;
1872 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1876 WARN_ON(s->role.level != PG_LEVEL_4K);
1877 ret |= kvm_sync_page(vcpu, s, invalid_list);
1883 struct mmu_page_path {
1884 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1885 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1888 #define for_each_sp(pvec, sp, parents, i) \
1889 for (i = mmu_pages_first(&pvec, &parents); \
1890 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1891 i = mmu_pages_next(&pvec, &parents, i))
1893 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1894 struct mmu_page_path *parents,
1899 for (n = i+1; n < pvec->nr; n++) {
1900 struct kvm_mmu_page *sp = pvec->page[n].sp;
1901 unsigned idx = pvec->page[n].idx;
1902 int level = sp->role.level;
1904 parents->idx[level-1] = idx;
1905 if (level == PG_LEVEL_4K)
1908 parents->parent[level-2] = sp;
1914 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1915 struct mmu_page_path *parents)
1917 struct kvm_mmu_page *sp;
1923 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1925 sp = pvec->page[0].sp;
1926 level = sp->role.level;
1927 WARN_ON(level == PG_LEVEL_4K);
1929 parents->parent[level-2] = sp;
1931 /* Also set up a sentinel. Further entries in pvec are all
1932 * children of sp, so this element is never overwritten.
1934 parents->parent[level-1] = NULL;
1935 return mmu_pages_next(pvec, parents, 0);
1938 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1940 struct kvm_mmu_page *sp;
1941 unsigned int level = 0;
1944 unsigned int idx = parents->idx[level];
1945 sp = parents->parent[level];
1949 WARN_ON(idx == INVALID_INDEX);
1950 clear_unsync_child_bit(sp, idx);
1952 } while (!sp->unsync_children);
1955 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1956 struct kvm_mmu_page *parent)
1959 struct kvm_mmu_page *sp;
1960 struct mmu_page_path parents;
1961 struct kvm_mmu_pages pages;
1962 LIST_HEAD(invalid_list);
1965 while (mmu_unsync_walk(parent, &pages)) {
1966 bool protected = false;
1968 for_each_sp(pages, sp, parents, i)
1969 protected |= rmap_write_protect(vcpu, sp->gfn);
1972 kvm_flush_remote_tlbs(vcpu->kvm);
1976 for_each_sp(pages, sp, parents, i) {
1977 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1978 mmu_pages_clear_parents(&parents);
1980 if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) {
1981 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1982 cond_resched_lock(&vcpu->kvm->mmu_lock);
1987 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1990 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1992 atomic_set(&sp->write_flooding_count, 0);
1995 static void clear_sp_write_flooding_count(u64 *spte)
1997 __clear_sp_write_flooding_count(sptep_to_sp(spte));
2000 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2005 unsigned int access)
2007 bool direct_mmu = vcpu->arch.mmu->direct_map;
2008 union kvm_mmu_page_role role;
2009 struct hlist_head *sp_list;
2011 struct kvm_mmu_page *sp;
2012 bool need_sync = false;
2015 LIST_HEAD(invalid_list);
2017 role = vcpu->arch.mmu->mmu_role.base;
2019 role.direct = direct;
2021 role.gpte_is_8_bytes = true;
2022 role.access = access;
2023 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2024 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2025 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2026 role.quadrant = quadrant;
2029 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2030 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2031 if (sp->gfn != gfn) {
2036 if (!need_sync && sp->unsync)
2039 if (sp->role.word != role.word)
2043 goto trace_get_page;
2046 /* The page is good, but __kvm_sync_page might still end
2047 * up zapping it. If so, break in order to rebuild it.
2049 if (!__kvm_sync_page(vcpu, sp, &invalid_list))
2052 WARN_ON(!list_empty(&invalid_list));
2053 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2056 if (sp->unsync_children)
2057 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2059 __clear_sp_write_flooding_count(sp);
2062 trace_kvm_mmu_get_page(sp, false);
2066 ++vcpu->kvm->stat.mmu_cache_miss;
2068 sp = kvm_mmu_alloc_page(vcpu, direct);
2072 hlist_add_head(&sp->hash_link, sp_list);
2075 * we should do write protection before syncing pages
2076 * otherwise the content of the synced shadow page may
2077 * be inconsistent with guest page table.
2079 account_shadowed(vcpu->kvm, sp);
2080 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2081 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2083 if (level > PG_LEVEL_4K && need_sync)
2084 flush |= kvm_sync_pages(vcpu, gfn, &invalid_list);
2086 trace_kvm_mmu_get_page(sp, true);
2088 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
2090 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2091 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2095 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2096 struct kvm_vcpu *vcpu, hpa_t root,
2099 iterator->addr = addr;
2100 iterator->shadow_addr = root;
2101 iterator->level = vcpu->arch.mmu->shadow_root_level;
2103 if (iterator->level == PT64_ROOT_4LEVEL &&
2104 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2105 !vcpu->arch.mmu->direct_map)
2108 if (iterator->level == PT32E_ROOT_LEVEL) {
2110 * prev_root is currently only used for 64-bit hosts. So only
2111 * the active root_hpa is valid here.
2113 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2115 iterator->shadow_addr
2116 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2117 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2119 if (!iterator->shadow_addr)
2120 iterator->level = 0;
2124 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2125 struct kvm_vcpu *vcpu, u64 addr)
2127 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2131 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2133 if (iterator->level < PG_LEVEL_4K)
2136 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2137 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2141 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2144 if (is_last_spte(spte, iterator->level)) {
2145 iterator->level = 0;
2149 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2153 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2155 __shadow_walk_next(iterator, *iterator->sptep);
2158 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2159 struct kvm_mmu_page *sp)
2163 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2165 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2167 mmu_spte_set(sptep, spte);
2169 mmu_page_add_parent_pte(vcpu, sp, sptep);
2171 if (sp->unsync_children || sp->unsync)
2175 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2176 unsigned direct_access)
2178 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2179 struct kvm_mmu_page *child;
2182 * For the direct sp, if the guest pte's dirty bit
2183 * changed form clean to dirty, it will corrupt the
2184 * sp's access: allow writable in the read-only sp,
2185 * so we should update the spte at this point to get
2186 * a new sp with the correct access.
2188 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2189 if (child->role.access == direct_access)
2192 drop_parent_pte(child, sptep);
2193 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2197 /* Returns the number of zapped non-leaf child shadow pages. */
2198 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2199 u64 *spte, struct list_head *invalid_list)
2202 struct kvm_mmu_page *child;
2205 if (is_shadow_present_pte(pte)) {
2206 if (is_last_spte(pte, sp->role.level)) {
2207 drop_spte(kvm, spte);
2208 if (is_large_pte(pte))
2211 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2212 drop_parent_pte(child, spte);
2215 * Recursively zap nested TDP SPs, parentless SPs are
2216 * unlikely to be used again in the near future. This
2217 * avoids retaining a large number of stale nested SPs.
2219 if (tdp_enabled && invalid_list &&
2220 child->role.guest_mode && !child->parent_ptes.val)
2221 return kvm_mmu_prepare_zap_page(kvm, child,
2224 } else if (is_mmio_spte(pte)) {
2225 mmu_spte_clear_no_track(spte);
2230 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2231 struct kvm_mmu_page *sp,
2232 struct list_head *invalid_list)
2237 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2238 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2243 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2246 struct rmap_iterator iter;
2248 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2249 drop_parent_pte(sp, sptep);
2252 static int mmu_zap_unsync_children(struct kvm *kvm,
2253 struct kvm_mmu_page *parent,
2254 struct list_head *invalid_list)
2257 struct mmu_page_path parents;
2258 struct kvm_mmu_pages pages;
2260 if (parent->role.level == PG_LEVEL_4K)
2263 while (mmu_unsync_walk(parent, &pages)) {
2264 struct kvm_mmu_page *sp;
2266 for_each_sp(pages, sp, parents, i) {
2267 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2268 mmu_pages_clear_parents(&parents);
2276 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2277 struct kvm_mmu_page *sp,
2278 struct list_head *invalid_list,
2283 trace_kvm_mmu_prepare_zap_page(sp);
2284 ++kvm->stat.mmu_shadow_zapped;
2285 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2286 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2287 kvm_mmu_unlink_parents(kvm, sp);
2289 /* Zapping children means active_mmu_pages has become unstable. */
2290 list_unstable = *nr_zapped;
2292 if (!sp->role.invalid && !sp->role.direct)
2293 unaccount_shadowed(kvm, sp);
2296 kvm_unlink_unsync_page(kvm, sp);
2297 if (!sp->root_count) {
2302 * Already invalid pages (previously active roots) are not on
2303 * the active page list. See list_del() in the "else" case of
2306 if (sp->role.invalid)
2307 list_add(&sp->link, invalid_list);
2309 list_move(&sp->link, invalid_list);
2310 kvm_mod_used_mmu_pages(kvm, -1);
2313 * Remove the active root from the active page list, the root
2314 * will be explicitly freed when the root_count hits zero.
2316 list_del(&sp->link);
2319 * Obsolete pages cannot be used on any vCPUs, see the comment
2320 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2321 * treats invalid shadow pages as being obsolete.
2323 if (!is_obsolete_sp(kvm, sp))
2324 kvm_reload_remote_mmus(kvm);
2327 if (sp->lpage_disallowed)
2328 unaccount_huge_nx_page(kvm, sp);
2330 sp->role.invalid = 1;
2331 return list_unstable;
2334 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2335 struct list_head *invalid_list)
2339 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2343 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2344 struct list_head *invalid_list)
2346 struct kvm_mmu_page *sp, *nsp;
2348 if (list_empty(invalid_list))
2352 * We need to make sure everyone sees our modifications to
2353 * the page tables and see changes to vcpu->mode here. The barrier
2354 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2355 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2357 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2358 * guest mode and/or lockless shadow page table walks.
2360 kvm_flush_remote_tlbs(kvm);
2362 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2363 WARN_ON(!sp->role.invalid || sp->root_count);
2364 kvm_mmu_free_page(sp);
2368 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2369 unsigned long nr_to_zap)
2371 unsigned long total_zapped = 0;
2372 struct kvm_mmu_page *sp, *tmp;
2373 LIST_HEAD(invalid_list);
2377 if (list_empty(&kvm->arch.active_mmu_pages))
2381 list_for_each_entry_safe(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2383 * Don't zap active root pages, the page itself can't be freed
2384 * and zapping it will just force vCPUs to realloc and reload.
2389 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2391 total_zapped += nr_zapped;
2392 if (total_zapped >= nr_to_zap)
2399 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2401 kvm->stat.mmu_recycled += total_zapped;
2402 return total_zapped;
2405 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2407 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2408 return kvm->arch.n_max_mmu_pages -
2409 kvm->arch.n_used_mmu_pages;
2414 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2416 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2418 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2421 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2423 if (!kvm_mmu_available_pages(vcpu->kvm))
2429 * Changing the number of mmu pages allocated to the vm
2430 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2432 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2434 spin_lock(&kvm->mmu_lock);
2436 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2437 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2440 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2443 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2445 spin_unlock(&kvm->mmu_lock);
2448 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2450 struct kvm_mmu_page *sp;
2451 LIST_HEAD(invalid_list);
2454 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2456 spin_lock(&kvm->mmu_lock);
2457 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2458 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2461 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2463 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2464 spin_unlock(&kvm->mmu_lock);
2468 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2470 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2472 trace_kvm_mmu_unsync_page(sp);
2473 ++vcpu->kvm->stat.mmu_unsync;
2476 kvm_mmu_mark_parents_unsync(sp);
2479 bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2482 struct kvm_mmu_page *sp;
2484 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2487 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2494 WARN_ON(sp->role.level != PG_LEVEL_4K);
2495 kvm_unsync_page(vcpu, sp);
2499 * We need to ensure that the marking of unsync pages is visible
2500 * before the SPTE is updated to allow writes because
2501 * kvm_mmu_sync_roots() checks the unsync flags without holding
2502 * the MMU lock and so can race with this. If the SPTE was updated
2503 * before the page had been marked as unsync-ed, something like the
2504 * following could happen:
2507 * ---------------------------------------------------------------------
2508 * 1.2 Host updates SPTE
2510 * 2.1 Guest writes a GPTE for GVA X.
2511 * (GPTE being in the guest page table shadowed
2512 * by the SP from CPU 1.)
2513 * This reads SPTE during the page table walk.
2514 * Since SPTE.W is read as 1, there is no
2517 * 2.2 Guest issues TLB flush.
2518 * That causes a VM Exit.
2520 * 2.3 kvm_mmu_sync_pages() reads sp->unsync.
2521 * Since it is false, so it just returns.
2523 * 2.4 Guest accesses GVA X.
2524 * Since the mapping in the SP was not updated,
2525 * so the old mapping for GVA X incorrectly
2529 * (sp->unsync = true)
2531 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2532 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2533 * pairs with this write barrier.
2540 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2541 unsigned int pte_access, int level,
2542 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2543 bool can_unsync, bool host_writable)
2546 struct kvm_mmu_page *sp;
2549 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2552 sp = sptep_to_sp(sptep);
2554 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2555 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2557 if (spte & PT_WRITABLE_MASK)
2558 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2561 ret |= SET_SPTE_SPURIOUS;
2562 else if (mmu_spte_update(sptep, spte))
2563 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2567 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2568 unsigned int pte_access, bool write_fault, int level,
2569 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2572 int was_rmapped = 0;
2575 int ret = RET_PF_FIXED;
2578 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2579 *sptep, write_fault, gfn);
2581 if (is_shadow_present_pte(*sptep)) {
2583 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2584 * the parent of the now unreachable PTE.
2586 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2587 struct kvm_mmu_page *child;
2590 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2591 drop_parent_pte(child, sptep);
2593 } else if (pfn != spte_to_pfn(*sptep)) {
2594 pgprintk("hfn old %llx new %llx\n",
2595 spte_to_pfn(*sptep), pfn);
2596 drop_spte(vcpu->kvm, sptep);
2602 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2603 speculative, true, host_writable);
2604 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2606 ret = RET_PF_EMULATE;
2607 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2610 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2611 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2612 KVM_PAGES_PER_HPAGE(level));
2614 if (unlikely(is_mmio_spte(*sptep)))
2615 ret = RET_PF_EMULATE;
2618 * The fault is fully spurious if and only if the new SPTE and old SPTE
2619 * are identical, and emulation is not required.
2621 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2622 WARN_ON_ONCE(!was_rmapped);
2623 return RET_PF_SPURIOUS;
2626 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2627 trace_kvm_mmu_set_spte(level, gfn, sptep);
2628 if (!was_rmapped && is_large_pte(*sptep))
2629 ++vcpu->kvm->stat.lpages;
2631 if (is_shadow_present_pte(*sptep)) {
2633 rmap_count = rmap_add(vcpu, sptep, gfn);
2634 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2635 rmap_recycle(vcpu, sptep, gfn);
2642 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2645 struct kvm_memory_slot *slot;
2647 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2649 return KVM_PFN_ERR_FAULT;
2651 return gfn_to_pfn_memslot_atomic(slot, gfn);
2654 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2655 struct kvm_mmu_page *sp,
2656 u64 *start, u64 *end)
2658 struct page *pages[PTE_PREFETCH_NUM];
2659 struct kvm_memory_slot *slot;
2660 unsigned int access = sp->role.access;
2664 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2665 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2669 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2673 for (i = 0; i < ret; i++, gfn++, start++) {
2674 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2675 page_to_pfn(pages[i]), true, true);
2682 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2683 struct kvm_mmu_page *sp, u64 *sptep)
2685 u64 *spte, *start = NULL;
2688 WARN_ON(!sp->role.direct);
2690 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2693 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2694 if (is_shadow_present_pte(*spte) || spte == sptep) {
2697 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2705 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2707 struct kvm_mmu_page *sp;
2709 sp = sptep_to_sp(sptep);
2712 * Without accessed bits, there's no way to distinguish between
2713 * actually accessed translations and prefetched, so disable pte
2714 * prefetch if accessed bits aren't available.
2716 if (sp_ad_disabled(sp))
2719 if (sp->role.level > PG_LEVEL_4K)
2722 __direct_pte_prefetch(vcpu, sp, sptep);
2725 static int host_pfn_mapping_level(struct kvm_vcpu *vcpu, gfn_t gfn,
2726 kvm_pfn_t pfn, struct kvm_memory_slot *slot)
2732 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2736 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2737 * is not solely for performance, it's also necessary to avoid the
2738 * "writable" check in __gfn_to_hva_many(), which will always fail on
2739 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2740 * page fault steps have already verified the guest isn't writing a
2741 * read-only memslot.
2743 hva = __gfn_to_hva_memslot(slot, gfn);
2745 pte = lookup_address_in_mm(vcpu->kvm->mm, hva, &level);
2752 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2753 int max_level, kvm_pfn_t *pfnp,
2754 bool huge_page_disallowed, int *req_level)
2756 struct kvm_memory_slot *slot;
2757 struct kvm_lpage_info *linfo;
2758 kvm_pfn_t pfn = *pfnp;
2762 *req_level = PG_LEVEL_4K;
2764 if (unlikely(max_level == PG_LEVEL_4K))
2767 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2770 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2774 max_level = min(max_level, max_huge_page_level);
2775 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2776 linfo = lpage_info_slot(gfn, slot, max_level);
2777 if (!linfo->disallow_lpage)
2781 if (max_level == PG_LEVEL_4K)
2784 level = host_pfn_mapping_level(vcpu, gfn, pfn, slot);
2785 if (level == PG_LEVEL_4K)
2788 *req_level = level = min(level, max_level);
2791 * Enforce the iTLB multihit workaround after capturing the requested
2792 * level, which will be used to do precise, accurate accounting.
2794 if (huge_page_disallowed)
2798 * mmu_notifier_retry() was successful and mmu_lock is held, so
2799 * the pmd can't be split from under us.
2801 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2802 VM_BUG_ON((gfn & mask) != (pfn & mask));
2803 *pfnp = pfn & ~mask;
2808 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2809 kvm_pfn_t *pfnp, int *goal_levelp)
2811 int level = *goal_levelp;
2813 if (cur_level == level && level > PG_LEVEL_4K &&
2814 is_shadow_present_pte(spte) &&
2815 !is_large_pte(spte)) {
2817 * A small SPTE exists for this pfn, but FNAME(fetch)
2818 * and __direct_map would like to create a large PTE
2819 * instead: just force them to go down another level,
2820 * patching back for them into pfn the next 9 bits of
2823 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2824 KVM_PAGES_PER_HPAGE(level - 1);
2825 *pfnp |= gfn & page_mask;
2830 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2831 int map_writable, int max_level, kvm_pfn_t pfn,
2832 bool prefault, bool is_tdp)
2834 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2835 bool write = error_code & PFERR_WRITE_MASK;
2836 bool exec = error_code & PFERR_FETCH_MASK;
2837 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2838 struct kvm_shadow_walk_iterator it;
2839 struct kvm_mmu_page *sp;
2840 int level, req_level, ret;
2841 gfn_t gfn = gpa >> PAGE_SHIFT;
2842 gfn_t base_gfn = gfn;
2844 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
2845 return RET_PF_RETRY;
2847 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2848 huge_page_disallowed, &req_level);
2850 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2851 for_each_shadow_entry(vcpu, gpa, it) {
2853 * We cannot overwrite existing page tables with an NX
2854 * large page, as the leaf could be executable.
2856 if (nx_huge_page_workaround_enabled)
2857 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2860 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2861 if (it.level == level)
2864 drop_large_spte(vcpu, it.sptep);
2865 if (!is_shadow_present_pte(*it.sptep)) {
2866 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2867 it.level - 1, true, ACC_ALL);
2869 link_shadow_page(vcpu, it.sptep, sp);
2870 if (is_tdp && huge_page_disallowed &&
2871 req_level >= it.level)
2872 account_huge_nx_page(vcpu->kvm, sp);
2876 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2877 write, level, base_gfn, pfn, prefault,
2879 if (ret == RET_PF_SPURIOUS)
2882 direct_pte_prefetch(vcpu, it.sptep);
2883 ++vcpu->stat.pf_fixed;
2887 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2889 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2892 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2895 * Do not cache the mmio info caused by writing the readonly gfn
2896 * into the spte otherwise read access on readonly gfn also can
2897 * caused mmio page fault and treat it as mmio access.
2899 if (pfn == KVM_PFN_ERR_RO_FAULT)
2900 return RET_PF_EMULATE;
2902 if (pfn == KVM_PFN_ERR_HWPOISON) {
2903 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2904 return RET_PF_RETRY;
2910 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2911 kvm_pfn_t pfn, unsigned int access,
2914 /* The pfn is invalid, report the error! */
2915 if (unlikely(is_error_pfn(pfn))) {
2916 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2920 if (unlikely(is_noslot_pfn(pfn)))
2921 vcpu_cache_mmio_info(vcpu, gva, gfn,
2922 access & shadow_mmio_access_mask);
2927 static bool page_fault_can_be_fast(u32 error_code)
2930 * Do not fix the mmio spte with invalid generation number which
2931 * need to be updated by slow page fault path.
2933 if (unlikely(error_code & PFERR_RSVD_MASK))
2936 /* See if the page fault is due to an NX violation */
2937 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2938 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2942 * #PF can be fast if:
2943 * 1. The shadow page table entry is not present, which could mean that
2944 * the fault is potentially caused by access tracking (if enabled).
2945 * 2. The shadow page table entry is present and the fault
2946 * is caused by write-protect, that means we just need change the W
2947 * bit of the spte which can be done out of mmu-lock.
2949 * However, if access tracking is disabled we know that a non-present
2950 * page must be a genuine page fault where we have to create a new SPTE.
2951 * So, if access tracking is disabled, we return true only for write
2952 * accesses to a present page.
2955 return shadow_acc_track_mask != 0 ||
2956 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
2957 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
2961 * Returns true if the SPTE was fixed successfully. Otherwise,
2962 * someone else modified the SPTE from its original value.
2965 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2966 u64 *sptep, u64 old_spte, u64 new_spte)
2970 WARN_ON(!sp->role.direct);
2973 * Theoretically we could also set dirty bit (and flush TLB) here in
2974 * order to eliminate unnecessary PML logging. See comments in
2975 * set_spte. But fast_page_fault is very unlikely to happen with PML
2976 * enabled, so we do not do this. This might result in the same GPA
2977 * to be logged in PML buffer again when the write really happens, and
2978 * eventually to be called by mark_page_dirty twice. But it's also no
2979 * harm. This also avoids the TLB flush needed after setting dirty bit
2980 * so non-PML cases won't be impacted.
2982 * Compare with set_spte where instead shadow_dirty_mask is set.
2984 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
2987 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
2989 * The gfn of direct spte is stable since it is
2990 * calculated by sp->gfn.
2992 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2993 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2999 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3001 if (fault_err_code & PFERR_FETCH_MASK)
3002 return is_executable_pte(spte);
3004 if (fault_err_code & PFERR_WRITE_MASK)
3005 return is_writable_pte(spte);
3007 /* Fault was on Read access */
3008 return spte & PT_PRESENT_MASK;
3012 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3014 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3017 struct kvm_shadow_walk_iterator iterator;
3018 struct kvm_mmu_page *sp;
3019 int ret = RET_PF_INVALID;
3021 uint retry_count = 0;
3023 if (!page_fault_can_be_fast(error_code))
3026 walk_shadow_page_lockless_begin(vcpu);
3031 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3032 if (!is_shadow_present_pte(spte))
3035 sp = sptep_to_sp(iterator.sptep);
3036 if (!is_last_spte(spte, sp->role.level))
3040 * Check whether the memory access that caused the fault would
3041 * still cause it if it were to be performed right now. If not,
3042 * then this is a spurious fault caused by TLB lazily flushed,
3043 * or some other CPU has already fixed the PTE after the
3044 * current CPU took the fault.
3046 * Need not check the access of upper level table entries since
3047 * they are always ACC_ALL.
3049 if (is_access_allowed(error_code, spte)) {
3050 ret = RET_PF_SPURIOUS;
3056 if (is_access_track_spte(spte))
3057 new_spte = restore_acc_track_spte(new_spte);
3060 * Currently, to simplify the code, write-protection can
3061 * be removed in the fast path only if the SPTE was
3062 * write-protected for dirty-logging or access tracking.
3064 if ((error_code & PFERR_WRITE_MASK) &&
3065 spte_can_locklessly_be_made_writable(spte)) {
3066 new_spte |= PT_WRITABLE_MASK;
3069 * Do not fix write-permission on the large spte. Since
3070 * we only dirty the first page into the dirty-bitmap in
3071 * fast_pf_fix_direct_spte(), other pages are missed
3072 * if its slot has dirty logging enabled.
3074 * Instead, we let the slow page fault path create a
3075 * normal spte to fix the access.
3077 * See the comments in kvm_arch_commit_memory_region().
3079 if (sp->role.level > PG_LEVEL_4K)
3083 /* Verify that the fault can be handled in the fast path */
3084 if (new_spte == spte ||
3085 !is_access_allowed(error_code, new_spte))
3089 * Currently, fast page fault only works for direct mapping
3090 * since the gfn is not stable for indirect shadow page. See
3091 * Documentation/virt/kvm/locking.rst to get more detail.
3093 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3099 if (++retry_count > 4) {
3100 printk_once(KERN_WARNING
3101 "kvm: Fast #PF retrying more than 4 times.\n");
3107 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3109 walk_shadow_page_lockless_end(vcpu);
3114 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3115 struct list_head *invalid_list)
3117 struct kvm_mmu_page *sp;
3119 if (!VALID_PAGE(*root_hpa))
3122 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3124 if (kvm_mmu_put_root(kvm, sp)) {
3125 if (sp->tdp_mmu_page)
3126 kvm_tdp_mmu_free_root(kvm, sp);
3127 else if (sp->role.invalid)
3128 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3131 *root_hpa = INVALID_PAGE;
3134 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3135 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3136 ulong roots_to_free)
3138 struct kvm *kvm = vcpu->kvm;
3140 LIST_HEAD(invalid_list);
3141 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3143 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3145 /* Before acquiring the MMU lock, see if we need to do any real work. */
3146 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3147 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3148 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3149 VALID_PAGE(mmu->prev_roots[i].hpa))
3152 if (i == KVM_MMU_NUM_PREV_ROOTS)
3156 spin_lock(&kvm->mmu_lock);
3158 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3159 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3160 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3163 if (free_active_root) {
3164 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3165 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3166 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3168 for (i = 0; i < 4; ++i)
3169 if (mmu->pae_root[i] != 0)
3170 mmu_free_root_page(kvm,
3173 mmu->root_hpa = INVALID_PAGE;
3178 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3179 spin_unlock(&kvm->mmu_lock);
3181 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3183 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3187 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3188 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3195 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3196 u8 level, bool direct)
3198 struct kvm_mmu_page *sp;
3200 spin_lock(&vcpu->kvm->mmu_lock);
3202 if (make_mmu_pages_available(vcpu)) {
3203 spin_unlock(&vcpu->kvm->mmu_lock);
3204 return INVALID_PAGE;
3206 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3209 spin_unlock(&vcpu->kvm->mmu_lock);
3210 return __pa(sp->spt);
3213 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3215 u8 shadow_root_level = vcpu->arch.mmu->shadow_root_level;
3219 if (vcpu->kvm->arch.tdp_mmu_enabled) {
3220 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3222 if (!VALID_PAGE(root))
3224 vcpu->arch.mmu->root_hpa = root;
3225 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3226 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level,
3229 if (!VALID_PAGE(root))
3231 vcpu->arch.mmu->root_hpa = root;
3232 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3233 for (i = 0; i < 4; ++i) {
3234 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3236 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3237 i << 30, PT32_ROOT_LEVEL, true);
3238 if (!VALID_PAGE(root))
3240 vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK;
3242 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3246 /* root_pgd is ignored for direct MMUs. */
3247 vcpu->arch.mmu->root_pgd = 0;
3252 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3255 gfn_t root_gfn, root_pgd;
3259 root_pgd = vcpu->arch.mmu->get_guest_pgd(vcpu);
3260 root_gfn = root_pgd >> PAGE_SHIFT;
3262 if (mmu_check_root(vcpu, root_gfn))
3266 * Do we shadow a long mode page table? If so we need to
3267 * write-protect the guests page table root.
3269 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3270 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->root_hpa));
3272 root = mmu_alloc_root(vcpu, root_gfn, 0,
3273 vcpu->arch.mmu->shadow_root_level, false);
3274 if (!VALID_PAGE(root))
3276 vcpu->arch.mmu->root_hpa = root;
3281 * We shadow a 32 bit page table. This may be a legacy 2-level
3282 * or a PAE 3-level page table. In either case we need to be aware that
3283 * the shadow page table may be a PAE or a long mode page table.
3285 pm_mask = PT_PRESENT_MASK;
3286 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3287 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3289 for (i = 0; i < 4; ++i) {
3290 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu->pae_root[i]));
3291 if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) {
3292 pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i);
3293 if (!(pdptr & PT_PRESENT_MASK)) {
3294 vcpu->arch.mmu->pae_root[i] = 0;
3297 root_gfn = pdptr >> PAGE_SHIFT;
3298 if (mmu_check_root(vcpu, root_gfn))
3302 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3303 PT32_ROOT_LEVEL, false);
3304 if (!VALID_PAGE(root))
3306 vcpu->arch.mmu->pae_root[i] = root | pm_mask;
3308 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root);
3311 * If we shadow a 32 bit page table with a long mode page
3312 * table we enter this path.
3314 if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3315 if (vcpu->arch.mmu->lm_root == NULL) {
3317 * The additional page necessary for this is only
3318 * allocated on demand.
3323 lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3324 if (lm_root == NULL)
3327 lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask;
3329 vcpu->arch.mmu->lm_root = lm_root;
3332 vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root);
3336 vcpu->arch.mmu->root_pgd = root_pgd;
3341 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3343 if (vcpu->arch.mmu->direct_map)
3344 return mmu_alloc_direct_roots(vcpu);
3346 return mmu_alloc_shadow_roots(vcpu);
3349 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3352 struct kvm_mmu_page *sp;
3354 if (vcpu->arch.mmu->direct_map)
3357 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3360 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3362 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3363 hpa_t root = vcpu->arch.mmu->root_hpa;
3364 sp = to_shadow_page(root);
3367 * Even if another CPU was marking the SP as unsync-ed
3368 * simultaneously, any guest page table changes are not
3369 * guaranteed to be visible anyway until this VCPU issues a TLB
3370 * flush strictly after those changes are made. We only need to
3371 * ensure that the other CPU sets these flags before any actual
3372 * changes to the page tables are made. The comments in
3373 * mmu_need_write_protect() describe what could go wrong if this
3374 * requirement isn't satisfied.
3376 if (!smp_load_acquire(&sp->unsync) &&
3377 !smp_load_acquire(&sp->unsync_children))
3380 spin_lock(&vcpu->kvm->mmu_lock);
3381 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3383 mmu_sync_children(vcpu, sp);
3385 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3386 spin_unlock(&vcpu->kvm->mmu_lock);
3390 spin_lock(&vcpu->kvm->mmu_lock);
3391 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3393 for (i = 0; i < 4; ++i) {
3394 hpa_t root = vcpu->arch.mmu->pae_root[i];
3396 if (root && VALID_PAGE(root)) {
3397 root &= PT64_BASE_ADDR_MASK;
3398 sp = to_shadow_page(root);
3399 mmu_sync_children(vcpu, sp);
3403 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3404 spin_unlock(&vcpu->kvm->mmu_lock);
3406 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3408 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3409 u32 access, struct x86_exception *exception)
3412 exception->error_code = 0;
3416 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3418 struct x86_exception *exception)
3421 exception->error_code = 0;
3422 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3426 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3428 int bit7 = (pte >> 7) & 1;
3430 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3433 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3435 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3438 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3441 * A nested guest cannot use the MMIO cache if it is using nested
3442 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3444 if (mmu_is_nested(vcpu))
3448 return vcpu_match_mmio_gpa(vcpu, addr);
3450 return vcpu_match_mmio_gva(vcpu, addr);
3453 /* return true if reserved bit is detected on spte. */
3455 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3457 struct kvm_shadow_walk_iterator iterator;
3458 u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull;
3459 struct rsvd_bits_validate *rsvd_check;
3461 bool reserved = false;
3463 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3465 walk_shadow_page_lockless_begin(vcpu);
3467 for (shadow_walk_init(&iterator, vcpu, addr),
3468 leaf = root = iterator.level;
3469 shadow_walk_okay(&iterator);
3470 __shadow_walk_next(&iterator, spte)) {
3471 spte = mmu_spte_get_lockless(iterator.sptep);
3473 sptes[leaf - 1] = spte;
3476 if (!is_shadow_present_pte(spte))
3480 * Use a bitwise-OR instead of a logical-OR to aggregate the
3481 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3482 * adding a Jcc in the loop.
3484 reserved |= __is_bad_mt_xwr(rsvd_check, spte) |
3485 __is_rsvd_bits_set(rsvd_check, spte, iterator.level);
3488 walk_shadow_page_lockless_end(vcpu);
3491 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3493 while (root > leaf) {
3494 pr_err("------ spte 0x%llx level %d.\n",
3495 sptes[root - 1], root);
3504 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3509 if (mmio_info_in_cache(vcpu, addr, direct))
3510 return RET_PF_EMULATE;
3512 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3513 if (WARN_ON(reserved))
3516 if (is_mmio_spte(spte)) {
3517 gfn_t gfn = get_mmio_spte_gfn(spte);
3518 unsigned int access = get_mmio_spte_access(spte);
3520 if (!check_mmio_spte(vcpu, spte))
3521 return RET_PF_INVALID;
3526 trace_handle_mmio_page_fault(addr, gfn, access);
3527 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3528 return RET_PF_EMULATE;
3532 * If the page table is zapped by other cpus, let CPU fault again on
3535 return RET_PF_RETRY;
3538 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3539 u32 error_code, gfn_t gfn)
3541 if (unlikely(error_code & PFERR_RSVD_MASK))
3544 if (!(error_code & PFERR_PRESENT_MASK) ||
3545 !(error_code & PFERR_WRITE_MASK))
3549 * guest is writing the page which is write tracked which can
3550 * not be fixed by page fault handler.
3552 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3558 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3560 struct kvm_shadow_walk_iterator iterator;
3563 walk_shadow_page_lockless_begin(vcpu);
3564 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3565 clear_sp_write_flooding_count(iterator.sptep);
3566 if (!is_shadow_present_pte(spte))
3569 walk_shadow_page_lockless_end(vcpu);
3572 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3575 struct kvm_arch_async_pf arch;
3577 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3579 arch.direct_map = vcpu->arch.mmu->direct_map;
3580 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3582 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3583 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3586 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3587 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, bool write,
3590 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3593 /* Don't expose private memslots to L2. */
3594 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3595 *pfn = KVM_PFN_NOSLOT;
3601 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3603 return false; /* *pfn has correct page already */
3605 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3606 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3607 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3608 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3609 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3611 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3615 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3619 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3620 bool prefault, int max_level, bool is_tdp)
3622 bool write = error_code & PFERR_WRITE_MASK;
3625 gfn_t gfn = gpa >> PAGE_SHIFT;
3626 unsigned long mmu_seq;
3630 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3631 return RET_PF_EMULATE;
3633 if (!is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) {
3634 r = fast_page_fault(vcpu, gpa, error_code);
3635 if (r != RET_PF_INVALID)
3639 r = mmu_topup_memory_caches(vcpu, false);
3643 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3646 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3647 return RET_PF_RETRY;
3649 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3653 spin_lock(&vcpu->kvm->mmu_lock);
3654 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3656 r = make_mmu_pages_available(vcpu);
3660 if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
3661 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3664 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3668 spin_unlock(&vcpu->kvm->mmu_lock);
3669 kvm_release_pfn_clean(pfn);
3673 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3674 u32 error_code, bool prefault)
3676 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3678 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3679 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3680 PG_LEVEL_2M, false);
3683 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3684 u64 fault_address, char *insn, int insn_len)
3687 u32 flags = vcpu->arch.apf.host_apf_flags;
3689 #ifndef CONFIG_X86_64
3690 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3691 if (WARN_ON_ONCE(fault_address >> 32))
3695 vcpu->arch.l1tf_flush_l1d = true;
3697 trace_kvm_page_fault(fault_address, error_code);
3699 if (kvm_event_needs_reinjection(vcpu))
3700 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3701 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3703 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3704 vcpu->arch.apf.host_apf_flags = 0;
3705 local_irq_disable();
3706 kvm_async_pf_task_wait_schedule(fault_address);
3709 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3714 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3716 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3721 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3722 max_level > PG_LEVEL_4K;
3724 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3725 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3727 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3731 return direct_page_fault(vcpu, gpa, error_code, prefault,
3735 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3736 struct kvm_mmu *context)
3738 context->page_fault = nonpaging_page_fault;
3739 context->gva_to_gpa = nonpaging_gva_to_gpa;
3740 context->sync_page = nonpaging_sync_page;
3741 context->invlpg = NULL;
3742 context->update_pte = nonpaging_update_pte;
3743 context->root_level = 0;
3744 context->shadow_root_level = PT32E_ROOT_LEVEL;
3745 context->direct_map = true;
3746 context->nx = false;
3749 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3750 union kvm_mmu_page_role role)
3752 return (role.direct || pgd == root->pgd) &&
3753 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3754 role.word == to_shadow_page(root->hpa)->role.word;
3758 * Find out if a previously cached root matching the new pgd/role is available.
3759 * The current root is also inserted into the cache.
3760 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3762 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3763 * false is returned. This root should now be freed by the caller.
3765 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3766 union kvm_mmu_page_role new_role)
3769 struct kvm_mmu_root_info root;
3770 struct kvm_mmu *mmu = vcpu->arch.mmu;
3772 root.pgd = mmu->root_pgd;
3773 root.hpa = mmu->root_hpa;
3775 if (is_root_usable(&root, new_pgd, new_role))
3778 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3779 swap(root, mmu->prev_roots[i]);
3781 if (is_root_usable(&root, new_pgd, new_role))
3785 mmu->root_hpa = root.hpa;
3786 mmu->root_pgd = root.pgd;
3788 return i < KVM_MMU_NUM_PREV_ROOTS;
3791 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3792 union kvm_mmu_page_role new_role)
3794 struct kvm_mmu *mmu = vcpu->arch.mmu;
3797 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3798 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3799 * later if necessary.
3801 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3802 mmu->root_level >= PT64_ROOT_4LEVEL)
3803 return cached_root_available(vcpu, new_pgd, new_role);
3808 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3809 union kvm_mmu_page_role new_role,
3810 bool skip_tlb_flush, bool skip_mmu_sync)
3812 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
3813 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
3818 * It's possible that the cached previous root page is obsolete because
3819 * of a change in the MMU generation number. However, changing the
3820 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
3821 * free the root set here and allocate a new one.
3823 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
3825 if (!skip_mmu_sync || force_flush_and_sync_on_reuse)
3826 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
3827 if (!skip_tlb_flush || force_flush_and_sync_on_reuse)
3828 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3831 * The last MMIO access's GVA and GPA are cached in the VCPU. When
3832 * switching to a new CR3, that GVA->GPA mapping may no longer be
3833 * valid. So clear any cached MMIO info even when we don't need to sync
3834 * the shadow page tables.
3836 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3838 __clear_sp_write_flooding_count(to_shadow_page(vcpu->arch.mmu->root_hpa));
3841 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
3844 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu),
3845 skip_tlb_flush, skip_mmu_sync);
3847 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
3849 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3851 return kvm_read_cr3(vcpu);
3854 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3855 unsigned int access, int *nr_present)
3857 if (unlikely(is_mmio_spte(*sptep))) {
3858 if (gfn != get_mmio_spte_gfn(*sptep)) {
3859 mmu_spte_clear_no_track(sptep);
3864 mark_mmio_spte(vcpu, sptep, gfn, access);
3871 static inline bool is_last_gpte(struct kvm_mmu *mmu,
3872 unsigned level, unsigned gpte)
3875 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
3876 * If it is clear, there are no large pages at this level, so clear
3877 * PT_PAGE_SIZE_MASK in gpte if that is the case.
3879 gpte &= level - mmu->last_nonleaf_level;
3882 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
3883 * iff level <= PG_LEVEL_4K, which for our purpose means
3884 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
3886 gpte |= level - PG_LEVEL_4K - 1;
3888 return gpte & PT_PAGE_SIZE_MASK;
3891 #define PTTYPE_EPT 18 /* arbitrary */
3892 #define PTTYPE PTTYPE_EPT
3893 #include "paging_tmpl.h"
3897 #include "paging_tmpl.h"
3901 #include "paging_tmpl.h"
3905 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3906 struct rsvd_bits_validate *rsvd_check,
3907 int maxphyaddr, int level, bool nx, bool gbpages,
3910 u64 exb_bit_rsvd = 0;
3911 u64 gbpages_bit_rsvd = 0;
3912 u64 nonleaf_bit8_rsvd = 0;
3914 rsvd_check->bad_mt_xwr = 0;
3917 exb_bit_rsvd = rsvd_bits(63, 63);
3919 gbpages_bit_rsvd = rsvd_bits(7, 7);
3922 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3923 * leaf entries) on AMD CPUs only.
3926 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3929 case PT32_ROOT_LEVEL:
3930 /* no rsvd bits for 2 level 4K page table entries */
3931 rsvd_check->rsvd_bits_mask[0][1] = 0;
3932 rsvd_check->rsvd_bits_mask[0][0] = 0;
3933 rsvd_check->rsvd_bits_mask[1][0] =
3934 rsvd_check->rsvd_bits_mask[0][0];
3937 rsvd_check->rsvd_bits_mask[1][1] = 0;
3941 if (is_cpuid_PSE36())
3942 /* 36bits PSE 4MB page */
3943 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3945 /* 32 bits PSE 4MB page */
3946 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3948 case PT32E_ROOT_LEVEL:
3949 rsvd_check->rsvd_bits_mask[0][2] =
3950 rsvd_bits(maxphyaddr, 63) |
3951 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3952 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3953 rsvd_bits(maxphyaddr, 62); /* PDE */
3954 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3955 rsvd_bits(maxphyaddr, 62); /* PTE */
3956 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3957 rsvd_bits(maxphyaddr, 62) |
3958 rsvd_bits(13, 20); /* large page */
3959 rsvd_check->rsvd_bits_mask[1][0] =
3960 rsvd_check->rsvd_bits_mask[0][0];
3962 case PT64_ROOT_5LEVEL:
3963 rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd |
3964 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3965 rsvd_bits(maxphyaddr, 51);
3966 rsvd_check->rsvd_bits_mask[1][4] =
3967 rsvd_check->rsvd_bits_mask[0][4];
3969 case PT64_ROOT_4LEVEL:
3970 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3971 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3972 rsvd_bits(maxphyaddr, 51);
3973 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3975 rsvd_bits(maxphyaddr, 51);
3976 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3977 rsvd_bits(maxphyaddr, 51);
3978 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3979 rsvd_bits(maxphyaddr, 51);
3980 rsvd_check->rsvd_bits_mask[1][3] =
3981 rsvd_check->rsvd_bits_mask[0][3];
3982 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3983 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3985 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3986 rsvd_bits(maxphyaddr, 51) |
3987 rsvd_bits(13, 20); /* large page */
3988 rsvd_check->rsvd_bits_mask[1][0] =
3989 rsvd_check->rsvd_bits_mask[0][0];
3994 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3995 struct kvm_mmu *context)
3997 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3998 cpuid_maxphyaddr(vcpu), context->root_level,
4000 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4002 guest_cpuid_is_amd_or_hygon(vcpu));
4006 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4007 int maxphyaddr, bool execonly)
4011 rsvd_check->rsvd_bits_mask[0][4] =
4012 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4013 rsvd_check->rsvd_bits_mask[0][3] =
4014 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
4015 rsvd_check->rsvd_bits_mask[0][2] =
4016 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4017 rsvd_check->rsvd_bits_mask[0][1] =
4018 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
4019 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
4022 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4023 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4024 rsvd_check->rsvd_bits_mask[1][2] =
4025 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
4026 rsvd_check->rsvd_bits_mask[1][1] =
4027 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
4028 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4030 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4031 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4032 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4033 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4034 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4036 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4037 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4039 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4042 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4043 struct kvm_mmu *context, bool execonly)
4045 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4046 cpuid_maxphyaddr(vcpu), execonly);
4050 * the page table on host is the shadow page table for the page
4051 * table in guest or amd nested guest, its mmu features completely
4052 * follow the features in guest.
4055 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
4057 bool uses_nx = context->nx ||
4058 context->mmu_role.base.smep_andnot_wp;
4059 struct rsvd_bits_validate *shadow_zero_check;
4063 * Passing "true" to the last argument is okay; it adds a check
4064 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4066 shadow_zero_check = &context->shadow_zero_check;
4067 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4069 context->shadow_root_level, uses_nx,
4070 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4071 is_pse(vcpu), true);
4073 if (!shadow_me_mask)
4076 for (i = context->shadow_root_level; --i >= 0;) {
4077 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4078 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4082 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
4084 static inline bool boot_cpu_is_amd(void)
4086 WARN_ON_ONCE(!tdp_enabled);
4087 return shadow_x_mask == 0;
4091 * the direct page table on host, use as much mmu features as
4092 * possible, however, kvm currently does not do execution-protection.
4095 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4096 struct kvm_mmu *context)
4098 struct rsvd_bits_validate *shadow_zero_check;
4101 shadow_zero_check = &context->shadow_zero_check;
4103 if (boot_cpu_is_amd())
4104 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4106 context->shadow_root_level, false,
4107 boot_cpu_has(X86_FEATURE_GBPAGES),
4110 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4114 if (!shadow_me_mask)
4117 for (i = context->shadow_root_level; --i >= 0;) {
4118 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4119 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4124 * as the comments in reset_shadow_zero_bits_mask() except it
4125 * is the shadow page table for intel nested guest.
4128 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4129 struct kvm_mmu *context, bool execonly)
4131 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4132 shadow_phys_bits, execonly);
4135 #define BYTE_MASK(access) \
4136 ((1 & (access) ? 2 : 0) | \
4137 (2 & (access) ? 4 : 0) | \
4138 (3 & (access) ? 8 : 0) | \
4139 (4 & (access) ? 16 : 0) | \
4140 (5 & (access) ? 32 : 0) | \
4141 (6 & (access) ? 64 : 0) | \
4142 (7 & (access) ? 128 : 0))
4145 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4146 struct kvm_mmu *mmu, bool ept)
4150 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4151 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4152 const u8 u = BYTE_MASK(ACC_USER_MASK);
4154 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4155 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4156 bool cr0_wp = is_write_protection(vcpu);
4158 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4159 unsigned pfec = byte << 1;
4162 * Each "*f" variable has a 1 bit for each UWX value
4163 * that causes a fault with the given PFEC.
4166 /* Faults from writes to non-writable pages */
4167 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4168 /* Faults from user mode accesses to supervisor pages */
4169 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4170 /* Faults from fetches of non-executable pages*/
4171 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4172 /* Faults from kernel mode fetches of user pages */
4174 /* Faults from kernel mode accesses of user pages */
4178 /* Faults from kernel mode accesses to user pages */
4179 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4181 /* Not really needed: !nx will cause pte.nx to fault */
4185 /* Allow supervisor writes if !cr0.wp */
4187 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4189 /* Disallow supervisor fetches of user code if cr4.smep */
4191 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4194 * SMAP:kernel-mode data accesses from user-mode
4195 * mappings should fault. A fault is considered
4196 * as a SMAP violation if all of the following
4197 * conditions are true:
4198 * - X86_CR4_SMAP is set in CR4
4199 * - A user page is accessed
4200 * - The access is not a fetch
4201 * - Page fault in kernel mode
4202 * - if CPL = 3 or X86_EFLAGS_AC is clear
4204 * Here, we cover the first three conditions.
4205 * The fourth is computed dynamically in permission_fault();
4206 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4207 * *not* subject to SMAP restrictions.
4210 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4213 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4218 * PKU is an additional mechanism by which the paging controls access to
4219 * user-mode addresses based on the value in the PKRU register. Protection
4220 * key violations are reported through a bit in the page fault error code.
4221 * Unlike other bits of the error code, the PK bit is not known at the
4222 * call site of e.g. gva_to_gpa; it must be computed directly in
4223 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4224 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4226 * In particular the following conditions come from the error code, the
4227 * page tables and the machine state:
4228 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4229 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4230 * - PK is always zero if U=0 in the page tables
4231 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4233 * The PKRU bitmask caches the result of these four conditions. The error
4234 * code (minus the P bit) and the page table's U bit form an index into the
4235 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4236 * with the two bits of the PKRU register corresponding to the protection key.
4237 * For the first three conditions above the bits will be 00, thus masking
4238 * away both AD and WD. For all reads or if the last condition holds, WD
4239 * only will be masked away.
4241 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4252 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4253 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4258 wp = is_write_protection(vcpu);
4260 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4261 unsigned pfec, pkey_bits;
4262 bool check_pkey, check_write, ff, uf, wf, pte_user;
4265 ff = pfec & PFERR_FETCH_MASK;
4266 uf = pfec & PFERR_USER_MASK;
4267 wf = pfec & PFERR_WRITE_MASK;
4269 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4270 pte_user = pfec & PFERR_RSVD_MASK;
4273 * Only need to check the access which is not an
4274 * instruction fetch and is to a user page.
4276 check_pkey = (!ff && pte_user);
4278 * write access is controlled by PKRU if it is a
4279 * user access or CR0.WP = 1.
4281 check_write = check_pkey && wf && (uf || wp);
4283 /* PKRU.AD stops both read and write access. */
4284 pkey_bits = !!check_pkey;
4285 /* PKRU.WD stops write access. */
4286 pkey_bits |= (!!check_write) << 1;
4288 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4292 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4294 unsigned root_level = mmu->root_level;
4296 mmu->last_nonleaf_level = root_level;
4297 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4298 mmu->last_nonleaf_level++;
4301 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4302 struct kvm_mmu *context,
4305 context->nx = is_nx(vcpu);
4306 context->root_level = level;
4308 reset_rsvds_bits_mask(vcpu, context);
4309 update_permission_bitmask(vcpu, context, false);
4310 update_pkru_bitmask(vcpu, context, false);
4311 update_last_nonleaf_level(vcpu, context);
4313 MMU_WARN_ON(!is_pae(vcpu));
4314 context->page_fault = paging64_page_fault;
4315 context->gva_to_gpa = paging64_gva_to_gpa;
4316 context->sync_page = paging64_sync_page;
4317 context->invlpg = paging64_invlpg;
4318 context->update_pte = paging64_update_pte;
4319 context->shadow_root_level = level;
4320 context->direct_map = false;
4323 static void paging64_init_context(struct kvm_vcpu *vcpu,
4324 struct kvm_mmu *context)
4326 int root_level = is_la57_mode(vcpu) ?
4327 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4329 paging64_init_context_common(vcpu, context, root_level);
4332 static void paging32_init_context(struct kvm_vcpu *vcpu,
4333 struct kvm_mmu *context)
4335 context->nx = false;
4336 context->root_level = PT32_ROOT_LEVEL;
4338 reset_rsvds_bits_mask(vcpu, context);
4339 update_permission_bitmask(vcpu, context, false);
4340 update_pkru_bitmask(vcpu, context, false);
4341 update_last_nonleaf_level(vcpu, context);
4343 context->page_fault = paging32_page_fault;
4344 context->gva_to_gpa = paging32_gva_to_gpa;
4345 context->sync_page = paging32_sync_page;
4346 context->invlpg = paging32_invlpg;
4347 context->update_pte = paging32_update_pte;
4348 context->shadow_root_level = PT32E_ROOT_LEVEL;
4349 context->direct_map = false;
4352 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4353 struct kvm_mmu *context)
4355 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4358 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4360 union kvm_mmu_extended_role ext = {0};
4362 ext.cr0_pg = !!is_paging(vcpu);
4363 ext.cr4_pae = !!is_pae(vcpu);
4364 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4365 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4366 ext.cr4_pse = !!is_pse(vcpu);
4367 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4368 ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
4375 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4378 union kvm_mmu_role role = {0};
4380 role.base.access = ACC_ALL;
4381 role.base.nxe = !!is_nx(vcpu);
4382 role.base.cr0_wp = is_write_protection(vcpu);
4383 role.base.smm = is_smm(vcpu);
4384 role.base.guest_mode = is_guest_mode(vcpu);
4389 role.ext = kvm_calc_mmu_role_ext(vcpu);
4394 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4396 /* Use 5-level TDP if and only if it's useful/necessary. */
4397 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4400 return max_tdp_level;
4403 static union kvm_mmu_role
4404 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4406 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4408 role.base.ad_disabled = (shadow_accessed_mask == 0);
4409 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4410 role.base.direct = true;
4411 role.base.gpte_is_8_bytes = true;
4416 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4418 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4419 union kvm_mmu_role new_role =
4420 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4422 if (new_role.as_u64 == context->mmu_role.as_u64)
4425 context->mmu_role.as_u64 = new_role.as_u64;
4426 context->page_fault = kvm_tdp_page_fault;
4427 context->sync_page = nonpaging_sync_page;
4428 context->invlpg = NULL;
4429 context->update_pte = nonpaging_update_pte;
4430 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4431 context->direct_map = true;
4432 context->get_guest_pgd = get_cr3;
4433 context->get_pdptr = kvm_pdptr_read;
4434 context->inject_page_fault = kvm_inject_page_fault;
4436 if (!is_paging(vcpu)) {
4437 context->nx = false;
4438 context->gva_to_gpa = nonpaging_gva_to_gpa;
4439 context->root_level = 0;
4440 } else if (is_long_mode(vcpu)) {
4441 context->nx = is_nx(vcpu);
4442 context->root_level = is_la57_mode(vcpu) ?
4443 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4444 reset_rsvds_bits_mask(vcpu, context);
4445 context->gva_to_gpa = paging64_gva_to_gpa;
4446 } else if (is_pae(vcpu)) {
4447 context->nx = is_nx(vcpu);
4448 context->root_level = PT32E_ROOT_LEVEL;
4449 reset_rsvds_bits_mask(vcpu, context);
4450 context->gva_to_gpa = paging64_gva_to_gpa;
4452 context->nx = false;
4453 context->root_level = PT32_ROOT_LEVEL;
4454 reset_rsvds_bits_mask(vcpu, context);
4455 context->gva_to_gpa = paging32_gva_to_gpa;
4458 update_permission_bitmask(vcpu, context, false);
4459 update_pkru_bitmask(vcpu, context, false);
4460 update_last_nonleaf_level(vcpu, context);
4461 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4464 static union kvm_mmu_role
4465 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4467 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4469 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4470 !is_write_protection(vcpu);
4471 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4472 !is_write_protection(vcpu);
4473 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4478 static union kvm_mmu_role
4479 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4481 union kvm_mmu_role role =
4482 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4484 role.base.direct = !is_paging(vcpu);
4486 if (!is_long_mode(vcpu))
4487 role.base.level = PT32E_ROOT_LEVEL;
4488 else if (is_la57_mode(vcpu))
4489 role.base.level = PT64_ROOT_5LEVEL;
4491 role.base.level = PT64_ROOT_4LEVEL;
4496 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4497 u32 cr0, u32 cr4, u32 efer,
4498 union kvm_mmu_role new_role)
4500 if (!(cr0 & X86_CR0_PG))
4501 nonpaging_init_context(vcpu, context);
4502 else if (efer & EFER_LMA)
4503 paging64_init_context(vcpu, context);
4504 else if (cr4 & X86_CR4_PAE)
4505 paging32E_init_context(vcpu, context);
4507 paging32_init_context(vcpu, context);
4509 context->mmu_role.as_u64 = new_role.as_u64;
4510 reset_shadow_zero_bits_mask(vcpu, context);
4513 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer)
4515 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4516 union kvm_mmu_role new_role =
4517 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4519 if (new_role.as_u64 != context->mmu_role.as_u64)
4520 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4523 static union kvm_mmu_role
4524 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4526 union kvm_mmu_role role =
4527 kvm_calc_shadow_root_page_role_common(vcpu, false);
4529 role.base.direct = false;
4530 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4535 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, u32 cr0, u32 cr4, u32 efer,
4538 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4539 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4541 context->shadow_root_level = new_role.base.level;
4543 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base, false, false);
4545 if (new_role.as_u64 != context->mmu_role.as_u64)
4546 shadow_mmu_init_context(vcpu, context, cr0, cr4, efer, new_role);
4548 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4550 static union kvm_mmu_role
4551 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4552 bool execonly, u8 level)
4554 union kvm_mmu_role role = {0};
4556 /* SMM flag is inherited from root_mmu */
4557 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4559 role.base.level = level;
4560 role.base.gpte_is_8_bytes = true;
4561 role.base.direct = false;
4562 role.base.ad_disabled = !accessed_dirty;
4563 role.base.guest_mode = true;
4564 role.base.access = ACC_ALL;
4567 * WP=1 and NOT_WP=1 is an impossible combination, use WP and the
4568 * SMAP variation to denote shadow EPT entries.
4570 role.base.cr0_wp = true;
4571 role.base.smap_andnot_wp = true;
4573 role.ext = kvm_calc_mmu_role_ext(vcpu);
4574 role.ext.execonly = execonly;
4579 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4580 bool accessed_dirty, gpa_t new_eptp)
4582 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4583 u8 level = vmx_eptp_page_walk_level(new_eptp);
4584 union kvm_mmu_role new_role =
4585 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4588 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base, true, true);
4590 if (new_role.as_u64 == context->mmu_role.as_u64)
4593 context->shadow_root_level = level;
4596 context->ept_ad = accessed_dirty;
4597 context->page_fault = ept_page_fault;
4598 context->gva_to_gpa = ept_gva_to_gpa;
4599 context->sync_page = ept_sync_page;
4600 context->invlpg = ept_invlpg;
4601 context->update_pte = ept_update_pte;
4602 context->root_level = level;
4603 context->direct_map = false;
4604 context->mmu_role.as_u64 = new_role.as_u64;
4606 update_permission_bitmask(vcpu, context, true);
4607 update_pkru_bitmask(vcpu, context, true);
4608 update_last_nonleaf_level(vcpu, context);
4609 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4610 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4612 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4614 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4616 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4618 kvm_init_shadow_mmu(vcpu,
4619 kvm_read_cr0_bits(vcpu, X86_CR0_PG),
4620 kvm_read_cr4_bits(vcpu, X86_CR4_PAE),
4623 context->get_guest_pgd = get_cr3;
4624 context->get_pdptr = kvm_pdptr_read;
4625 context->inject_page_fault = kvm_inject_page_fault;
4628 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4630 union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false);
4631 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4633 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4636 g_context->mmu_role.as_u64 = new_role.as_u64;
4637 g_context->get_guest_pgd = get_cr3;
4638 g_context->get_pdptr = kvm_pdptr_read;
4639 g_context->inject_page_fault = kvm_inject_page_fault;
4642 * L2 page tables are never shadowed, so there is no need to sync
4645 g_context->invlpg = NULL;
4648 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4649 * L1's nested page tables (e.g. EPT12). The nested translation
4650 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4651 * L2's page tables as the first level of translation and L1's
4652 * nested page tables as the second level of translation. Basically
4653 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4655 if (!is_paging(vcpu)) {
4656 g_context->nx = false;
4657 g_context->root_level = 0;
4658 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4659 } else if (is_long_mode(vcpu)) {
4660 g_context->nx = is_nx(vcpu);
4661 g_context->root_level = is_la57_mode(vcpu) ?
4662 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4663 reset_rsvds_bits_mask(vcpu, g_context);
4664 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4665 } else if (is_pae(vcpu)) {
4666 g_context->nx = is_nx(vcpu);
4667 g_context->root_level = PT32E_ROOT_LEVEL;
4668 reset_rsvds_bits_mask(vcpu, g_context);
4669 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4671 g_context->nx = false;
4672 g_context->root_level = PT32_ROOT_LEVEL;
4673 reset_rsvds_bits_mask(vcpu, g_context);
4674 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4677 update_permission_bitmask(vcpu, g_context, false);
4678 update_pkru_bitmask(vcpu, g_context, false);
4679 update_last_nonleaf_level(vcpu, g_context);
4682 void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots)
4687 vcpu->arch.mmu->root_hpa = INVALID_PAGE;
4689 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
4690 vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
4693 if (mmu_is_nested(vcpu))
4694 init_kvm_nested_mmu(vcpu);
4695 else if (tdp_enabled)
4696 init_kvm_tdp_mmu(vcpu);
4698 init_kvm_softmmu(vcpu);
4700 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4702 static union kvm_mmu_page_role
4703 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4705 union kvm_mmu_role role;
4708 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4710 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4715 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4717 kvm_mmu_unload(vcpu);
4718 kvm_init_mmu(vcpu, true);
4720 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4722 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4726 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4729 r = mmu_alloc_roots(vcpu);
4730 kvm_mmu_sync_roots(vcpu);
4733 kvm_mmu_load_pgd(vcpu);
4734 kvm_x86_ops.tlb_flush_current(vcpu);
4738 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4740 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4742 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4743 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4744 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4745 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4747 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4749 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4750 struct kvm_mmu_page *sp, u64 *spte,
4753 if (sp->role.level != PG_LEVEL_4K) {
4754 ++vcpu->kvm->stat.mmu_pde_zapped;
4758 ++vcpu->kvm->stat.mmu_pte_updated;
4759 vcpu->arch.mmu->update_pte(vcpu, sp, spte, new);
4762 static bool need_remote_flush(u64 old, u64 new)
4764 if (!is_shadow_present_pte(old))
4766 if (!is_shadow_present_pte(new))
4768 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4770 old ^= shadow_nx_mask;
4771 new ^= shadow_nx_mask;
4772 return (old & ~new & PT64_PERM_MASK) != 0;
4775 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4782 * Assume that the pte write on a page table of the same type
4783 * as the current vcpu paging mode since we update the sptes only
4784 * when they have the same mode.
4786 if (is_pae(vcpu) && *bytes == 4) {
4787 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4792 if (*bytes == 4 || *bytes == 8) {
4793 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
4802 * If we're seeing too many writes to a page, it may no longer be a page table,
4803 * or we may be forking, in which case it is better to unmap the page.
4805 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4808 * Skip write-flooding detected for the sp whose level is 1, because
4809 * it can become unsync, then the guest page is not write-protected.
4811 if (sp->role.level == PG_LEVEL_4K)
4814 atomic_inc(&sp->write_flooding_count);
4815 return atomic_read(&sp->write_flooding_count) >= 3;
4819 * Misaligned accesses are too much trouble to fix up; also, they usually
4820 * indicate a page is not used as a page table.
4822 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4825 unsigned offset, pte_size, misaligned;
4827 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4828 gpa, bytes, sp->role.word);
4830 offset = offset_in_page(gpa);
4831 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
4834 * Sometimes, the OS only writes the last one bytes to update status
4835 * bits, for example, in linux, andb instruction is used in clear_bit().
4837 if (!(offset & (pte_size - 1)) && bytes == 1)
4840 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4841 misaligned |= bytes < 4;
4846 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4848 unsigned page_offset, quadrant;
4852 page_offset = offset_in_page(gpa);
4853 level = sp->role.level;
4855 if (!sp->role.gpte_is_8_bytes) {
4856 page_offset <<= 1; /* 32->64 */
4858 * A 32-bit pde maps 4MB while the shadow pdes map
4859 * only 2MB. So we need to double the offset again
4860 * and zap two pdes instead of one.
4862 if (level == PT32_ROOT_LEVEL) {
4863 page_offset &= ~7; /* kill rounding error */
4867 quadrant = page_offset >> PAGE_SHIFT;
4868 page_offset &= ~PAGE_MASK;
4869 if (quadrant != sp->role.quadrant)
4873 spte = &sp->spt[page_offset / sizeof(*spte)];
4878 * Ignore various flags when determining if a SPTE can be immediately
4879 * overwritten for the current MMU.
4880 * - level: explicitly checked in mmu_pte_write_new_pte(), and will never
4881 * match the current MMU role, as MMU's level tracks the root level.
4882 * - access: updated based on the new guest PTE
4883 * - quadrant: handled by get_written_sptes()
4884 * - invalid: always false (loop only walks valid shadow pages)
4886 static const union kvm_mmu_page_role role_ign = {
4893 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4894 const u8 *new, int bytes,
4895 struct kvm_page_track_notifier_node *node)
4897 gfn_t gfn = gpa >> PAGE_SHIFT;
4898 struct kvm_mmu_page *sp;
4899 LIST_HEAD(invalid_list);
4900 u64 entry, gentry, *spte;
4902 bool remote_flush, local_flush;
4905 * If we don't have indirect shadow pages, it means no page is
4906 * write-protected, so we can exit simply.
4908 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4911 remote_flush = local_flush = false;
4913 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4916 * No need to care whether allocation memory is successful
4917 * or not since pte prefetch is skiped if it does not have
4918 * enough objects in the cache.
4920 mmu_topup_memory_caches(vcpu, true);
4922 spin_lock(&vcpu->kvm->mmu_lock);
4924 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
4926 ++vcpu->kvm->stat.mmu_pte_write;
4927 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4929 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4930 if (detect_write_misaligned(sp, gpa, bytes) ||
4931 detect_write_flooding(sp)) {
4932 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
4933 ++vcpu->kvm->stat.mmu_flooded;
4937 spte = get_written_sptes(sp, gpa, &npte);
4943 u32 base_role = vcpu->arch.mmu->mmu_role.base.word;
4946 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
4948 !((sp->role.word ^ base_role) & ~role_ign.word) &&
4950 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4951 if (need_remote_flush(entry, *spte))
4952 remote_flush = true;
4956 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
4957 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4958 spin_unlock(&vcpu->kvm->mmu_lock);
4961 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4966 if (vcpu->arch.mmu->direct_map)
4969 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4971 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4975 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4977 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
4978 void *insn, int insn_len)
4980 int r, emulation_type = EMULTYPE_PF;
4981 bool direct = vcpu->arch.mmu->direct_map;
4983 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
4984 return RET_PF_RETRY;
4987 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4988 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
4989 if (r == RET_PF_EMULATE)
4993 if (r == RET_PF_INVALID) {
4994 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
4995 lower_32_bits(error_code), false);
4996 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5002 if (r != RET_PF_EMULATE)
5006 * Before emulating the instruction, check if the error code
5007 * was due to a RO violation while translating the guest page.
5008 * This can occur when using nested virtualization with nested
5009 * paging in both guests. If true, we simply unprotect the page
5010 * and resume the guest.
5012 if (vcpu->arch.mmu->direct_map &&
5013 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5014 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5019 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5020 * optimistically try to just unprotect the page and let the processor
5021 * re-execute the instruction that caused the page fault. Do not allow
5022 * retrying MMIO emulation, as it's not only pointless but could also
5023 * cause us to enter an infinite loop because the processor will keep
5024 * faulting on the non-existent MMIO address. Retrying an instruction
5025 * from a nested guest is also pointless and dangerous as we are only
5026 * explicitly shadowing L1's page tables, i.e. unprotecting something
5027 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5029 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5030 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5032 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5035 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5037 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5038 gva_t gva, hpa_t root_hpa)
5042 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5043 if (mmu != &vcpu->arch.guest_mmu) {
5044 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5045 if (is_noncanonical_address(gva, vcpu))
5048 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5054 if (root_hpa == INVALID_PAGE) {
5055 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5058 * INVLPG is required to invalidate any global mappings for the VA,
5059 * irrespective of PCID. Since it would take us roughly similar amount
5060 * of work to determine whether any of the prev_root mappings of the VA
5061 * is marked global, or to just sync it blindly, so we might as well
5062 * just always sync it.
5064 * Mappings not reachable via the current cr3 or the prev_roots will be
5065 * synced when switching to that cr3, so nothing needs to be done here
5068 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5069 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5070 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5072 mmu->invlpg(vcpu, gva, root_hpa);
5075 EXPORT_SYMBOL_GPL(kvm_mmu_invalidate_gva);
5077 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5079 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5080 ++vcpu->stat.invlpg;
5082 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5085 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5087 struct kvm_mmu *mmu = vcpu->arch.mmu;
5088 bool tlb_flush = false;
5091 if (pcid == kvm_get_active_pcid(vcpu)) {
5092 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5096 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5097 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5098 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5099 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5105 kvm_x86_ops.tlb_flush_gva(vcpu, gva);
5107 ++vcpu->stat.invlpg;
5110 * Mappings not reachable via the current cr3 or the prev_roots will be
5111 * synced when switching to that cr3, so nothing needs to be done here
5115 EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva);
5117 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5118 int tdp_huge_page_level)
5120 tdp_enabled = enable_tdp;
5121 max_tdp_level = tdp_max_root_level;
5124 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5125 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5126 * the kernel is not. But, KVM never creates a page size greater than
5127 * what is used by the kernel for any given HVA, i.e. the kernel's
5128 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5131 max_huge_page_level = tdp_huge_page_level;
5132 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5133 max_huge_page_level = PG_LEVEL_1G;
5135 max_huge_page_level = PG_LEVEL_2M;
5137 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5139 /* The return value indicates if tlb flush on all vcpus is needed. */
5140 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
5142 /* The caller should hold mmu-lock before calling this function. */
5143 static __always_inline bool
5144 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5145 slot_level_handler fn, int start_level, int end_level,
5146 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
5148 struct slot_rmap_walk_iterator iterator;
5151 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5152 end_gfn, &iterator) {
5154 flush |= fn(kvm, iterator.rmap);
5156 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5157 if (flush && lock_flush_tlb) {
5158 kvm_flush_remote_tlbs_with_address(kvm,
5160 iterator.gfn - start_gfn + 1);
5163 cond_resched_lock(&kvm->mmu_lock);
5167 if (flush && lock_flush_tlb) {
5168 kvm_flush_remote_tlbs_with_address(kvm, start_gfn,
5169 end_gfn - start_gfn + 1);
5176 static __always_inline bool
5177 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5178 slot_level_handler fn, int start_level, int end_level,
5179 bool lock_flush_tlb)
5181 return slot_handle_level_range(kvm, memslot, fn, start_level,
5182 end_level, memslot->base_gfn,
5183 memslot->base_gfn + memslot->npages - 1,
5187 static __always_inline bool
5188 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5189 slot_level_handler fn, bool lock_flush_tlb)
5191 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5192 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5195 static __always_inline bool
5196 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5197 slot_level_handler fn, bool lock_flush_tlb)
5199 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K + 1,
5200 KVM_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
5203 static __always_inline bool
5204 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5205 slot_level_handler fn, bool lock_flush_tlb)
5207 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5208 PG_LEVEL_4K, lock_flush_tlb);
5211 static void free_mmu_pages(struct kvm_mmu *mmu)
5213 free_page((unsigned long)mmu->pae_root);
5214 free_page((unsigned long)mmu->lm_root);
5217 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5222 mmu->root_hpa = INVALID_PAGE;
5224 mmu->translate_gpa = translate_gpa;
5225 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5226 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5229 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5230 * while the PDP table is a per-vCPU construct that's allocated at MMU
5231 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5232 * x86_64. Therefore we need to allocate the PDP table in the first
5233 * 4GB of memory, which happens to fit the DMA32 zone. Except for
5234 * SVM's 32-bit NPT support, TDP paging doesn't use PAE paging and can
5235 * skip allocating the PDP table.
5237 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5240 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5244 mmu->pae_root = page_address(page);
5245 for (i = 0; i < 4; ++i)
5246 mmu->pae_root[i] = INVALID_PAGE;
5251 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5255 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5256 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5258 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5259 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5261 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5263 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5264 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5266 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5268 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5272 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5274 goto fail_allocate_root;
5278 free_mmu_pages(&vcpu->arch.guest_mmu);
5282 #define BATCH_ZAP_PAGES 10
5283 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5285 struct kvm_mmu_page *sp, *node;
5286 int nr_zapped, batch = 0;
5289 list_for_each_entry_safe_reverse(sp, node,
5290 &kvm->arch.active_mmu_pages, link) {
5292 * No obsolete valid page exists before a newly created page
5293 * since active_mmu_pages is a FIFO list.
5295 if (!is_obsolete_sp(kvm, sp))
5299 * Invalid pages should never land back on the list of active
5300 * pages. Skip the bogus page, otherwise we'll get stuck in an
5301 * infinite loop if the page gets put back on the list (again).
5303 if (WARN_ON(sp->role.invalid))
5307 * No need to flush the TLB since we're only zapping shadow
5308 * pages with an obsolete generation number and all vCPUS have
5309 * loaded a new root, i.e. the shadow pages being zapped cannot
5310 * be in active use by the guest.
5312 if (batch >= BATCH_ZAP_PAGES &&
5313 cond_resched_lock(&kvm->mmu_lock)) {
5318 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5319 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5326 * Trigger a remote TLB flush before freeing the page tables to ensure
5327 * KVM is not in the middle of a lockless shadow page table walk, which
5328 * may reference the pages.
5330 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5334 * Fast invalidate all shadow pages and use lock-break technique
5335 * to zap obsolete pages.
5337 * It's required when memslot is being deleted or VM is being
5338 * destroyed, in these cases, we should ensure that KVM MMU does
5339 * not use any resource of the being-deleted slot or all slots
5340 * after calling the function.
5342 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5344 lockdep_assert_held(&kvm->slots_lock);
5346 spin_lock(&kvm->mmu_lock);
5347 trace_kvm_mmu_zap_all_fast(kvm);
5350 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5351 * held for the entire duration of zapping obsolete pages, it's
5352 * impossible for there to be multiple invalid generations associated
5353 * with *valid* shadow pages at any given time, i.e. there is exactly
5354 * one valid generation and (at most) one invalid generation.
5356 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5359 * Notify all vcpus to reload its shadow page table and flush TLB.
5360 * Then all vcpus will switch to new shadow page table with the new
5363 * Note: we need to do this under the protection of mmu_lock,
5364 * otherwise, vcpu would purge shadow page but miss tlb flush.
5366 kvm_reload_remote_mmus(kvm);
5368 kvm_zap_obsolete_pages(kvm);
5370 if (kvm->arch.tdp_mmu_enabled)
5371 kvm_tdp_mmu_zap_all(kvm);
5373 spin_unlock(&kvm->mmu_lock);
5376 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5378 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5381 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5382 struct kvm_memory_slot *slot,
5383 struct kvm_page_track_notifier_node *node)
5385 kvm_mmu_zap_all_fast(kvm);
5388 void kvm_mmu_init_vm(struct kvm *kvm)
5390 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5392 kvm_mmu_init_tdp_mmu(kvm);
5394 node->track_write = kvm_mmu_pte_write;
5395 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5396 kvm_page_track_register_notifier(kvm, node);
5399 void kvm_mmu_uninit_vm(struct kvm *kvm)
5401 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5403 kvm_page_track_unregister_notifier(kvm, node);
5405 kvm_mmu_uninit_tdp_mmu(kvm);
5408 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5410 struct kvm_memslots *slots;
5411 struct kvm_memory_slot *memslot;
5415 spin_lock(&kvm->mmu_lock);
5416 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5417 slots = __kvm_memslots(kvm, i);
5418 kvm_for_each_memslot(memslot, slots) {
5421 start = max(gfn_start, memslot->base_gfn);
5422 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5426 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
5428 KVM_MAX_HUGEPAGE_LEVEL,
5429 start, end - 1, true);
5433 if (kvm->arch.tdp_mmu_enabled) {
5434 flush = kvm_tdp_mmu_zap_gfn_range(kvm, gfn_start, gfn_end);
5436 kvm_flush_remote_tlbs(kvm);
5439 spin_unlock(&kvm->mmu_lock);
5442 static bool slot_rmap_write_protect(struct kvm *kvm,
5443 struct kvm_rmap_head *rmap_head)
5445 return __rmap_write_protect(kvm, rmap_head, false);
5448 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5449 struct kvm_memory_slot *memslot,
5454 spin_lock(&kvm->mmu_lock);
5455 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5456 start_level, KVM_MAX_HUGEPAGE_LEVEL, false);
5457 spin_unlock(&kvm->mmu_lock);
5460 * We can flush all the TLBs out of the mmu lock without TLB
5461 * corruption since we just change the spte from writable to
5462 * readonly so that we only need to care the case of changing
5463 * spte from present to present (changing the spte from present
5464 * to nonpresent will flush all the TLBs immediately), in other
5465 * words, the only case we care is mmu_spte_update() where we
5466 * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
5467 * instead of PT_WRITABLE_MASK, that means it does not depend
5468 * on PT_WRITABLE_MASK anymore.
5471 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5474 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5475 struct kvm_rmap_head *rmap_head)
5478 struct rmap_iterator iter;
5479 int need_tlb_flush = 0;
5481 struct kvm_mmu_page *sp;
5484 for_each_rmap_spte(rmap_head, &iter, sptep) {
5485 sp = sptep_to_sp(sptep);
5486 pfn = spte_to_pfn(*sptep);
5489 * We cannot do huge page mapping for indirect shadow pages,
5490 * which are found on the last rmap (level = 1) when not using
5491 * tdp; such shadow pages are synced with the page table in
5492 * the guest, and the guest page table is using 4K page size
5493 * mapping if the indirect sp has level = 1.
5495 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5496 (kvm_is_zone_device_pfn(pfn) ||
5497 PageCompound(pfn_to_page(pfn)))) {
5498 pte_list_remove(rmap_head, sptep);
5500 if (kvm_available_flush_tlb_with_range())
5501 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5502 KVM_PAGES_PER_HPAGE(sp->role.level));
5510 return need_tlb_flush;
5513 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5514 const struct kvm_memory_slot *memslot)
5516 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5517 spin_lock(&kvm->mmu_lock);
5518 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
5519 kvm_mmu_zap_collapsible_spte, true);
5520 spin_unlock(&kvm->mmu_lock);
5523 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5524 struct kvm_memory_slot *memslot)
5527 * All current use cases for flushing the TLBs for a specific memslot
5528 * are related to dirty logging, and do the TLB flush out of mmu_lock.
5529 * The interaction between the various operations on memslot must be
5530 * serialized by slots_locks to ensure the TLB flush from one operation
5531 * is observed by any other operation on the same memslot.
5533 lockdep_assert_held(&kvm->slots_lock);
5534 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5538 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5539 struct kvm_memory_slot *memslot)
5543 spin_lock(&kvm->mmu_lock);
5544 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
5545 spin_unlock(&kvm->mmu_lock);
5548 * It's also safe to flush TLBs out of mmu lock here as currently this
5549 * function is only used for dirty logging, in which case flushing TLB
5550 * out of mmu lock also guarantees no dirty pages will be lost in
5554 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5556 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
5558 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
5559 struct kvm_memory_slot *memslot)
5563 spin_lock(&kvm->mmu_lock);
5564 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
5566 spin_unlock(&kvm->mmu_lock);
5569 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5571 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
5573 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
5574 struct kvm_memory_slot *memslot)
5578 spin_lock(&kvm->mmu_lock);
5579 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
5580 spin_unlock(&kvm->mmu_lock);
5583 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5585 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
5587 void kvm_mmu_zap_all(struct kvm *kvm)
5589 struct kvm_mmu_page *sp, *node;
5590 LIST_HEAD(invalid_list);
5593 spin_lock(&kvm->mmu_lock);
5595 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5596 if (WARN_ON(sp->role.invalid))
5598 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5600 if (cond_resched_lock(&kvm->mmu_lock))
5604 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5606 if (kvm->arch.tdp_mmu_enabled)
5607 kvm_tdp_mmu_zap_all(kvm);
5609 spin_unlock(&kvm->mmu_lock);
5612 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5614 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5616 gen &= MMIO_SPTE_GEN_MASK;
5619 * Generation numbers are incremented in multiples of the number of
5620 * address spaces in order to provide unique generations across all
5621 * address spaces. Strip what is effectively the address space
5622 * modifier prior to checking for a wrap of the MMIO generation so
5623 * that a wrap in any address space is detected.
5625 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5628 * The very rare case: if the MMIO generation number has wrapped,
5629 * zap all shadow pages.
5631 if (unlikely(gen == 0)) {
5632 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5633 kvm_mmu_zap_all_fast(kvm);
5637 static unsigned long
5638 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5641 int nr_to_scan = sc->nr_to_scan;
5642 unsigned long freed = 0;
5644 mutex_lock(&kvm_lock);
5646 list_for_each_entry(kvm, &vm_list, vm_list) {
5648 LIST_HEAD(invalid_list);
5651 * Never scan more than sc->nr_to_scan VM instances.
5652 * Will not hit this condition practically since we do not try
5653 * to shrink more than one VM and it is very unlikely to see
5654 * !n_used_mmu_pages so many times.
5659 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5660 * here. We may skip a VM instance errorneosly, but we do not
5661 * want to shrink a VM that only started to populate its MMU
5664 if (!kvm->arch.n_used_mmu_pages &&
5665 !kvm_has_zapped_obsolete_pages(kvm))
5668 idx = srcu_read_lock(&kvm->srcu);
5669 spin_lock(&kvm->mmu_lock);
5671 if (kvm_has_zapped_obsolete_pages(kvm)) {
5672 kvm_mmu_commit_zap_page(kvm,
5673 &kvm->arch.zapped_obsolete_pages);
5677 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5680 spin_unlock(&kvm->mmu_lock);
5681 srcu_read_unlock(&kvm->srcu, idx);
5684 * unfair on small ones
5685 * per-vm shrinkers cry out
5686 * sadness comes quickly
5688 list_move_tail(&kvm->vm_list, &vm_list);
5692 mutex_unlock(&kvm_lock);
5696 static unsigned long
5697 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5699 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5702 static struct shrinker mmu_shrinker = {
5703 .count_objects = mmu_shrink_count,
5704 .scan_objects = mmu_shrink_scan,
5705 .seeks = DEFAULT_SEEKS * 10,
5708 static void mmu_destroy_caches(void)
5710 kmem_cache_destroy(pte_list_desc_cache);
5711 kmem_cache_destroy(mmu_page_header_cache);
5714 static void kvm_set_mmio_spte_mask(void)
5719 * Set a reserved PA bit in MMIO SPTEs to generate page faults with
5720 * PFEC.RSVD=1 on MMIO accesses. 64-bit PTEs (PAE, x86-64, and EPT
5721 * paging) support a maximum of 52 bits of PA, i.e. if the CPU supports
5722 * 52-bit physical addresses then there are no reserved PA bits in the
5723 * PTEs and so the reserved PA approach must be disabled.
5725 if (shadow_phys_bits < 52)
5726 mask = BIT_ULL(51) | PT_PRESENT_MASK;
5730 kvm_mmu_set_mmio_spte_mask(mask, ACC_WRITE_MASK | ACC_USER_MASK);
5733 static bool get_nx_auto_mode(void)
5735 /* Return true when CPU has the bug, and mitigations are ON */
5736 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5739 static void __set_nx_huge_pages(bool val)
5741 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5744 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5746 bool old_val = nx_huge_pages;
5749 /* In "auto" mode deploy workaround only if CPU has the bug. */
5750 if (sysfs_streq(val, "off"))
5752 else if (sysfs_streq(val, "force"))
5754 else if (sysfs_streq(val, "auto"))
5755 new_val = get_nx_auto_mode();
5756 else if (strtobool(val, &new_val) < 0)
5759 __set_nx_huge_pages(new_val);
5761 if (new_val != old_val) {
5764 mutex_lock(&kvm_lock);
5766 list_for_each_entry(kvm, &vm_list, vm_list) {
5767 mutex_lock(&kvm->slots_lock);
5768 kvm_mmu_zap_all_fast(kvm);
5769 mutex_unlock(&kvm->slots_lock);
5771 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5773 mutex_unlock(&kvm_lock);
5779 int kvm_mmu_module_init(void)
5783 if (nx_huge_pages == -1)
5784 __set_nx_huge_pages(get_nx_auto_mode());
5787 * MMU roles use union aliasing which is, generally speaking, an
5788 * undefined behavior. However, we supposedly know how compilers behave
5789 * and the current status quo is unlikely to change. Guardians below are
5790 * supposed to let us know if the assumption becomes false.
5792 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
5793 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
5794 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
5796 kvm_mmu_reset_all_pte_masks();
5798 kvm_set_mmio_spte_mask();
5800 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
5801 sizeof(struct pte_list_desc),
5802 0, SLAB_ACCOUNT, NULL);
5803 if (!pte_list_desc_cache)
5806 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
5807 sizeof(struct kvm_mmu_page),
5808 0, SLAB_ACCOUNT, NULL);
5809 if (!mmu_page_header_cache)
5812 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
5815 ret = register_shrinker(&mmu_shrinker);
5822 mmu_destroy_caches();
5827 * Calculate mmu pages needed for kvm.
5829 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
5831 unsigned long nr_mmu_pages;
5832 unsigned long nr_pages = 0;
5833 struct kvm_memslots *slots;
5834 struct kvm_memory_slot *memslot;
5837 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5838 slots = __kvm_memslots(kvm, i);
5840 kvm_for_each_memslot(memslot, slots)
5841 nr_pages += memslot->npages;
5844 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
5845 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
5847 return nr_mmu_pages;
5850 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
5852 kvm_mmu_unload(vcpu);
5853 free_mmu_pages(&vcpu->arch.root_mmu);
5854 free_mmu_pages(&vcpu->arch.guest_mmu);
5855 mmu_free_memory_caches(vcpu);
5858 void kvm_mmu_module_exit(void)
5860 mmu_destroy_caches();
5861 percpu_counter_destroy(&kvm_total_used_mmu_pages);
5862 unregister_shrinker(&mmu_shrinker);
5863 mmu_audit_disable();
5866 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
5868 unsigned int old_val;
5871 old_val = nx_huge_pages_recovery_ratio;
5872 err = param_set_uint(val, kp);
5876 if (READ_ONCE(nx_huge_pages) &&
5877 !old_val && nx_huge_pages_recovery_ratio) {
5880 mutex_lock(&kvm_lock);
5882 list_for_each_entry(kvm, &vm_list, vm_list)
5883 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5885 mutex_unlock(&kvm_lock);
5891 static void kvm_recover_nx_lpages(struct kvm *kvm)
5894 struct kvm_mmu_page *sp;
5896 LIST_HEAD(invalid_list);
5899 rcu_idx = srcu_read_lock(&kvm->srcu);
5900 spin_lock(&kvm->mmu_lock);
5902 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
5903 to_zap = ratio ? DIV_ROUND_UP(kvm->stat.nx_lpage_splits, ratio) : 0;
5904 for ( ; to_zap; --to_zap) {
5905 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
5909 * We use a separate list instead of just using active_mmu_pages
5910 * because the number of lpage_disallowed pages is expected to
5911 * be relatively small compared to the total.
5913 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
5914 struct kvm_mmu_page,
5915 lpage_disallowed_link);
5916 WARN_ON_ONCE(!sp->lpage_disallowed);
5917 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
5918 WARN_ON_ONCE(sp->lpage_disallowed);
5920 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
5921 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5922 cond_resched_lock(&kvm->mmu_lock);
5925 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5927 spin_unlock(&kvm->mmu_lock);
5928 srcu_read_unlock(&kvm->srcu, rcu_idx);
5931 static long get_nx_lpage_recovery_timeout(u64 start_time)
5933 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
5934 ? start_time + 60 * HZ - get_jiffies_64()
5935 : MAX_SCHEDULE_TIMEOUT;
5938 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
5941 long remaining_time;
5944 start_time = get_jiffies_64();
5945 remaining_time = get_nx_lpage_recovery_timeout(start_time);
5947 set_current_state(TASK_INTERRUPTIBLE);
5948 while (!kthread_should_stop() && remaining_time > 0) {
5949 schedule_timeout(remaining_time);
5950 remaining_time = get_nx_lpage_recovery_timeout(start_time);
5951 set_current_state(TASK_INTERRUPTIBLE);
5954 set_current_state(TASK_RUNNING);
5956 if (kthread_should_stop())
5959 kvm_recover_nx_lpages(kvm);
5963 int kvm_mmu_post_init_vm(struct kvm *kvm)
5967 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
5968 "kvm-nx-lpage-recovery",
5969 &kvm->arch.nx_lpage_recovery_thread);
5971 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
5976 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
5978 if (kvm->arch.nx_lpage_recovery_thread)
5979 kthread_stop(kvm->arch.nx_lpage_recovery_thread);