arch/x86/kvm/lapic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 /*
   4  * Local APIC virtualization
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  * Copyright (C) 2007 Novell
   8  * Copyright (C) 2007 Intel
   9  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
  10  *
  11  * Authors:
  12  *   Dor Laor <dor.laor@qumranet.com>
  13  *   Gregory Haskins <ghaskins@novell.com>
  14  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  15  *
  16  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  17  */
  18
  19 #include <linux/kvm_host.h>
  20 #include <linux/kvm.h>
  21 #include <linux/mm.h>
  22 #include <linux/highmem.h>
  23 #include <linux/smp.h>
  24 #include <linux/hrtimer.h>
  25 #include <linux/io.h>
  26 #include <linux/export.h>
  27 #include <linux/math64.h>
  28 #include <linux/slab.h>
  29 #include <asm/processor.h>
  30 #include <asm/msr.h>
  31 #include <asm/page.h>
  32 #include <asm/current.h>
  33 #include <asm/apicdef.h>
  34 #include <asm/delay.h>
  35 #include <linux/atomic.h>
  36 #include <linux/jump_label.h>
  37 #include "kvm_cache_regs.h"
  38 #include "irq.h"
  39 #include "ioapic.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43 #include "hyperv.h"
  44
  45 #ifndef CONFIG_X86_64
  46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  47 #else
  48 #define mod_64(x, y) ((x) % (y))
  49 #endif
  50
  51 #define PRId64 "d"
  52 #define PRIx64 "llx"
  53 #define PRIu64 "u"
  54 #define PRIo64 "o"
  55
  56 /* 14 is the version for Xeon and Pentium 8.4.8*/
  57 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  58 #define LAPIC_MMIO_LENGTH               (1 << 12)
  59 /* followed define is not in apicdef.h */
  60 #define MAX_APIC_VECTOR                 256
  61 #define APIC_VECTORS_PER_REG            32
  62
  63 static bool lapic_timer_advance_dynamic __read_mostly;
  64 #define LAPIC_TIMER_ADVANCE_ADJUST_MIN  100     /* clock cycles */
  65 #define LAPIC_TIMER_ADVANCE_ADJUST_MAX  10000   /* clock cycles */
  66 #define LAPIC_TIMER_ADVANCE_NS_INIT     1000
  67 #define LAPIC_TIMER_ADVANCE_NS_MAX     5000
  68 /* step-by-step approximation to mitigate fluctuation */
  69 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
  70
  71 static inline int apic_test_vector(int vec, void *bitmap)
  72 {
  73         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  74 }
  75
  76 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  77 {
  78         struct kvm_lapic *apic = vcpu->arch.apic;
  79
  80         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  81                 apic_test_vector(vector, apic->regs + APIC_IRR);
  82 }
  83
  84 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  85 {
  86         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  87 }
  88
  89 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
  90 {
  91         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  92 }
  93
  94 struct static_key_deferred apic_hw_disabled __read_mostly;
  95 struct static_key_deferred apic_sw_disabled __read_mostly;
  96
  97 static inline int apic_enabled(struct kvm_lapic *apic)
  98 {
  99         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 100 }
 101
 102 #define LVT_MASK        \
 103         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 104
 105 #define LINT_MASK       \
 106         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 107          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 108
 109 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 110 {
 111         return apic->vcpu->vcpu_id;
 112 }
 113
 114 static bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
 115 {
 116         return pi_inject_timer && kvm_vcpu_apicv_active(vcpu);
 117 }
 118
 119 bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu)
 120 {
 121         return kvm_x86_ops.set_hv_timer
 122                && !(kvm_mwait_in_guest(vcpu->kvm) ||
 123                     kvm_can_post_timer_interrupt(vcpu));
 124 }
 125 EXPORT_SYMBOL_GPL(kvm_can_use_hv_timer);
 126
 127 static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
 128 {
 129         return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
 130 }
 131
 132 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 133                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 134         switch (map->mode) {
 135         case KVM_APIC_MODE_X2APIC: {
 136                 u32 offset = (dest_id >> 16) * 16;
 137                 u32 max_apic_id = map->max_apic_id;
 138
 139                 if (offset <= max_apic_id) {
 140                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 141
 142                         offset = array_index_nospec(offset, map->max_apic_id + 1);
 143                         *cluster = &map->phys_map[offset];
 144                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 145                 } else {
 146                         *mask = 0;
 147                 }
 148
 149                 return true;
 150                 }
 151         case KVM_APIC_MODE_XAPIC_FLAT:
 152                 *cluster = map->xapic_flat_map;
 153                 *mask = dest_id & 0xff;
 154                 return true;
 155         case KVM_APIC_MODE_XAPIC_CLUSTER:
 156                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 157                 *mask = dest_id & 0xf;
 158                 return true;
 159         default:
 160                 /* Not optimized. */
 161                 return false;
 162         }
 163 }
 164
 165 static void kvm_apic_map_free(struct rcu_head *rcu)
 166 {
 167         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 168
 169         kvfree(map);
 170 }
 171
 172 /*
 173  * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
 174  *
 175  * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
 176  * apic_map_lock_held.
 177  */
 178 enum {
 179         CLEAN,
 180         UPDATE_IN_PROGRESS,
 181         DIRTY
 182 };
 183
 184 void kvm_recalculate_apic_map(struct kvm *kvm)
 185 {
 186         struct kvm_apic_map *new, *old = NULL;
 187         struct kvm_vcpu *vcpu;
 188         int i;
 189         u32 max_id = 255; /* enough space for any xAPIC ID */
 190
 191         /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map.  */
 192         if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN)
 193                 return;
 194
 195         mutex_lock(&kvm->arch.apic_map_lock);
 196         /*
 197          * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map
 198          * (if clean) or the APIC registers (if dirty).
 199          */
 200         if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty,
 201                                    DIRTY, UPDATE_IN_PROGRESS) == CLEAN) {
 202                 /* Someone else has updated the map. */
 203                 mutex_unlock(&kvm->arch.apic_map_lock);
 204                 return;
 205         }
 206
 207         kvm_for_each_vcpu(i, vcpu, kvm)
 208                 if (kvm_apic_present(vcpu))
 209                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 210
 211         new = kvzalloc(sizeof(struct kvm_apic_map) +
 212                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
 213                            GFP_KERNEL_ACCOUNT);
 214
 215         if (!new)
 216                 goto out;
 217
 218         new->max_apic_id = max_id;
 219
 220         kvm_for_each_vcpu(i, vcpu, kvm) {
 221                 struct kvm_lapic *apic = vcpu->arch.apic;
 222                 struct kvm_lapic **cluster;
 223                 u16 mask;
 224                 u32 ldr;
 225                 u8 xapic_id;
 226                 u32 x2apic_id;
 227
 228                 if (!kvm_apic_present(vcpu))
 229                         continue;
 230
 231                 xapic_id = kvm_xapic_id(apic);
 232                 x2apic_id = kvm_x2apic_id(apic);
 233
 234                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 235                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 236                                 x2apic_id <= new->max_apic_id)
 237                         new->phys_map[x2apic_id] = apic;
 238                 /*
 239                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 240                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 241                  */
 242                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 243                         new->phys_map[xapic_id] = apic;
 244
 245                 if (!kvm_apic_sw_enabled(apic))
 246                         continue;
 247
 248                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 249
 250                 if (apic_x2apic_mode(apic)) {
 251                         new->mode |= KVM_APIC_MODE_X2APIC;
 252                 } else if (ldr) {
 253                         ldr = GET_APIC_LOGICAL_ID(ldr);
 254                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 255                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 256                         else
 257                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 258                 }
 259
 260                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 261                         continue;
 262
 263                 if (mask)
 264                         cluster[ffs(mask) - 1] = apic;
 265         }
 266 out:
 267         old = rcu_dereference_protected(kvm->arch.apic_map,
 268                         lockdep_is_held(&kvm->arch.apic_map_lock));
 269         rcu_assign_pointer(kvm->arch.apic_map, new);
 270         /*
 271          * Write kvm->arch.apic_map before clearing apic->apic_map_dirty.
 272          * If another update has come in, leave it DIRTY.
 273          */
 274         atomic_cmpxchg_release(&kvm->arch.apic_map_dirty,
 275                                UPDATE_IN_PROGRESS, CLEAN);
 276         mutex_unlock(&kvm->arch.apic_map_lock);
 277
 278         if (old)
 279                 call_rcu(&old->rcu, kvm_apic_map_free);
 280
 281         kvm_make_scan_ioapic_request(kvm);
 282 }
 283
 284 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 285 {
 286         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 287
 288         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 289
 290         if (enabled != apic->sw_enabled) {
 291                 apic->sw_enabled = enabled;
 292                 if (enabled)
 293                         static_key_slow_dec_deferred(&apic_sw_disabled);
 294                 else
 295                         static_key_slow_inc(&apic_sw_disabled.key);
 296
 297                 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
 298         }
 299 }
 300
 301 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 302 {
 303         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 304         atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
 305 }
 306
 307 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 308 {
 309         kvm_lapic_set_reg(apic, APIC_LDR, id);
 310         atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
 311 }
 312
 313 static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val)
 314 {
 315         kvm_lapic_set_reg(apic, APIC_DFR, val);
 316         atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
 317 }
 318
 319 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
 320 {
 321         return ((id >> 4) << 16) | (1 << (id & 0xf));
 322 }
 323
 324 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 325 {
 326         u32 ldr = kvm_apic_calc_x2apic_ldr(id);
 327
 328         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 329
 330         kvm_lapic_set_reg(apic, APIC_ID, id);
 331         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 332         atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
 333 }
 334
 335 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 336 {
 337         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 338 }
 339
 340 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 341 {
 342         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 343 }
 344
 345 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 346 {
 347         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 348 }
 349
 350 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 351 {
 352         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 353 }
 354
 355 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 356 {
 357         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 358 }
 359
 360 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 361 {
 362         struct kvm_lapic *apic = vcpu->arch.apic;
 363         u32 v = APIC_VERSION;
 364
 365         if (!lapic_in_kernel(vcpu))
 366                 return;
 367
 368         /*
 369          * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
 370          * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
 371          * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
 372          * version first and level-triggered interrupts never get EOIed in
 373          * IOAPIC.
 374          */
 375         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) &&
 376             !ioapic_in_kernel(vcpu->kvm))
 377                 v |= APIC_LVR_DIRECTED_EOI;
 378         kvm_lapic_set_reg(apic, APIC_LVR, v);
 379 }
 380
 381 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 382         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 383         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 384         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 385         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 386         LVT_MASK                /* LVTERR */
 387 };
 388
 389 static int find_highest_vector(void *bitmap)
 390 {
 391         int vec;
 392         u32 *reg;
 393
 394         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 395              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 396                 reg = bitmap + REG_POS(vec);
 397                 if (*reg)
 398                         return __fls(*reg) + vec;
 399         }
 400
 401         return -1;
 402 }
 403
 404 static u8 count_vectors(void *bitmap)
 405 {
 406         int vec;
 407         u32 *reg;
 408         u8 count = 0;
 409
 410         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 411                 reg = bitmap + REG_POS(vec);
 412                 count += hweight32(*reg);
 413         }
 414
 415         return count;
 416 }
 417
 418 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
 419 {
 420         u32 i, vec;
 421         u32 pir_val, irr_val, prev_irr_val;
 422         int max_updated_irr;
 423
 424         max_updated_irr = -1;
 425         *max_irr = -1;
 426
 427         for (i = vec = 0; i <= 7; i++, vec += 32) {
 428                 pir_val = READ_ONCE(pir[i]);
 429                 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
 430                 if (pir_val) {
 431                         prev_irr_val = irr_val;
 432                         irr_val |= xchg(&pir[i], 0);
 433                         *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
 434                         if (prev_irr_val != irr_val) {
 435                                 max_updated_irr =
 436                                         __fls(irr_val ^ prev_irr_val) + vec;
 437                         }
 438                 }
 439                 if (irr_val)
 440                         *max_irr = __fls(irr_val) + vec;
 441         }
 442
 443         return ((max_updated_irr != -1) &&
 444                 (max_updated_irr == *max_irr));
 445 }
 446 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 447
 448 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
 449 {
 450         struct kvm_lapic *apic = vcpu->arch.apic;
 451
 452         return __kvm_apic_update_irr(pir, apic->regs, max_irr);
 453 }
 454 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 455
 456 static inline int apic_search_irr(struct kvm_lapic *apic)
 457 {
 458         return find_highest_vector(apic->regs + APIC_IRR);
 459 }
 460
 461 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 462 {
 463         int result;
 464
 465         /*
 466          * Note that irr_pending is just a hint. It will be always
 467          * true with virtual interrupt delivery enabled.
 468          */
 469         if (!apic->irr_pending)
 470                 return -1;
 471
 472         result = apic_search_irr(apic);
 473         ASSERT(result == -1 || result >= 16);
 474
 475         return result;
 476 }
 477
 478 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 479 {
 480         struct kvm_vcpu *vcpu;
 481
 482         vcpu = apic->vcpu;
 483
 484         if (unlikely(vcpu->arch.apicv_active)) {
 485                 /* need to update RVI */
 486                 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
 487                 kvm_x86_ops.hwapic_irr_update(vcpu,
 488                                 apic_find_highest_irr(apic));
 489         } else {
 490                 apic->irr_pending = false;
 491                 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
 492                 if (apic_search_irr(apic) != -1)
 493                         apic->irr_pending = true;
 494         }
 495 }
 496
 497 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 498 {
 499         struct kvm_vcpu *vcpu;
 500
 501         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 502                 return;
 503
 504         vcpu = apic->vcpu;
 505
 506         /*
 507          * With APIC virtualization enabled, all caching is disabled
 508          * because the processor can modify ISR under the hood.  Instead
 509          * just set SVI.
 510          */
 511         if (unlikely(vcpu->arch.apicv_active))
 512                 kvm_x86_ops.hwapic_isr_update(vcpu, vec);
 513         else {
 514                 ++apic->isr_count;
 515                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 516                 /*
 517                  * ISR (in service register) bit is set when injecting an interrupt.
 518                  * The highest vector is injected. Thus the latest bit set matches
 519                  * the highest bit in ISR.
 520                  */
 521                 apic->highest_isr_cache = vec;
 522         }
 523 }
 524
 525 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 526 {
 527         int result;
 528
 529         /*
 530          * Note that isr_count is always 1, and highest_isr_cache
 531          * is always -1, with APIC virtualization enabled.
 532          */
 533         if (!apic->isr_count)
 534                 return -1;
 535         if (likely(apic->highest_isr_cache != -1))
 536                 return apic->highest_isr_cache;
 537
 538         result = find_highest_vector(apic->regs + APIC_ISR);
 539         ASSERT(result == -1 || result >= 16);
 540
 541         return result;
 542 }
 543
 544 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 545 {
 546         struct kvm_vcpu *vcpu;
 547         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 548                 return;
 549
 550         vcpu = apic->vcpu;
 551
 552         /*
 553          * We do get here for APIC virtualization enabled if the guest
 554          * uses the Hyper-V APIC enlightenment.  In this case we may need
 555          * to trigger a new interrupt delivery by writing the SVI field;
 556          * on the other hand isr_count and highest_isr_cache are unused
 557          * and must be left alone.
 558          */
 559         if (unlikely(vcpu->arch.apicv_active))
 560                 kvm_x86_ops.hwapic_isr_update(vcpu,
 561                                                apic_find_highest_isr(apic));
 562         else {
 563                 --apic->isr_count;
 564                 BUG_ON(apic->isr_count < 0);
 565                 apic->highest_isr_cache = -1;
 566         }
 567 }
 568
 569 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 570 {
 571         /* This may race with setting of irr in __apic_accept_irq() and
 572          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 573          * will cause vmexit immediately and the value will be recalculated
 574          * on the next vmentry.
 575          */
 576         return apic_find_highest_irr(vcpu->arch.apic);
 577 }
 578 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 579
 580 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 581                              int vector, int level, int trig_mode,
 582                              struct dest_map *dest_map);
 583
 584 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 585                      struct dest_map *dest_map)
 586 {
 587         struct kvm_lapic *apic = vcpu->arch.apic;
 588
 589         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 590                         irq->level, irq->trig_mode, dest_map);
 591 }
 592
 593 static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map,
 594                          struct kvm_lapic_irq *irq, u32 min)
 595 {
 596         int i, count = 0;
 597         struct kvm_vcpu *vcpu;
 598
 599         if (min > map->max_apic_id)
 600                 return 0;
 601
 602         for_each_set_bit(i, ipi_bitmap,
 603                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 604                 if (map->phys_map[min + i]) {
 605                         vcpu = map->phys_map[min + i]->vcpu;
 606                         count += kvm_apic_set_irq(vcpu, irq, NULL);
 607                 }
 608         }
 609
 610         return count;
 611 }
 612
 613 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
 614                     unsigned long ipi_bitmap_high, u32 min,
 615                     unsigned long icr, int op_64_bit)
 616 {
 617         struct kvm_apic_map *map;
 618         struct kvm_lapic_irq irq = {0};
 619         int cluster_size = op_64_bit ? 64 : 32;
 620         int count;
 621
 622         if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK))
 623                 return -KVM_EINVAL;
 624
 625         irq.vector = icr & APIC_VECTOR_MASK;
 626         irq.delivery_mode = icr & APIC_MODE_MASK;
 627         irq.level = (icr & APIC_INT_ASSERT) != 0;
 628         irq.trig_mode = icr & APIC_INT_LEVELTRIG;
 629
 630         rcu_read_lock();
 631         map = rcu_dereference(kvm->arch.apic_map);
 632
 633         count = -EOPNOTSUPP;
 634         if (likely(map)) {
 635                 count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min);
 636                 min += cluster_size;
 637                 count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min);
 638         }
 639
 640         rcu_read_unlock();
 641         return count;
 642 }
 643
 644 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 645 {
 646
 647         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 648                                       sizeof(val));
 649 }
 650
 651 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 652 {
 653
 654         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 655                                       sizeof(*val));
 656 }
 657
 658 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 659 {
 660         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 661 }
 662
 663 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 664 {
 665         u8 val;
 666         if (pv_eoi_get_user(vcpu, &val) < 0) {
 667                 printk(KERN_WARNING "Can't read EOI MSR value: 0x%llx\n",
 668                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 669                 return false;
 670         }
 671         return val & 0x1;
 672 }
 673
 674 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 675 {
 676         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 677                 printk(KERN_WARNING "Can't set EOI MSR value: 0x%llx\n",
 678                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 679                 return;
 680         }
 681         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 682 }
 683
 684 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 685 {
 686         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 687                 printk(KERN_WARNING "Can't clear EOI MSR value: 0x%llx\n",
 688                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 689                 return;
 690         }
 691         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 692 }
 693
 694 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 695 {
 696         int highest_irr;
 697         if (apic->vcpu->arch.apicv_active)
 698                 highest_irr = kvm_x86_ops.sync_pir_to_irr(apic->vcpu);
 699         else
 700                 highest_irr = apic_find_highest_irr(apic);
 701         if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
 702                 return -1;
 703         return highest_irr;
 704 }
 705
 706 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
 707 {
 708         u32 tpr, isrv, ppr, old_ppr;
 709         int isr;
 710
 711         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 712         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 713         isr = apic_find_highest_isr(apic);
 714         isrv = (isr != -1) ? isr : 0;
 715
 716         if ((tpr & 0xf0) >= (isrv & 0xf0))
 717                 ppr = tpr & 0xff;
 718         else
 719                 ppr = isrv & 0xf0;
 720
 721         *new_ppr = ppr;
 722         if (old_ppr != ppr)
 723                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 724
 725         return ppr < old_ppr;
 726 }
 727
 728 static void apic_update_ppr(struct kvm_lapic *apic)
 729 {
 730         u32 ppr;
 731
 732         if (__apic_update_ppr(apic, &ppr) &&
 733             apic_has_interrupt_for_ppr(apic, ppr) != -1)
 734                 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 735 }
 736
 737 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 738 {
 739         apic_update_ppr(vcpu->arch.apic);
 740 }
 741 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 742
 743 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 744 {
 745         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 746         apic_update_ppr(apic);
 747 }
 748
 749 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 750 {
 751         return mda == (apic_x2apic_mode(apic) ?
 752                         X2APIC_BROADCAST : APIC_BROADCAST);
 753 }
 754
 755 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 756 {
 757         if (kvm_apic_broadcast(apic, mda))
 758                 return true;
 759
 760         if (apic_x2apic_mode(apic))
 761                 return mda == kvm_x2apic_id(apic);
 762
 763         /*
 764          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 765          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 766          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 767          * The 0xff condition is needed because writeable xAPIC ID.
 768          */
 769         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 770                 return true;
 771
 772         return mda == kvm_xapic_id(apic);
 773 }
 774
 775 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 776 {
 777         u32 logical_id;
 778
 779         if (kvm_apic_broadcast(apic, mda))
 780                 return true;
 781
 782         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 783
 784         if (apic_x2apic_mode(apic))
 785                 return ((logical_id >> 16) == (mda >> 16))
 786                        && (logical_id & mda & 0xffff) != 0;
 787
 788         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 789
 790         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 791         case APIC_DFR_FLAT:
 792                 return (logical_id & mda) != 0;
 793         case APIC_DFR_CLUSTER:
 794                 return ((logical_id >> 4) == (mda >> 4))
 795                        && (logical_id & mda & 0xf) != 0;
 796         default:
 797                 return false;
 798         }
 799 }
 800
 801 /* The KVM local APIC implementation has two quirks:
 802  *
 803  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 804  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 805  *    KVM doesn't do that aliasing.
 806  *
 807  *  - in-kernel IOAPIC messages have to be delivered directly to
 808  *    x2APIC, because the kernel does not support interrupt remapping.
 809  *    In order to support broadcast without interrupt remapping, x2APIC
 810  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 811  *    to X2APIC_BROADCAST.
 812  *
 813  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 814  * important when userspace wants to use x2APIC-format MSIs, because
 815  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 816  */
 817 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 818                 struct kvm_lapic *source, struct kvm_lapic *target)
 819 {
 820         bool ipi = source != NULL;
 821
 822         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 823             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 824                 return X2APIC_BROADCAST;
 825
 826         return dest_id;
 827 }
 828
 829 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 830                            int shorthand, unsigned int dest, int dest_mode)
 831 {
 832         struct kvm_lapic *target = vcpu->arch.apic;
 833         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 834
 835         ASSERT(target);
 836         switch (shorthand) {
 837         case APIC_DEST_NOSHORT:
 838                 if (dest_mode == APIC_DEST_PHYSICAL)
 839                         return kvm_apic_match_physical_addr(target, mda);
 840                 else
 841                         return kvm_apic_match_logical_addr(target, mda);
 842         case APIC_DEST_SELF:
 843                 return target == source;
 844         case APIC_DEST_ALLINC:
 845                 return true;
 846         case APIC_DEST_ALLBUT:
 847                 return target != source;
 848         default:
 849                 return false;
 850         }
 851 }
 852 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 853
 854 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 855                        const unsigned long *bitmap, u32 bitmap_size)
 856 {
 857         u32 mod;
 858         int i, idx = -1;
 859
 860         mod = vector % dest_vcpus;
 861
 862         for (i = 0; i <= mod; i++) {
 863                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 864                 BUG_ON(idx == bitmap_size);
 865         }
 866
 867         return idx;
 868 }
 869
 870 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 871 {
 872         if (!kvm->arch.disabled_lapic_found) {
 873                 kvm->arch.disabled_lapic_found = true;
 874                 printk(KERN_INFO
 875                        "Disabled LAPIC found during irq injection\n");
 876         }
 877 }
 878
 879 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 880                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 881 {
 882         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 883                 if ((irq->dest_id == APIC_BROADCAST &&
 884                                 map->mode != KVM_APIC_MODE_X2APIC))
 885                         return true;
 886                 if (irq->dest_id == X2APIC_BROADCAST)
 887                         return true;
 888         } else {
 889                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 890                 if (irq->dest_id == (x2apic_ipi ?
 891                                      X2APIC_BROADCAST : APIC_BROADCAST))
 892                         return true;
 893         }
 894
 895         return false;
 896 }
 897
 898 /* Return true if the interrupt can be handled by using *bitmap as index mask
 899  * for valid destinations in *dst array.
 900  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 901  * Note: we may have zero kvm_lapic destinations when we return true, which
 902  * means that the interrupt should be dropped.  In this case, *bitmap would be
 903  * zero and *dst undefined.
 904  */
 905 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 906                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 907                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 908                 unsigned long *bitmap)
 909 {
 910         int i, lowest;
 911
 912         if (irq->shorthand == APIC_DEST_SELF && src) {
 913                 *dst = src;
 914                 *bitmap = 1;
 915                 return true;
 916         } else if (irq->shorthand)
 917                 return false;
 918
 919         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 920                 return false;
 921
 922         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 923                 if (irq->dest_id > map->max_apic_id) {
 924                         *bitmap = 0;
 925                 } else {
 926                         u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
 927                         *dst = &map->phys_map[dest_id];
 928                         *bitmap = 1;
 929                 }
 930                 return true;
 931         }
 932
 933         *bitmap = 0;
 934         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 935                                 (u16 *)bitmap))
 936                 return false;
 937
 938         if (!kvm_lowest_prio_delivery(irq))
 939                 return true;
 940
 941         if (!kvm_vector_hashing_enabled()) {
 942                 lowest = -1;
 943                 for_each_set_bit(i, bitmap, 16) {
 944                         if (!(*dst)[i])
 945                                 continue;
 946                         if (lowest < 0)
 947                                 lowest = i;
 948                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 949                                                 (*dst)[lowest]->vcpu) < 0)
 950                                 lowest = i;
 951                 }
 952         } else {
 953                 if (!*bitmap)
 954                         return true;
 955
 956                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 957                                 bitmap, 16);
 958
 959                 if (!(*dst)[lowest]) {
 960                         kvm_apic_disabled_lapic_found(kvm);
 961                         *bitmap = 0;
 962                         return true;
 963                 }
 964         }
 965
 966         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 967
 968         return true;
 969 }
 970
 971 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 972                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 973 {
 974         struct kvm_apic_map *map;
 975         unsigned long bitmap;
 976         struct kvm_lapic **dst = NULL;
 977         int i;
 978         bool ret;
 979
 980         *r = -1;
 981
 982         if (irq->shorthand == APIC_DEST_SELF) {
 983                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 984                 return true;
 985         }
 986
 987         rcu_read_lock();
 988         map = rcu_dereference(kvm->arch.apic_map);
 989
 990         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 991         if (ret) {
 992                 *r = 0;
 993                 for_each_set_bit(i, &bitmap, 16) {
 994                         if (!dst[i])
 995                                 continue;
 996                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 997                 }
 998         }
 999
1000         rcu_read_unlock();
1001         return ret;
1002 }
1003
1004 /*
1005  * This routine tries to handle interrupts in posted mode, here is how
1006  * it deals with different cases:
1007  * - For single-destination interrupts, handle it in posted mode
1008  * - Else if vector hashing is enabled and it is a lowest-priority
1009  *   interrupt, handle it in posted mode and use the following mechanism
1010  *   to find the destination vCPU.
1011  *      1. For lowest-priority interrupts, store all the possible
1012  *         destination vCPUs in an array.
1013  *      2. Use "guest vector % max number of destination vCPUs" to find
1014  *         the right destination vCPU in the array for the lowest-priority
1015  *         interrupt.
1016  * - Otherwise, use remapped mode to inject the interrupt.
1017  */
1018 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
1019                         struct kvm_vcpu **dest_vcpu)
1020 {
1021         struct kvm_apic_map *map;
1022         unsigned long bitmap;
1023         struct kvm_lapic **dst = NULL;
1024         bool ret = false;
1025
1026         if (irq->shorthand)
1027                 return false;
1028
1029         rcu_read_lock();
1030         map = rcu_dereference(kvm->arch.apic_map);
1031
1032         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1033                         hweight16(bitmap) == 1) {
1034                 unsigned long i = find_first_bit(&bitmap, 16);
1035
1036                 if (dst[i]) {
1037                         *dest_vcpu = dst[i]->vcpu;
1038                         ret = true;
1039                 }
1040         }
1041
1042         rcu_read_unlock();
1043         return ret;
1044 }
1045
1046 /*
1047  * Add a pending IRQ into lapic.
1048  * Return 1 if successfully added and 0 if discarded.
1049  */
1050 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1051                              int vector, int level, int trig_mode,
1052                              struct dest_map *dest_map)
1053 {
1054         int result = 0;
1055         struct kvm_vcpu *vcpu = apic->vcpu;
1056
1057         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1058                                   trig_mode, vector);
1059         switch (delivery_mode) {
1060         case APIC_DM_LOWEST:
1061                 vcpu->arch.apic_arb_prio++;
1062                 fallthrough;
1063         case APIC_DM_FIXED:
1064                 if (unlikely(trig_mode && !level))
1065                         break;
1066
1067                 /* FIXME add logic for vcpu on reset */
1068                 if (unlikely(!apic_enabled(apic)))
1069                         break;
1070
1071                 result = 1;
1072
1073                 if (dest_map) {
1074                         __set_bit(vcpu->vcpu_id, dest_map->map);
1075                         dest_map->vectors[vcpu->vcpu_id] = vector;
1076                 }
1077
1078                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1079                         if (trig_mode)
1080                                 kvm_lapic_set_vector(vector,
1081                                                      apic->regs + APIC_TMR);
1082                         else
1083                                 kvm_lapic_clear_vector(vector,
1084                                                        apic->regs + APIC_TMR);
1085                 }
1086
1087                 if (kvm_x86_ops.deliver_posted_interrupt(vcpu, vector)) {
1088                         kvm_lapic_set_irr(vector, apic);
1089                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1090                         kvm_vcpu_kick(vcpu);
1091                 }
1092                 break;
1093
1094         case APIC_DM_REMRD:
1095                 result = 1;
1096                 vcpu->arch.pv.pv_unhalted = 1;
1097                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1098                 kvm_vcpu_kick(vcpu);
1099                 break;
1100
1101         case APIC_DM_SMI:
1102                 result = 1;
1103                 kvm_make_request(KVM_REQ_SMI, vcpu);
1104                 kvm_vcpu_kick(vcpu);
1105                 break;
1106
1107         case APIC_DM_NMI:
1108                 result = 1;
1109                 kvm_inject_nmi(vcpu);
1110                 kvm_vcpu_kick(vcpu);
1111                 break;
1112
1113         case APIC_DM_INIT:
1114                 if (!trig_mode || level) {
1115                         result = 1;
1116                         /* assumes that there are only KVM_APIC_INIT/SIPI */
1117                         apic->pending_events = (1UL << KVM_APIC_INIT);
1118                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1119                         kvm_vcpu_kick(vcpu);
1120                 }
1121                 break;
1122
1123         case APIC_DM_STARTUP:
1124                 result = 1;
1125                 apic->sipi_vector = vector;
1126                 /* make sure sipi_vector is visible for the receiver */
1127                 smp_wmb();
1128                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1129                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1130                 kvm_vcpu_kick(vcpu);
1131                 break;
1132
1133         case APIC_DM_EXTINT:
1134                 /*
1135                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1136                  * before NMI watchdog was enabled. Already handled by
1137                  * kvm_apic_accept_pic_intr().
1138                  */
1139                 break;
1140
1141         default:
1142                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1143                        delivery_mode);
1144                 break;
1145         }
1146         return result;
1147 }
1148
1149 /*
1150  * This routine identifies the destination vcpus mask meant to receive the
1151  * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find
1152  * out the destination vcpus array and set the bitmap or it traverses to
1153  * each available vcpu to identify the same.
1154  */
1155 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
1156                               unsigned long *vcpu_bitmap)
1157 {
1158         struct kvm_lapic **dest_vcpu = NULL;
1159         struct kvm_lapic *src = NULL;
1160         struct kvm_apic_map *map;
1161         struct kvm_vcpu *vcpu;
1162         unsigned long bitmap;
1163         int i, vcpu_idx;
1164         bool ret;
1165
1166         rcu_read_lock();
1167         map = rcu_dereference(kvm->arch.apic_map);
1168
1169         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu,
1170                                           &bitmap);
1171         if (ret) {
1172                 for_each_set_bit(i, &bitmap, 16) {
1173                         if (!dest_vcpu[i])
1174                                 continue;
1175                         vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx;
1176                         __set_bit(vcpu_idx, vcpu_bitmap);
1177                 }
1178         } else {
1179                 kvm_for_each_vcpu(i, vcpu, kvm) {
1180                         if (!kvm_apic_present(vcpu))
1181                                 continue;
1182                         if (!kvm_apic_match_dest(vcpu, NULL,
1183                                                  irq->shorthand,
1184                                                  irq->dest_id,
1185                                                  irq->dest_mode))
1186                                 continue;
1187                         __set_bit(i, vcpu_bitmap);
1188                 }
1189         }
1190         rcu_read_unlock();
1191 }
1192
1193 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1194 {
1195         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1196 }
1197
1198 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1199 {
1200         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1201 }
1202
1203 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1204 {
1205         int trigger_mode;
1206
1207         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1208         if (!kvm_ioapic_handles_vector(apic, vector))
1209                 return;
1210
1211         /* Request a KVM exit to inform the userspace IOAPIC. */
1212         if (irqchip_split(apic->vcpu->kvm)) {
1213                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1214                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1215                 return;
1216         }
1217
1218         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1219                 trigger_mode = IOAPIC_LEVEL_TRIG;
1220         else
1221                 trigger_mode = IOAPIC_EDGE_TRIG;
1222
1223         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1224 }
1225
1226 static int apic_set_eoi(struct kvm_lapic *apic)
1227 {
1228         int vector = apic_find_highest_isr(apic);
1229
1230         trace_kvm_eoi(apic, vector);
1231
1232         /*
1233          * Not every write EOI will has corresponding ISR,
1234          * one example is when Kernel check timer on setup_IO_APIC
1235          */
1236         if (vector == -1)
1237                 return vector;
1238
1239         apic_clear_isr(vector, apic);
1240         apic_update_ppr(apic);
1241
1242         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1243                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1244
1245         kvm_ioapic_send_eoi(apic, vector);
1246         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1247         return vector;
1248 }
1249
1250 /*
1251  * this interface assumes a trap-like exit, which has already finished
1252  * desired side effect including vISR and vPPR update.
1253  */
1254 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1255 {
1256         struct kvm_lapic *apic = vcpu->arch.apic;
1257
1258         trace_kvm_eoi(apic, vector);
1259
1260         kvm_ioapic_send_eoi(apic, vector);
1261         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1262 }
1263 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1264
1265 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
1266 {
1267         struct kvm_lapic_irq irq;
1268
1269         irq.vector = icr_low & APIC_VECTOR_MASK;
1270         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1271         irq.dest_mode = icr_low & APIC_DEST_MASK;
1272         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1273         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1274         irq.shorthand = icr_low & APIC_SHORT_MASK;
1275         irq.msi_redir_hint = false;
1276         if (apic_x2apic_mode(apic))
1277                 irq.dest_id = icr_high;
1278         else
1279                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1280
1281         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1282
1283         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1284 }
1285
1286 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1287 {
1288         ktime_t remaining, now;
1289         s64 ns;
1290         u32 tmcct;
1291
1292         ASSERT(apic != NULL);
1293
1294         /* if initial count is 0, current count should also be 0 */
1295         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1296                 apic->lapic_timer.period == 0)
1297                 return 0;
1298
1299         now = ktime_get();
1300         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1301         if (ktime_to_ns(remaining) < 0)
1302                 remaining = 0;
1303
1304         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1305         tmcct = div64_u64(ns,
1306                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1307
1308         return tmcct;
1309 }
1310
1311 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1312 {
1313         struct kvm_vcpu *vcpu = apic->vcpu;
1314         struct kvm_run *run = vcpu->run;
1315
1316         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1317         run->tpr_access.rip = kvm_rip_read(vcpu);
1318         run->tpr_access.is_write = write;
1319 }
1320
1321 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1322 {
1323         if (apic->vcpu->arch.tpr_access_reporting)
1324                 __report_tpr_access(apic, write);
1325 }
1326
1327 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1328 {
1329         u32 val = 0;
1330
1331         if (offset >= LAPIC_MMIO_LENGTH)
1332                 return 0;
1333
1334         switch (offset) {
1335         case APIC_ARBPRI:
1336                 break;
1337
1338         case APIC_TMCCT:        /* Timer CCR */
1339                 if (apic_lvtt_tscdeadline(apic))
1340                         return 0;
1341
1342                 val = apic_get_tmcct(apic);
1343                 break;
1344         case APIC_PROCPRI:
1345                 apic_update_ppr(apic);
1346                 val = kvm_lapic_get_reg(apic, offset);
1347                 break;
1348         case APIC_TASKPRI:
1349                 report_tpr_access(apic, false);
1350                 fallthrough;
1351         default:
1352                 val = kvm_lapic_get_reg(apic, offset);
1353                 break;
1354         }
1355
1356         return val;
1357 }
1358
1359 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1360 {
1361         return container_of(dev, struct kvm_lapic, dev);
1362 }
1363
1364 #define APIC_REG_MASK(reg)      (1ull << ((reg) >> 4))
1365 #define APIC_REGS_MASK(first, count) \
1366         (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1367
1368 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1369                 void *data)
1370 {
1371         unsigned char alignment = offset & 0xf;
1372         u32 result;
1373         /* this bitmask has a bit cleared for each reserved register */
1374         u64 valid_reg_mask =
1375                 APIC_REG_MASK(APIC_ID) |
1376                 APIC_REG_MASK(APIC_LVR) |
1377                 APIC_REG_MASK(APIC_TASKPRI) |
1378                 APIC_REG_MASK(APIC_PROCPRI) |
1379                 APIC_REG_MASK(APIC_LDR) |
1380                 APIC_REG_MASK(APIC_DFR) |
1381                 APIC_REG_MASK(APIC_SPIV) |
1382                 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1383                 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1384                 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1385                 APIC_REG_MASK(APIC_ESR) |
1386                 APIC_REG_MASK(APIC_ICR) |
1387                 APIC_REG_MASK(APIC_ICR2) |
1388                 APIC_REG_MASK(APIC_LVTT) |
1389                 APIC_REG_MASK(APIC_LVTTHMR) |
1390                 APIC_REG_MASK(APIC_LVTPC) |
1391                 APIC_REG_MASK(APIC_LVT0) |
1392                 APIC_REG_MASK(APIC_LVT1) |
1393                 APIC_REG_MASK(APIC_LVTERR) |
1394                 APIC_REG_MASK(APIC_TMICT) |
1395                 APIC_REG_MASK(APIC_TMCCT) |
1396                 APIC_REG_MASK(APIC_TDCR);
1397
1398         /* ARBPRI is not valid on x2APIC */
1399         if (!apic_x2apic_mode(apic))
1400                 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI);
1401
1402         if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
1403                 return 1;
1404
1405         result = __apic_read(apic, offset & ~0xf);
1406
1407         trace_kvm_apic_read(offset, result);
1408
1409         switch (len) {
1410         case 1:
1411         case 2:
1412         case 4:
1413                 memcpy(data, (char *)&result + alignment, len);
1414                 break;
1415         default:
1416                 printk(KERN_ERR "Local APIC read with len = %x, "
1417                        "should be 1,2, or 4 instead\n", len);
1418                 break;
1419         }
1420         return 0;
1421 }
1422 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1423
1424 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1425 {
1426         return addr >= apic->base_address &&
1427                 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1428 }
1429
1430 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1431                            gpa_t address, int len, void *data)
1432 {
1433         struct kvm_lapic *apic = to_lapic(this);
1434         u32 offset = address - apic->base_address;
1435
1436         if (!apic_mmio_in_range(apic, address))
1437                 return -EOPNOTSUPP;
1438
1439         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1440                 if (!kvm_check_has_quirk(vcpu->kvm,
1441                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1442                         return -EOPNOTSUPP;
1443
1444                 memset(data, 0xff, len);
1445                 return 0;
1446         }
1447
1448         kvm_lapic_reg_read(apic, offset, len, data);
1449
1450         return 0;
1451 }
1452
1453 static void update_divide_count(struct kvm_lapic *apic)
1454 {
1455         u32 tmp1, tmp2, tdcr;
1456
1457         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1458         tmp1 = tdcr & 0xf;
1459         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1460         apic->divide_count = 0x1 << (tmp2 & 0x7);
1461 }
1462
1463 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1464 {
1465         /*
1466          * Do not allow the guest to program periodic timers with small
1467          * interval, since the hrtimers are not throttled by the host
1468          * scheduler.
1469          */
1470         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1471                 s64 min_period = min_timer_period_us * 1000LL;
1472
1473                 if (apic->lapic_timer.period < min_period) {
1474                         pr_info_ratelimited(
1475                             "kvm: vcpu %i: requested %lld ns "
1476                             "lapic timer period limited to %lld ns\n",
1477                             apic->vcpu->vcpu_id,
1478                             apic->lapic_timer.period, min_period);
1479                         apic->lapic_timer.period = min_period;
1480                 }
1481         }
1482 }
1483
1484 static void cancel_hv_timer(struct kvm_lapic *apic);
1485
1486 static void apic_update_lvtt(struct kvm_lapic *apic)
1487 {
1488         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1489                         apic->lapic_timer.timer_mode_mask;
1490
1491         if (apic->lapic_timer.timer_mode != timer_mode) {
1492                 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1493                                 APIC_LVT_TIMER_TSCDEADLINE)) {
1494                         hrtimer_cancel(&apic->lapic_timer.timer);
1495                         preempt_disable();
1496                         if (apic->lapic_timer.hv_timer_in_use)
1497                                 cancel_hv_timer(apic);
1498                         preempt_enable();
1499                         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1500                         apic->lapic_timer.period = 0;
1501                         apic->lapic_timer.tscdeadline = 0;
1502                 }
1503                 apic->lapic_timer.timer_mode = timer_mode;
1504                 limit_periodic_timer_frequency(apic);
1505         }
1506 }
1507
1508 /*
1509  * On APICv, this test will cause a busy wait
1510  * during a higher-priority task.
1511  */
1512
1513 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1514 {
1515         struct kvm_lapic *apic = vcpu->arch.apic;
1516         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1517
1518         if (kvm_apic_hw_enabled(apic)) {
1519                 int vec = reg & APIC_VECTOR_MASK;
1520                 void *bitmap = apic->regs + APIC_ISR;
1521
1522                 if (vcpu->arch.apicv_active)
1523                         bitmap = apic->regs + APIC_IRR;
1524
1525                 if (apic_test_vector(vec, bitmap))
1526                         return true;
1527         }
1528         return false;
1529 }
1530
1531 static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1532 {
1533         u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1534
1535         /*
1536          * If the guest TSC is running at a different ratio than the host, then
1537          * convert the delay to nanoseconds to achieve an accurate delay.  Note
1538          * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1539          * always for VMX enabled hardware.
1540          */
1541         if (vcpu->arch.tsc_scaling_ratio == kvm_default_tsc_scaling_ratio) {
1542                 __delay(min(guest_cycles,
1543                         nsec_to_cycles(vcpu, timer_advance_ns)));
1544         } else {
1545                 u64 delay_ns = guest_cycles * 1000000ULL;
1546                 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1547                 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1548         }
1549 }
1550
1551 static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
1552                                               s64 advance_expire_delta)
1553 {
1554         struct kvm_lapic *apic = vcpu->arch.apic;
1555         u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1556         u64 ns;
1557
1558         /* Do not adjust for tiny fluctuations or large random spikes. */
1559         if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX ||
1560             abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN)
1561                 return;
1562
1563         /* too early */
1564         if (advance_expire_delta < 0) {
1565                 ns = -advance_expire_delta * 1000000ULL;
1566                 do_div(ns, vcpu->arch.virtual_tsc_khz);
1567                 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1568         } else {
1569         /* too late */
1570                 ns = advance_expire_delta * 1000000ULL;
1571                 do_div(ns, vcpu->arch.virtual_tsc_khz);
1572                 timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1573         }
1574
1575         if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX))
1576                 timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
1577         apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1578 }
1579
1580 static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1581 {
1582         struct kvm_lapic *apic = vcpu->arch.apic;
1583         u64 guest_tsc, tsc_deadline;
1584
1585         if (apic->lapic_timer.expired_tscdeadline == 0)
1586                 return;
1587
1588         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1589         apic->lapic_timer.expired_tscdeadline = 0;
1590         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1591         apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline;
1592
1593         if (guest_tsc < tsc_deadline)
1594                 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1595
1596         if (lapic_timer_advance_dynamic)
1597                 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta);
1598 }
1599
1600 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1601 {
1602         if (lapic_timer_int_injected(vcpu))
1603                 __kvm_wait_lapic_expire(vcpu);
1604 }
1605 EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
1606
1607 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1608 {
1609         struct kvm_timer *ktimer = &apic->lapic_timer;
1610
1611         kvm_apic_local_deliver(apic, APIC_LVTT);
1612         if (apic_lvtt_tscdeadline(apic)) {
1613                 ktimer->tscdeadline = 0;
1614         } else if (apic_lvtt_oneshot(apic)) {
1615                 ktimer->tscdeadline = 0;
1616                 ktimer->target_expiration = 0;
1617         }
1618 }
1619
1620 static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn)
1621 {
1622         struct kvm_vcpu *vcpu = apic->vcpu;
1623         struct kvm_timer *ktimer = &apic->lapic_timer;
1624
1625         if (atomic_read(&apic->lapic_timer.pending))
1626                 return;
1627
1628         if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1629                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1630
1631         if (!from_timer_fn && vcpu->arch.apicv_active) {
1632                 WARN_ON(kvm_get_running_vcpu() != vcpu);
1633                 kvm_apic_inject_pending_timer_irqs(apic);
1634                 return;
1635         }
1636
1637         if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1638                 if (apic->lapic_timer.timer_advance_ns)
1639                         __kvm_wait_lapic_expire(vcpu);
1640                 kvm_apic_inject_pending_timer_irqs(apic);
1641                 return;
1642         }
1643
1644         atomic_inc(&apic->lapic_timer.pending);
1645         kvm_set_pending_timer(vcpu);
1646 }
1647
1648 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1649 {
1650         struct kvm_timer *ktimer = &apic->lapic_timer;
1651         u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1652         u64 ns = 0;
1653         ktime_t expire;
1654         struct kvm_vcpu *vcpu = apic->vcpu;
1655         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1656         unsigned long flags;
1657         ktime_t now;
1658
1659         if (unlikely(!tscdeadline || !this_tsc_khz))
1660                 return;
1661
1662         local_irq_save(flags);
1663
1664         now = ktime_get();
1665         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1666
1667         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1668         do_div(ns, this_tsc_khz);
1669
1670         if (likely(tscdeadline > guest_tsc) &&
1671             likely(ns > apic->lapic_timer.timer_advance_ns)) {
1672                 expire = ktime_add_ns(now, ns);
1673                 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1674                 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD);
1675         } else
1676                 apic_timer_expired(apic, false);
1677
1678         local_irq_restore(flags);
1679 }
1680
1681 static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)
1682 {
1683         return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count;
1684 }
1685
1686 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1687 {
1688         ktime_t now, remaining;
1689         u64 ns_remaining_old, ns_remaining_new;
1690
1691         apic->lapic_timer.period =
1692                         tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1693         limit_periodic_timer_frequency(apic);
1694
1695         now = ktime_get();
1696         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1697         if (ktime_to_ns(remaining) < 0)
1698                 remaining = 0;
1699
1700         ns_remaining_old = ktime_to_ns(remaining);
1701         ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1702                                            apic->divide_count, old_divisor);
1703
1704         apic->lapic_timer.tscdeadline +=
1705                 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1706                 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1707         apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1708 }
1709
1710 static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg)
1711 {
1712         ktime_t now;
1713         u64 tscl = rdtsc();
1714         s64 deadline;
1715
1716         now = ktime_get();
1717         apic->lapic_timer.period =
1718                         tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1719
1720         if (!apic->lapic_timer.period) {
1721                 apic->lapic_timer.tscdeadline = 0;
1722                 return false;
1723         }
1724
1725         limit_periodic_timer_frequency(apic);
1726         deadline = apic->lapic_timer.period;
1727
1728         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1729                 if (unlikely(count_reg != APIC_TMICT)) {
1730                         deadline = tmict_to_ns(apic,
1731                                      kvm_lapic_get_reg(apic, count_reg));
1732                         if (unlikely(deadline <= 0))
1733                                 deadline = apic->lapic_timer.period;
1734                         else if (unlikely(deadline > apic->lapic_timer.period)) {
1735                                 pr_info_ratelimited(
1736                                     "kvm: vcpu %i: requested lapic timer restore with "
1737                                     "starting count register %#x=%u (%lld ns) > initial count (%lld ns). "
1738                                     "Using initial count to start timer.\n",
1739                                     apic->vcpu->vcpu_id,
1740                                     count_reg,
1741                                     kvm_lapic_get_reg(apic, count_reg),
1742                                     deadline, apic->lapic_timer.period);
1743                                 kvm_lapic_set_reg(apic, count_reg, 0);
1744                                 deadline = apic->lapic_timer.period;
1745                         }
1746                 }
1747         }
1748
1749         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1750                 nsec_to_cycles(apic->vcpu, deadline);
1751         apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline);
1752
1753         return true;
1754 }
1755
1756 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1757 {
1758         ktime_t now = ktime_get();
1759         u64 tscl = rdtsc();
1760         ktime_t delta;
1761
1762         /*
1763          * Synchronize both deadlines to the same time source or
1764          * differences in the periods (caused by differences in the
1765          * underlying clocks or numerical approximation errors) will
1766          * cause the two to drift apart over time as the errors
1767          * accumulate.
1768          */
1769         apic->lapic_timer.target_expiration =
1770                 ktime_add_ns(apic->lapic_timer.target_expiration,
1771                                 apic->lapic_timer.period);
1772         delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1773         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1774                 nsec_to_cycles(apic->vcpu, delta);
1775 }
1776
1777 static void start_sw_period(struct kvm_lapic *apic)
1778 {
1779         if (!apic->lapic_timer.period)
1780                 return;
1781
1782         if (ktime_after(ktime_get(),
1783                         apic->lapic_timer.target_expiration)) {
1784                 apic_timer_expired(apic, false);
1785
1786                 if (apic_lvtt_oneshot(apic))
1787                         return;
1788
1789                 advance_periodic_target_expiration(apic);
1790         }
1791
1792         hrtimer_start(&apic->lapic_timer.timer,
1793                 apic->lapic_timer.target_expiration,
1794                 HRTIMER_MODE_ABS_HARD);
1795 }
1796
1797 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1798 {
1799         if (!lapic_in_kernel(vcpu))
1800                 return false;
1801
1802         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1803 }
1804 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1805
1806 static void cancel_hv_timer(struct kvm_lapic *apic)
1807 {
1808         WARN_ON(preemptible());
1809         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1810         kvm_x86_ops.cancel_hv_timer(apic->vcpu);
1811         apic->lapic_timer.hv_timer_in_use = false;
1812 }
1813
1814 static bool start_hv_timer(struct kvm_lapic *apic)
1815 {
1816         struct kvm_timer *ktimer = &apic->lapic_timer;
1817         struct kvm_vcpu *vcpu = apic->vcpu;
1818         bool expired;
1819
1820         WARN_ON(preemptible());
1821         if (!kvm_can_use_hv_timer(vcpu))
1822                 return false;
1823
1824         if (!ktimer->tscdeadline)
1825                 return false;
1826
1827         if (kvm_x86_ops.set_hv_timer(vcpu, ktimer->tscdeadline, &expired))
1828                 return false;
1829
1830         ktimer->hv_timer_in_use = true;
1831         hrtimer_cancel(&ktimer->timer);
1832
1833         /*
1834          * To simplify handling the periodic timer, leave the hv timer running
1835          * even if the deadline timer has expired, i.e. rely on the resulting
1836          * VM-Exit to recompute the periodic timer's target expiration.
1837          */
1838         if (!apic_lvtt_period(apic)) {
1839                 /*
1840                  * Cancel the hv timer if the sw timer fired while the hv timer
1841                  * was being programmed, or if the hv timer itself expired.
1842                  */
1843                 if (atomic_read(&ktimer->pending)) {
1844                         cancel_hv_timer(apic);
1845                 } else if (expired) {
1846                         apic_timer_expired(apic, false);
1847                         cancel_hv_timer(apic);
1848                 }
1849         }
1850
1851         trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
1852
1853         return true;
1854 }
1855
1856 static void start_sw_timer(struct kvm_lapic *apic)
1857 {
1858         struct kvm_timer *ktimer = &apic->lapic_timer;
1859
1860         WARN_ON(preemptible());
1861         if (apic->lapic_timer.hv_timer_in_use)
1862                 cancel_hv_timer(apic);
1863         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1864                 return;
1865
1866         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1867                 start_sw_period(apic);
1868         else if (apic_lvtt_tscdeadline(apic))
1869                 start_sw_tscdeadline(apic);
1870         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1871 }
1872
1873 static void restart_apic_timer(struct kvm_lapic *apic)
1874 {
1875         preempt_disable();
1876
1877         if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
1878                 goto out;
1879
1880         if (!start_hv_timer(apic))
1881                 start_sw_timer(apic);
1882 out:
1883         preempt_enable();
1884 }
1885
1886 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1887 {
1888         struct kvm_lapic *apic = vcpu->arch.apic;
1889
1890         preempt_disable();
1891         /* If the preempt notifier has already run, it also called apic_timer_expired */
1892         if (!apic->lapic_timer.hv_timer_in_use)
1893                 goto out;
1894         WARN_ON(rcuwait_active(&vcpu->wait));
1895         cancel_hv_timer(apic);
1896         apic_timer_expired(apic, false);
1897
1898         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1899                 advance_periodic_target_expiration(apic);
1900                 restart_apic_timer(apic);
1901         }
1902 out:
1903         preempt_enable();
1904 }
1905 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1906
1907 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1908 {
1909         restart_apic_timer(vcpu->arch.apic);
1910 }
1911 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1912
1913 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1914 {
1915         struct kvm_lapic *apic = vcpu->arch.apic;
1916
1917         preempt_disable();
1918         /* Possibly the TSC deadline timer is not enabled yet */
1919         if (apic->lapic_timer.hv_timer_in_use)
1920                 start_sw_timer(apic);
1921         preempt_enable();
1922 }
1923 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1924
1925 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1926 {
1927         struct kvm_lapic *apic = vcpu->arch.apic;
1928
1929         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1930         restart_apic_timer(apic);
1931 }
1932
1933 static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg)
1934 {
1935         atomic_set(&apic->lapic_timer.pending, 0);
1936
1937         if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1938             && !set_target_expiration(apic, count_reg))
1939                 return;
1940
1941         restart_apic_timer(apic);
1942 }
1943
1944 static void start_apic_timer(struct kvm_lapic *apic)
1945 {
1946         __start_apic_timer(apic, APIC_TMICT);
1947 }
1948
1949 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1950 {
1951         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1952
1953         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1954                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1955                 if (lvt0_in_nmi_mode) {
1956                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1957                 } else
1958                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1959         }
1960 }
1961
1962 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1963 {
1964         int ret = 0;
1965
1966         trace_kvm_apic_write(reg, val);
1967
1968         switch (reg) {
1969         case APIC_ID:           /* Local APIC ID */
1970                 if (!apic_x2apic_mode(apic))
1971                         kvm_apic_set_xapic_id(apic, val >> 24);
1972                 else
1973                         ret = 1;
1974                 break;
1975
1976         case APIC_TASKPRI:
1977                 report_tpr_access(apic, true);
1978                 apic_set_tpr(apic, val & 0xff);
1979                 break;
1980
1981         case APIC_EOI:
1982                 apic_set_eoi(apic);
1983                 break;
1984
1985         case APIC_LDR:
1986                 if (!apic_x2apic_mode(apic))
1987                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1988                 else
1989                         ret = 1;
1990                 break;
1991
1992         case APIC_DFR:
1993                 if (!apic_x2apic_mode(apic))
1994                         kvm_apic_set_dfr(apic, val | 0x0FFFFFFF);
1995                 else
1996                         ret = 1;
1997                 break;
1998
1999         case APIC_SPIV: {
2000                 u32 mask = 0x3ff;
2001                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
2002                         mask |= APIC_SPIV_DIRECTED_EOI;
2003                 apic_set_spiv(apic, val & mask);
2004                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
2005                         int i;
2006                         u32 lvt_val;
2007
2008                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
2009                                 lvt_val = kvm_lapic_get_reg(apic,
2010                                                        APIC_LVTT + 0x10 * i);
2011                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
2012                                              lvt_val | APIC_LVT_MASKED);
2013                         }
2014                         apic_update_lvtt(apic);
2015                         atomic_set(&apic->lapic_timer.pending, 0);
2016
2017                 }
2018                 break;
2019         }
2020         case APIC_ICR:
2021                 /* No delay here, so we always clear the pending bit */
2022                 val &= ~(1 << 12);
2023                 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
2024                 kvm_lapic_set_reg(apic, APIC_ICR, val);
2025                 break;
2026
2027         case APIC_ICR2:
2028                 if (!apic_x2apic_mode(apic))
2029                         val &= 0xff000000;
2030                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
2031                 break;
2032
2033         case APIC_LVT0:
2034                 apic_manage_nmi_watchdog(apic, val);
2035                 fallthrough;
2036         case APIC_LVTTHMR:
2037         case APIC_LVTPC:
2038         case APIC_LVT1:
2039         case APIC_LVTERR: {
2040                 /* TODO: Check vector */
2041                 size_t size;
2042                 u32 index;
2043
2044                 if (!kvm_apic_sw_enabled(apic))
2045                         val |= APIC_LVT_MASKED;
2046                 size = ARRAY_SIZE(apic_lvt_mask);
2047                 index = array_index_nospec(
2048                                 (reg - APIC_LVTT) >> 4, size);
2049                 val &= apic_lvt_mask[index];
2050                 kvm_lapic_set_reg(apic, reg, val);
2051                 break;
2052         }
2053
2054         case APIC_LVTT:
2055                 if (!kvm_apic_sw_enabled(apic))
2056                         val |= APIC_LVT_MASKED;
2057                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
2058                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
2059                 apic_update_lvtt(apic);
2060                 break;
2061
2062         case APIC_TMICT:
2063                 if (apic_lvtt_tscdeadline(apic))
2064                         break;
2065
2066                 hrtimer_cancel(&apic->lapic_timer.timer);
2067                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
2068                 start_apic_timer(apic);
2069                 break;
2070
2071         case APIC_TDCR: {
2072                 uint32_t old_divisor = apic->divide_count;
2073
2074                 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
2075                 update_divide_count(apic);
2076                 if (apic->divide_count != old_divisor &&
2077                                 apic->lapic_timer.period) {
2078                         hrtimer_cancel(&apic->lapic_timer.timer);
2079                         update_target_expiration(apic, old_divisor);
2080                         restart_apic_timer(apic);
2081                 }
2082                 break;
2083         }
2084         case APIC_ESR:
2085                 if (apic_x2apic_mode(apic) && val != 0)
2086                         ret = 1;
2087                 break;
2088
2089         case APIC_SELF_IPI:
2090                 if (apic_x2apic_mode(apic)) {
2091                         kvm_lapic_reg_write(apic, APIC_ICR,
2092                                             APIC_DEST_SELF | (val & APIC_VECTOR_MASK));
2093                 } else
2094                         ret = 1;
2095                 break;
2096         default:
2097                 ret = 1;
2098                 break;
2099         }
2100
2101         kvm_recalculate_apic_map(apic->vcpu->kvm);
2102
2103         return ret;
2104 }
2105 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
2106
2107 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
2108                             gpa_t address, int len, const void *data)
2109 {
2110         struct kvm_lapic *apic = to_lapic(this);
2111         unsigned int offset = address - apic->base_address;
2112         u32 val;
2113
2114         if (!apic_mmio_in_range(apic, address))
2115                 return -EOPNOTSUPP;
2116
2117         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2118                 if (!kvm_check_has_quirk(vcpu->kvm,
2119                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2120                         return -EOPNOTSUPP;
2121
2122                 return 0;
2123         }
2124
2125         /*
2126          * APIC register must be aligned on 128-bits boundary.
2127          * 32/64/128 bits registers must be accessed thru 32 bits.
2128          * Refer SDM 8.4.1
2129          */
2130         if (len != 4 || (offset & 0xf))
2131                 return 0;
2132
2133         val = *(u32*)data;
2134
2135         kvm_lapic_reg_write(apic, offset & 0xff0, val);
2136
2137         return 0;
2138 }
2139
2140 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2141 {
2142         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2143 }
2144 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2145
2146 /* emulate APIC access in a trap manner */
2147 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2148 {
2149         u32 val = 0;
2150
2151         /* hw has done the conditional check and inst decode */
2152         offset &= 0xff0;
2153
2154         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2155
2156         /* TODO: optimize to just emulate side effect w/o one more write */
2157         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2158 }
2159 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2160
2161 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2162 {
2163         struct kvm_lapic *apic = vcpu->arch.apic;
2164
2165         if (!vcpu->arch.apic)
2166                 return;
2167
2168         hrtimer_cancel(&apic->lapic_timer.timer);
2169
2170         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2171                 static_key_slow_dec_deferred(&apic_hw_disabled);
2172
2173         if (!apic->sw_enabled)
2174                 static_key_slow_dec_deferred(&apic_sw_disabled);
2175
2176         if (apic->regs)
2177                 free_page((unsigned long)apic->regs);
2178
2179         kfree(apic);
2180 }
2181
2182 /*
2183  *----------------------------------------------------------------------
2184  * LAPIC interface
2185  *----------------------------------------------------------------------
2186  */
2187 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2188 {
2189         struct kvm_lapic *apic = vcpu->arch.apic;
2190
2191         if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
2192                 return 0;
2193
2194         return apic->lapic_timer.tscdeadline;
2195 }
2196
2197 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2198 {
2199         struct kvm_lapic *apic = vcpu->arch.apic;
2200
2201         if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
2202                         apic_lvtt_period(apic))
2203                 return;
2204
2205         hrtimer_cancel(&apic->lapic_timer.timer);
2206         apic->lapic_timer.tscdeadline = data;
2207         start_apic_timer(apic);
2208 }
2209
2210 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2211 {
2212         struct kvm_lapic *apic = vcpu->arch.apic;
2213
2214         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2215                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2216 }
2217
2218 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2219 {
2220         u64 tpr;
2221
2222         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2223
2224         return (tpr & 0xf0) >> 4;
2225 }
2226
2227 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2228 {
2229         u64 old_value = vcpu->arch.apic_base;
2230         struct kvm_lapic *apic = vcpu->arch.apic;
2231
2232         if (!apic)
2233                 value |= MSR_IA32_APICBASE_BSP;
2234
2235         vcpu->arch.apic_base = value;
2236
2237         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2238                 kvm_update_cpuid_runtime(vcpu);
2239
2240         if (!apic)
2241                 return;
2242
2243         /* update jump label if enable bit changes */
2244         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2245                 if (value & MSR_IA32_APICBASE_ENABLE) {
2246                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2247                         static_key_slow_dec_deferred(&apic_hw_disabled);
2248                 } else {
2249                         static_key_slow_inc(&apic_hw_disabled.key);
2250                         atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2251                 }
2252         }
2253
2254         if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2255                 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2256
2257         if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2258                 kvm_x86_ops.set_virtual_apic_mode(vcpu);
2259
2260         apic->base_address = apic->vcpu->arch.apic_base &
2261                              MSR_IA32_APICBASE_BASE;
2262
2263         if ((value & MSR_IA32_APICBASE_ENABLE) &&
2264              apic->base_address != APIC_DEFAULT_PHYS_BASE)
2265                 pr_warn_once("APIC base relocation is unsupported by KVM");
2266 }
2267
2268 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
2269 {
2270         struct kvm_lapic *apic = vcpu->arch.apic;
2271
2272         if (vcpu->arch.apicv_active) {
2273                 /* irr_pending is always true when apicv is activated. */
2274                 apic->irr_pending = true;
2275                 apic->isr_count = 1;
2276         } else {
2277                 apic->irr_pending = (apic_search_irr(apic) != -1);
2278                 apic->isr_count = count_vectors(apic->regs + APIC_ISR);
2279         }
2280 }
2281 EXPORT_SYMBOL_GPL(kvm_apic_update_apicv);
2282
2283 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2284 {
2285         struct kvm_lapic *apic = vcpu->arch.apic;
2286         int i;
2287
2288         if (!apic)
2289                 return;
2290
2291         /* Stop the timer in case it's a reset to an active apic */
2292         hrtimer_cancel(&apic->lapic_timer.timer);
2293
2294         if (!init_event) {
2295                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2296                                          MSR_IA32_APICBASE_ENABLE);
2297                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2298         }
2299         kvm_apic_set_version(apic->vcpu);
2300
2301         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2302                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2303         apic_update_lvtt(apic);
2304         if (kvm_vcpu_is_reset_bsp(vcpu) &&
2305             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2306                 kvm_lapic_set_reg(apic, APIC_LVT0,
2307                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2308         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2309
2310         kvm_apic_set_dfr(apic, 0xffffffffU);
2311         apic_set_spiv(apic, 0xff);
2312         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2313         if (!apic_x2apic_mode(apic))
2314                 kvm_apic_set_ldr(apic, 0);
2315         kvm_lapic_set_reg(apic, APIC_ESR, 0);
2316         kvm_lapic_set_reg(apic, APIC_ICR, 0);
2317         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2318         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2319         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2320         for (i = 0; i < 8; i++) {
2321                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2322                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2323                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2324         }
2325         kvm_apic_update_apicv(vcpu);
2326         apic->highest_isr_cache = -1;
2327         update_divide_count(apic);
2328         atomic_set(&apic->lapic_timer.pending, 0);
2329         if (kvm_vcpu_is_bsp(vcpu))
2330                 kvm_lapic_set_base(vcpu,
2331                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2332         vcpu->arch.pv_eoi.msr_val = 0;
2333         apic_update_ppr(apic);
2334         if (vcpu->arch.apicv_active) {
2335                 kvm_x86_ops.apicv_post_state_restore(vcpu);
2336                 kvm_x86_ops.hwapic_irr_update(vcpu, -1);
2337                 kvm_x86_ops.hwapic_isr_update(vcpu, -1);
2338         }
2339
2340         vcpu->arch.apic_arb_prio = 0;
2341         vcpu->arch.apic_attention = 0;
2342
2343         kvm_recalculate_apic_map(vcpu->kvm);
2344 }
2345
2346 /*
2347  *----------------------------------------------------------------------
2348  * timer interface
2349  *----------------------------------------------------------------------
2350  */
2351
2352 static bool lapic_is_periodic(struct kvm_lapic *apic)
2353 {
2354         return apic_lvtt_period(apic);
2355 }
2356
2357 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2358 {
2359         struct kvm_lapic *apic = vcpu->arch.apic;
2360
2361         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2362                 return atomic_read(&apic->lapic_timer.pending);
2363
2364         return 0;
2365 }
2366
2367 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2368 {
2369         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2370         int vector, mode, trig_mode;
2371
2372         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2373                 vector = reg & APIC_VECTOR_MASK;
2374                 mode = reg & APIC_MODE_MASK;
2375                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2376                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2377                                         NULL);
2378         }
2379         return 0;
2380 }
2381
2382 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2383 {
2384         struct kvm_lapic *apic = vcpu->arch.apic;
2385
2386         if (apic)
2387                 kvm_apic_local_deliver(apic, APIC_LVT0);
2388 }
2389
2390 static const struct kvm_io_device_ops apic_mmio_ops = {
2391         .read     = apic_mmio_read,
2392         .write    = apic_mmio_write,
2393 };
2394
2395 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2396 {
2397         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2398         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2399
2400         apic_timer_expired(apic, true);
2401
2402         if (lapic_is_periodic(apic)) {
2403                 advance_periodic_target_expiration(apic);
2404                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2405                 return HRTIMER_RESTART;
2406         } else
2407                 return HRTIMER_NORESTART;
2408 }
2409
2410 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns)
2411 {
2412         struct kvm_lapic *apic;
2413
2414         ASSERT(vcpu != NULL);
2415
2416         apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2417         if (!apic)
2418                 goto nomem;
2419
2420         vcpu->arch.apic = apic;
2421
2422         apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2423         if (!apic->regs) {
2424                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2425                        vcpu->vcpu_id);
2426                 goto nomem_free_apic;
2427         }
2428         apic->vcpu = vcpu;
2429
2430         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2431                      HRTIMER_MODE_ABS_HARD);
2432         apic->lapic_timer.timer.function = apic_timer_fn;
2433         if (timer_advance_ns == -1) {
2434                 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
2435                 lapic_timer_advance_dynamic = true;
2436         } else {
2437                 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
2438                 lapic_timer_advance_dynamic = false;
2439         }
2440
2441         /*
2442          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2443          * thinking that APIC state has changed.
2444          */
2445         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2446         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2447         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2448
2449         return 0;
2450 nomem_free_apic:
2451         kfree(apic);
2452         vcpu->arch.apic = NULL;
2453 nomem:
2454         return -ENOMEM;
2455 }
2456
2457 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2458 {
2459         struct kvm_lapic *apic = vcpu->arch.apic;
2460         u32 ppr;
2461
2462         if (!kvm_apic_hw_enabled(apic))
2463                 return -1;
2464
2465         __apic_update_ppr(apic, &ppr);
2466         return apic_has_interrupt_for_ppr(apic, ppr);
2467 }
2468
2469 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2470 {
2471         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2472
2473         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2474                 return 1;
2475         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2476             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2477                 return 1;
2478         return 0;
2479 }
2480
2481 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2482 {
2483         struct kvm_lapic *apic = vcpu->arch.apic;
2484
2485         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2486                 kvm_apic_inject_pending_timer_irqs(apic);
2487                 atomic_set(&apic->lapic_timer.pending, 0);
2488         }
2489 }
2490
2491 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2492 {
2493         int vector = kvm_apic_has_interrupt(vcpu);
2494         struct kvm_lapic *apic = vcpu->arch.apic;
2495         u32 ppr;
2496
2497         if (vector == -1)
2498                 return -1;
2499
2500         /*
2501          * We get here even with APIC virtualization enabled, if doing
2502          * nested virtualization and L1 runs with the "acknowledge interrupt
2503          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2504          * because the process would deliver it through the IDT.
2505          */
2506
2507         apic_clear_irr(vector, apic);
2508         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2509                 /*
2510                  * For auto-EOI interrupts, there might be another pending
2511                  * interrupt above PPR, so check whether to raise another
2512                  * KVM_REQ_EVENT.
2513                  */
2514                 apic_update_ppr(apic);
2515         } else {
2516                 /*
2517                  * For normal interrupts, PPR has been raised and there cannot
2518                  * be a higher-priority pending interrupt---except if there was
2519                  * a concurrent interrupt injection, but that would have
2520                  * triggered KVM_REQ_EVENT already.
2521                  */
2522                 apic_set_isr(vector, apic);
2523                 __apic_update_ppr(apic, &ppr);
2524         }
2525
2526         return vector;
2527 }
2528
2529 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2530                 struct kvm_lapic_state *s, bool set)
2531 {
2532         if (apic_x2apic_mode(vcpu->arch.apic)) {
2533                 u32 *id = (u32 *)(s->regs + APIC_ID);
2534                 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2535
2536                 if (vcpu->kvm->arch.x2apic_format) {
2537                         if (*id != vcpu->vcpu_id)
2538                                 return -EINVAL;
2539                 } else {
2540                         if (set)
2541                                 *id >>= 24;
2542                         else
2543                                 *id <<= 24;
2544                 }
2545
2546                 /* In x2APIC mode, the LDR is fixed and based on the id */
2547                 if (set)
2548                         *ldr = kvm_apic_calc_x2apic_ldr(*id);
2549         }
2550
2551         return 0;
2552 }
2553
2554 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2555 {
2556         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2557
2558         /*
2559          * Get calculated timer current count for remaining timer period (if
2560          * any) and store it in the returned register set.
2561          */
2562         __kvm_lapic_set_reg(s->regs, APIC_TMCCT,
2563                             __apic_read(vcpu->arch.apic, APIC_TMCCT));
2564
2565         return kvm_apic_state_fixup(vcpu, s, false);
2566 }
2567
2568 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2569 {
2570         struct kvm_lapic *apic = vcpu->arch.apic;
2571         int r;
2572
2573         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2574         /* set SPIV separately to get count of SW disabled APICs right */
2575         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2576
2577         r = kvm_apic_state_fixup(vcpu, s, true);
2578         if (r) {
2579                 kvm_recalculate_apic_map(vcpu->kvm);
2580                 return r;
2581         }
2582         memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2583
2584         atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2585         kvm_recalculate_apic_map(vcpu->kvm);
2586         kvm_apic_set_version(vcpu);
2587
2588         apic_update_ppr(apic);
2589         hrtimer_cancel(&apic->lapic_timer.timer);
2590         apic_update_lvtt(apic);
2591         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2592         update_divide_count(apic);
2593         __start_apic_timer(apic, APIC_TMCCT);
2594         kvm_apic_update_apicv(vcpu);
2595         apic->highest_isr_cache = -1;
2596         if (vcpu->arch.apicv_active) {
2597                 kvm_x86_ops.apicv_post_state_restore(vcpu);
2598                 kvm_x86_ops.hwapic_irr_update(vcpu,
2599                                 apic_find_highest_irr(apic));
2600                 kvm_x86_ops.hwapic_isr_update(vcpu,
2601                                 apic_find_highest_isr(apic));
2602         }
2603         kvm_make_request(KVM_REQ_EVENT, vcpu);
2604         if (ioapic_in_kernel(vcpu->kvm))
2605                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2606
2607         vcpu->arch.apic_arb_prio = 0;
2608
2609         return 0;
2610 }
2611
2612 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2613 {
2614         struct hrtimer *timer;
2615
2616         if (!lapic_in_kernel(vcpu) ||
2617                 kvm_can_post_timer_interrupt(vcpu))
2618                 return;
2619
2620         timer = &vcpu->arch.apic->lapic_timer.timer;
2621         if (hrtimer_cancel(timer))
2622                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD);
2623 }
2624
2625 /*
2626  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2627  *
2628  * Detect whether guest triggered PV EOI since the
2629  * last entry. If yes, set EOI on guests's behalf.
2630  * Clear PV EOI in guest memory in any case.
2631  */
2632 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2633                                         struct kvm_lapic *apic)
2634 {
2635         bool pending;
2636         int vector;
2637         /*
2638          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2639          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2640          *
2641          * KVM_APIC_PV_EOI_PENDING is unset:
2642          *      -> host disabled PV EOI.
2643          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2644          *      -> host enabled PV EOI, guest did not execute EOI yet.
2645          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2646          *      -> host enabled PV EOI, guest executed EOI.
2647          */
2648         BUG_ON(!pv_eoi_enabled(vcpu));
2649         pending = pv_eoi_get_pending(vcpu);
2650         /*
2651          * Clear pending bit in any case: it will be set again on vmentry.
2652          * While this might not be ideal from performance point of view,
2653          * this makes sure pv eoi is only enabled when we know it's safe.
2654          */
2655         pv_eoi_clr_pending(vcpu);
2656         if (pending)
2657                 return;
2658         vector = apic_set_eoi(apic);
2659         trace_kvm_pv_eoi(apic, vector);
2660 }
2661
2662 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2663 {
2664         u32 data;
2665
2666         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2667                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2668
2669         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2670                 return;
2671
2672         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2673                                   sizeof(u32)))
2674                 return;
2675
2676         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2677 }
2678
2679 /*
2680  * apic_sync_pv_eoi_to_guest - called before vmentry
2681  *
2682  * Detect whether it's safe to enable PV EOI and
2683  * if yes do so.
2684  */
2685 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2686                                         struct kvm_lapic *apic)
2687 {
2688         if (!pv_eoi_enabled(vcpu) ||
2689             /* IRR set or many bits in ISR: could be nested. */
2690             apic->irr_pending ||
2691             /* Cache not set: could be safe but we don't bother. */
2692             apic->highest_isr_cache == -1 ||
2693             /* Need EOI to update ioapic. */
2694             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2695                 /*
2696                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2697                  * so we need not do anything here.
2698                  */
2699                 return;
2700         }
2701
2702         pv_eoi_set_pending(apic->vcpu);
2703 }
2704
2705 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2706 {
2707         u32 data, tpr;
2708         int max_irr, max_isr;
2709         struct kvm_lapic *apic = vcpu->arch.apic;
2710
2711         apic_sync_pv_eoi_to_guest(vcpu, apic);
2712
2713         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2714                 return;
2715
2716         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2717         max_irr = apic_find_highest_irr(apic);
2718         if (max_irr < 0)
2719                 max_irr = 0;
2720         max_isr = apic_find_highest_isr(apic);
2721         if (max_isr < 0)
2722                 max_isr = 0;
2723         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2724
2725         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2726                                 sizeof(u32));
2727 }
2728
2729 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2730 {
2731         if (vapic_addr) {
2732                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2733                                         &vcpu->arch.apic->vapic_cache,
2734                                         vapic_addr, sizeof(u32)))
2735                         return -EINVAL;
2736                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2737         } else {
2738                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2739         }
2740
2741         vcpu->arch.apic->vapic_addr = vapic_addr;
2742         return 0;
2743 }
2744
2745 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2746 {
2747         struct kvm_lapic *apic = vcpu->arch.apic;
2748         u32 reg = (msr - APIC_BASE_MSR) << 4;
2749
2750         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2751                 return 1;
2752
2753         if (reg == APIC_ICR2)
2754                 return 1;
2755
2756         /* if this is ICR write vector before command */
2757         if (reg == APIC_ICR)
2758                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2759         return kvm_lapic_reg_write(apic, reg, (u32)data);
2760 }
2761
2762 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2763 {
2764         struct kvm_lapic *apic = vcpu->arch.apic;
2765         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2766
2767         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2768                 return 1;
2769
2770         if (reg == APIC_DFR || reg == APIC_ICR2)
2771                 return 1;
2772
2773         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2774                 return 1;
2775         if (reg == APIC_ICR)
2776                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2777
2778         *data = (((u64)high) << 32) | low;
2779
2780         return 0;
2781 }
2782
2783 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2784 {
2785         struct kvm_lapic *apic = vcpu->arch.apic;
2786
2787         if (!lapic_in_kernel(vcpu))
2788                 return 1;
2789
2790         /* if this is ICR write vector before command */
2791         if (reg == APIC_ICR)
2792                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2793         return kvm_lapic_reg_write(apic, reg, (u32)data);
2794 }
2795
2796 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2797 {
2798         struct kvm_lapic *apic = vcpu->arch.apic;
2799         u32 low, high = 0;
2800
2801         if (!lapic_in_kernel(vcpu))
2802                 return 1;
2803
2804         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2805                 return 1;
2806         if (reg == APIC_ICR)
2807                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2808
2809         *data = (((u64)high) << 32) | low;
2810
2811         return 0;
2812 }
2813
2814 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2815 {
2816         u64 addr = data & ~KVM_MSR_ENABLED;
2817         struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2818         unsigned long new_len;
2819
2820         if (!IS_ALIGNED(addr, 4))
2821                 return 1;
2822
2823         vcpu->arch.pv_eoi.msr_val = data;
2824         if (!pv_eoi_enabled(vcpu))
2825                 return 0;
2826
2827         if (addr == ghc->gpa && len <= ghc->len)
2828                 new_len = ghc->len;
2829         else
2830                 new_len = len;
2831
2832         return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2833 }
2834
2835 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2836 {
2837         struct kvm_lapic *apic = vcpu->arch.apic;
2838         u8 sipi_vector;
2839         unsigned long pe;
2840
2841         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2842                 return;
2843
2844         /*
2845          * INITs are latched while CPU is in specific states
2846          * (SMM, VMX non-root mode, SVM with GIF=0).
2847          * Because a CPU cannot be in these states immediately
2848          * after it has processed an INIT signal (and thus in
2849          * KVM_MP_STATE_INIT_RECEIVED state), just eat SIPIs
2850          * and leave the INIT pending.
2851          */
2852         if (kvm_vcpu_latch_init(vcpu)) {
2853                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2854                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2855                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2856                 return;
2857         }
2858
2859         pe = xchg(&apic->pending_events, 0);
2860         if (test_bit(KVM_APIC_INIT, &pe)) {
2861                 kvm_vcpu_reset(vcpu, true);
2862                 if (kvm_vcpu_is_bsp(apic->vcpu))
2863                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2864                 else
2865                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2866         }
2867         if (test_bit(KVM_APIC_SIPI, &pe) &&
2868             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2869                 /* evaluate pending_events before reading the vector */
2870                 smp_rmb();
2871                 sipi_vector = apic->sipi_vector;
2872                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2873                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2874         }
2875 }
2876
2877 void kvm_lapic_init(void)
2878 {
2879         /* do not patch jump label more than once per second */
2880         jump_label_rate_limit(&apic_hw_disabled, HZ);
2881         jump_label_rate_limit(&apic_sw_disabled, HZ);
2882 }
2883
2884 void kvm_lapic_exit(void)
2885 {
2886         static_key_deferred_flush(&apic_hw_disabled);
2887         static_key_deferred_flush(&apic_sw_disabled);
2888 }