arch/x86/kvm/ioapic.c

   1 /*
   2  *  Copyright (C) 2001  MandrakeSoft S.A.
   3  *  Copyright 2010 Red Hat, Inc. and/or its affiliates.
   4  *
   5  *    MandrakeSoft S.A.
   6  *    43, rue d'Aboukir
   7  *    75002 Paris - France
   8  *    http://www.linux-mandrake.com/
   9  *    http://www.mandrakesoft.com/
  10  *
  11  *  This library is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU Lesser General Public
  13  *  License as published by the Free Software Foundation; either
  14  *  version 2 of the License, or (at your option) any later version.
  15  *
  16  *  This library is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  *  Lesser General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU Lesser General Public
  22  *  License along with this library; if not, write to the Free Software
  23  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  24  *
  25  *  Yunhong Jiang <yunhong.jiang@intel.com>
  26  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
  27  *  Based on Xen 3.1 code.
  28  */
  29
  30 #include <linux/kvm_host.h>
  31 #include <linux/kvm.h>
  32 #include <linux/mm.h>
  33 #include <linux/highmem.h>
  34 #include <linux/smp.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/export.h>
  39 #include <linux/nospec.h>
  40 #include <asm/processor.h>
  41 #include <asm/page.h>
  42 #include <asm/current.h>
  43 #include <trace/events/kvm.h>
  44
  45 #include "ioapic.h"
  46 #include "lapic.h"
  47 #include "irq.h"
  48
  49 static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
  50                 bool line_status);
  51
  52 static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
  53                                       struct kvm_ioapic *ioapic,
  54                                       int trigger_mode,
  55                                       int pin);
  56
  57 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  58                                           unsigned long addr,
  59                                           unsigned long length)
  60 {
  61         unsigned long result = 0;
  62
  63         switch (ioapic->ioregsel) {
  64         case IOAPIC_REG_VERSION:
  65                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  66                           | (IOAPIC_VERSION_ID & 0xff));
  67                 break;
  68
  69         case IOAPIC_REG_APIC_ID:
  70         case IOAPIC_REG_ARB_ID:
  71                 result = ((ioapic->id & 0xf) << 24);
  72                 break;
  73
  74         default:
  75                 {
  76                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  77                         u64 redir_content = ~0ULL;
  78
  79                         if (redir_index < IOAPIC_NUM_PINS) {
  80                                 u32 index = array_index_nospec(
  81                                         redir_index, IOAPIC_NUM_PINS);
  82
  83                                 redir_content = ioapic->redirtbl[index].bits;
  84                         }
  85
  86                         result = (ioapic->ioregsel & 0x1) ?
  87                             (redir_content >> 32) & 0xffffffff :
  88                             redir_content & 0xffffffff;
  89                         break;
  90                 }
  91         }
  92
  93         return result;
  94 }
  95
  96 static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
  97 {
  98         ioapic->rtc_status.pending_eoi = 0;
  99         bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_ID + 1);
 100 }
 101
 102 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic);
 103
 104 static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic)
 105 {
 106         if (WARN_ON(ioapic->rtc_status.pending_eoi < 0))
 107                 kvm_rtc_eoi_tracking_restore_all(ioapic);
 108 }
 109
 110 static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
 111 {
 112         bool new_val, old_val;
 113         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
 114         struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
 115         union kvm_ioapic_redirect_entry *e;
 116
 117         e = &ioapic->redirtbl[RTC_GSI];
 118         if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
 119                                  e->fields.dest_id,
 120                                  kvm_lapic_irq_dest_mode(!!e->fields.dest_mode)))
 121                 return;
 122
 123         new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
 124         old_val = test_bit(vcpu->vcpu_id, dest_map->map);
 125
 126         if (new_val == old_val)
 127                 return;
 128
 129         if (new_val) {
 130                 __set_bit(vcpu->vcpu_id, dest_map->map);
 131                 dest_map->vectors[vcpu->vcpu_id] = e->fields.vector;
 132                 ioapic->rtc_status.pending_eoi++;
 133         } else {
 134                 __clear_bit(vcpu->vcpu_id, dest_map->map);
 135                 ioapic->rtc_status.pending_eoi--;
 136                 rtc_status_pending_eoi_check_valid(ioapic);
 137         }
 138 }
 139
 140 void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
 141 {
 142         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
 143
 144         spin_lock(&ioapic->lock);
 145         __rtc_irq_eoi_tracking_restore_one(vcpu);
 146         spin_unlock(&ioapic->lock);
 147 }
 148
 149 static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
 150 {
 151         struct kvm_vcpu *vcpu;
 152         int i;
 153
 154         if (RTC_GSI >= IOAPIC_NUM_PINS)
 155                 return;
 156
 157         rtc_irq_eoi_tracking_reset(ioapic);
 158         kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
 159             __rtc_irq_eoi_tracking_restore_one(vcpu);
 160 }
 161
 162 static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu,
 163                         int vector)
 164 {
 165         struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
 166
 167         /* RTC special handling */
 168         if (test_bit(vcpu->vcpu_id, dest_map->map) &&
 169             (vector == dest_map->vectors[vcpu->vcpu_id]) &&
 170             (test_and_clear_bit(vcpu->vcpu_id,
 171                                 ioapic->rtc_status.dest_map.map))) {
 172                 --ioapic->rtc_status.pending_eoi;
 173                 rtc_status_pending_eoi_check_valid(ioapic);
 174         }
 175 }
 176
 177 static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
 178 {
 179         if (ioapic->rtc_status.pending_eoi > 0)
 180                 return true; /* coalesced */
 181
 182         return false;
 183 }
 184
 185 static void ioapic_lazy_update_eoi(struct kvm_ioapic *ioapic, int irq)
 186 {
 187         int i;
 188         struct kvm_vcpu *vcpu;
 189         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
 190
 191         kvm_for_each_vcpu(i, vcpu, ioapic->kvm) {
 192                 if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
 193                                          entry->fields.dest_id,
 194                                          entry->fields.dest_mode) ||
 195                     kvm_apic_pending_eoi(vcpu, entry->fields.vector))
 196                         continue;
 197
 198                 /*
 199                  * If no longer has pending EOI in LAPICs, update
 200                  * EOI for this vector.
 201                  */
 202                 rtc_irq_eoi(ioapic, vcpu, entry->fields.vector);
 203                 break;
 204         }
 205 }
 206
 207 static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
 208                 int irq_level, bool line_status)
 209 {
 210         union kvm_ioapic_redirect_entry entry;
 211         u32 mask = 1 << irq;
 212         u32 old_irr;
 213         int edge, ret;
 214
 215         entry = ioapic->redirtbl[irq];
 216         edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
 217
 218         if (!irq_level) {
 219                 ioapic->irr &= ~mask;
 220                 ret = 1;
 221                 goto out;
 222         }
 223
 224         /*
 225          * AMD SVM AVIC accelerate EOI write iff the interrupt is edge
 226          * triggered, in which case the in-kernel IOAPIC will not be able
 227          * to receive the EOI.  In this case, we do a lazy update of the
 228          * pending EOI when trying to set IOAPIC irq.
 229          */
 230         if (edge && kvm_apicv_activated(ioapic->kvm))
 231                 ioapic_lazy_update_eoi(ioapic, irq);
 232
 233         /*
 234          * Return 0 for coalesced interrupts; for edge-triggered interrupts,
 235          * this only happens if a previous edge has not been delivered due
 236          * to masking.  For level interrupts, the remote_irr field tells
 237          * us if the interrupt is waiting for an EOI.
 238          *
 239          * RTC is special: it is edge-triggered, but userspace likes to know
 240          * if it has been already ack-ed via EOI because coalesced RTC
 241          * interrupts lead to time drift in Windows guests.  So we track
 242          * EOI manually for the RTC interrupt.
 243          */
 244         if (irq == RTC_GSI && line_status &&
 245                 rtc_irq_check_coalesced(ioapic)) {
 246                 ret = 0;
 247                 goto out;
 248         }
 249
 250         old_irr = ioapic->irr;
 251         ioapic->irr |= mask;
 252         if (edge) {
 253                 ioapic->irr_delivered &= ~mask;
 254                 if (old_irr == ioapic->irr) {
 255                         ret = 0;
 256                         goto out;
 257                 }
 258         }
 259
 260         ret = ioapic_service(ioapic, irq, line_status);
 261
 262 out:
 263         trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
 264         return ret;
 265 }
 266
 267 static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr)
 268 {
 269         u32 idx;
 270
 271         rtc_irq_eoi_tracking_reset(ioapic);
 272         for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS)
 273                 ioapic_set_irq(ioapic, idx, 1, true);
 274
 275         kvm_rtc_eoi_tracking_restore_all(ioapic);
 276 }
 277
 278
 279 void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors)
 280 {
 281         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
 282         struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
 283         union kvm_ioapic_redirect_entry *e;
 284         int index;
 285
 286         spin_lock(&ioapic->lock);
 287
 288         /* Make sure we see any missing RTC EOI */
 289         if (test_bit(vcpu->vcpu_id, dest_map->map))
 290                 __set_bit(dest_map->vectors[vcpu->vcpu_id],
 291                           ioapic_handled_vectors);
 292
 293         for (index = 0; index < IOAPIC_NUM_PINS; index++) {
 294                 e = &ioapic->redirtbl[index];
 295                 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
 296                     kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) ||
 297                     index == RTC_GSI) {
 298                         u16 dm = kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
 299
 300                         if (kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
 301                                                 e->fields.dest_id, dm) ||
 302                             kvm_apic_pending_eoi(vcpu, e->fields.vector))
 303                                 __set_bit(e->fields.vector,
 304                                           ioapic_handled_vectors);
 305                 }
 306         }
 307         spin_unlock(&ioapic->lock);
 308 }
 309
 310 void kvm_arch_post_irq_ack_notifier_list_update(struct kvm *kvm)
 311 {
 312         if (!ioapic_in_kernel(kvm))
 313                 return;
 314         kvm_make_scan_ioapic_request(kvm);
 315 }
 316
 317 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 318 {
 319         unsigned index;
 320         bool mask_before, mask_after;
 321         union kvm_ioapic_redirect_entry *e;
 322         unsigned long vcpu_bitmap;
 323         int old_remote_irr, old_delivery_status, old_dest_id, old_dest_mode;
 324
 325         switch (ioapic->ioregsel) {
 326         case IOAPIC_REG_VERSION:
 327                 /* Writes are ignored. */
 328                 break;
 329
 330         case IOAPIC_REG_APIC_ID:
 331                 ioapic->id = (val >> 24) & 0xf;
 332                 break;
 333
 334         case IOAPIC_REG_ARB_ID:
 335                 break;
 336
 337         default:
 338                 index = (ioapic->ioregsel - 0x10) >> 1;
 339
 340                 if (index >= IOAPIC_NUM_PINS)
 341                         return;
 342                 index = array_index_nospec(index, IOAPIC_NUM_PINS);
 343                 e = &ioapic->redirtbl[index];
 344                 mask_before = e->fields.mask;
 345                 /* Preserve read-only fields */
 346                 old_remote_irr = e->fields.remote_irr;
 347                 old_delivery_status = e->fields.delivery_status;
 348                 old_dest_id = e->fields.dest_id;
 349                 old_dest_mode = e->fields.dest_mode;
 350                 if (ioapic->ioregsel & 1) {
 351                         e->bits &= 0xffffffff;
 352                         e->bits |= (u64) val << 32;
 353                 } else {
 354                         e->bits &= ~0xffffffffULL;
 355                         e->bits |= (u32) val;
 356                 }
 357                 e->fields.remote_irr = old_remote_irr;
 358                 e->fields.delivery_status = old_delivery_status;
 359
 360                 /*
 361                  * Some OSes (Linux, Xen) assume that Remote IRR bit will
 362                  * be cleared by IOAPIC hardware when the entry is configured
 363                  * as edge-triggered. This behavior is used to simulate an
 364                  * explicit EOI on IOAPICs that don't have the EOI register.
 365                  */
 366                 if (e->fields.trig_mode == IOAPIC_EDGE_TRIG)
 367                         e->fields.remote_irr = 0;
 368
 369                 mask_after = e->fields.mask;
 370                 if (mask_before != mask_after)
 371                         kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
 372                 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
 373                     && ioapic->irr & (1 << index))
 374                         ioapic_service(ioapic, index, false);
 375                 if (e->fields.delivery_mode == APIC_DM_FIXED) {
 376                         struct kvm_lapic_irq irq;
 377
 378                         irq.vector = e->fields.vector;
 379                         irq.delivery_mode = e->fields.delivery_mode << 8;
 380                         irq.dest_mode =
 381                             kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
 382                         irq.level = false;
 383                         irq.trig_mode = e->fields.trig_mode;
 384                         irq.shorthand = APIC_DEST_NOSHORT;
 385                         irq.dest_id = e->fields.dest_id;
 386                         irq.msi_redir_hint = false;
 387                         bitmap_zero(&vcpu_bitmap, 16);
 388                         kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
 389                                                  &vcpu_bitmap);
 390                         if (old_dest_mode != e->fields.dest_mode ||
 391                             old_dest_id != e->fields.dest_id) {
 392                                 /*
 393                                  * Update vcpu_bitmap with vcpus specified in
 394                                  * the previous request as well. This is done to
 395                                  * keep ioapic_handled_vectors synchronized.
 396                                  */
 397                                 irq.dest_id = old_dest_id;
 398                                 irq.dest_mode =
 399                                     kvm_lapic_irq_dest_mode(
 400                                         !!e->fields.dest_mode);
 401                                 kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
 402                                                          &vcpu_bitmap);
 403                         }
 404                         kvm_make_scan_ioapic_request_mask(ioapic->kvm,
 405                                                           &vcpu_bitmap);
 406                 } else {
 407                         kvm_make_scan_ioapic_request(ioapic->kvm);
 408                 }
 409                 break;
 410         }
 411 }
 412
 413 static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
 414 {
 415         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
 416         struct kvm_lapic_irq irqe;
 417         int ret;
 418
 419         if (entry->fields.mask ||
 420             (entry->fields.trig_mode == IOAPIC_LEVEL_TRIG &&
 421             entry->fields.remote_irr))
 422                 return -1;
 423
 424         irqe.dest_id = entry->fields.dest_id;
 425         irqe.vector = entry->fields.vector;
 426         irqe.dest_mode = kvm_lapic_irq_dest_mode(!!entry->fields.dest_mode);
 427         irqe.trig_mode = entry->fields.trig_mode;
 428         irqe.delivery_mode = entry->fields.delivery_mode << 8;
 429         irqe.level = 1;
 430         irqe.shorthand = APIC_DEST_NOSHORT;
 431         irqe.msi_redir_hint = false;
 432
 433         if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
 434                 ioapic->irr_delivered |= 1 << irq;
 435
 436         if (irq == RTC_GSI && line_status) {
 437                 /*
 438                  * pending_eoi cannot ever become negative (see
 439                  * rtc_status_pending_eoi_check_valid) and the caller
 440                  * ensures that it is only called if it is >= zero, namely
 441                  * if rtc_irq_check_coalesced returns false).
 442                  */
 443                 BUG_ON(ioapic->rtc_status.pending_eoi != 0);
 444                 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
 445                                                &ioapic->rtc_status.dest_map);
 446                 ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret);
 447         } else
 448                 ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);
 449
 450         if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG)
 451                 entry->fields.remote_irr = 1;
 452
 453         return ret;
 454 }
 455
 456 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
 457                        int level, bool line_status)
 458 {
 459         int ret, irq_level;
 460
 461         BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
 462
 463         spin_lock(&ioapic->lock);
 464         irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
 465                                          irq_source_id, level);
 466         ret = ioapic_set_irq(ioapic, irq, irq_level, line_status);
 467
 468         spin_unlock(&ioapic->lock);
 469
 470         return ret;
 471 }
 472
 473 void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
 474 {
 475         int i;
 476
 477         spin_lock(&ioapic->lock);
 478         for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
 479                 __clear_bit(irq_source_id, &ioapic->irq_states[i]);
 480         spin_unlock(&ioapic->lock);
 481 }
 482
 483 static void kvm_ioapic_eoi_inject_work(struct work_struct *work)
 484 {
 485         int i;
 486         struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic,
 487                                                  eoi_inject.work);
 488         spin_lock(&ioapic->lock);
 489         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 490                 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
 491
 492                 if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG)
 493                         continue;
 494
 495                 if (ioapic->irr & (1 << i) && !ent->fields.remote_irr)
 496                         ioapic_service(ioapic, i, false);
 497         }
 498         spin_unlock(&ioapic->lock);
 499 }
 500
 501 #define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000
 502 static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
 503                                       struct kvm_ioapic *ioapic,
 504                                       int trigger_mode,
 505                                       int pin)
 506 {
 507         struct kvm_lapic *apic = vcpu->arch.apic;
 508         union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[pin];
 509
 510         /*
 511          * We are dropping lock while calling ack notifiers because ack
 512          * notifier callbacks for assigned devices call into IOAPIC
 513          * recursively. Since remote_irr is cleared only after call
 514          * to notifiers if the same vector will be delivered while lock
 515          * is dropped it will be put into irr and will be delivered
 516          * after ack notifier returns.
 517          */
 518         spin_unlock(&ioapic->lock);
 519         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
 520         spin_lock(&ioapic->lock);
 521
 522         if (trigger_mode != IOAPIC_LEVEL_TRIG ||
 523             kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)
 524                 return;
 525
 526         ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
 527         ent->fields.remote_irr = 0;
 528         if (!ent->fields.mask && (ioapic->irr & (1 << pin))) {
 529                 ++ioapic->irq_eoi[pin];
 530                 if (ioapic->irq_eoi[pin] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) {
 531                         /*
 532                          * Real hardware does not deliver the interrupt
 533                          * immediately during eoi broadcast, and this
 534                          * lets a buggy guest make slow progress
 535                          * even if it does not correctly handle a
 536                          * level-triggered interrupt.  Emulate this
 537                          * behavior if we detect an interrupt storm.
 538                          */
 539                         schedule_delayed_work(&ioapic->eoi_inject, HZ / 100);
 540                         ioapic->irq_eoi[pin] = 0;
 541                         trace_kvm_ioapic_delayed_eoi_inj(ent->bits);
 542                 } else {
 543                         ioapic_service(ioapic, pin, false);
 544                 }
 545         } else {
 546                 ioapic->irq_eoi[pin] = 0;
 547         }
 548 }
 549
 550 void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
 551 {
 552         int i;
 553         struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
 554
 555         spin_lock(&ioapic->lock);
 556         rtc_irq_eoi(ioapic, vcpu, vector);
 557         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 558                 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
 559
 560                 if (ent->fields.vector != vector)
 561                         continue;
 562                 kvm_ioapic_update_eoi_one(vcpu, ioapic, trigger_mode, i);
 563         }
 564         spin_unlock(&ioapic->lock);
 565 }
 566
 567 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
 568 {
 569         return container_of(dev, struct kvm_ioapic, dev);
 570 }
 571
 572 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
 573 {
 574         return ((addr >= ioapic->base_address &&
 575                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
 576 }
 577
 578 static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
 579                                 gpa_t addr, int len, void *val)
 580 {
 581         struct kvm_ioapic *ioapic = to_ioapic(this);
 582         u32 result;
 583         if (!ioapic_in_range(ioapic, addr))
 584                 return -EOPNOTSUPP;
 585
 586         ASSERT(!(addr & 0xf));  /* check alignment */
 587
 588         addr &= 0xff;
 589         spin_lock(&ioapic->lock);
 590         switch (addr) {
 591         case IOAPIC_REG_SELECT:
 592                 result = ioapic->ioregsel;
 593                 break;
 594
 595         case IOAPIC_REG_WINDOW:
 596                 result = ioapic_read_indirect(ioapic, addr, len);
 597                 break;
 598
 599         default:
 600                 result = 0;
 601                 break;
 602         }
 603         spin_unlock(&ioapic->lock);
 604
 605         switch (len) {
 606         case 8:
 607                 *(u64 *) val = result;
 608                 break;
 609         case 1:
 610         case 2:
 611         case 4:
 612                 memcpy(val, (char *)&result, len);
 613                 break;
 614         default:
 615                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
 616         }
 617         return 0;
 618 }
 619
 620 static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
 621                                  gpa_t addr, int len, const void *val)
 622 {
 623         struct kvm_ioapic *ioapic = to_ioapic(this);
 624         u32 data;
 625         if (!ioapic_in_range(ioapic, addr))
 626                 return -EOPNOTSUPP;
 627
 628         ASSERT(!(addr & 0xf));  /* check alignment */
 629
 630         switch (len) {
 631         case 8:
 632         case 4:
 633                 data = *(u32 *) val;
 634                 break;
 635         case 2:
 636                 data = *(u16 *) val;
 637                 break;
 638         case 1:
 639                 data = *(u8  *) val;
 640                 break;
 641         default:
 642                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
 643                 return 0;
 644         }
 645
 646         addr &= 0xff;
 647         spin_lock(&ioapic->lock);
 648         switch (addr) {
 649         case IOAPIC_REG_SELECT:
 650                 ioapic->ioregsel = data & 0xFF; /* 8-bit register */
 651                 break;
 652
 653         case IOAPIC_REG_WINDOW:
 654                 ioapic_write_indirect(ioapic, data);
 655                 break;
 656
 657         default:
 658                 break;
 659         }
 660         spin_unlock(&ioapic->lock);
 661         return 0;
 662 }
 663
 664 static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
 665 {
 666         int i;
 667
 668         cancel_delayed_work_sync(&ioapic->eoi_inject);
 669         for (i = 0; i < IOAPIC_NUM_PINS; i++)
 670                 ioapic->redirtbl[i].fields.mask = 1;
 671         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 672         ioapic->ioregsel = 0;
 673         ioapic->irr = 0;
 674         ioapic->irr_delivered = 0;
 675         ioapic->id = 0;
 676         memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi));
 677         rtc_irq_eoi_tracking_reset(ioapic);
 678 }
 679
 680 static const struct kvm_io_device_ops ioapic_mmio_ops = {
 681         .read     = ioapic_mmio_read,
 682         .write    = ioapic_mmio_write,
 683 };
 684
 685 int kvm_ioapic_init(struct kvm *kvm)
 686 {
 687         struct kvm_ioapic *ioapic;
 688         int ret;
 689
 690         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL_ACCOUNT);
 691         if (!ioapic)
 692                 return -ENOMEM;
 693         spin_lock_init(&ioapic->lock);
 694         INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work);
 695         kvm->arch.vioapic = ioapic;
 696         kvm_ioapic_reset(ioapic);
 697         kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
 698         ioapic->kvm = kvm;
 699         mutex_lock(&kvm->slots_lock);
 700         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
 701                                       IOAPIC_MEM_LENGTH, &ioapic->dev);
 702         mutex_unlock(&kvm->slots_lock);
 703         if (ret < 0) {
 704                 kvm->arch.vioapic = NULL;
 705                 kfree(ioapic);
 706         }
 707
 708         return ret;
 709 }
 710
 711 void kvm_ioapic_destroy(struct kvm *kvm)
 712 {
 713         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 714
 715         if (!ioapic)
 716                 return;
 717
 718         cancel_delayed_work_sync(&ioapic->eoi_inject);
 719         mutex_lock(&kvm->slots_lock);
 720         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
 721         mutex_unlock(&kvm->slots_lock);
 722         kvm->arch.vioapic = NULL;
 723         kfree(ioapic);
 724 }
 725
 726 void kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 727 {
 728         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 729
 730         spin_lock(&ioapic->lock);
 731         memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
 732         state->irr &= ~ioapic->irr_delivered;
 733         spin_unlock(&ioapic->lock);
 734 }
 735
 736 void kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
 737 {
 738         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 739
 740         spin_lock(&ioapic->lock);
 741         memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
 742         ioapic->irr = 0;
 743         ioapic->irr_delivered = 0;
 744         kvm_make_scan_ioapic_request(kvm);
 745         kvm_ioapic_inject_all(ioapic, state->irr);
 746         spin_unlock(&ioapic->lock);
 747 }