2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 * Copyright (C) 2007 Alan Stern
17 * Copyright (C) 2009 IBM Corporation
18 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
20 * Authors: Alan Stern <stern@rowland.harvard.edu>
21 * K.Prasad <prasad@linux.vnet.ibm.com>
22 * Frederic Weisbecker <fweisbec@gmail.com>
26 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
27 * using the CPU's debug registers.
30 #include <linux/perf_event.h>
31 #include <linux/hw_breakpoint.h>
32 #include <linux/irqflags.h>
33 #include <linux/notifier.h>
34 #include <linux/kallsyms.h>
35 #include <linux/kprobes.h>
36 #include <linux/percpu.h>
37 #include <linux/kdebug.h>
38 #include <linux/kernel.h>
39 #include <linux/export.h>
40 #include <linux/sched.h>
41 #include <linux/smp.h>
43 #include <asm/hw_breakpoint.h>
44 #include <asm/processor.h>
45 #include <asm/debugreg.h>
48 /* Per cpu debug control register value */
49 DEFINE_PER_CPU(unsigned long, cpu_dr7);
50 EXPORT_PER_CPU_SYMBOL(cpu_dr7);
52 /* Per cpu debug address registers values */
53 static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
56 * Stores the breakpoints currently in use on each breakpoint address
57 * register for each cpus
59 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
62 static inline unsigned long
63 __encode_dr7(int drnum, unsigned int len, unsigned int type)
65 unsigned long bp_info;
67 bp_info = (len | type) & 0xf;
68 bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
69 bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));
75 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
76 * as stored in debug register 7.
78 unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
80 return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN;
84 * Decode the length and type bits for a particular breakpoint as
85 * stored in debug register 7. Return the "enabled" status.
87 int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
89 int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
91 *len = (bp_info & 0xc) | 0x40;
92 *type = (bp_info & 0x3) | 0x80;
94 return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
98 * Install a perf counter breakpoint.
100 * We seek a free debug address register and use it for this
101 * breakpoint. Eventually we enable it in the debug control register.
103 * Atomic: we hold the counter->ctx->lock and we only handle variables
104 * and registers local to this cpu.
106 int arch_install_hw_breakpoint(struct perf_event *bp)
108 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
112 for (i = 0; i < HBP_NUM; i++) {
113 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
121 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
124 set_debugreg(info->address, i);
125 __this_cpu_write(cpu_debugreg[i], info->address);
127 dr7 = this_cpu_ptr(&cpu_dr7);
128 *dr7 |= encode_dr7(i, info->len, info->type);
130 set_debugreg(*dr7, 7);
132 set_dr_addr_mask(info->mask, i);
138 * Uninstall the breakpoint contained in the given counter.
140 * First we search the debug address register it uses and then we disable
143 * Atomic: we hold the counter->ctx->lock and we only handle variables
144 * and registers local to this cpu.
146 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
148 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
152 for (i = 0; i < HBP_NUM; i++) {
153 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
161 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
164 dr7 = this_cpu_ptr(&cpu_dr7);
165 *dr7 &= ~__encode_dr7(i, info->len, info->type);
167 set_debugreg(*dr7, 7);
169 set_dr_addr_mask(0, i);
172 static int arch_bp_generic_len(int x86_len)
175 case X86_BREAKPOINT_LEN_1:
176 return HW_BREAKPOINT_LEN_1;
177 case X86_BREAKPOINT_LEN_2:
178 return HW_BREAKPOINT_LEN_2;
179 case X86_BREAKPOINT_LEN_4:
180 return HW_BREAKPOINT_LEN_4;
182 case X86_BREAKPOINT_LEN_8:
183 return HW_BREAKPOINT_LEN_8;
190 int arch_bp_generic_fields(int x86_len, int x86_type,
191 int *gen_len, int *gen_type)
197 case X86_BREAKPOINT_EXECUTE:
198 if (x86_len != X86_BREAKPOINT_LEN_X)
201 *gen_type = HW_BREAKPOINT_X;
202 *gen_len = sizeof(long);
204 case X86_BREAKPOINT_WRITE:
205 *gen_type = HW_BREAKPOINT_W;
207 case X86_BREAKPOINT_RW:
208 *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
215 len = arch_bp_generic_len(x86_len);
224 * Check for virtual address in kernel space.
226 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
232 len = arch_bp_generic_len(hw->len);
233 WARN_ON_ONCE(len < 0);
236 * We don't need to worry about va + len - 1 overflowing:
237 * we already require that va is aligned to a multiple of len.
239 return (va >= TASK_SIZE_MAX) || ((va + len - 1) >= TASK_SIZE_MAX);
242 static int arch_build_bp_info(struct perf_event *bp,
243 const struct perf_event_attr *attr,
244 struct arch_hw_breakpoint *hw)
246 hw->address = attr->bp_addr;
250 switch (attr->bp_type) {
251 case HW_BREAKPOINT_W:
252 hw->type = X86_BREAKPOINT_WRITE;
254 case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
255 hw->type = X86_BREAKPOINT_RW;
257 case HW_BREAKPOINT_X:
259 * We don't allow kernel breakpoints in places that are not
260 * acceptable for kprobes. On non-kprobes kernels, we don't
261 * allow kernel breakpoints at all.
263 if (attr->bp_addr >= TASK_SIZE_MAX) {
264 if (within_kprobe_blacklist(attr->bp_addr))
268 hw->type = X86_BREAKPOINT_EXECUTE;
270 * x86 inst breakpoints need to have a specific undefined len.
271 * But we still need to check userspace is not trying to setup
272 * an unsupported length, to get a range breakpoint for example.
274 if (attr->bp_len == sizeof(long)) {
275 hw->len = X86_BREAKPOINT_LEN_X;
284 switch (attr->bp_len) {
285 case HW_BREAKPOINT_LEN_1:
286 hw->len = X86_BREAKPOINT_LEN_1;
288 case HW_BREAKPOINT_LEN_2:
289 hw->len = X86_BREAKPOINT_LEN_2;
291 case HW_BREAKPOINT_LEN_4:
292 hw->len = X86_BREAKPOINT_LEN_4;
295 case HW_BREAKPOINT_LEN_8:
296 hw->len = X86_BREAKPOINT_LEN_8;
300 /* AMD range breakpoint */
301 if (!is_power_of_2(attr->bp_len))
303 if (attr->bp_addr & (attr->bp_len - 1))
306 if (!boot_cpu_has(X86_FEATURE_BPEXT))
310 * It's impossible to use a range breakpoint to fake out
311 * user vs kernel detection because bp_len - 1 can't
312 * have the high bit set. If we ever allow range instruction
313 * breakpoints, then we'll have to check for kprobe-blacklisted
314 * addresses anywhere in the range.
316 hw->mask = attr->bp_len - 1;
317 hw->len = X86_BREAKPOINT_LEN_1;
324 * Validate the arch-specific HW Breakpoint register settings
326 int hw_breakpoint_arch_parse(struct perf_event *bp,
327 const struct perf_event_attr *attr,
328 struct arch_hw_breakpoint *hw)
334 ret = arch_build_bp_info(bp, attr, hw);
339 case X86_BREAKPOINT_LEN_1:
344 case X86_BREAKPOINT_LEN_2:
347 case X86_BREAKPOINT_LEN_4:
351 case X86_BREAKPOINT_LEN_8:
361 * Check that the low-order bits of the address are appropriate
362 * for the alignment implied by len.
364 if (hw->address & align)
371 * Dump the debug register contents to the user.
372 * We can't dump our per cpu values because it
373 * may contain cpu wide breakpoint, something that
374 * doesn't belong to the current task.
376 * TODO: include non-ptrace user breakpoints (perf)
378 void aout_dump_debugregs(struct user *dump)
382 struct perf_event *bp;
383 struct arch_hw_breakpoint *info;
384 struct thread_struct *thread = ¤t->thread;
386 for (i = 0; i < HBP_NUM; i++) {
387 bp = thread->ptrace_bps[i];
389 if (bp && !bp->attr.disabled) {
390 dump->u_debugreg[i] = bp->attr.bp_addr;
391 info = counter_arch_bp(bp);
392 dr7 |= encode_dr7(i, info->len, info->type);
394 dump->u_debugreg[i] = 0;
398 dump->u_debugreg[4] = 0;
399 dump->u_debugreg[5] = 0;
400 dump->u_debugreg[6] = current->thread.debugreg6;
402 dump->u_debugreg[7] = dr7;
404 EXPORT_SYMBOL_GPL(aout_dump_debugregs);
407 * Release the user breakpoints used by ptrace
409 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
412 struct thread_struct *t = &tsk->thread;
414 for (i = 0; i < HBP_NUM; i++) {
415 unregister_hw_breakpoint(t->ptrace_bps[i]);
416 t->ptrace_bps[i] = NULL;
423 void hw_breakpoint_restore(void)
425 set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
426 set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
427 set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
428 set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
429 set_debugreg(current->thread.debugreg6, 6);
430 set_debugreg(__this_cpu_read(cpu_dr7), 7);
432 EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
435 * Handle debug exception notifications.
437 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
439 * NOTIFY_DONE returned if one of the following conditions is true.
440 * i) When the causative address is from user-space and the exception
441 * is a valid one, i.e. not triggered as a result of lazy debug register
443 * ii) When there are more bits than trap<n> set in DR6 register (such
444 * as BD, BS or BT) indicating that more than one debug condition is
445 * met and requires some more action in do_debug().
447 * NOTIFY_STOP returned for all other cases
450 static int hw_breakpoint_handler(struct die_args *args)
452 int i, cpu, rc = NOTIFY_STOP;
453 struct perf_event *bp;
454 unsigned long dr7, dr6;
455 unsigned long *dr6_p;
457 /* The DR6 value is pointed by args->err */
458 dr6_p = (unsigned long *)ERR_PTR(args->err);
461 /* If it's a single step, TRAP bits are random */
465 /* Do an early return if no trap bits are set in DR6 */
466 if ((dr6 & DR_TRAP_BITS) == 0)
469 get_debugreg(dr7, 7);
470 /* Disable breakpoints during exception handling */
471 set_debugreg(0UL, 7);
473 * Assert that local interrupts are disabled
474 * Reset the DRn bits in the virtualized register value.
475 * The ptrace trigger routine will add in whatever is needed.
477 current->thread.debugreg6 &= ~DR_TRAP_BITS;
480 /* Handle all the breakpoints that were triggered */
481 for (i = 0; i < HBP_NUM; ++i) {
482 if (likely(!(dr6 & (DR_TRAP0 << i))))
486 * The counter may be concurrently released but that can only
487 * occur from a call_rcu() path. We can then safely fetch
488 * the breakpoint, use its callback, touch its counter
489 * while we are in an rcu_read_lock() path.
493 bp = per_cpu(bp_per_reg[i], cpu);
495 * Reset the 'i'th TRAP bit in dr6 to denote completion of
498 (*dr6_p) &= ~(DR_TRAP0 << i);
500 * bp can be NULL due to lazy debug register switching
501 * or due to concurrent perf counter removing.
508 perf_bp_event(bp, args->regs);
511 * Set up resume flag to avoid breakpoint recursion when
512 * returning back to origin.
514 if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
515 args->regs->flags |= X86_EFLAGS_RF;
520 * Further processing in do_debug() is needed for a) user-space
521 * breakpoints (to generate signals) and b) when the system has
522 * taken exception due to multiple causes
524 if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
525 (dr6 & (~DR_TRAP_BITS)))
528 set_debugreg(dr7, 7);
535 * Handle debug exception notifications.
537 int hw_breakpoint_exceptions_notify(
538 struct notifier_block *unused, unsigned long val, void *data)
540 if (val != DIE_DEBUG)
543 return hw_breakpoint_handler(data);
546 void hw_breakpoint_pmu_read(struct perf_event *bp)