1 // SPDX-License-Identifier: GPL-2.0
3 * FPU register's regset abstraction, for ptrace, core dumps, etc.
5 #include <asm/fpu/internal.h>
6 #include <asm/fpu/signal.h>
7 #include <asm/fpu/regset.h>
8 #include <asm/fpu/xstate.h>
9 #include <linux/sched/task_stack.h>
12 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
13 * as the "regset->n" for the xstate regset will be updated based on the feature
14 * capabilities supported by the xsave.
16 int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
21 int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
23 if (boot_cpu_has(X86_FEATURE_FXSR))
29 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
32 struct fpu *fpu = &target->thread.fpu;
34 if (!boot_cpu_has(X86_FEATURE_FXSR))
37 fpu__prepare_read(fpu);
38 fpstate_sanitize_xstate(fpu);
40 return membuf_write(&to, &fpu->state.fxsave, sizeof(struct fxregs_state));
43 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
44 unsigned int pos, unsigned int count,
45 const void *kbuf, const void __user *ubuf)
47 struct fpu *fpu = &target->thread.fpu;
50 if (!boot_cpu_has(X86_FEATURE_FXSR))
53 fpu__prepare_write(fpu);
54 fpstate_sanitize_xstate(fpu);
56 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
57 &fpu->state.fxsave, 0, -1);
60 * mxcsr reserved bits must be masked to zero for security reasons.
62 fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
65 * update the header bits in the xsave header, indicating the
66 * presence of FP and SSE state.
68 if (boot_cpu_has(X86_FEATURE_XSAVE))
69 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
74 int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
77 struct fpu *fpu = &target->thread.fpu;
78 struct xregs_state *xsave;
80 if (!boot_cpu_has(X86_FEATURE_XSAVE))
83 xsave = &fpu->state.xsave;
85 fpu__prepare_read(fpu);
87 if (using_compacted_format()) {
88 copy_xstate_to_kernel(to, xsave);
91 fpstate_sanitize_xstate(fpu);
93 * Copy the 48 bytes defined by the software into the xsave
94 * area in the thread struct, so that we can copy the whole
95 * area to user using one user_regset_copyout().
97 memcpy(&xsave->i387.sw_reserved, xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
100 * Copy the xstate memory layout.
102 return membuf_write(&to, xsave, fpu_user_xstate_size);
106 int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
107 unsigned int pos, unsigned int count,
108 const void *kbuf, const void __user *ubuf)
110 struct fpu *fpu = &target->thread.fpu;
111 struct xregs_state *xsave;
114 if (!boot_cpu_has(X86_FEATURE_XSAVE))
118 * A whole standard-format XSAVE buffer is needed:
120 if ((pos != 0) || (count < fpu_user_xstate_size))
123 xsave = &fpu->state.xsave;
125 fpu__prepare_write(fpu);
127 if (using_compacted_format()) {
129 ret = copy_kernel_to_xstate(xsave, kbuf);
131 ret = copy_user_to_xstate(xsave, ubuf);
133 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
135 ret = validate_user_xstate_header(&xsave->header);
139 * mxcsr reserved bits must be masked to zero for security reasons.
141 xsave->i387.mxcsr &= mxcsr_feature_mask;
144 * In case of failure, mark all states as init:
147 fpstate_init(&fpu->state);
152 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
155 * FPU tag word conversions.
158 static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
160 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
162 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
164 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
165 /* and move the valid bits to the lower byte. */
166 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
167 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
168 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
173 #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
174 #define FP_EXP_TAG_VALID 0
175 #define FP_EXP_TAG_ZERO 1
176 #define FP_EXP_TAG_SPECIAL 2
177 #define FP_EXP_TAG_EMPTY 3
179 static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
182 u32 tos = (fxsave->swd >> 11) & 7;
183 u32 twd = (unsigned long) fxsave->twd;
185 u32 ret = 0xffff0000u;
188 for (i = 0; i < 8; i++, twd >>= 1) {
190 st = FPREG_ADDR(fxsave, (i - tos) & 7);
192 switch (st->exponent & 0x7fff) {
194 tag = FP_EXP_TAG_SPECIAL;
197 if (!st->significand[0] &&
198 !st->significand[1] &&
199 !st->significand[2] &&
201 tag = FP_EXP_TAG_ZERO;
203 tag = FP_EXP_TAG_SPECIAL;
206 if (st->significand[3] & 0x8000)
207 tag = FP_EXP_TAG_VALID;
209 tag = FP_EXP_TAG_SPECIAL;
213 tag = FP_EXP_TAG_EMPTY;
215 ret |= tag << (2 * i);
221 * FXSR floating point environment conversions.
225 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
227 struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
228 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
229 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
232 env->cwd = fxsave->cwd | 0xffff0000u;
233 env->swd = fxsave->swd | 0xffff0000u;
234 env->twd = twd_fxsr_to_i387(fxsave);
237 env->fip = fxsave->rip;
238 env->foo = fxsave->rdp;
240 * should be actually ds/cs at fpu exception time, but
241 * that information is not available in 64bit mode.
243 env->fcs = task_pt_regs(tsk)->cs;
244 if (tsk == current) {
245 savesegment(ds, env->fos);
247 env->fos = tsk->thread.ds;
249 env->fos |= 0xffff0000;
251 env->fip = fxsave->fip;
252 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
253 env->foo = fxsave->foo;
254 env->fos = fxsave->fos;
257 for (i = 0; i < 8; ++i)
258 memcpy(&to[i], &from[i], sizeof(to[0]));
261 void convert_to_fxsr(struct fxregs_state *fxsave,
262 const struct user_i387_ia32_struct *env)
265 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
266 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
269 fxsave->cwd = env->cwd;
270 fxsave->swd = env->swd;
271 fxsave->twd = twd_i387_to_fxsr(env->twd);
272 fxsave->fop = (u16) ((u32) env->fcs >> 16);
274 fxsave->rip = env->fip;
275 fxsave->rdp = env->foo;
276 /* cs and ds ignored */
278 fxsave->fip = env->fip;
279 fxsave->fcs = (env->fcs & 0xffff);
280 fxsave->foo = env->foo;
281 fxsave->fos = env->fos;
284 for (i = 0; i < 8; ++i)
285 memcpy(&to[i], &from[i], sizeof(from[0]));
288 int fpregs_get(struct task_struct *target, const struct user_regset *regset,
291 struct fpu *fpu = &target->thread.fpu;
292 struct user_i387_ia32_struct env;
294 fpu__prepare_read(fpu);
296 if (!boot_cpu_has(X86_FEATURE_FPU))
297 return fpregs_soft_get(target, regset, to);
299 if (!boot_cpu_has(X86_FEATURE_FXSR)) {
300 return membuf_write(&to, &fpu->state.fsave,
301 sizeof(struct fregs_state));
304 fpstate_sanitize_xstate(fpu);
306 if (to.left == sizeof(env)) {
307 convert_from_fxsr(to.p, target);
311 convert_from_fxsr(&env, target);
312 return membuf_write(&to, &env, sizeof(env));
315 int fpregs_set(struct task_struct *target, const struct user_regset *regset,
316 unsigned int pos, unsigned int count,
317 const void *kbuf, const void __user *ubuf)
319 struct fpu *fpu = &target->thread.fpu;
320 struct user_i387_ia32_struct env;
323 fpu__prepare_write(fpu);
324 fpstate_sanitize_xstate(fpu);
326 if (!boot_cpu_has(X86_FEATURE_FPU))
327 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
329 if (!boot_cpu_has(X86_FEATURE_FXSR))
330 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
331 &fpu->state.fsave, 0,
334 if (pos > 0 || count < sizeof(env))
335 convert_from_fxsr(&env, target);
337 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
339 convert_to_fxsr(&target->thread.fpu.state.fxsave, &env);
342 * update the header bit in the xsave header, indicating the
345 if (boot_cpu_has(X86_FEATURE_XSAVE))
346 fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
350 #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */