1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/pgtable.h>
26 #include <asm/stackprotector.h>
27 #include <asm/perf_event.h>
28 #include <asm/mmu_context.h>
29 #include <asm/doublefault.h>
30 #include <asm/archrandom.h>
31 #include <asm/hypervisor.h>
32 #include <asm/processor.h>
33 #include <asm/tlbflush.h>
34 #include <asm/debugreg.h>
35 #include <asm/sections.h>
36 #include <asm/vsyscall.h>
37 #include <linux/topology.h>
38 #include <linux/cpumask.h>
39 #include <linux/atomic.h>
40 #include <asm/proto.h>
41 #include <asm/setup.h>
44 #include <asm/fpu/internal.h>
46 #include <asm/hwcap2.h>
47 #include <linux/numa.h>
53 #include <asm/memtype.h>
54 #include <asm/microcode.h>
55 #include <asm/microcode_intel.h>
56 #include <asm/intel-family.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/uv/uv.h>
62 u32 elf_hwcap2 __read_mostly;
64 /* all of these masks are initialized in setup_cpu_local_masks() */
65 cpumask_var_t cpu_initialized_mask;
66 cpumask_var_t cpu_callout_mask;
67 cpumask_var_t cpu_callin_mask;
69 /* representing cpus for which sibling maps can be computed */
70 cpumask_var_t cpu_sibling_setup_mask;
72 /* Number of siblings per CPU package */
73 int smp_num_siblings = 1;
74 EXPORT_SYMBOL(smp_num_siblings);
76 /* Last level cache ID of each logical CPU */
77 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
79 /* correctly size the local cpu masks */
80 void __init setup_cpu_local_masks(void)
82 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
83 alloc_bootmem_cpumask_var(&cpu_callin_mask);
84 alloc_bootmem_cpumask_var(&cpu_callout_mask);
85 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
88 static void default_init(struct cpuinfo_x86 *c)
91 cpu_detect_cache_sizes(c);
93 /* Not much we can do here... */
94 /* Check if at least it has cpuid */
95 if (c->cpuid_level == -1) {
96 /* No cpuid. It must be an ancient CPU */
98 strcpy(c->x86_model_id, "486");
100 strcpy(c->x86_model_id, "386");
105 static const struct cpu_dev default_cpu = {
106 .c_init = default_init,
107 .c_vendor = "Unknown",
108 .c_x86_vendor = X86_VENDOR_UNKNOWN,
111 static const struct cpu_dev *this_cpu = &default_cpu;
113 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
116 * We need valid kernel segments for data and code in long mode too
117 * IRET will check the segment types kkeil 2000/10/28
118 * Also sysret mandates a special GDT layout
120 * TLS descriptors are currently at a different place compared to i386.
121 * Hopefully nobody expects them at a fixed place (Wine?)
123 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
124 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
126 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
130 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
131 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
132 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
135 * Segments used for calling PnP BIOS have byte granularity.
136 * They code segments and data segments have fixed 64k limits,
137 * the transfer segment sizes are set at run time.
140 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
142 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
144 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
146 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
148 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
150 * The APM segments have byte granularity and their bases
151 * are set at run time. All have 64k limits.
154 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
156 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
158 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
160 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
161 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 GDT_STACK_CANARY_INIT
165 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
168 static int __init x86_nopcid_setup(char *s)
170 /* nopcid doesn't accept parameters */
174 /* do not emit a message if the feature is not present */
175 if (!boot_cpu_has(X86_FEATURE_PCID))
178 setup_clear_cpu_cap(X86_FEATURE_PCID);
179 pr_info("nopcid: PCID feature disabled\n");
182 early_param("nopcid", x86_nopcid_setup);
185 static int __init x86_noinvpcid_setup(char *s)
187 /* noinvpcid doesn't accept parameters */
191 /* do not emit a message if the feature is not present */
192 if (!boot_cpu_has(X86_FEATURE_INVPCID))
195 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
196 pr_info("noinvpcid: INVPCID feature disabled\n");
199 early_param("noinvpcid", x86_noinvpcid_setup);
202 static int cachesize_override = -1;
203 static int disable_x86_serial_nr = 1;
205 static int __init cachesize_setup(char *str)
207 get_option(&str, &cachesize_override);
210 __setup("cachesize=", cachesize_setup);
212 static int __init x86_sep_setup(char *s)
214 setup_clear_cpu_cap(X86_FEATURE_SEP);
217 __setup("nosep", x86_sep_setup);
219 /* Standard macro to see if a specific flag is changeable */
220 static inline int flag_is_changeable_p(u32 flag)
225 * Cyrix and IDT cpus allow disabling of CPUID
226 * so the code below may return different results
227 * when it is executed before and after enabling
228 * the CPUID. Add "volatile" to not allow gcc to
229 * optimize the subsequent calls to this function.
231 asm volatile ("pushfl \n\t"
242 : "=&r" (f1), "=&r" (f2)
245 return ((f1^f2) & flag) != 0;
248 /* Probe for the CPUID instruction */
249 int have_cpuid_p(void)
251 return flag_is_changeable_p(X86_EFLAGS_ID);
254 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
256 unsigned long lo, hi;
258 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
261 /* Disable processor serial number: */
263 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
265 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
267 pr_notice("CPU serial number disabled.\n");
268 clear_cpu_cap(c, X86_FEATURE_PN);
270 /* Disabling the serial number may affect the cpuid level */
271 c->cpuid_level = cpuid_eax(0);
274 static int __init x86_serial_nr_setup(char *s)
276 disable_x86_serial_nr = 0;
279 __setup("serialnumber", x86_serial_nr_setup);
281 static inline int flag_is_changeable_p(u32 flag)
285 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
290 static __init int setup_disable_smep(char *arg)
292 setup_clear_cpu_cap(X86_FEATURE_SMEP);
295 __setup("nosmep", setup_disable_smep);
297 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
299 if (cpu_has(c, X86_FEATURE_SMEP))
300 cr4_set_bits(X86_CR4_SMEP);
303 static __init int setup_disable_smap(char *arg)
305 setup_clear_cpu_cap(X86_FEATURE_SMAP);
308 __setup("nosmap", setup_disable_smap);
310 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
312 unsigned long eflags = native_save_fl();
314 /* This should have been cleared long ago */
315 BUG_ON(eflags & X86_EFLAGS_AC);
317 if (cpu_has(c, X86_FEATURE_SMAP)) {
318 #ifdef CONFIG_X86_SMAP
319 cr4_set_bits(X86_CR4_SMAP);
321 cr4_clear_bits(X86_CR4_SMAP);
326 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
328 /* Check the boot processor, plus build option for UMIP. */
329 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
332 /* Check the current processor's cpuid bits. */
333 if (!cpu_has(c, X86_FEATURE_UMIP))
336 cr4_set_bits(X86_CR4_UMIP);
338 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
344 * Make sure UMIP is disabled in case it was enabled in a
345 * previous boot (e.g., via kexec).
347 cr4_clear_bits(X86_CR4_UMIP);
350 /* These bits should not change their value after CPU init is finished. */
351 static const unsigned long cr4_pinned_mask =
352 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE;
353 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
354 static unsigned long cr4_pinned_bits __ro_after_init;
356 void native_write_cr0(unsigned long val)
358 unsigned long bits_missing = 0;
361 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order));
363 if (static_branch_likely(&cr_pinning)) {
364 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
365 bits_missing = X86_CR0_WP;
369 /* Warn after we've set the missing bits. */
370 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
373 EXPORT_SYMBOL(native_write_cr0);
375 void native_write_cr4(unsigned long val)
377 unsigned long bits_changed = 0;
380 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits));
382 if (static_branch_likely(&cr_pinning)) {
383 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
384 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
385 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
388 /* Warn after we've corrected the changed bits. */
389 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
393 #if IS_MODULE(CONFIG_LKDTM)
394 EXPORT_SYMBOL_GPL(native_write_cr4);
397 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
399 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
401 lockdep_assert_irqs_disabled();
403 newval = (cr4 & ~clear) | set;
405 this_cpu_write(cpu_tlbstate.cr4, newval);
409 EXPORT_SYMBOL(cr4_update_irqsoff);
411 /* Read the CR4 shadow. */
412 unsigned long cr4_read_shadow(void)
414 return this_cpu_read(cpu_tlbstate.cr4);
416 EXPORT_SYMBOL_GPL(cr4_read_shadow);
420 unsigned long cr4 = __read_cr4();
422 if (boot_cpu_has(X86_FEATURE_PCID))
423 cr4 |= X86_CR4_PCIDE;
424 if (static_branch_likely(&cr_pinning))
425 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
429 /* Initialize cr4 shadow for this CPU. */
430 this_cpu_write(cpu_tlbstate.cr4, cr4);
434 * Once CPU feature detection is finished (and boot params have been
435 * parsed), record any of the sensitive CR bits that are set, and
438 static void __init setup_cr_pinning(void)
440 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
441 static_key_enable(&cr_pinning.key);
444 static __init int x86_nofsgsbase_setup(char *arg)
446 /* Require an exact match without trailing characters. */
450 /* Do not emit a message if the feature is not present. */
451 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
454 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
455 pr_info("FSGSBASE disabled via kernel command line\n");
458 __setup("nofsgsbase", x86_nofsgsbase_setup);
461 * Protection Keys are not available in 32-bit mode.
463 static bool pku_disabled;
465 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
467 struct pkru_state *pk;
469 /* check the boot processor, plus compile options for PKU: */
470 if (!cpu_feature_enabled(X86_FEATURE_PKU))
472 /* checks the actual processor's cpuid bits: */
473 if (!cpu_has(c, X86_FEATURE_PKU))
478 cr4_set_bits(X86_CR4_PKE);
479 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU);
481 pk->pkru = init_pkru_value;
483 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
484 * cpuid bit to be set. We need to ensure that we
485 * update that bit in this CPU's "cpu_info".
487 set_cpu_cap(c, X86_FEATURE_OSPKE);
490 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
491 static __init int setup_disable_pku(char *arg)
494 * Do not clear the X86_FEATURE_PKU bit. All of the
495 * runtime checks are against OSPKE so clearing the
498 * This way, we will see "pku" in cpuinfo, but not
499 * "ospke", which is exactly what we want. It shows
500 * that the CPU has PKU, but the OS has not enabled it.
501 * This happens to be exactly how a system would look
502 * if we disabled the config option.
504 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
508 __setup("nopku", setup_disable_pku);
509 #endif /* CONFIG_X86_64 */
512 * Some CPU features depend on higher CPUID levels, which may not always
513 * be available due to CPUID level capping or broken virtualization
514 * software. Add those features to this table to auto-disable them.
516 struct cpuid_dependent_feature {
521 static const struct cpuid_dependent_feature
522 cpuid_dependent_features[] = {
523 { X86_FEATURE_MWAIT, 0x00000005 },
524 { X86_FEATURE_DCA, 0x00000009 },
525 { X86_FEATURE_XSAVE, 0x0000000d },
529 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
531 const struct cpuid_dependent_feature *df;
533 for (df = cpuid_dependent_features; df->feature; df++) {
535 if (!cpu_has(c, df->feature))
538 * Note: cpuid_level is set to -1 if unavailable, but
539 * extended_extended_level is set to 0 if unavailable
540 * and the legitimate extended levels are all negative
541 * when signed; hence the weird messing around with
544 if (!((s32)df->level < 0 ?
545 (u32)df->level > (u32)c->extended_cpuid_level :
546 (s32)df->level > (s32)c->cpuid_level))
549 clear_cpu_cap(c, df->feature);
553 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
554 x86_cap_flag(df->feature), df->level);
559 * Naming convention should be: <Name> [(<Codename>)]
560 * This table only is used unless init_<vendor>() below doesn't set it;
561 * in particular, if CPUID levels 0x80000002..4 are supported, this
565 /* Look up CPU names by table lookup. */
566 static const char *table_lookup_model(struct cpuinfo_x86 *c)
569 const struct legacy_cpu_model_info *info;
571 if (c->x86_model >= 16)
572 return NULL; /* Range check */
577 info = this_cpu->legacy_models;
579 while (info->family) {
580 if (info->family == c->x86)
581 return info->model_names[c->x86_model];
585 return NULL; /* Not found */
588 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
589 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
590 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
592 void load_percpu_segment(int cpu)
595 loadsegment(fs, __KERNEL_PERCPU);
597 __loadsegment_simple(gs, 0);
598 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
600 load_stack_canary_segment();
604 /* The 32-bit entry code needs to find cpu_entry_area. */
605 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
608 /* Load the original GDT from the per-cpu structure */
609 void load_direct_gdt(int cpu)
611 struct desc_ptr gdt_descr;
613 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
614 gdt_descr.size = GDT_SIZE - 1;
615 load_gdt(&gdt_descr);
617 EXPORT_SYMBOL_GPL(load_direct_gdt);
619 /* Load a fixmap remapping of the per-cpu GDT */
620 void load_fixmap_gdt(int cpu)
622 struct desc_ptr gdt_descr;
624 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
625 gdt_descr.size = GDT_SIZE - 1;
626 load_gdt(&gdt_descr);
628 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
631 * Current gdt points %fs at the "master" per-cpu area: after this,
632 * it's on the real one.
634 void switch_to_new_gdt(int cpu)
636 /* Load the original GDT */
637 load_direct_gdt(cpu);
638 /* Reload the per-cpu base */
639 load_percpu_segment(cpu);
642 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
644 static void get_model_name(struct cpuinfo_x86 *c)
649 if (c->extended_cpuid_level < 0x80000004)
652 v = (unsigned int *)c->x86_model_id;
653 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
654 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
655 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
656 c->x86_model_id[48] = 0;
658 /* Trim whitespace */
659 p = q = s = &c->x86_model_id[0];
665 /* Note the last non-whitespace index */
675 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
677 unsigned int eax, ebx, ecx, edx;
679 c->x86_max_cores = 1;
680 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
683 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
685 c->x86_max_cores = (eax >> 26) + 1;
688 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
690 unsigned int n, dummy, ebx, ecx, edx, l2size;
692 n = c->extended_cpuid_level;
694 if (n >= 0x80000005) {
695 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
696 c->x86_cache_size = (ecx>>24) + (edx>>24);
698 /* On K8 L1 TLB is inclusive, so don't count it */
703 if (n < 0x80000006) /* Some chips just has a large L1. */
706 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
710 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
712 /* do processor-specific cache resizing */
713 if (this_cpu->legacy_cache_size)
714 l2size = this_cpu->legacy_cache_size(c, l2size);
716 /* Allow user to override all this if necessary. */
717 if (cachesize_override != -1)
718 l2size = cachesize_override;
721 return; /* Again, no L2 cache is possible */
724 c->x86_cache_size = l2size;
727 u16 __read_mostly tlb_lli_4k[NR_INFO];
728 u16 __read_mostly tlb_lli_2m[NR_INFO];
729 u16 __read_mostly tlb_lli_4m[NR_INFO];
730 u16 __read_mostly tlb_lld_4k[NR_INFO];
731 u16 __read_mostly tlb_lld_2m[NR_INFO];
732 u16 __read_mostly tlb_lld_4m[NR_INFO];
733 u16 __read_mostly tlb_lld_1g[NR_INFO];
735 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
737 if (this_cpu->c_detect_tlb)
738 this_cpu->c_detect_tlb(c);
740 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
741 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
742 tlb_lli_4m[ENTRIES]);
744 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
745 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
746 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
749 int detect_ht_early(struct cpuinfo_x86 *c)
752 u32 eax, ebx, ecx, edx;
754 if (!cpu_has(c, X86_FEATURE_HT))
757 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
760 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
763 cpuid(1, &eax, &ebx, &ecx, &edx);
765 smp_num_siblings = (ebx & 0xff0000) >> 16;
766 if (smp_num_siblings == 1)
767 pr_info_once("CPU0: Hyper-Threading is disabled\n");
772 void detect_ht(struct cpuinfo_x86 *c)
775 int index_msb, core_bits;
777 if (detect_ht_early(c) < 0)
780 index_msb = get_count_order(smp_num_siblings);
781 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
783 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
785 index_msb = get_count_order(smp_num_siblings);
787 core_bits = get_count_order(c->x86_max_cores);
789 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
790 ((1 << core_bits) - 1);
794 static void get_cpu_vendor(struct cpuinfo_x86 *c)
796 char *v = c->x86_vendor_id;
799 for (i = 0; i < X86_VENDOR_NUM; i++) {
803 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
804 (cpu_devs[i]->c_ident[1] &&
805 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
807 this_cpu = cpu_devs[i];
808 c->x86_vendor = this_cpu->c_x86_vendor;
813 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
814 "CPU: Your system may be unstable.\n", v);
816 c->x86_vendor = X86_VENDOR_UNKNOWN;
817 this_cpu = &default_cpu;
820 void cpu_detect(struct cpuinfo_x86 *c)
822 /* Get vendor name */
823 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
824 (unsigned int *)&c->x86_vendor_id[0],
825 (unsigned int *)&c->x86_vendor_id[8],
826 (unsigned int *)&c->x86_vendor_id[4]);
829 /* Intel-defined flags: level 0x00000001 */
830 if (c->cpuid_level >= 0x00000001) {
831 u32 junk, tfms, cap0, misc;
833 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
834 c->x86 = x86_family(tfms);
835 c->x86_model = x86_model(tfms);
836 c->x86_stepping = x86_stepping(tfms);
838 if (cap0 & (1<<19)) {
839 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
840 c->x86_cache_alignment = c->x86_clflush_size;
845 static void apply_forced_caps(struct cpuinfo_x86 *c)
849 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
850 c->x86_capability[i] &= ~cpu_caps_cleared[i];
851 c->x86_capability[i] |= cpu_caps_set[i];
855 static void init_speculation_control(struct cpuinfo_x86 *c)
858 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
859 * and they also have a different bit for STIBP support. Also,
860 * a hypervisor might have set the individual AMD bits even on
861 * Intel CPUs, for finer-grained selection of what's available.
863 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
864 set_cpu_cap(c, X86_FEATURE_IBRS);
865 set_cpu_cap(c, X86_FEATURE_IBPB);
866 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
869 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
870 set_cpu_cap(c, X86_FEATURE_STIBP);
872 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
873 cpu_has(c, X86_FEATURE_VIRT_SSBD))
874 set_cpu_cap(c, X86_FEATURE_SSBD);
876 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
877 set_cpu_cap(c, X86_FEATURE_IBRS);
878 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
881 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
882 set_cpu_cap(c, X86_FEATURE_IBPB);
884 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
885 set_cpu_cap(c, X86_FEATURE_STIBP);
886 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
889 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
890 set_cpu_cap(c, X86_FEATURE_SSBD);
891 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
892 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
896 void get_cpu_cap(struct cpuinfo_x86 *c)
898 u32 eax, ebx, ecx, edx;
900 /* Intel-defined flags: level 0x00000001 */
901 if (c->cpuid_level >= 0x00000001) {
902 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
904 c->x86_capability[CPUID_1_ECX] = ecx;
905 c->x86_capability[CPUID_1_EDX] = edx;
908 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
909 if (c->cpuid_level >= 0x00000006)
910 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
912 /* Additional Intel-defined flags: level 0x00000007 */
913 if (c->cpuid_level >= 0x00000007) {
914 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
915 c->x86_capability[CPUID_7_0_EBX] = ebx;
916 c->x86_capability[CPUID_7_ECX] = ecx;
917 c->x86_capability[CPUID_7_EDX] = edx;
919 /* Check valid sub-leaf index before accessing it */
921 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
922 c->x86_capability[CPUID_7_1_EAX] = eax;
926 /* Extended state features: level 0x0000000d */
927 if (c->cpuid_level >= 0x0000000d) {
928 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
930 c->x86_capability[CPUID_D_1_EAX] = eax;
933 /* AMD-defined flags: level 0x80000001 */
934 eax = cpuid_eax(0x80000000);
935 c->extended_cpuid_level = eax;
937 if ((eax & 0xffff0000) == 0x80000000) {
938 if (eax >= 0x80000001) {
939 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
941 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
942 c->x86_capability[CPUID_8000_0001_EDX] = edx;
946 if (c->extended_cpuid_level >= 0x80000007) {
947 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
949 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
953 if (c->extended_cpuid_level >= 0x80000008) {
954 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
955 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
958 if (c->extended_cpuid_level >= 0x8000000a)
959 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
961 init_scattered_cpuid_features(c);
962 init_speculation_control(c);
965 * Clear/Set all flags overridden by options, after probe.
966 * This needs to happen each time we re-probe, which may happen
967 * several times during CPU initialization.
969 apply_forced_caps(c);
972 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
974 u32 eax, ebx, ecx, edx;
976 if (c->extended_cpuid_level >= 0x80000008) {
977 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
979 c->x86_virt_bits = (eax >> 8) & 0xff;
980 c->x86_phys_bits = eax & 0xff;
983 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
984 c->x86_phys_bits = 36;
986 c->x86_cache_bits = c->x86_phys_bits;
989 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
995 * First of all, decide if this is a 486 or higher
996 * It's a 486 if we can modify the AC flag
998 if (flag_is_changeable_p(X86_EFLAGS_AC))
1003 for (i = 0; i < X86_VENDOR_NUM; i++)
1004 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1005 c->x86_vendor_id[0] = 0;
1006 cpu_devs[i]->c_identify(c);
1007 if (c->x86_vendor_id[0]) {
1015 #define NO_SPECULATION BIT(0)
1016 #define NO_MELTDOWN BIT(1)
1017 #define NO_SSB BIT(2)
1018 #define NO_L1TF BIT(3)
1019 #define NO_MDS BIT(4)
1020 #define MSBDS_ONLY BIT(5)
1021 #define NO_SWAPGS BIT(6)
1022 #define NO_ITLB_MULTIHIT BIT(7)
1023 #define NO_SPECTRE_V2 BIT(8)
1025 #define VULNWL(vendor, family, model, whitelist) \
1026 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1028 #define VULNWL_INTEL(model, whitelist) \
1029 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1031 #define VULNWL_AMD(family, whitelist) \
1032 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1034 #define VULNWL_HYGON(family, whitelist) \
1035 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1037 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1038 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1039 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1040 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1041 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1043 /* Intel Family 6 */
1044 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1045 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1046 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1047 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1048 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1050 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1051 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1052 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1053 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1054 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1055 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1057 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1059 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1060 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1062 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1063 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1064 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1067 * Technically, swapgs isn't serializing on AMD (despite it previously
1068 * being documented as such in the APM). But according to AMD, %gs is
1069 * updated non-speculatively, and the issuing of %gs-relative memory
1070 * operands will be blocked until the %gs update completes, which is
1071 * good enough for our purposes.
1074 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT),
1076 /* AMD Family 0xf - 0x12 */
1077 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1078 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1079 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1080 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1082 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1083 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1084 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1086 /* Zhaoxin Family 7 */
1087 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1088 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1092 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1093 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1094 INTEL_FAM6_##model, steppings, \
1095 X86_FEATURE_ANY, issues)
1097 #define SRBDS BIT(0)
1099 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1100 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1101 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1102 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1103 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1104 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1105 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1106 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS),
1107 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS),
1108 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS),
1109 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS),
1113 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1115 const struct x86_cpu_id *m = x86_match_cpu(table);
1117 return m && !!(m->driver_data & which);
1120 u64 x86_read_arch_cap_msr(void)
1124 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1125 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1130 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1132 u64 ia32_cap = x86_read_arch_cap_msr();
1134 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1135 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1136 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1137 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1139 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1142 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1144 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1145 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1147 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1148 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1149 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1150 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1152 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1153 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1155 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1156 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1157 setup_force_cpu_bug(X86_BUG_MDS);
1158 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1159 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1162 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1163 setup_force_cpu_bug(X86_BUG_SWAPGS);
1166 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1167 * - TSX is supported or
1168 * - TSX_CTRL is present
1170 * TSX_CTRL check is needed for cases when TSX could be disabled before
1171 * the kernel boot e.g. kexec.
1172 * TSX_CTRL check alone is not sufficient for cases when the microcode
1173 * update is not present or running as guest that don't get TSX_CTRL.
1175 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1176 (cpu_has(c, X86_FEATURE_RTM) ||
1177 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1178 setup_force_cpu_bug(X86_BUG_TAA);
1181 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1182 * in the vulnerability blacklist.
1184 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1185 cpu_has(c, X86_FEATURE_RDSEED)) &&
1186 cpu_matches(cpu_vuln_blacklist, SRBDS))
1187 setup_force_cpu_bug(X86_BUG_SRBDS);
1189 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1192 /* Rogue Data Cache Load? No! */
1193 if (ia32_cap & ARCH_CAP_RDCL_NO)
1196 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1198 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1201 setup_force_cpu_bug(X86_BUG_L1TF);
1205 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1206 * unfortunately, that's not true in practice because of early VIA
1207 * chips and (more importantly) broken virtualizers that are not easy
1208 * to detect. In the latter case it doesn't even *fail* reliably, so
1209 * probing for it doesn't even work. Disable it completely on 32-bit
1210 * unless we can find a reliable way to detect all the broken cases.
1211 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1213 static void detect_nopl(void)
1215 #ifdef CONFIG_X86_32
1216 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1218 setup_force_cpu_cap(X86_FEATURE_NOPL);
1223 * Do minimum CPU detection early.
1224 * Fields really needed: vendor, cpuid_level, family, model, mask,
1226 * The others are not touched to avoid unwanted side effects.
1228 * WARNING: this function is only called on the boot CPU. Don't add code
1229 * here that is supposed to run on all CPUs.
1231 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1233 #ifdef CONFIG_X86_64
1234 c->x86_clflush_size = 64;
1235 c->x86_phys_bits = 36;
1236 c->x86_virt_bits = 48;
1238 c->x86_clflush_size = 32;
1239 c->x86_phys_bits = 32;
1240 c->x86_virt_bits = 32;
1242 c->x86_cache_alignment = c->x86_clflush_size;
1244 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1245 c->extended_cpuid_level = 0;
1247 if (!have_cpuid_p())
1248 identify_cpu_without_cpuid(c);
1250 /* cyrix could have cpuid enabled via c_identify()*/
1251 if (have_cpuid_p()) {
1255 get_cpu_address_sizes(c);
1256 setup_force_cpu_cap(X86_FEATURE_CPUID);
1258 if (this_cpu->c_early_init)
1259 this_cpu->c_early_init(c);
1262 filter_cpuid_features(c, false);
1264 if (this_cpu->c_bsp_init)
1265 this_cpu->c_bsp_init(c);
1267 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1270 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1272 cpu_set_bug_bits(c);
1274 cpu_set_core_cap_bits(c);
1276 fpu__init_system(c);
1278 #ifdef CONFIG_X86_32
1280 * Regardless of whether PCID is enumerated, the SDM says
1281 * that it can't be enabled in 32-bit mode.
1283 setup_clear_cpu_cap(X86_FEATURE_PCID);
1287 * Later in the boot process pgtable_l5_enabled() relies on
1288 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1289 * enabled by this point we need to clear the feature bit to avoid
1290 * false-positives at the later stage.
1292 * pgtable_l5_enabled() can be false here for several reasons:
1293 * - 5-level paging is disabled compile-time;
1294 * - it's 32-bit kernel;
1295 * - machine doesn't support 5-level paging;
1296 * - user specified 'no5lvl' in kernel command line.
1298 if (!pgtable_l5_enabled())
1299 setup_clear_cpu_cap(X86_FEATURE_LA57);
1304 void __init early_cpu_init(void)
1306 const struct cpu_dev *const *cdev;
1309 #ifdef CONFIG_PROCESSOR_SELECT
1310 pr_info("KERNEL supported cpus:\n");
1313 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1314 const struct cpu_dev *cpudev = *cdev;
1316 if (count >= X86_VENDOR_NUM)
1318 cpu_devs[count] = cpudev;
1321 #ifdef CONFIG_PROCESSOR_SELECT
1325 for (j = 0; j < 2; j++) {
1326 if (!cpudev->c_ident[j])
1328 pr_info(" %s %s\n", cpudev->c_vendor,
1329 cpudev->c_ident[j]);
1334 early_identify_cpu(&boot_cpu_data);
1337 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1339 #ifdef CONFIG_X86_64
1341 * Empirically, writing zero to a segment selector on AMD does
1342 * not clear the base, whereas writing zero to a segment
1343 * selector on Intel does clear the base. Intel's behavior
1344 * allows slightly faster context switches in the common case
1345 * where GS is unused by the prev and next threads.
1347 * Since neither vendor documents this anywhere that I can see,
1348 * detect it directly instead of hardcoding the choice by
1351 * I've designated AMD's behavior as the "bug" because it's
1352 * counterintuitive and less friendly.
1355 unsigned long old_base, tmp;
1356 rdmsrl(MSR_FS_BASE, old_base);
1357 wrmsrl(MSR_FS_BASE, 1);
1359 rdmsrl(MSR_FS_BASE, tmp);
1361 set_cpu_bug(c, X86_BUG_NULL_SEG);
1362 wrmsrl(MSR_FS_BASE, old_base);
1366 static void generic_identify(struct cpuinfo_x86 *c)
1368 c->extended_cpuid_level = 0;
1370 if (!have_cpuid_p())
1371 identify_cpu_without_cpuid(c);
1373 /* cyrix could have cpuid enabled via c_identify()*/
1374 if (!have_cpuid_p())
1383 get_cpu_address_sizes(c);
1385 if (c->cpuid_level >= 0x00000001) {
1386 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1387 #ifdef CONFIG_X86_32
1389 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1391 c->apicid = c->initial_apicid;
1394 c->phys_proc_id = c->initial_apicid;
1397 get_model_name(c); /* Default name */
1399 detect_null_seg_behavior(c);
1402 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1403 * systems that run Linux at CPL > 0 may or may not have the
1404 * issue, but, even if they have the issue, there's absolutely
1405 * nothing we can do about it because we can't use the real IRET
1408 * NB: For the time being, only 32-bit kernels support
1409 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1410 * whether to apply espfix using paravirt hooks. If any
1411 * non-paravirt system ever shows up that does *not* have the
1412 * ESPFIX issue, we can change this.
1414 #ifdef CONFIG_X86_32
1415 # ifdef CONFIG_PARAVIRT_XXL
1417 extern void native_iret(void);
1418 if (pv_ops.cpu.iret == native_iret)
1419 set_cpu_bug(c, X86_BUG_ESPFIX);
1422 set_cpu_bug(c, X86_BUG_ESPFIX);
1428 * Validate that ACPI/mptables have the same information about the
1429 * effective APIC id and update the package map.
1431 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1434 unsigned int apicid, cpu = smp_processor_id();
1436 apicid = apic->cpu_present_to_apicid(cpu);
1438 if (apicid != c->apicid) {
1439 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1440 cpu, apicid, c->initial_apicid);
1442 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1443 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1445 c->logical_proc_id = 0;
1450 * This does the hard work of actually picking apart the CPU stuff...
1452 static void identify_cpu(struct cpuinfo_x86 *c)
1456 c->loops_per_jiffy = loops_per_jiffy;
1457 c->x86_cache_size = 0;
1458 c->x86_vendor = X86_VENDOR_UNKNOWN;
1459 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1460 c->x86_vendor_id[0] = '\0'; /* Unset */
1461 c->x86_model_id[0] = '\0'; /* Unset */
1462 c->x86_max_cores = 1;
1463 c->x86_coreid_bits = 0;
1465 #ifdef CONFIG_X86_64
1466 c->x86_clflush_size = 64;
1467 c->x86_phys_bits = 36;
1468 c->x86_virt_bits = 48;
1470 c->cpuid_level = -1; /* CPUID not detected */
1471 c->x86_clflush_size = 32;
1472 c->x86_phys_bits = 32;
1473 c->x86_virt_bits = 32;
1475 c->x86_cache_alignment = c->x86_clflush_size;
1476 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1477 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1478 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1481 generic_identify(c);
1483 if (this_cpu->c_identify)
1484 this_cpu->c_identify(c);
1486 /* Clear/Set all flags overridden by options, after probe */
1487 apply_forced_caps(c);
1489 #ifdef CONFIG_X86_64
1490 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1494 * Vendor-specific initialization. In this section we
1495 * canonicalize the feature flags, meaning if there are
1496 * features a certain CPU supports which CPUID doesn't
1497 * tell us, CPUID claiming incorrect flags, or other bugs,
1498 * we handle them here.
1500 * At the end of this section, c->x86_capability better
1501 * indicate the features this CPU genuinely supports!
1503 if (this_cpu->c_init)
1504 this_cpu->c_init(c);
1506 /* Disable the PN if appropriate */
1507 squash_the_stupid_serial_number(c);
1509 /* Set up SMEP/SMAP/UMIP */
1514 /* Enable FSGSBASE instructions if available. */
1515 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1516 cr4_set_bits(X86_CR4_FSGSBASE);
1517 elf_hwcap2 |= HWCAP2_FSGSBASE;
1521 * The vendor-specific functions might have changed features.
1522 * Now we do "generic changes."
1525 /* Filter out anything that depends on CPUID levels we don't have */
1526 filter_cpuid_features(c, true);
1528 /* If the model name is still unset, do table lookup. */
1529 if (!c->x86_model_id[0]) {
1531 p = table_lookup_model(c);
1533 strcpy(c->x86_model_id, p);
1535 /* Last resort... */
1536 sprintf(c->x86_model_id, "%02x/%02x",
1537 c->x86, c->x86_model);
1540 #ifdef CONFIG_X86_64
1548 * Clear/Set all flags overridden by options, need do it
1549 * before following smp all cpus cap AND.
1551 apply_forced_caps(c);
1554 * On SMP, boot_cpu_data holds the common feature set between
1555 * all CPUs; so make sure that we indicate which features are
1556 * common between the CPUs. The first time this routine gets
1557 * executed, c == &boot_cpu_data.
1559 if (c != &boot_cpu_data) {
1560 /* AND the already accumulated flags with these */
1561 for (i = 0; i < NCAPINTS; i++)
1562 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1564 /* OR, i.e. replicate the bug flags */
1565 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1566 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1569 /* Init Machine Check Exception if available. */
1572 select_idle_routine(c);
1575 numa_add_cpu(smp_processor_id());
1580 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1581 * on 32-bit kernels:
1583 #ifdef CONFIG_X86_32
1584 void enable_sep_cpu(void)
1586 struct tss_struct *tss;
1589 if (!boot_cpu_has(X86_FEATURE_SEP))
1593 tss = &per_cpu(cpu_tss_rw, cpu);
1596 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1597 * see the big comment in struct x86_hw_tss's definition.
1600 tss->x86_tss.ss1 = __KERNEL_CS;
1601 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1602 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1603 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1609 void __init identify_boot_cpu(void)
1611 identify_cpu(&boot_cpu_data);
1612 #ifdef CONFIG_X86_32
1616 cpu_detect_tlb(&boot_cpu_data);
1622 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1624 BUG_ON(c == &boot_cpu_data);
1626 #ifdef CONFIG_X86_32
1630 validate_apic_and_package_id(c);
1631 x86_spec_ctrl_setup_ap();
1635 static __init int setup_noclflush(char *arg)
1637 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1638 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1641 __setup("noclflush", setup_noclflush);
1643 void print_cpu_info(struct cpuinfo_x86 *c)
1645 const char *vendor = NULL;
1647 if (c->x86_vendor < X86_VENDOR_NUM) {
1648 vendor = this_cpu->c_vendor;
1650 if (c->cpuid_level >= 0)
1651 vendor = c->x86_vendor_id;
1654 if (vendor && !strstr(c->x86_model_id, vendor))
1655 pr_cont("%s ", vendor);
1657 if (c->x86_model_id[0])
1658 pr_cont("%s", c->x86_model_id);
1660 pr_cont("%d86", c->x86);
1662 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1664 if (c->x86_stepping || c->cpuid_level >= 0)
1665 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1671 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1672 * But we need to keep a dummy __setup around otherwise it would
1673 * show up as an environment variable for init.
1675 static __init int setup_clearcpuid(char *arg)
1679 __setup("clearcpuid=", setup_clearcpuid);
1681 #ifdef CONFIG_X86_64
1682 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1683 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1684 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1687 * The following percpu variables are hot. Align current_task to
1688 * cacheline size such that they fall in the same cacheline.
1690 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1692 EXPORT_PER_CPU_SYMBOL(current_task);
1694 DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
1695 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1697 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1698 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1700 /* May not be marked __init: used by software suspend */
1701 void syscall_init(void)
1703 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1704 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1706 #ifdef CONFIG_IA32_EMULATION
1707 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1709 * This only works on Intel CPUs.
1710 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1711 * This does not cause SYSENTER to jump to the wrong location, because
1712 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1714 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1715 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1716 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1717 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1719 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1720 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1721 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1722 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1725 /* Flags to clear on syscall */
1726 wrmsrl(MSR_SYSCALL_MASK,
1727 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1728 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1731 #else /* CONFIG_X86_64 */
1733 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1734 EXPORT_PER_CPU_SYMBOL(current_task);
1735 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1736 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1739 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1740 * the top of the kernel stack. Use an extra percpu variable to track the
1741 * top of the kernel stack directly.
1743 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1744 (unsigned long)&init_thread_union + THREAD_SIZE;
1745 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1747 #ifdef CONFIG_STACKPROTECTOR
1748 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1751 #endif /* CONFIG_X86_64 */
1754 * Clear all 6 debug registers:
1756 static void clear_all_debug_regs(void)
1760 for (i = 0; i < 8; i++) {
1761 /* Ignore db4, db5 */
1762 if ((i == 4) || (i == 5))
1771 * Restore debug regs if using kgdbwait and you have a kernel debugger
1772 * connection established.
1774 static void dbg_restore_debug_regs(void)
1776 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1777 arch_kgdb_ops.correct_hw_break();
1779 #else /* ! CONFIG_KGDB */
1780 #define dbg_restore_debug_regs()
1781 #endif /* ! CONFIG_KGDB */
1783 static void wait_for_master_cpu(int cpu)
1787 * wait for ACK from master CPU before continuing
1788 * with AP initialization
1790 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1791 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1796 #ifdef CONFIG_X86_64
1797 static inline void setup_getcpu(int cpu)
1799 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1800 struct desc_struct d = { };
1802 if (boot_cpu_has(X86_FEATURE_RDTSCP))
1803 write_rdtscp_aux(cpudata);
1805 /* Store CPU and node number in limit. */
1807 d.limit1 = cpudata >> 16;
1809 d.type = 5; /* RO data, expand down, accessed */
1810 d.dpl = 3; /* Visible to user code */
1811 d.s = 1; /* Not a system segment */
1812 d.p = 1; /* Present */
1813 d.d = 1; /* 32-bit */
1815 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1818 static inline void ucode_cpu_init(int cpu)
1824 static inline void tss_setup_ist(struct tss_struct *tss)
1826 /* Set up the per-CPU TSS IST stacks */
1827 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
1828 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
1829 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
1830 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
1833 #else /* CONFIG_X86_64 */
1835 static inline void setup_getcpu(int cpu) { }
1837 static inline void ucode_cpu_init(int cpu)
1839 show_ucode_info_early();
1842 static inline void tss_setup_ist(struct tss_struct *tss) { }
1844 #endif /* !CONFIG_X86_64 */
1846 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
1848 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
1850 #ifdef CONFIG_X86_IOPL_IOPERM
1851 tss->io_bitmap.prev_max = 0;
1852 tss->io_bitmap.prev_sequence = 0;
1853 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
1855 * Invalidate the extra array entry past the end of the all
1856 * permission bitmap as required by the hardware.
1858 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
1863 * cpu_init() initializes state that is per-CPU. Some data is already
1864 * initialized (naturally) in the bootstrap process, such as the GDT
1865 * and IDT. We reload them nevertheless, this function acts as a
1866 * 'CPU state barrier', nothing should get across.
1870 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1871 struct task_struct *cur = current;
1872 int cpu = raw_smp_processor_id();
1874 wait_for_master_cpu(cpu);
1876 ucode_cpu_init(cpu);
1879 if (this_cpu_read(numa_node) == 0 &&
1880 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1881 set_numa_node(early_cpu_to_node(cpu));
1885 pr_debug("Initializing CPU#%d\n", cpu);
1887 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
1888 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
1889 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1892 * Initialize the per-CPU GDT with the boot GDT,
1893 * and set up the GDT descriptor:
1895 switch_to_new_gdt(cpu);
1898 if (IS_ENABLED(CONFIG_X86_64)) {
1900 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1903 wrmsrl(MSR_FS_BASE, 0);
1904 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1911 cur->active_mm = &init_mm;
1913 initialize_tlbstate_and_flush();
1914 enter_lazy_tlb(&init_mm, cur);
1916 /* Initialize the TSS. */
1918 tss_setup_io_bitmap(tss);
1919 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1923 * sp0 points to the entry trampoline stack regardless of what task
1926 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1928 load_mm_ldt(&init_mm);
1930 clear_all_debug_regs();
1931 dbg_restore_debug_regs();
1933 doublefault_init_cpu_tss();
1940 load_fixmap_gdt(cpu);
1944 * The microcode loader calls this upon late microcode load to recheck features,
1945 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1948 void microcode_check(void)
1950 struct cpuinfo_x86 info;
1952 perf_check_microcode();
1954 /* Reload CPUID max function as it might've changed. */
1955 info.cpuid_level = cpuid_eax(0);
1958 * Copy all capability leafs to pick up the synthetic ones so that
1959 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1960 * get overwritten in get_cpu_cap().
1962 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1966 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1969 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1970 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1974 * Invoked from core CPU hotplug code after hotplug operations
1976 void arch_smt_update(void)
1978 /* Handle the speculative execution misfeatures */
1979 cpu_bugs_smt_update();
1980 /* Check whether IPI broadcasting can be enabled */