1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/smp.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/pgtable.h>
26 #include <asm/cmdline.h>
27 #include <asm/stackprotector.h>
28 #include <asm/perf_event.h>
29 #include <asm/mmu_context.h>
30 #include <asm/doublefault.h>
31 #include <asm/archrandom.h>
32 #include <asm/hypervisor.h>
33 #include <asm/processor.h>
34 #include <asm/tlbflush.h>
35 #include <asm/debugreg.h>
36 #include <asm/sections.h>
37 #include <asm/vsyscall.h>
38 #include <linux/topology.h>
39 #include <linux/cpumask.h>
40 #include <linux/atomic.h>
41 #include <asm/proto.h>
42 #include <asm/setup.h>
45 #include <asm/fpu/api.h>
47 #include <asm/hwcap2.h>
48 #include <linux/numa.h>
55 #include <asm/memtype.h>
56 #include <asm/microcode.h>
57 #include <asm/microcode_intel.h>
58 #include <asm/intel-family.h>
59 #include <asm/cpu_device_id.h>
60 #include <asm/uv/uv.h>
61 #include <asm/sigframe.h>
62 #include <asm/traps.h>
66 u32 elf_hwcap2 __read_mostly;
68 /* all of these masks are initialized in setup_cpu_local_masks() */
69 cpumask_var_t cpu_initialized_mask;
70 cpumask_var_t cpu_callout_mask;
71 cpumask_var_t cpu_callin_mask;
73 /* representing cpus for which sibling maps can be computed */
74 cpumask_var_t cpu_sibling_setup_mask;
76 /* Number of siblings per CPU package */
77 int smp_num_siblings = 1;
78 EXPORT_SYMBOL(smp_num_siblings);
80 /* Last level cache ID of each logical CPU */
81 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
83 u16 get_llc_id(unsigned int cpu)
85 return per_cpu(cpu_llc_id, cpu);
87 EXPORT_SYMBOL_GPL(get_llc_id);
89 /* L2 cache ID of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID;
92 static struct ppin_info {
97 [X86_VENDOR_INTEL] = {
98 .feature = X86_FEATURE_INTEL_PPIN,
99 .msr_ppin_ctl = MSR_PPIN_CTL,
103 .feature = X86_FEATURE_AMD_PPIN,
104 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
105 .msr_ppin = MSR_AMD_PPIN
109 static const struct x86_cpu_id ppin_cpuids[] = {
110 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
111 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
113 /* Legacy models without CPUID enumeration */
114 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
115 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
116 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
117 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
118 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
119 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
120 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
121 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
122 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
123 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
128 static void ppin_init(struct cpuinfo_x86 *c)
130 const struct x86_cpu_id *id;
131 unsigned long long val;
132 struct ppin_info *info;
134 id = x86_match_cpu(ppin_cpuids);
139 * Testing the presence of the MSR is not enough. Need to check
140 * that the PPIN_CTL allows reading of the PPIN.
142 info = (struct ppin_info *)id->driver_data;
144 if (rdmsrl_safe(info->msr_ppin_ctl, &val))
147 if ((val & 3UL) == 1UL) {
148 /* PPIN locked in disabled mode */
152 /* If PPIN is disabled, try to enable */
154 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL);
155 rdmsrl_safe(info->msr_ppin_ctl, &val);
158 /* Is the enable bit set? */
160 c->ppin = __rdmsr(info->msr_ppin);
161 set_cpu_cap(c, info->feature);
166 clear_cpu_cap(c, info->feature);
169 /* correctly size the local cpu masks */
170 void __init setup_cpu_local_masks(void)
172 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
173 alloc_bootmem_cpumask_var(&cpu_callin_mask);
174 alloc_bootmem_cpumask_var(&cpu_callout_mask);
175 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
178 static void default_init(struct cpuinfo_x86 *c)
181 cpu_detect_cache_sizes(c);
183 /* Not much we can do here... */
184 /* Check if at least it has cpuid */
185 if (c->cpuid_level == -1) {
186 /* No cpuid. It must be an ancient CPU */
188 strcpy(c->x86_model_id, "486");
189 else if (c->x86 == 3)
190 strcpy(c->x86_model_id, "386");
195 static const struct cpu_dev default_cpu = {
196 .c_init = default_init,
197 .c_vendor = "Unknown",
198 .c_x86_vendor = X86_VENDOR_UNKNOWN,
201 static const struct cpu_dev *this_cpu = &default_cpu;
203 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
206 * We need valid kernel segments for data and code in long mode too
207 * IRET will check the segment types kkeil 2000/10/28
208 * Also sysret mandates a special GDT layout
210 * TLS descriptors are currently at a different place compared to i386.
211 * Hopefully nobody expects them at a fixed place (Wine?)
213 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
214 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
215 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
216 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
217 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
218 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
220 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
221 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
222 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
223 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
225 * Segments used for calling PnP BIOS have byte granularity.
226 * They code segments and data segments have fixed 64k limits,
227 * the transfer segment sizes are set at run time.
230 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
232 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
234 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
236 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
238 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
240 * The APM segments have byte granularity and their bases
241 * are set at run time. All have 64k limits.
244 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
246 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
248 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
250 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
251 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
254 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
257 static int __init x86_nopcid_setup(char *s)
259 /* nopcid doesn't accept parameters */
263 /* do not emit a message if the feature is not present */
264 if (!boot_cpu_has(X86_FEATURE_PCID))
267 setup_clear_cpu_cap(X86_FEATURE_PCID);
268 pr_info("nopcid: PCID feature disabled\n");
271 early_param("nopcid", x86_nopcid_setup);
274 static int __init x86_noinvpcid_setup(char *s)
276 /* noinvpcid doesn't accept parameters */
280 /* do not emit a message if the feature is not present */
281 if (!boot_cpu_has(X86_FEATURE_INVPCID))
284 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
285 pr_info("noinvpcid: INVPCID feature disabled\n");
288 early_param("noinvpcid", x86_noinvpcid_setup);
291 static int cachesize_override = -1;
292 static int disable_x86_serial_nr = 1;
294 static int __init cachesize_setup(char *str)
296 get_option(&str, &cachesize_override);
299 __setup("cachesize=", cachesize_setup);
301 static int __init x86_sep_setup(char *s)
303 setup_clear_cpu_cap(X86_FEATURE_SEP);
306 __setup("nosep", x86_sep_setup);
308 /* Standard macro to see if a specific flag is changeable */
309 static inline int flag_is_changeable_p(u32 flag)
314 * Cyrix and IDT cpus allow disabling of CPUID
315 * so the code below may return different results
316 * when it is executed before and after enabling
317 * the CPUID. Add "volatile" to not allow gcc to
318 * optimize the subsequent calls to this function.
320 asm volatile ("pushfl \n\t"
331 : "=&r" (f1), "=&r" (f2)
334 return ((f1^f2) & flag) != 0;
337 /* Probe for the CPUID instruction */
338 int have_cpuid_p(void)
340 return flag_is_changeable_p(X86_EFLAGS_ID);
343 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
345 unsigned long lo, hi;
347 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
350 /* Disable processor serial number: */
352 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
354 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
356 pr_notice("CPU serial number disabled.\n");
357 clear_cpu_cap(c, X86_FEATURE_PN);
359 /* Disabling the serial number may affect the cpuid level */
360 c->cpuid_level = cpuid_eax(0);
363 static int __init x86_serial_nr_setup(char *s)
365 disable_x86_serial_nr = 0;
368 __setup("serialnumber", x86_serial_nr_setup);
370 static inline int flag_is_changeable_p(u32 flag)
374 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
379 static __init int setup_disable_smep(char *arg)
381 setup_clear_cpu_cap(X86_FEATURE_SMEP);
384 __setup("nosmep", setup_disable_smep);
386 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
388 if (cpu_has(c, X86_FEATURE_SMEP))
389 cr4_set_bits(X86_CR4_SMEP);
392 static __init int setup_disable_smap(char *arg)
394 setup_clear_cpu_cap(X86_FEATURE_SMAP);
397 __setup("nosmap", setup_disable_smap);
399 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
401 unsigned long eflags = native_save_fl();
403 /* This should have been cleared long ago */
404 BUG_ON(eflags & X86_EFLAGS_AC);
406 if (cpu_has(c, X86_FEATURE_SMAP)) {
407 #ifdef CONFIG_X86_SMAP
408 cr4_set_bits(X86_CR4_SMAP);
410 clear_cpu_cap(c, X86_FEATURE_SMAP);
411 cr4_clear_bits(X86_CR4_SMAP);
416 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
418 /* Check the boot processor, plus build option for UMIP. */
419 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
422 /* Check the current processor's cpuid bits. */
423 if (!cpu_has(c, X86_FEATURE_UMIP))
426 cr4_set_bits(X86_CR4_UMIP);
428 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
434 * Make sure UMIP is disabled in case it was enabled in a
435 * previous boot (e.g., via kexec).
437 cr4_clear_bits(X86_CR4_UMIP);
440 /* These bits should not change their value after CPU init is finished. */
441 static const unsigned long cr4_pinned_mask =
442 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
443 X86_CR4_FSGSBASE | X86_CR4_CET;
444 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
445 static unsigned long cr4_pinned_bits __ro_after_init;
447 void native_write_cr0(unsigned long val)
449 unsigned long bits_missing = 0;
452 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
454 if (static_branch_likely(&cr_pinning)) {
455 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
456 bits_missing = X86_CR0_WP;
460 /* Warn after we've set the missing bits. */
461 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
464 EXPORT_SYMBOL(native_write_cr0);
466 void __no_profile native_write_cr4(unsigned long val)
468 unsigned long bits_changed = 0;
471 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
473 if (static_branch_likely(&cr_pinning)) {
474 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
475 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
476 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
479 /* Warn after we've corrected the changed bits. */
480 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
484 #if IS_MODULE(CONFIG_LKDTM)
485 EXPORT_SYMBOL_GPL(native_write_cr4);
488 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
490 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
492 lockdep_assert_irqs_disabled();
494 newval = (cr4 & ~clear) | set;
496 this_cpu_write(cpu_tlbstate.cr4, newval);
500 EXPORT_SYMBOL(cr4_update_irqsoff);
502 /* Read the CR4 shadow. */
503 unsigned long cr4_read_shadow(void)
505 return this_cpu_read(cpu_tlbstate.cr4);
507 EXPORT_SYMBOL_GPL(cr4_read_shadow);
511 unsigned long cr4 = __read_cr4();
513 if (boot_cpu_has(X86_FEATURE_PCID))
514 cr4 |= X86_CR4_PCIDE;
515 if (static_branch_likely(&cr_pinning))
516 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
520 /* Initialize cr4 shadow for this CPU. */
521 this_cpu_write(cpu_tlbstate.cr4, cr4);
525 * Once CPU feature detection is finished (and boot params have been
526 * parsed), record any of the sensitive CR bits that are set, and
529 static void __init setup_cr_pinning(void)
531 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
532 static_key_enable(&cr_pinning.key);
535 static __init int x86_nofsgsbase_setup(char *arg)
537 /* Require an exact match without trailing characters. */
541 /* Do not emit a message if the feature is not present. */
542 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
545 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
546 pr_info("FSGSBASE disabled via kernel command line\n");
549 __setup("nofsgsbase", x86_nofsgsbase_setup);
552 * Protection Keys are not available in 32-bit mode.
554 static bool pku_disabled;
556 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
558 if (c == &boot_cpu_data) {
559 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
562 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
563 * bit to be set. Enforce it.
565 setup_force_cpu_cap(X86_FEATURE_OSPKE);
567 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
571 cr4_set_bits(X86_CR4_PKE);
572 /* Load the default PKRU value */
573 pkru_write_default();
576 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
577 static __init int setup_disable_pku(char *arg)
580 * Do not clear the X86_FEATURE_PKU bit. All of the
581 * runtime checks are against OSPKE so clearing the
584 * This way, we will see "pku" in cpuinfo, but not
585 * "ospke", which is exactly what we want. It shows
586 * that the CPU has PKU, but the OS has not enabled it.
587 * This happens to be exactly how a system would look
588 * if we disabled the config option.
590 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
594 __setup("nopku", setup_disable_pku);
595 #endif /* CONFIG_X86_64 */
597 #ifdef CONFIG_X86_KERNEL_IBT
599 __noendbr u64 ibt_save(void)
603 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
604 rdmsrl(MSR_IA32_S_CET, msr);
605 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
611 __noendbr void ibt_restore(u64 save)
615 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
616 rdmsrl(MSR_IA32_S_CET, msr);
617 msr &= ~CET_ENDBR_EN;
618 msr |= (save & CET_ENDBR_EN);
619 wrmsrl(MSR_IA32_S_CET, msr);
625 static __always_inline void setup_cet(struct cpuinfo_x86 *c)
627 u64 msr = CET_ENDBR_EN;
629 if (!HAS_KERNEL_IBT ||
630 !cpu_feature_enabled(X86_FEATURE_IBT))
633 wrmsrl(MSR_IA32_S_CET, msr);
634 cr4_set_bits(X86_CR4_CET);
636 if (!ibt_selftest()) {
637 pr_err("IBT selftest: Failed!\n");
638 setup_clear_cpu_cap(X86_FEATURE_IBT);
643 __noendbr void cet_disable(void)
645 if (cpu_feature_enabled(X86_FEATURE_IBT))
646 wrmsrl(MSR_IA32_S_CET, 0);
650 * Some CPU features depend on higher CPUID levels, which may not always
651 * be available due to CPUID level capping or broken virtualization
652 * software. Add those features to this table to auto-disable them.
654 struct cpuid_dependent_feature {
659 static const struct cpuid_dependent_feature
660 cpuid_dependent_features[] = {
661 { X86_FEATURE_MWAIT, 0x00000005 },
662 { X86_FEATURE_DCA, 0x00000009 },
663 { X86_FEATURE_XSAVE, 0x0000000d },
667 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
669 const struct cpuid_dependent_feature *df;
671 for (df = cpuid_dependent_features; df->feature; df++) {
673 if (!cpu_has(c, df->feature))
676 * Note: cpuid_level is set to -1 if unavailable, but
677 * extended_extended_level is set to 0 if unavailable
678 * and the legitimate extended levels are all negative
679 * when signed; hence the weird messing around with
682 if (!((s32)df->level < 0 ?
683 (u32)df->level > (u32)c->extended_cpuid_level :
684 (s32)df->level > (s32)c->cpuid_level))
687 clear_cpu_cap(c, df->feature);
691 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
692 x86_cap_flag(df->feature), df->level);
697 * Naming convention should be: <Name> [(<Codename>)]
698 * This table only is used unless init_<vendor>() below doesn't set it;
699 * in particular, if CPUID levels 0x80000002..4 are supported, this
703 /* Look up CPU names by table lookup. */
704 static const char *table_lookup_model(struct cpuinfo_x86 *c)
707 const struct legacy_cpu_model_info *info;
709 if (c->x86_model >= 16)
710 return NULL; /* Range check */
715 info = this_cpu->legacy_models;
717 while (info->family) {
718 if (info->family == c->x86)
719 return info->model_names[c->x86_model];
723 return NULL; /* Not found */
726 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
727 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
728 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
730 void load_percpu_segment(int cpu)
733 loadsegment(fs, __KERNEL_PERCPU);
735 __loadsegment_simple(gs, 0);
736 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
741 /* The 32-bit entry code needs to find cpu_entry_area. */
742 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
745 /* Load the original GDT from the per-cpu structure */
746 void load_direct_gdt(int cpu)
748 struct desc_ptr gdt_descr;
750 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
751 gdt_descr.size = GDT_SIZE - 1;
752 load_gdt(&gdt_descr);
754 EXPORT_SYMBOL_GPL(load_direct_gdt);
756 /* Load a fixmap remapping of the per-cpu GDT */
757 void load_fixmap_gdt(int cpu)
759 struct desc_ptr gdt_descr;
761 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
762 gdt_descr.size = GDT_SIZE - 1;
763 load_gdt(&gdt_descr);
765 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
768 * Current gdt points %fs at the "master" per-cpu area: after this,
769 * it's on the real one.
771 void switch_to_new_gdt(int cpu)
773 /* Load the original GDT */
774 load_direct_gdt(cpu);
775 /* Reload the per-cpu base */
776 load_percpu_segment(cpu);
779 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
781 static void get_model_name(struct cpuinfo_x86 *c)
786 if (c->extended_cpuid_level < 0x80000004)
789 v = (unsigned int *)c->x86_model_id;
790 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
791 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
792 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
793 c->x86_model_id[48] = 0;
795 /* Trim whitespace */
796 p = q = s = &c->x86_model_id[0];
802 /* Note the last non-whitespace index */
812 void detect_num_cpu_cores(struct cpuinfo_x86 *c)
814 unsigned int eax, ebx, ecx, edx;
816 c->x86_max_cores = 1;
817 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
820 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
822 c->x86_max_cores = (eax >> 26) + 1;
825 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
827 unsigned int n, dummy, ebx, ecx, edx, l2size;
829 n = c->extended_cpuid_level;
831 if (n >= 0x80000005) {
832 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
833 c->x86_cache_size = (ecx>>24) + (edx>>24);
835 /* On K8 L1 TLB is inclusive, so don't count it */
840 if (n < 0x80000006) /* Some chips just has a large L1. */
843 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
847 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
849 /* do processor-specific cache resizing */
850 if (this_cpu->legacy_cache_size)
851 l2size = this_cpu->legacy_cache_size(c, l2size);
853 /* Allow user to override all this if necessary. */
854 if (cachesize_override != -1)
855 l2size = cachesize_override;
858 return; /* Again, no L2 cache is possible */
861 c->x86_cache_size = l2size;
864 u16 __read_mostly tlb_lli_4k[NR_INFO];
865 u16 __read_mostly tlb_lli_2m[NR_INFO];
866 u16 __read_mostly tlb_lli_4m[NR_INFO];
867 u16 __read_mostly tlb_lld_4k[NR_INFO];
868 u16 __read_mostly tlb_lld_2m[NR_INFO];
869 u16 __read_mostly tlb_lld_4m[NR_INFO];
870 u16 __read_mostly tlb_lld_1g[NR_INFO];
872 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
874 if (this_cpu->c_detect_tlb)
875 this_cpu->c_detect_tlb(c);
877 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
878 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
879 tlb_lli_4m[ENTRIES]);
881 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
882 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
883 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
886 int detect_ht_early(struct cpuinfo_x86 *c)
889 u32 eax, ebx, ecx, edx;
891 if (!cpu_has(c, X86_FEATURE_HT))
894 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
897 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
900 cpuid(1, &eax, &ebx, &ecx, &edx);
902 smp_num_siblings = (ebx & 0xff0000) >> 16;
903 if (smp_num_siblings == 1)
904 pr_info_once("CPU0: Hyper-Threading is disabled\n");
909 void detect_ht(struct cpuinfo_x86 *c)
912 int index_msb, core_bits;
914 if (detect_ht_early(c) < 0)
917 index_msb = get_count_order(smp_num_siblings);
918 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
920 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
922 index_msb = get_count_order(smp_num_siblings);
924 core_bits = get_count_order(c->x86_max_cores);
926 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
927 ((1 << core_bits) - 1);
931 static void get_cpu_vendor(struct cpuinfo_x86 *c)
933 char *v = c->x86_vendor_id;
936 for (i = 0; i < X86_VENDOR_NUM; i++) {
940 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
941 (cpu_devs[i]->c_ident[1] &&
942 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
944 this_cpu = cpu_devs[i];
945 c->x86_vendor = this_cpu->c_x86_vendor;
950 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
951 "CPU: Your system may be unstable.\n", v);
953 c->x86_vendor = X86_VENDOR_UNKNOWN;
954 this_cpu = &default_cpu;
957 void cpu_detect(struct cpuinfo_x86 *c)
959 /* Get vendor name */
960 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
961 (unsigned int *)&c->x86_vendor_id[0],
962 (unsigned int *)&c->x86_vendor_id[8],
963 (unsigned int *)&c->x86_vendor_id[4]);
966 /* Intel-defined flags: level 0x00000001 */
967 if (c->cpuid_level >= 0x00000001) {
968 u32 junk, tfms, cap0, misc;
970 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
971 c->x86 = x86_family(tfms);
972 c->x86_model = x86_model(tfms);
973 c->x86_stepping = x86_stepping(tfms);
975 if (cap0 & (1<<19)) {
976 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
977 c->x86_cache_alignment = c->x86_clflush_size;
982 static void apply_forced_caps(struct cpuinfo_x86 *c)
986 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
987 c->x86_capability[i] &= ~cpu_caps_cleared[i];
988 c->x86_capability[i] |= cpu_caps_set[i];
992 static void init_speculation_control(struct cpuinfo_x86 *c)
995 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
996 * and they also have a different bit for STIBP support. Also,
997 * a hypervisor might have set the individual AMD bits even on
998 * Intel CPUs, for finer-grained selection of what's available.
1000 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
1001 set_cpu_cap(c, X86_FEATURE_IBRS);
1002 set_cpu_cap(c, X86_FEATURE_IBPB);
1003 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1006 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
1007 set_cpu_cap(c, X86_FEATURE_STIBP);
1009 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
1010 cpu_has(c, X86_FEATURE_VIRT_SSBD))
1011 set_cpu_cap(c, X86_FEATURE_SSBD);
1013 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
1014 set_cpu_cap(c, X86_FEATURE_IBRS);
1015 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1018 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
1019 set_cpu_cap(c, X86_FEATURE_IBPB);
1021 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
1022 set_cpu_cap(c, X86_FEATURE_STIBP);
1023 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1026 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
1027 set_cpu_cap(c, X86_FEATURE_SSBD);
1028 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
1029 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
1033 void get_cpu_cap(struct cpuinfo_x86 *c)
1035 u32 eax, ebx, ecx, edx;
1037 /* Intel-defined flags: level 0x00000001 */
1038 if (c->cpuid_level >= 0x00000001) {
1039 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
1041 c->x86_capability[CPUID_1_ECX] = ecx;
1042 c->x86_capability[CPUID_1_EDX] = edx;
1045 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
1046 if (c->cpuid_level >= 0x00000006)
1047 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
1049 /* Additional Intel-defined flags: level 0x00000007 */
1050 if (c->cpuid_level >= 0x00000007) {
1051 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
1052 c->x86_capability[CPUID_7_0_EBX] = ebx;
1053 c->x86_capability[CPUID_7_ECX] = ecx;
1054 c->x86_capability[CPUID_7_EDX] = edx;
1056 /* Check valid sub-leaf index before accessing it */
1058 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
1059 c->x86_capability[CPUID_7_1_EAX] = eax;
1063 /* Extended state features: level 0x0000000d */
1064 if (c->cpuid_level >= 0x0000000d) {
1065 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
1067 c->x86_capability[CPUID_D_1_EAX] = eax;
1070 /* AMD-defined flags: level 0x80000001 */
1071 eax = cpuid_eax(0x80000000);
1072 c->extended_cpuid_level = eax;
1074 if ((eax & 0xffff0000) == 0x80000000) {
1075 if (eax >= 0x80000001) {
1076 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1078 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1079 c->x86_capability[CPUID_8000_0001_EDX] = edx;
1083 if (c->extended_cpuid_level >= 0x80000007) {
1084 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1086 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1090 if (c->extended_cpuid_level >= 0x80000008) {
1091 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1092 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1095 if (c->extended_cpuid_level >= 0x8000000a)
1096 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1098 if (c->extended_cpuid_level >= 0x8000001f)
1099 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1101 init_scattered_cpuid_features(c);
1102 init_speculation_control(c);
1105 * Clear/Set all flags overridden by options, after probe.
1106 * This needs to happen each time we re-probe, which may happen
1107 * several times during CPU initialization.
1109 apply_forced_caps(c);
1112 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1114 u32 eax, ebx, ecx, edx;
1116 if (c->extended_cpuid_level >= 0x80000008) {
1117 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1119 c->x86_virt_bits = (eax >> 8) & 0xff;
1120 c->x86_phys_bits = eax & 0xff;
1122 #ifdef CONFIG_X86_32
1123 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
1124 c->x86_phys_bits = 36;
1126 c->x86_cache_bits = c->x86_phys_bits;
1129 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1131 #ifdef CONFIG_X86_32
1135 * First of all, decide if this is a 486 or higher
1136 * It's a 486 if we can modify the AC flag
1138 if (flag_is_changeable_p(X86_EFLAGS_AC))
1143 for (i = 0; i < X86_VENDOR_NUM; i++)
1144 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1145 c->x86_vendor_id[0] = 0;
1146 cpu_devs[i]->c_identify(c);
1147 if (c->x86_vendor_id[0]) {
1155 #define NO_SPECULATION BIT(0)
1156 #define NO_MELTDOWN BIT(1)
1157 #define NO_SSB BIT(2)
1158 #define NO_L1TF BIT(3)
1159 #define NO_MDS BIT(4)
1160 #define MSBDS_ONLY BIT(5)
1161 #define NO_SWAPGS BIT(6)
1162 #define NO_ITLB_MULTIHIT BIT(7)
1163 #define NO_SPECTRE_V2 BIT(8)
1165 #define VULNWL(vendor, family, model, whitelist) \
1166 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1168 #define VULNWL_INTEL(model, whitelist) \
1169 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1171 #define VULNWL_AMD(family, whitelist) \
1172 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1174 #define VULNWL_HYGON(family, whitelist) \
1175 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1177 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1178 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1179 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1180 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1181 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1182 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION),
1183 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
1185 /* Intel Family 6 */
1186 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1187 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1188 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1189 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1190 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1192 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1193 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1194 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1195 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1196 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1197 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1199 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1201 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1202 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1204 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1205 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1206 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1209 * Technically, swapgs isn't serializing on AMD (despite it previously
1210 * being documented as such in the APM). But according to AMD, %gs is
1211 * updated non-speculatively, and the issuing of %gs-relative memory
1212 * operands will be blocked until the %gs update completes, which is
1213 * good enough for our purposes.
1216 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT),
1218 /* AMD Family 0xf - 0x12 */
1219 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1220 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1221 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1222 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1224 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1225 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1226 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1228 /* Zhaoxin Family 7 */
1229 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1230 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1234 #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1235 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1236 INTEL_FAM6_##model, steppings, \
1237 X86_FEATURE_ANY, issues)
1239 #define SRBDS BIT(0)
1241 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1242 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1243 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1244 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1245 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1246 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1247 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1248 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS),
1249 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS),
1250 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS),
1251 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS),
1255 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1257 const struct x86_cpu_id *m = x86_match_cpu(table);
1259 return m && !!(m->driver_data & which);
1262 u64 x86_read_arch_cap_msr(void)
1266 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1267 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1272 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1274 u64 ia32_cap = x86_read_arch_cap_msr();
1276 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1277 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1278 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1279 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1281 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1284 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1286 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1287 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1289 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1290 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1291 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1292 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1294 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1295 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1297 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1298 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1299 setup_force_cpu_bug(X86_BUG_MDS);
1300 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1301 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1304 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1305 setup_force_cpu_bug(X86_BUG_SWAPGS);
1308 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1309 * - TSX is supported or
1310 * - TSX_CTRL is present
1312 * TSX_CTRL check is needed for cases when TSX could be disabled before
1313 * the kernel boot e.g. kexec.
1314 * TSX_CTRL check alone is not sufficient for cases when the microcode
1315 * update is not present or running as guest that don't get TSX_CTRL.
1317 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1318 (cpu_has(c, X86_FEATURE_RTM) ||
1319 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1320 setup_force_cpu_bug(X86_BUG_TAA);
1323 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1324 * in the vulnerability blacklist.
1326 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1327 cpu_has(c, X86_FEATURE_RDSEED)) &&
1328 cpu_matches(cpu_vuln_blacklist, SRBDS))
1329 setup_force_cpu_bug(X86_BUG_SRBDS);
1331 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1334 /* Rogue Data Cache Load? No! */
1335 if (ia32_cap & ARCH_CAP_RDCL_NO)
1338 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1340 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1343 setup_force_cpu_bug(X86_BUG_L1TF);
1347 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1348 * unfortunately, that's not true in practice because of early VIA
1349 * chips and (more importantly) broken virtualizers that are not easy
1350 * to detect. In the latter case it doesn't even *fail* reliably, so
1351 * probing for it doesn't even work. Disable it completely on 32-bit
1352 * unless we can find a reliable way to detect all the broken cases.
1353 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1355 static void detect_nopl(void)
1357 #ifdef CONFIG_X86_32
1358 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1360 setup_force_cpu_cap(X86_FEATURE_NOPL);
1365 * We parse cpu parameters early because fpu__init_system() is executed
1366 * before parse_early_param().
1368 static void __init cpu_parse_early_param(void)
1372 int arglen, res, bit;
1374 #ifdef CONFIG_X86_32
1375 if (cmdline_find_option_bool(boot_command_line, "no387"))
1376 #ifdef CONFIG_MATH_EMULATION
1377 setup_clear_cpu_cap(X86_FEATURE_FPU);
1379 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1382 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1383 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1386 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1387 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1389 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1390 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1392 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1393 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1395 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1399 pr_info("Clearing CPUID bits:");
1401 res = get_option(&argptr, &bit);
1402 if (res == 0 || res == 3)
1405 /* If the argument was too long, the last bit may be cut off */
1406 if (res == 1 && arglen >= sizeof(arg))
1409 if (bit >= 0 && bit < NCAPINTS * 32) {
1410 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1411 setup_clear_cpu_cap(bit);
1418 * Do minimum CPU detection early.
1419 * Fields really needed: vendor, cpuid_level, family, model, mask,
1421 * The others are not touched to avoid unwanted side effects.
1423 * WARNING: this function is only called on the boot CPU. Don't add code
1424 * here that is supposed to run on all CPUs.
1426 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1428 #ifdef CONFIG_X86_64
1429 c->x86_clflush_size = 64;
1430 c->x86_phys_bits = 36;
1431 c->x86_virt_bits = 48;
1433 c->x86_clflush_size = 32;
1434 c->x86_phys_bits = 32;
1435 c->x86_virt_bits = 32;
1437 c->x86_cache_alignment = c->x86_clflush_size;
1439 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1440 c->extended_cpuid_level = 0;
1442 if (!have_cpuid_p())
1443 identify_cpu_without_cpuid(c);
1445 /* cyrix could have cpuid enabled via c_identify()*/
1446 if (have_cpuid_p()) {
1450 get_cpu_address_sizes(c);
1451 setup_force_cpu_cap(X86_FEATURE_CPUID);
1452 cpu_parse_early_param();
1454 if (this_cpu->c_early_init)
1455 this_cpu->c_early_init(c);
1458 filter_cpuid_features(c, false);
1460 if (this_cpu->c_bsp_init)
1461 this_cpu->c_bsp_init(c);
1463 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1466 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1468 cpu_set_bug_bits(c);
1472 fpu__init_system(c);
1474 init_sigframe_size();
1476 #ifdef CONFIG_X86_32
1478 * Regardless of whether PCID is enumerated, the SDM says
1479 * that it can't be enabled in 32-bit mode.
1481 setup_clear_cpu_cap(X86_FEATURE_PCID);
1485 * Later in the boot process pgtable_l5_enabled() relies on
1486 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1487 * enabled by this point we need to clear the feature bit to avoid
1488 * false-positives at the later stage.
1490 * pgtable_l5_enabled() can be false here for several reasons:
1491 * - 5-level paging is disabled compile-time;
1492 * - it's 32-bit kernel;
1493 * - machine doesn't support 5-level paging;
1494 * - user specified 'no5lvl' in kernel command line.
1496 if (!pgtable_l5_enabled())
1497 setup_clear_cpu_cap(X86_FEATURE_LA57);
1502 void __init early_cpu_init(void)
1504 const struct cpu_dev *const *cdev;
1507 #ifdef CONFIG_PROCESSOR_SELECT
1508 pr_info("KERNEL supported cpus:\n");
1511 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1512 const struct cpu_dev *cpudev = *cdev;
1514 if (count >= X86_VENDOR_NUM)
1516 cpu_devs[count] = cpudev;
1519 #ifdef CONFIG_PROCESSOR_SELECT
1523 for (j = 0; j < 2; j++) {
1524 if (!cpudev->c_ident[j])
1526 pr_info(" %s %s\n", cpudev->c_vendor,
1527 cpudev->c_ident[j]);
1532 early_identify_cpu(&boot_cpu_data);
1535 static bool detect_null_seg_behavior(void)
1538 * Empirically, writing zero to a segment selector on AMD does
1539 * not clear the base, whereas writing zero to a segment
1540 * selector on Intel does clear the base. Intel's behavior
1541 * allows slightly faster context switches in the common case
1542 * where GS is unused by the prev and next threads.
1544 * Since neither vendor documents this anywhere that I can see,
1545 * detect it directly instead of hard-coding the choice by
1548 * I've designated AMD's behavior as the "bug" because it's
1549 * counterintuitive and less friendly.
1552 unsigned long old_base, tmp;
1553 rdmsrl(MSR_FS_BASE, old_base);
1554 wrmsrl(MSR_FS_BASE, 1);
1556 rdmsrl(MSR_FS_BASE, tmp);
1557 wrmsrl(MSR_FS_BASE, old_base);
1561 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1563 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1564 if (!IS_ENABLED(CONFIG_X86_64))
1567 /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */
1568 if (c->extended_cpuid_level >= 0x80000021 &&
1569 cpuid_eax(0x80000021) & BIT(6))
1573 * CPUID bit above wasn't set. If this kernel is still running
1574 * as a HV guest, then the HV has decided not to advertize
1575 * that CPUID bit for whatever reason. For example, one
1576 * member of the migration pool might be vulnerable. Which
1577 * means, the bug is present: set the BUG flag and return.
1579 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1580 set_cpu_bug(c, X86_BUG_NULL_SEG);
1585 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1586 * 0x18 is the respective family for Hygon.
1588 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1589 detect_null_seg_behavior())
1592 /* All the remaining ones are affected */
1593 set_cpu_bug(c, X86_BUG_NULL_SEG);
1596 static void generic_identify(struct cpuinfo_x86 *c)
1598 c->extended_cpuid_level = 0;
1600 if (!have_cpuid_p())
1601 identify_cpu_without_cpuid(c);
1603 /* cyrix could have cpuid enabled via c_identify()*/
1604 if (!have_cpuid_p())
1613 get_cpu_address_sizes(c);
1615 if (c->cpuid_level >= 0x00000001) {
1616 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1617 #ifdef CONFIG_X86_32
1619 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1621 c->apicid = c->initial_apicid;
1624 c->phys_proc_id = c->initial_apicid;
1627 get_model_name(c); /* Default name */
1630 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1631 * systems that run Linux at CPL > 0 may or may not have the
1632 * issue, but, even if they have the issue, there's absolutely
1633 * nothing we can do about it because we can't use the real IRET
1636 * NB: For the time being, only 32-bit kernels support
1637 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1638 * whether to apply espfix using paravirt hooks. If any
1639 * non-paravirt system ever shows up that does *not* have the
1640 * ESPFIX issue, we can change this.
1642 #ifdef CONFIG_X86_32
1643 set_cpu_bug(c, X86_BUG_ESPFIX);
1648 * Validate that ACPI/mptables have the same information about the
1649 * effective APIC id and update the package map.
1651 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1654 unsigned int apicid, cpu = smp_processor_id();
1656 apicid = apic->cpu_present_to_apicid(cpu);
1658 if (apicid != c->apicid) {
1659 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1660 cpu, apicid, c->initial_apicid);
1662 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1663 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1665 c->logical_proc_id = 0;
1670 * This does the hard work of actually picking apart the CPU stuff...
1672 static void identify_cpu(struct cpuinfo_x86 *c)
1676 c->loops_per_jiffy = loops_per_jiffy;
1677 c->x86_cache_size = 0;
1678 c->x86_vendor = X86_VENDOR_UNKNOWN;
1679 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1680 c->x86_vendor_id[0] = '\0'; /* Unset */
1681 c->x86_model_id[0] = '\0'; /* Unset */
1682 c->x86_max_cores = 1;
1683 c->x86_coreid_bits = 0;
1685 #ifdef CONFIG_X86_64
1686 c->x86_clflush_size = 64;
1687 c->x86_phys_bits = 36;
1688 c->x86_virt_bits = 48;
1690 c->cpuid_level = -1; /* CPUID not detected */
1691 c->x86_clflush_size = 32;
1692 c->x86_phys_bits = 32;
1693 c->x86_virt_bits = 32;
1695 c->x86_cache_alignment = c->x86_clflush_size;
1696 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1697 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1698 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1701 generic_identify(c);
1703 if (this_cpu->c_identify)
1704 this_cpu->c_identify(c);
1706 /* Clear/Set all flags overridden by options, after probe */
1707 apply_forced_caps(c);
1709 #ifdef CONFIG_X86_64
1710 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1714 * Vendor-specific initialization. In this section we
1715 * canonicalize the feature flags, meaning if there are
1716 * features a certain CPU supports which CPUID doesn't
1717 * tell us, CPUID claiming incorrect flags, or other bugs,
1718 * we handle them here.
1720 * At the end of this section, c->x86_capability better
1721 * indicate the features this CPU genuinely supports!
1723 if (this_cpu->c_init)
1724 this_cpu->c_init(c);
1726 /* Disable the PN if appropriate */
1727 squash_the_stupid_serial_number(c);
1729 /* Set up SMEP/SMAP/UMIP */
1734 /* Enable FSGSBASE instructions if available. */
1735 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1736 cr4_set_bits(X86_CR4_FSGSBASE);
1737 elf_hwcap2 |= HWCAP2_FSGSBASE;
1741 * The vendor-specific functions might have changed features.
1742 * Now we do "generic changes."
1745 /* Filter out anything that depends on CPUID levels we don't have */
1746 filter_cpuid_features(c, true);
1748 /* If the model name is still unset, do table lookup. */
1749 if (!c->x86_model_id[0]) {
1751 p = table_lookup_model(c);
1753 strcpy(c->x86_model_id, p);
1755 /* Last resort... */
1756 sprintf(c->x86_model_id, "%02x/%02x",
1757 c->x86, c->x86_model);
1760 #ifdef CONFIG_X86_64
1769 * Clear/Set all flags overridden by options, need do it
1770 * before following smp all cpus cap AND.
1772 apply_forced_caps(c);
1775 * On SMP, boot_cpu_data holds the common feature set between
1776 * all CPUs; so make sure that we indicate which features are
1777 * common between the CPUs. The first time this routine gets
1778 * executed, c == &boot_cpu_data.
1780 if (c != &boot_cpu_data) {
1781 /* AND the already accumulated flags with these */
1782 for (i = 0; i < NCAPINTS; i++)
1783 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1785 /* OR, i.e. replicate the bug flags */
1786 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1787 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1792 /* Init Machine Check Exception if available. */
1795 select_idle_routine(c);
1798 numa_add_cpu(smp_processor_id());
1803 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1804 * on 32-bit kernels:
1806 #ifdef CONFIG_X86_32
1807 void enable_sep_cpu(void)
1809 struct tss_struct *tss;
1812 if (!boot_cpu_has(X86_FEATURE_SEP))
1816 tss = &per_cpu(cpu_tss_rw, cpu);
1819 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1820 * see the big comment in struct x86_hw_tss's definition.
1823 tss->x86_tss.ss1 = __KERNEL_CS;
1824 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1825 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1826 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1832 void __init identify_boot_cpu(void)
1834 identify_cpu(&boot_cpu_data);
1835 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1836 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1837 #ifdef CONFIG_X86_32
1841 cpu_detect_tlb(&boot_cpu_data);
1847 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1849 BUG_ON(c == &boot_cpu_data);
1851 #ifdef CONFIG_X86_32
1855 validate_apic_and_package_id(c);
1856 x86_spec_ctrl_setup_ap();
1862 static __init int setup_noclflush(char *arg)
1864 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1865 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1868 __setup("noclflush", setup_noclflush);
1870 void print_cpu_info(struct cpuinfo_x86 *c)
1872 const char *vendor = NULL;
1874 if (c->x86_vendor < X86_VENDOR_NUM) {
1875 vendor = this_cpu->c_vendor;
1877 if (c->cpuid_level >= 0)
1878 vendor = c->x86_vendor_id;
1881 if (vendor && !strstr(c->x86_model_id, vendor))
1882 pr_cont("%s ", vendor);
1884 if (c->x86_model_id[0])
1885 pr_cont("%s", c->x86_model_id);
1887 pr_cont("%d86", c->x86);
1889 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1891 if (c->x86_stepping || c->cpuid_level >= 0)
1892 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1898 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
1899 * function prevents it from becoming an environment variable for init.
1901 static __init int setup_clearcpuid(char *arg)
1905 __setup("clearcpuid=", setup_clearcpuid);
1907 #ifdef CONFIG_X86_64
1908 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1909 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1910 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1913 * The following percpu variables are hot. Align current_task to
1914 * cacheline size such that they fall in the same cacheline.
1916 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1918 EXPORT_PER_CPU_SYMBOL(current_task);
1920 DEFINE_PER_CPU(void *, hardirq_stack_ptr);
1921 DEFINE_PER_CPU(bool, hardirq_stack_inuse);
1923 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1924 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1926 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK;
1928 static void wrmsrl_cstar(unsigned long val)
1931 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
1932 * is so far ignored by the CPU, but raises a #VE trap in a TDX
1933 * guest. Avoid the pointless write on all Intel CPUs.
1935 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1936 wrmsrl(MSR_CSTAR, val);
1939 /* May not be marked __init: used by software suspend */
1940 void syscall_init(void)
1942 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1943 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1945 #ifdef CONFIG_IA32_EMULATION
1946 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
1948 * This only works on Intel CPUs.
1949 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1950 * This does not cause SYSENTER to jump to the wrong location, because
1951 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1953 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1954 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1955 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1956 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1958 wrmsrl_cstar((unsigned long)ignore_sysret);
1959 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1960 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1961 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1965 * Flags to clear on syscall; clear as much as possible
1966 * to minimize user space-kernel interference.
1968 wrmsrl(MSR_SYSCALL_MASK,
1969 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
1970 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
1971 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
1972 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
1973 X86_EFLAGS_AC|X86_EFLAGS_ID);
1976 #else /* CONFIG_X86_64 */
1978 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1979 EXPORT_PER_CPU_SYMBOL(current_task);
1980 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1981 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1984 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1985 * the top of the kernel stack. Use an extra percpu variable to track the
1986 * top of the kernel stack directly.
1988 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1989 (unsigned long)&init_thread_union + THREAD_SIZE;
1990 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1992 #ifdef CONFIG_STACKPROTECTOR
1993 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
1994 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
1997 #endif /* CONFIG_X86_64 */
2000 * Clear all 6 debug registers:
2002 static void clear_all_debug_regs(void)
2006 for (i = 0; i < 8; i++) {
2007 /* Ignore db4, db5 */
2008 if ((i == 4) || (i == 5))
2017 * Restore debug regs if using kgdbwait and you have a kernel debugger
2018 * connection established.
2020 static void dbg_restore_debug_regs(void)
2022 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2023 arch_kgdb_ops.correct_hw_break();
2025 #else /* ! CONFIG_KGDB */
2026 #define dbg_restore_debug_regs()
2027 #endif /* ! CONFIG_KGDB */
2029 static void wait_for_master_cpu(int cpu)
2033 * wait for ACK from master CPU before continuing
2034 * with AP initialization
2036 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
2037 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
2042 #ifdef CONFIG_X86_64
2043 static inline void setup_getcpu(int cpu)
2045 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2046 struct desc_struct d = { };
2048 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2049 wrmsr(MSR_TSC_AUX, cpudata, 0);
2051 /* Store CPU and node number in limit. */
2053 d.limit1 = cpudata >> 16;
2055 d.type = 5; /* RO data, expand down, accessed */
2056 d.dpl = 3; /* Visible to user code */
2057 d.s = 1; /* Not a system segment */
2058 d.p = 1; /* Present */
2059 d.d = 1; /* 32-bit */
2061 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2064 static inline void ucode_cpu_init(int cpu)
2070 static inline void tss_setup_ist(struct tss_struct *tss)
2072 /* Set up the per-CPU TSS IST stacks */
2073 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2074 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2075 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2076 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2077 /* Only mapped when SEV-ES is active */
2078 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2081 #else /* CONFIG_X86_64 */
2083 static inline void setup_getcpu(int cpu) { }
2085 static inline void ucode_cpu_init(int cpu)
2087 show_ucode_info_early();
2090 static inline void tss_setup_ist(struct tss_struct *tss) { }
2092 #endif /* !CONFIG_X86_64 */
2094 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2096 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2098 #ifdef CONFIG_X86_IOPL_IOPERM
2099 tss->io_bitmap.prev_max = 0;
2100 tss->io_bitmap.prev_sequence = 0;
2101 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2103 * Invalidate the extra array entry past the end of the all
2104 * permission bitmap as required by the hardware.
2106 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2111 * Setup everything needed to handle exceptions from the IDT, including the IST
2112 * exceptions which use paranoid_entry().
2114 void cpu_init_exception_handling(void)
2116 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2117 int cpu = raw_smp_processor_id();
2119 /* paranoid_entry() gets the CPU number from the GDT */
2122 /* IST vectors need TSS to be set up. */
2124 tss_setup_io_bitmap(tss);
2125 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2129 /* Finally load the IDT */
2134 * cpu_init() initializes state that is per-CPU. Some data is already
2135 * initialized (naturally) in the bootstrap process, such as the GDT. We
2136 * reload it nevertheless, this function acts as a 'CPU state barrier',
2137 * nothing should get across.
2141 struct task_struct *cur = current;
2142 int cpu = raw_smp_processor_id();
2144 wait_for_master_cpu(cpu);
2146 ucode_cpu_init(cpu);
2149 if (this_cpu_read(numa_node) == 0 &&
2150 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2151 set_numa_node(early_cpu_to_node(cpu));
2153 pr_debug("Initializing CPU#%d\n", cpu);
2155 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2156 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2157 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2160 * Initialize the per-CPU GDT with the boot GDT,
2161 * and set up the GDT descriptor:
2163 switch_to_new_gdt(cpu);
2165 if (IS_ENABLED(CONFIG_X86_64)) {
2167 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2170 wrmsrl(MSR_FS_BASE, 0);
2171 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2178 cur->active_mm = &init_mm;
2180 initialize_tlbstate_and_flush();
2181 enter_lazy_tlb(&init_mm, cur);
2184 * sp0 points to the entry trampoline stack regardless of what task
2187 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2189 load_mm_ldt(&init_mm);
2191 clear_all_debug_regs();
2192 dbg_restore_debug_regs();
2194 doublefault_init_cpu_tss();
2201 load_fixmap_gdt(cpu);
2205 void cpu_init_secondary(void)
2208 * Relies on the BP having set-up the IDT tables, which are loaded
2209 * on this CPU in cpu_init_exception_handling().
2211 cpu_init_exception_handling();
2217 * The microcode loader calls this upon late microcode load to recheck features,
2218 * only when microcode has been updated. Caller holds microcode_mutex and CPU
2221 void microcode_check(void)
2223 struct cpuinfo_x86 info;
2225 perf_check_microcode();
2227 /* Reload CPUID max function as it might've changed. */
2228 info.cpuid_level = cpuid_eax(0);
2231 * Copy all capability leafs to pick up the synthetic ones so that
2232 * memcmp() below doesn't fail on that. The ones coming from CPUID will
2233 * get overwritten in get_cpu_cap().
2235 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
2239 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
2242 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2243 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2247 * Invoked from core CPU hotplug code after hotplug operations
2249 void arch_smt_update(void)
2251 /* Handle the speculative execution misfeatures */
2252 cpu_bugs_smt_update();
2253 /* Check whether IPI broadcasting can be enabled */