arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
   9  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
  10  */
  11 #include <linux/crash_dump.h>
  12 #include <linux/cpuhotplug.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/proc_fs.h>
  15 #include <linux/memory.h>
  16 #include <linux/export.h>
  17 #include <linux/pci.h>
  18 #include <linux/acpi.h>
  19 #include <linux/efi.h>
  20
  21 #include <asm/e820/api.h>
  22 #include <asm/uv/uv_mmrs.h>
  23 #include <asm/uv/uv_hub.h>
  24 #include <asm/uv/bios.h>
  25 #include <asm/uv/uv.h>
  26 #include <asm/apic.h>
  27
  28 static enum uv_system_type      uv_system_type;
  29 static int                      uv_hubbed_system;
  30 static int                      uv_hubless_system;
  31 static u64                      gru_start_paddr, gru_end_paddr;
  32 static union uvh_apicid         uvh_apicid;
  33 static int                      uv_node_id;
  34
  35 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */
  36 static u8 uv_archtype[UV_AT_SIZE];
  37 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
  38 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
  39
  40 /* Information derived from CPUID and some UV MMRs */
  41 static struct {
  42         unsigned int apicid_shift;
  43         unsigned int apicid_mask;
  44         unsigned int socketid_shift;    /* aka pnode_shift for UV2/3 */
  45         unsigned int pnode_mask;
  46         unsigned int nasid_shift;
  47         unsigned int gpa_shift;
  48         unsigned int gnode_shift;
  49         unsigned int m_skt;
  50         unsigned int n_skt;
  51 } uv_cpuid;
  52
  53 static int uv_min_hub_revision_id;
  54
  55 static struct apic apic_x2apic_uv_x;
  56 static struct uv_hub_info_s uv_hub_info_node0;
  57
  58 /* Set this to use hardware error handler instead of kernel panic: */
  59 static int disable_uv_undefined_panic = 1;
  60
  61 unsigned long uv_undefined(char *str)
  62 {
  63         if (likely(!disable_uv_undefined_panic))
  64                 panic("UV: error: undefined MMR: %s\n", str);
  65         else
  66                 pr_crit("UV: error: undefined MMR: %s\n", str);
  67
  68         /* Cause a machine fault: */
  69         return ~0ul;
  70 }
  71 EXPORT_SYMBOL(uv_undefined);
  72
  73 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  74 {
  75         unsigned long val, *mmr;
  76
  77         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  78         val = *mmr;
  79         early_iounmap(mmr, sizeof(*mmr));
  80
  81         return val;
  82 }
  83
  84 static inline bool is_GRU_range(u64 start, u64 end)
  85 {
  86         if (!gru_start_paddr)
  87                 return false;
  88
  89         return start >= gru_start_paddr && end <= gru_end_paddr;
  90 }
  91
  92 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  93 {
  94         return is_ISA_range(start, end) || is_GRU_range(start, end);
  95 }
  96
  97 static void __init early_get_pnodeid(void)
  98 {
  99         int pnode;
 100
 101         uv_cpuid.m_skt = 0;
 102         if (UVH_RH10_GAM_ADDR_MAP_CONFIG) {
 103                 union uvh_rh10_gam_addr_map_config_u  m_n_config;
 104
 105                 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
 106                 uv_cpuid.n_skt = m_n_config.s.n_skt;
 107                 uv_cpuid.nasid_shift = 0;
 108         } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) {
 109                 union uvh_rh_gam_addr_map_config_u  m_n_config;
 110
 111         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
 112                 uv_cpuid.n_skt = m_n_config.s.n_skt;
 113                 if (is_uv(UV3))
 114                         uv_cpuid.m_skt = m_n_config.s3.m_skt;
 115                 if (is_uv(UV2))
 116                         uv_cpuid.m_skt = m_n_config.s2.m_skt;
 117                 uv_cpuid.nasid_shift = 1;
 118         } else {
 119                 unsigned long GAM_ADDR_MAP_CONFIG = 0;
 120
 121                 WARN(GAM_ADDR_MAP_CONFIG == 0,
 122                         "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n");
 123                 uv_cpuid.n_skt = 0;
 124                 uv_cpuid.nasid_shift = 0;
 125         }
 126
 127         if (is_uv(UV4|UVY))
 128                 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
 129
 130         uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1;
 131         pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask;
 132         uv_cpuid.gpa_shift = 46;        /* Default unless changed */
 133
 134         pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
 135                 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode);
 136 }
 137
 138 /* Running on a UV Hubbed system, determine which UV Hub Type it is */
 139 static int __init early_set_hub_type(void)
 140 {
 141         union uvh_node_id_u node_id;
 142
 143         /*
 144          * The NODE_ID MMR is always at offset 0.
 145          * Contains the chip part # + revision.
 146          * Node_id field started with 15 bits,
 147          * ... now 7 but upper 8 are masked to 0.
 148          * All blades/nodes have the same part # and hub revision.
 149          */
 150         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
 151         uv_node_id = node_id.sx.node_id;
 152
 153         switch (node_id.s.part_number) {
 154
 155         case UV5_HUB_PART_NUMBER:
 156                 uv_min_hub_revision_id = node_id.s.revision
 157                                          + UV5_HUB_REVISION_BASE;
 158                 uv_hub_type_set(UV5);
 159                 break;
 160
 161         /* UV4/4A only have a revision difference */
 162         case UV4_HUB_PART_NUMBER:
 163                 uv_min_hub_revision_id = node_id.s.revision
 164                                          + UV4_HUB_REVISION_BASE;
 165                 uv_hub_type_set(UV4);
 166                 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
 167                         uv_hub_type_set(UV4|UV4A);
 168                 break;
 169
 170         case UV3_HUB_PART_NUMBER:
 171         case UV3_HUB_PART_NUMBER_X:
 172                 uv_min_hub_revision_id = node_id.s.revision
 173                                          + UV3_HUB_REVISION_BASE;
 174                 uv_hub_type_set(UV3);
 175                 break;
 176
 177         case UV2_HUB_PART_NUMBER:
 178         case UV2_HUB_PART_NUMBER_X:
 179                 uv_min_hub_revision_id = node_id.s.revision
 180                                          + UV2_HUB_REVISION_BASE - 1;
 181                 uv_hub_type_set(UV2);
 182                 break;
 183
 184         default:
 185                 return 0;
 186         }
 187
 188         pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
 189                 node_id.s.part_number, node_id.s.revision,
 190                 uv_min_hub_revision_id, is_uv(~0));
 191
 192         return 1;
 193 }
 194
 195 static void __init uv_tsc_check_sync(void)
 196 {
 197         u64 mmr;
 198         int sync_state;
 199         int mmr_shift;
 200         char *state;
 201
 202         /* Different returns from different UV BIOS versions */
 203         mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
 204         mmr_shift =
 205                 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
 206         sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
 207
 208         /* Check if TSC is valid for all sockets */
 209         switch (sync_state) {
 210         case UVH_TSC_SYNC_VALID:
 211                 state = "in sync";
 212                 mark_tsc_async_resets("UV BIOS");
 213                 break;
 214
 215         /* If BIOS state unknown, don't do anything */
 216         case UVH_TSC_SYNC_UNKNOWN:
 217                 state = "unknown";
 218                 break;
 219
 220         /* Otherwise, BIOS indicates problem with TSC */
 221         default:
 222                 state = "unstable";
 223                 mark_tsc_unstable("UV BIOS");
 224                 break;
 225         }
 226         pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
 227 }
 228
 229 /* Selector for (4|4A|5) structs */
 230 #define uvxy_field(sname, field, undef) (       \
 231         is_uv(UV4A) ? sname.s4a.field :         \
 232         is_uv(UV4) ? sname.s4.field :           \
 233         is_uv(UV3) ? sname.s3.field :           \
 234         undef)
 235
 236 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
 237
 238 #define SMT_LEVEL                       0       /* Leaf 0xb SMT level */
 239 #define INVALID_TYPE                    0       /* Leaf 0xb sub-leaf types */
 240 #define SMT_TYPE                        1
 241 #define CORE_TYPE                       2
 242 #define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
 243 #define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
 244
 245 static void set_x2apic_bits(void)
 246 {
 247         unsigned int eax, ebx, ecx, edx, sub_index;
 248         unsigned int sid_shift;
 249
 250         cpuid(0, &eax, &ebx, &ecx, &edx);
 251         if (eax < 0xb) {
 252                 pr_info("UV: CPU does not have CPUID.11\n");
 253                 return;
 254         }
 255
 256         cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
 257         if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
 258                 pr_info("UV: CPUID.11 not implemented\n");
 259                 return;
 260         }
 261
 262         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 263         sub_index = 1;
 264         do {
 265                 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
 266                 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
 267                         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
 268                         break;
 269                 }
 270                 sub_index++;
 271         } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
 272
 273         uv_cpuid.apicid_shift   = 0;
 274         uv_cpuid.apicid_mask    = (~(-1 << sid_shift));
 275         uv_cpuid.socketid_shift = sid_shift;
 276 }
 277
 278 static void __init early_get_apic_socketid_shift(void)
 279 {
 280         if (is_uv2_hub() || is_uv3_hub())
 281                 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
 282
 283         set_x2apic_bits();
 284
 285         pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
 286         pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
 287 }
 288
 289 static void __init uv_stringify(int len, char *to, char *from)
 290 {
 291         /* Relies on 'to' being NULL chars so result will be NULL terminated */
 292         strncpy(to, from, len-1);
 293
 294         /* Trim trailing spaces */
 295         (void)strim(to);
 296 }
 297
 298 /* Find UV arch type entry in UVsystab */
 299 static unsigned long __init early_find_archtype(struct uv_systab *st)
 300 {
 301         int i;
 302
 303         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
 304                 unsigned long ptr = st->entry[i].offset;
 305
 306                 if (!ptr)
 307                         continue;
 308                 ptr += (unsigned long)st;
 309                 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE)
 310                         return ptr;
 311         }
 312         return 0;
 313 }
 314
 315 /* Validate UV arch type field in UVsystab */
 316 static int __init decode_arch_type(unsigned long ptr)
 317 {
 318         struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr;
 319         int n = strlen(uv_ate->archtype);
 320
 321         if (n > 0 && n < sizeof(uv_ate->archtype)) {
 322                 pr_info("UV: UVarchtype received from BIOS\n");
 323                 uv_stringify(UV_AT_SIZE, uv_archtype, uv_ate->archtype);
 324                 return 1;
 325         }
 326         return 0;
 327 }
 328
 329 /* Determine if UV arch type entry might exist in UVsystab */
 330 static int __init early_get_arch_type(void)
 331 {
 332         unsigned long uvst_physaddr, uvst_size, ptr;
 333         struct uv_systab *st;
 334         u32 rev;
 335         int ret;
 336
 337         uvst_physaddr = get_uv_systab_phys(0);
 338         if (!uvst_physaddr)
 339                 return 0;
 340
 341         st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab));
 342         if (!st) {
 343                 pr_err("UV: Cannot access UVsystab, remap failed\n");
 344                 return 0;
 345         }
 346
 347         rev = st->revision;
 348         if (rev < UV_SYSTAB_VERSION_UV5) {
 349                 early_memunmap(st, sizeof(struct uv_systab));
 350                 return 0;
 351         }
 352
 353         uvst_size = st->size;
 354         early_memunmap(st, sizeof(struct uv_systab));
 355         st = early_memremap_ro(uvst_physaddr, uvst_size);
 356         if (!st) {
 357                 pr_err("UV: Cannot access UVarchtype, remap failed\n");
 358                 return 0;
 359         }
 360
 361         ptr = early_find_archtype(st);
 362         if (!ptr) {
 363                 early_memunmap(st, uvst_size);
 364                 return 0;
 365         }
 366
 367         ret = decode_arch_type(ptr);
 368         early_memunmap(st, uvst_size);
 369         return ret;
 370 }
 371
 372 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
 373 {
 374         /* Save OEM_ID passed from ACPI MADT */
 375         uv_stringify(sizeof(oem_id), oem_id, _oem_id);
 376
 377         /* Check if BIOS sent us a UVarchtype */
 378         if (!early_get_arch_type())
 379
 380                 /* If not use OEM ID for UVarchtype */
 381                 uv_stringify(UV_AT_SIZE, uv_archtype, _oem_id);
 382
 383         /* Check if not hubbed */
 384         if (strncmp(uv_archtype, "SGI", 3) != 0) {
 385
 386                 /* (Not hubbed), check if not hubless */
 387                 if (strncmp(uv_archtype, "NSGI", 4) != 0)
 388
 389                         /* (Not hubless), not a UV */
 390                         return 0;
 391
 392                 /* Is UV hubless system */
 393                 uv_hubless_system = 0x01;
 394
 395                 /* UV5 Hubless */
 396                 if (strncmp(uv_archtype, "NSGI5", 5) == 0)
 397                         uv_hubless_system |= 0x20;
 398
 399                 /* UV4 Hubless: CH */
 400                 else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
 401                         uv_hubless_system |= 0x10;
 402
 403                 /* UV3 Hubless: UV300/MC990X w/o hub */
 404                 else
 405                         uv_hubless_system |= 0x8;
 406
 407                 /* Copy APIC type */
 408                 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
 409
 410                 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
 411                         oem_id, oem_table_id, uv_system_type, uv_hubless_system);
 412                 return 0;
 413         }
 414
 415         if (numa_off) {
 416                 pr_err("UV: NUMA is off, disabling UV support\n");
 417                 return 0;
 418         }
 419
 420         /* Set hubbed type if true */
 421         uv_hub_info->hub_revision =
 422                 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE :
 423                 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
 424                 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
 425                 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
 426
 427         switch (uv_hub_info->hub_revision) {
 428         case UV5_HUB_REVISION_BASE:
 429                 uv_hubbed_system = 0x21;
 430                 uv_hub_type_set(UV5);
 431                 break;
 432
 433         case UV4_HUB_REVISION_BASE:
 434                 uv_hubbed_system = 0x11;
 435                 uv_hub_type_set(UV4);
 436                 break;
 437
 438         case UV3_HUB_REVISION_BASE:
 439                 uv_hubbed_system = 0x9;
 440                 uv_hub_type_set(UV3);
 441                 break;
 442
 443         case UV2_HUB_REVISION_BASE:
 444                 uv_hubbed_system = 0x5;
 445                 uv_hub_type_set(UV2);
 446                 break;
 447
 448         default:
 449                 return 0;
 450         }
 451
 452         /* Get UV hub chip part number & revision */
 453         early_set_hub_type();
 454
 455         /* Other UV setup functions */
 456         early_get_pnodeid();
 457         early_get_apic_socketid_shift();
 458         x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
 459         x86_platform.nmi_init = uv_nmi_init;
 460         uv_tsc_check_sync();
 461
 462         return 1;
 463 }
 464
 465 /* Called early to probe for the correct APIC driver */
 466 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
 467 {
 468         /* Set up early hub info fields for Node 0 */
 469         uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
 470
 471         /* If not UV, return. */
 472         if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
 473                 return 0;
 474
 475         /* Save and Decode OEM Table ID */
 476         uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
 477
 478         /* This is the most common hardware variant, x2apic mode */
 479         if (!strcmp(oem_table_id, "UVX"))
 480                 uv_system_type = UV_X2APIC;
 481
 482         /* Only used for very small systems, usually 1 chassis, legacy mode  */
 483         else if (!strcmp(oem_table_id, "UVL"))
 484                 uv_system_type = UV_LEGACY_APIC;
 485
 486         else
 487                 goto badbios;
 488
 489         pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
 490                 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
 491                 uv_min_hub_revision_id);
 492
 493         return 0;
 494
 495 badbios:
 496         pr_err("UV: UVarchtype:%s not supported\n", uv_archtype);
 497         BUG();
 498 }
 499
 500 enum uv_system_type get_uv_system_type(void)
 501 {
 502         return uv_system_type;
 503 }
 504
 505 int is_uv_system(void)
 506 {
 507         return uv_system_type != UV_NONE;
 508 }
 509 EXPORT_SYMBOL_GPL(is_uv_system);
 510
 511 int is_uv_hubbed(int uvtype)
 512 {
 513         return (uv_hubbed_system & uvtype);
 514 }
 515 EXPORT_SYMBOL_GPL(is_uv_hubbed);
 516
 517 static int is_uv_hubless(int uvtype)
 518 {
 519         return (uv_hubless_system & uvtype);
 520 }
 521
 522 void **__uv_hub_info_list;
 523 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
 524
 525 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
 526 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
 527
 528 short uv_possible_blades;
 529 EXPORT_SYMBOL_GPL(uv_possible_blades);
 530
 531 unsigned long sn_rtc_cycles_per_second;
 532 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 533
 534 /* The following values are used for the per node hub info struct */
 535 static __initdata unsigned short                *_node_to_pnode;
 536 static __initdata unsigned short                _min_socket, _max_socket;
 537 static __initdata unsigned short                _min_pnode, _max_pnode, _gr_table_len;
 538 static __initdata struct uv_gam_range_entry     *uv_gre_table;
 539 static __initdata struct uv_gam_parameters      *uv_gp_table;
 540 static __initdata unsigned short                *_socket_to_node;
 541 static __initdata unsigned short                *_socket_to_pnode;
 542 static __initdata unsigned short                *_pnode_to_socket;
 543
 544 static __initdata struct uv_gam_range_s         *_gr_table;
 545
 546 #define SOCK_EMPTY      ((unsigned short)~0)
 547
 548 /* Default UV memory block size is 2GB */
 549 static unsigned long mem_block_size __initdata = (2UL << 30);
 550
 551 /* Kernel parameter to specify UV mem block size */
 552 static int __init parse_mem_block_size(char *ptr)
 553 {
 554         unsigned long size = memparse(ptr, NULL);
 555
 556         /* Size will be rounded down by set_block_size() below */
 557         mem_block_size = size;
 558         return 0;
 559 }
 560 early_param("uv_memblksize", parse_mem_block_size);
 561
 562 static __init int adj_blksize(u32 lgre)
 563 {
 564         unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
 565         unsigned long size;
 566
 567         for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
 568                 if (IS_ALIGNED(base, size))
 569                         break;
 570
 571         if (size >= mem_block_size)
 572                 return 0;
 573
 574         mem_block_size = size;
 575         return 1;
 576 }
 577
 578 static __init void set_block_size(void)
 579 {
 580         unsigned int order = ffs(mem_block_size);
 581
 582         if (order) {
 583                 /* adjust for ffs return of 1..64 */
 584                 set_memory_block_size_order(order - 1);
 585                 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
 586         } else {
 587                 /* bad or zero value, default to 1UL << 31 (2GB) */
 588                 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
 589                 set_memory_block_size_order(31);
 590         }
 591 }
 592
 593 /* Build GAM range lookup table: */
 594 static __init void build_uv_gr_table(void)
 595 {
 596         struct uv_gam_range_entry *gre = uv_gre_table;
 597         struct uv_gam_range_s *grt;
 598         unsigned long last_limit = 0, ram_limit = 0;
 599         int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
 600
 601         if (!gre)
 602                 return;
 603
 604         bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
 605         grt = kzalloc(bytes, GFP_KERNEL);
 606         BUG_ON(!grt);
 607         _gr_table = grt;
 608
 609         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
 610                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
 611                         if (!ram_limit) {
 612                                 /* Mark hole between RAM/non-RAM: */
 613                                 ram_limit = last_limit;
 614                                 last_limit = gre->limit;
 615                                 lsid++;
 616                                 continue;
 617                         }
 618                         last_limit = gre->limit;
 619                         pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
 620                         continue;
 621                 }
 622                 if (_max_socket < gre->sockid) {
 623                         pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
 624                         continue;
 625                 }
 626                 sid = gre->sockid - _min_socket;
 627                 if (lsid < sid) {
 628                         /* New range: */
 629                         grt = &_gr_table[indx];
 630                         grt->base = lindx;
 631                         grt->nasid = gre->nasid;
 632                         grt->limit = last_limit = gre->limit;
 633                         lsid = sid;
 634                         lindx = indx++;
 635                         continue;
 636                 }
 637                 /* Update range: */
 638                 if (lsid == sid && !ram_limit) {
 639                         /* .. if contiguous: */
 640                         if (grt->limit == last_limit) {
 641                                 grt->limit = last_limit = gre->limit;
 642                                 continue;
 643                         }
 644                 }
 645                 /* Non-contiguous RAM range: */
 646                 if (!ram_limit) {
 647                         grt++;
 648                         grt->base = lindx;
 649                         grt->nasid = gre->nasid;
 650                         grt->limit = last_limit = gre->limit;
 651                         continue;
 652                 }
 653                 /* Non-contiguous/non-RAM: */
 654                 grt++;
 655                 /* base is this entry */
 656                 grt->base = grt - _gr_table;
 657                 grt->nasid = gre->nasid;
 658                 grt->limit = last_limit = gre->limit;
 659                 lsid++;
 660         }
 661
 662         /* Shorten table if possible */
 663         grt++;
 664         i = grt - _gr_table;
 665         if (i < _gr_table_len) {
 666                 void *ret;
 667
 668                 bytes = i * sizeof(struct uv_gam_range_s);
 669                 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
 670                 if (ret) {
 671                         _gr_table = ret;
 672                         _gr_table_len = i;
 673                 }
 674         }
 675
 676         /* Display resultant GAM range table: */
 677         for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
 678                 unsigned long start, end;
 679                 int gb = grt->base;
 680
 681                 start = gb < 0 ?  0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
 682                 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
 683
 684                 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
 685         }
 686 }
 687
 688 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 689 {
 690         unsigned long val;
 691         int pnode;
 692
 693         pnode = uv_apicid_to_pnode(phys_apicid);
 694
 695         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 696             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 697             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 698             APIC_DM_INIT;
 699
 700         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 701
 702         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 703             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 704             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 705             APIC_DM_STARTUP;
 706
 707         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 708
 709         return 0;
 710 }
 711
 712 static void uv_send_IPI_one(int cpu, int vector)
 713 {
 714         unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
 715         int pnode = uv_apicid_to_pnode(apicid);
 716         unsigned long dmode, val;
 717
 718         if (vector == NMI_VECTOR)
 719                 dmode = dest_NMI;
 720         else
 721                 dmode = dest_Fixed;
 722
 723         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 724                 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 725                 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
 726                 (vector << UVH_IPI_INT_VECTOR_SHFT);
 727
 728         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 729 }
 730
 731 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 732 {
 733         unsigned int cpu;
 734
 735         for_each_cpu(cpu, mask)
 736                 uv_send_IPI_one(cpu, vector);
 737 }
 738
 739 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 740 {
 741         unsigned int this_cpu = smp_processor_id();
 742         unsigned int cpu;
 743
 744         for_each_cpu(cpu, mask) {
 745                 if (cpu != this_cpu)
 746                         uv_send_IPI_one(cpu, vector);
 747         }
 748 }
 749
 750 static void uv_send_IPI_allbutself(int vector)
 751 {
 752         unsigned int this_cpu = smp_processor_id();
 753         unsigned int cpu;
 754
 755         for_each_online_cpu(cpu) {
 756                 if (cpu != this_cpu)
 757                         uv_send_IPI_one(cpu, vector);
 758         }
 759 }
 760
 761 static void uv_send_IPI_all(int vector)
 762 {
 763         uv_send_IPI_mask(cpu_online_mask, vector);
 764 }
 765
 766 static int uv_apic_id_valid(u32 apicid)
 767 {
 768         return 1;
 769 }
 770
 771 static int uv_apic_id_registered(void)
 772 {
 773         return 1;
 774 }
 775
 776 static void uv_init_apic_ldr(void)
 777 {
 778 }
 779
 780 static u32 apic_uv_calc_apicid(unsigned int cpu)
 781 {
 782         return apic_default_calc_apicid(cpu);
 783 }
 784
 785 static unsigned int x2apic_get_apic_id(unsigned long id)
 786 {
 787         return id;
 788 }
 789
 790 static u32 set_apic_id(unsigned int id)
 791 {
 792         return id;
 793 }
 794
 795 static unsigned int uv_read_apic_id(void)
 796 {
 797         return x2apic_get_apic_id(apic_read(APIC_ID));
 798 }
 799
 800 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 801 {
 802         return uv_read_apic_id() >> index_msb;
 803 }
 804
 805 static void uv_send_IPI_self(int vector)
 806 {
 807         apic_write(APIC_SELF_IPI, vector);
 808 }
 809
 810 static int uv_probe(void)
 811 {
 812         return apic == &apic_x2apic_uv_x;
 813 }
 814
 815 static struct apic apic_x2apic_uv_x __ro_after_init = {
 816
 817         .name                           = "UV large system",
 818         .probe                          = uv_probe,
 819         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 820         .apic_id_valid                  = uv_apic_id_valid,
 821         .apic_id_registered             = uv_apic_id_registered,
 822
 823         .irq_delivery_mode              = dest_Fixed,
 824         .irq_dest_mode                  = 0, /* Physical */
 825
 826         .disable_esr                    = 0,
 827         .dest_logical                   = APIC_DEST_LOGICAL,
 828         .check_apicid_used              = NULL,
 829
 830         .init_apic_ldr                  = uv_init_apic_ldr,
 831
 832         .ioapic_phys_id_map             = NULL,
 833         .setup_apic_routing             = NULL,
 834         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 835         .apicid_to_cpu_present          = NULL,
 836         .check_phys_apicid_present      = default_check_phys_apicid_present,
 837         .phys_pkg_id                    = uv_phys_pkg_id,
 838
 839         .get_apic_id                    = x2apic_get_apic_id,
 840         .set_apic_id                    = set_apic_id,
 841
 842         .calc_dest_apicid               = apic_uv_calc_apicid,
 843
 844         .send_IPI                       = uv_send_IPI_one,
 845         .send_IPI_mask                  = uv_send_IPI_mask,
 846         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 847         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 848         .send_IPI_all                   = uv_send_IPI_all,
 849         .send_IPI_self                  = uv_send_IPI_self,
 850
 851         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 852         .inquire_remote_apic            = NULL,
 853
 854         .read                           = native_apic_msr_read,
 855         .write                          = native_apic_msr_write,
 856         .eoi_write                      = native_apic_msr_eoi_write,
 857         .icr_read                       = native_x2apic_icr_read,
 858         .icr_write                      = native_x2apic_icr_write,
 859         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 860         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 861 };
 862
 863 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
 864 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
 865
 866 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 867 {
 868         union uvh_rh_gam_alias_2_overlay_config_u alias;
 869         union uvh_rh_gam_alias_2_redirect_config_u redirect;
 870         unsigned long m_redirect;
 871         unsigned long m_overlay;
 872         int i;
 873
 874         for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
 875                 switch (i) {
 876                 case 0:
 877                         m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
 878                         m_overlay  = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
 879                         break;
 880                 case 1:
 881                         m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
 882                         m_overlay  = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
 883                         break;
 884                 case 2:
 885                         m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
 886                         m_overlay  = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
 887                         break;
 888                 }
 889                 alias.v = uv_read_local_mmr(m_overlay);
 890                 if (alias.s.enable && alias.s.base == 0) {
 891                         *size = (1UL << alias.s.m_alias);
 892                         redirect.v = uv_read_local_mmr(m_redirect);
 893                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 894                         return;
 895                 }
 896         }
 897         *base = *size = 0;
 898 }
 899
 900 enum map_type {map_wb, map_uc};
 901 static const char * const mt[] = { "WB", "UC" };
 902
 903 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
 904 {
 905         unsigned long bytes, paddr;
 906
 907         paddr = base << pshift;
 908         bytes = (1UL << bshift) * (max_pnode + 1);
 909         if (!paddr) {
 910                 pr_info("UV: Map %s_HI base address NULL\n", id);
 911                 return;
 912         }
 913         if (map_type == map_uc)
 914                 init_extra_mapping_uc(paddr, bytes);
 915         else
 916                 init_extra_mapping_wb(paddr, bytes);
 917
 918         pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
 919                 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
 920 }
 921
 922 static __init void map_gru_high(int max_pnode)
 923 {
 924         union uvh_rh_gam_gru_overlay_config_u gru;
 925         unsigned long mask, base;
 926         int shift;
 927
 928         if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) {
 929                 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
 930                 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
 931                 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
 932         } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) {
 933                 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
 934                 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
 935                 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
 936         } else {
 937                 pr_err("UV: GRU unavailable (no MMR)\n");
 938                 return;
 939         }
 940
 941         if (!gru.s.enable) {
 942                 pr_info("UV: GRU disabled (by BIOS)\n");
 943                 return;
 944         }
 945
 946         base = (gru.v & mask) >> shift;
 947         map_high("GRU", base, shift, shift, max_pnode, map_wb);
 948         gru_start_paddr = ((u64)base << shift);
 949         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 950 }
 951
 952 static __init void map_mmr_high(int max_pnode)
 953 {
 954         unsigned long base;
 955         int shift;
 956         bool enable;
 957
 958         if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) {
 959                 union uvh_rh10_gam_mmr_overlay_config_u mmr;
 960
 961                 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
 962                 enable = mmr.s.enable;
 963                 base = mmr.s.base;
 964                 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
 965         } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) {
 966                 union uvh_rh_gam_mmr_overlay_config_u mmr;
 967
 968                 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
 969                 enable = mmr.s.enable;
 970                 base = mmr.s.base;
 971                 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
 972         } else {
 973                 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n",
 974                         __func__);
 975                 return;
 976         }
 977
 978         if (enable)
 979                 map_high("MMR", base, shift, shift, max_pnode, map_uc);
 980         else
 981                 pr_info("UV: MMR disabled\n");
 982 }
 983
 984 /* Arch specific ENUM cases */
 985 enum mmioh_arch {
 986         UV2_MMIOH = -1,
 987         UVY_MMIOH0, UVY_MMIOH1,
 988         UVX_MMIOH0, UVX_MMIOH1,
 989 };
 990
 991 /* Calculate and Map MMIOH Regions */
 992 static void __init calc_mmioh_map(enum mmioh_arch index,
 993         int min_pnode, int max_pnode,
 994         int shift, unsigned long base, int m_io, int n_io)
 995 {
 996         unsigned long mmr, nasid_mask;
 997         int nasid, min_nasid, max_nasid, lnasid, mapped;
 998         int i, fi, li, n, max_io;
 999         char id[8];
1000
1001         /* One (UV2) mapping */
1002         if (index == UV2_MMIOH) {
1003                 strncpy(id, "MMIOH", sizeof(id));
1004                 max_io = max_pnode;
1005                 mapped = 0;
1006                 goto map_exit;
1007         }
1008
1009         /* small and large MMIOH mappings */
1010         switch (index) {
1011         case UVY_MMIOH0:
1012                 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
1013                 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1014                 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1015                 min_nasid = min_pnode;
1016                 max_nasid = max_pnode;
1017                 mapped = 1;
1018                 break;
1019         case UVY_MMIOH1:
1020                 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
1021                 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1022                 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1023                 min_nasid = min_pnode;
1024                 max_nasid = max_pnode;
1025                 mapped = 1;
1026                 break;
1027         case UVX_MMIOH0:
1028                 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
1029                 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1030                 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1031                 min_nasid = min_pnode * 2;
1032                 max_nasid = max_pnode * 2;
1033                 mapped = 1;
1034                 break;
1035         case UVX_MMIOH1:
1036                 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
1037                 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1038                 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1039                 min_nasid = min_pnode * 2;
1040                 max_nasid = max_pnode * 2;
1041                 mapped = 1;
1042                 break;
1043         default:
1044                 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
1045                 return;
1046         }
1047
1048         /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */
1049         snprintf(id, sizeof(id), "MMIOH%d", index%2);
1050
1051         max_io = lnasid = fi = li = -1;
1052         for (i = 0; i < n; i++) {
1053                 unsigned long m_redirect = mmr + i * 8;
1054                 unsigned long redirect = uv_read_local_mmr(m_redirect);
1055
1056                 nasid = redirect & nasid_mask;
1057                 if (i == 0)
1058                         pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
1059                                 id, redirect, m_redirect, nasid);
1060
1061                 /* Invalid NASID check */
1062                 if (nasid < min_nasid || max_nasid < nasid) {
1063                         pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n",
1064                                 __func__, index, min_nasid, max_nasid);
1065                         nasid = -1;
1066                 }
1067
1068                 if (nasid == lnasid) {
1069                         li = i;
1070                         /* Last entry check: */
1071                         if (i != n-1)
1072                                 continue;
1073                 }
1074
1075                 /* Check if we have a cached (or last) redirect to print: */
1076                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
1077                         unsigned long addr1, addr2;
1078                         int f, l;
1079
1080                         if (lnasid == -1) {
1081                                 f = l = i;
1082                                 lnasid = nasid;
1083                         } else {
1084                                 f = fi;
1085                                 l = li;
1086                         }
1087                         addr1 = (base << shift) + f * (1ULL << m_io);
1088                         addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
1089                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
1090                                 id, fi, li, lnasid, addr1, addr2);
1091                         if (max_io < l)
1092                                 max_io = l;
1093                 }
1094                 fi = li = i;
1095                 lnasid = nasid;
1096         }
1097
1098 map_exit:
1099         pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
1100                 id, base, shift, m_io, max_io, max_pnode);
1101
1102         if (max_io >= 0 && !mapped)
1103                 map_high(id, base, shift, m_io, max_io, map_uc);
1104 }
1105
1106 static __init void map_mmioh_high(int min_pnode, int max_pnode)
1107 {
1108         /* UVY flavor */
1109         if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
1110                 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
1111                 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
1112
1113                 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
1114                 if (unlikely(mmioh0.s.enable == 0))
1115                         pr_info("UV: MMIOH0 disabled\n");
1116                 else
1117                         calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
1118                                 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1119                                 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
1120
1121                 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
1122                 if (unlikely(mmioh1.s.enable == 0))
1123                         pr_info("UV: MMIOH1 disabled\n");
1124                 else
1125                         calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
1126                                 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1127                                 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
1128                 return;
1129         }
1130         /* UVX flavor */
1131         if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
1132                 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
1133                 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
1134
1135                 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
1136                 if (unlikely(mmioh0.s.enable == 0))
1137                         pr_info("UV: MMIOH0 disabled\n");
1138                 else {
1139                         unsigned long base = uvxy_field(mmioh0, base, 0);
1140                         int m_io = uvxy_field(mmioh0, m_io, 0);
1141                         int n_io = uvxy_field(mmioh0, n_io, 0);
1142
1143                         calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
1144                                 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1145                                 base, m_io, n_io);
1146                 }
1147
1148                 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
1149                 if (unlikely(mmioh1.s.enable == 0))
1150                         pr_info("UV: MMIOH1 disabled\n");
1151                 else {
1152                         unsigned long base = uvxy_field(mmioh1, base, 0);
1153                         int m_io = uvxy_field(mmioh1, m_io, 0);
1154                         int n_io = uvxy_field(mmioh1, n_io, 0);
1155
1156                         calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
1157                                 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1158                                 base, m_io, n_io);
1159                 }
1160                 return;
1161         }
1162
1163         /* UV2 flavor */
1164         if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
1165                 union uvh_rh_gam_mmioh_overlay_config_u mmioh;
1166
1167                 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
1168                 if (unlikely(mmioh.s2.enable == 0))
1169                         pr_info("UV: MMIOH disabled\n");
1170                 else
1171                         calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
1172                                 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
1173                                 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
1174                 return;
1175         }
1176 }
1177
1178 static __init void map_low_mmrs(void)
1179 {
1180         if (UV_GLOBAL_MMR32_BASE)
1181                 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1182
1183         if (UV_LOCAL_MMR_BASE)
1184                 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1185 }
1186
1187 static __init void uv_rtc_init(void)
1188 {
1189         long status;
1190         u64 ticks_per_sec;
1191
1192         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1193
1194         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1195                 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1196
1197                 /* BIOS gives wrong value for clock frequency, so guess: */
1198                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1199         } else {
1200                 sn_rtc_cycles_per_second = ticks_per_sec;
1201         }
1202 }
1203
1204 /* Direct Legacy VGA I/O traffic to designated IOH */
1205 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1206 {
1207         int domain, bus, rc;
1208
1209         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1210                 return 0;
1211
1212         if ((command_bits & PCI_COMMAND_IO) == 0)
1213                 return 0;
1214
1215         domain = pci_domain_nr(pdev->bus);
1216         bus = pdev->bus->number;
1217
1218         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1219
1220         return rc;
1221 }
1222
1223 /*
1224  * Called on each CPU to initialize the per_cpu UV data area.
1225  * FIXME: hotplug not supported yet
1226  */
1227 void uv_cpu_init(void)
1228 {
1229         /* CPU 0 initialization will be done via uv_system_init. */
1230         if (smp_processor_id() == 0)
1231                 return;
1232
1233         uv_hub_info->nr_online_cpus++;
1234 }
1235
1236 struct mn {
1237         unsigned char   m_val;
1238         unsigned char   n_val;
1239         unsigned char   m_shift;
1240         unsigned char   n_lshift;
1241 };
1242
1243 /* Initialize caller's MN struct and fill in values */
1244 static void get_mn(struct mn *mnp)
1245 {
1246         memset(mnp, 0, sizeof(*mnp));
1247         mnp->n_val      = uv_cpuid.n_skt;
1248         if (is_uv(UV4|UVY)) {
1249                 mnp->m_val      = 0;
1250                 mnp->n_lshift   = 0;
1251         } else if (is_uv3_hub()) {
1252                 union uvyh_gr0_gam_gr_config_u m_gr_config;
1253
1254                 mnp->m_val      = uv_cpuid.m_skt;
1255                 m_gr_config.v   = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1256                 mnp->n_lshift   = m_gr_config.s3.m_skt;
1257         } else if (is_uv2_hub()) {
1258                 mnp->m_val      = uv_cpuid.m_skt;
1259                 mnp->n_lshift   = mnp->m_val == 40 ? 40 : 39;
1260         }
1261         mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1262 }
1263
1264 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1265 {
1266         struct mn mn;
1267
1268         get_mn(&mn);
1269         hi->gpa_mask = mn.m_val ?
1270                 (1UL << (mn.m_val + mn.n_val)) - 1 :
1271                 (1UL << uv_cpuid.gpa_shift) - 1;
1272
1273         hi->m_val               = mn.m_val;
1274         hi->n_val               = mn.n_val;
1275         hi->m_shift             = mn.m_shift;
1276         hi->n_lshift            = mn.n_lshift ? mn.n_lshift : 0;
1277         hi->hub_revision        = uv_hub_info->hub_revision;
1278         hi->hub_type            = uv_hub_info->hub_type;
1279         hi->pnode_mask          = uv_cpuid.pnode_mask;
1280         hi->nasid_shift         = uv_cpuid.nasid_shift;
1281         hi->min_pnode           = _min_pnode;
1282         hi->min_socket          = _min_socket;
1283         hi->pnode_to_socket     = _pnode_to_socket;
1284         hi->socket_to_node      = _socket_to_node;
1285         hi->socket_to_pnode     = _socket_to_pnode;
1286         hi->gr_table_len        = _gr_table_len;
1287         hi->gr_table            = _gr_table;
1288
1289         uv_cpuid.gnode_shift    = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1290         hi->gnode_extra         = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1291         if (mn.m_val)
1292                 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1293
1294         if (uv_gp_table) {
1295                 hi->global_mmr_base     = uv_gp_table->mmr_base;
1296                 hi->global_mmr_shift    = uv_gp_table->mmr_shift;
1297                 hi->global_gru_base     = uv_gp_table->gru_base;
1298                 hi->global_gru_shift    = uv_gp_table->gru_shift;
1299                 hi->gpa_shift           = uv_gp_table->gpa_shift;
1300                 hi->gpa_mask            = (1UL << hi->gpa_shift) - 1;
1301         } else {
1302                 hi->global_mmr_base     =
1303                         uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1304                         ~UV_MMR_ENABLE;
1305                 hi->global_mmr_shift    = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1306         }
1307
1308         get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1309
1310         hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1311
1312         /* Show system specific info: */
1313         pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1314         pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1315         pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift);
1316         if (hi->global_gru_base)
1317                 pr_info("UV: gru_base/shift:0x%lx/%ld\n",
1318                         hi->global_gru_base, hi->global_gru_shift);
1319
1320         pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1321 }
1322
1323 static void __init decode_gam_params(unsigned long ptr)
1324 {
1325         uv_gp_table = (struct uv_gam_parameters *)ptr;
1326
1327         pr_info("UV: GAM Params...\n");
1328         pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1329                 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1330                 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1331                 uv_gp_table->gpa_shift);
1332 }
1333
1334 static void __init decode_gam_rng_tbl(unsigned long ptr)
1335 {
1336         struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1337         unsigned long lgre = 0;
1338         int index = 0;
1339         int sock_min = 999999, pnode_min = 99999;
1340         int sock_max = -1, pnode_max = -1;
1341
1342         uv_gre_table = gre;
1343         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1344                 unsigned long size = ((unsigned long)(gre->limit - lgre)
1345                                         << UV_GAM_RANGE_SHFT);
1346                 int order = 0;
1347                 char suffix[] = " KMGTPE";
1348                 int flag = ' ';
1349
1350                 while (size > 9999 && order < sizeof(suffix)) {
1351                         size /= 1024;
1352                         order++;
1353                 }
1354
1355                 /* adjust max block size to current range start */
1356                 if (gre->type == 1 || gre->type == 2)
1357                         if (adj_blksize(lgre))
1358                                 flag = '*';
1359
1360                 if (!index) {
1361                         pr_info("UV: GAM Range Table...\n");
1362                         pr_info("UV:  # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1363                 }
1364                 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d   %04x  %02x %02x\n",
1365                         index++,
1366                         (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1367                         (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1368                         flag, size, suffix[order],
1369                         gre->type, gre->nasid, gre->sockid, gre->pnode);
1370
1371                 /* update to next range start */
1372                 lgre = gre->limit;
1373                 if (sock_min > gre->sockid)
1374                         sock_min = gre->sockid;
1375                 if (sock_max < gre->sockid)
1376                         sock_max = gre->sockid;
1377                 if (pnode_min > gre->pnode)
1378                         pnode_min = gre->pnode;
1379                 if (pnode_max < gre->pnode)
1380                         pnode_max = gre->pnode;
1381         }
1382         _min_socket     = sock_min;
1383         _max_socket     = sock_max;
1384         _min_pnode      = pnode_min;
1385         _max_pnode      = pnode_max;
1386         _gr_table_len   = index;
1387
1388         pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1389 }
1390
1391 /* Walk through UVsystab decoding the fields */
1392 static int __init decode_uv_systab(void)
1393 {
1394         struct uv_systab *st;
1395         int i;
1396
1397         /* Get mapped UVsystab pointer */
1398         st = uv_systab;
1399
1400         /* If UVsystab is version 1, there is no extended UVsystab */
1401         if (st && st->revision == UV_SYSTAB_VERSION_1)
1402                 return 0;
1403
1404         if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1405                 int rev = st ? st->revision : 0;
1406
1407                 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n",
1408                         rev, UV_SYSTAB_VERSION_UV4_LATEST);
1409                 pr_err("UV: Does not support UV, switch to non-UV x86_64\n");
1410                 uv_system_type = UV_NONE;
1411
1412                 return -EINVAL;
1413         }
1414
1415         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1416                 unsigned long ptr = st->entry[i].offset;
1417
1418                 if (!ptr)
1419                         continue;
1420
1421                 /* point to payload */
1422                 ptr += (unsigned long)st;
1423
1424                 switch (st->entry[i].type) {
1425                 case UV_SYSTAB_TYPE_GAM_PARAMS:
1426                         decode_gam_params(ptr);
1427                         break;
1428
1429                 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1430                         decode_gam_rng_tbl(ptr);
1431                         break;
1432
1433                 case UV_SYSTAB_TYPE_ARCH_TYPE:
1434                         /* already processed in early startup */
1435                         break;
1436
1437                 default:
1438                         pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n",
1439                                 __func__, st->entry[i].type);
1440                         break;
1441                 }
1442         }
1443         return 0;
1444 }
1445
1446 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */
1447 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1448 {
1449         unsigned long np;
1450         int i, uv_pb = 0;
1451
1452         if (UVH_NODE_PRESENT_TABLE) {
1453                 pr_info("UV: NODE_PRESENT_DEPTH = %d\n",
1454                         UVH_NODE_PRESENT_TABLE_DEPTH);
1455                 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1456                         np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1457                         pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1458                         uv_pb += hweight64(np);
1459                 }
1460         }
1461         if (UVH_NODE_PRESENT_0) {
1462                 np = uv_read_local_mmr(UVH_NODE_PRESENT_0);
1463                 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np);
1464                 uv_pb += hweight64(np);
1465         }
1466         if (UVH_NODE_PRESENT_1) {
1467                 np = uv_read_local_mmr(UVH_NODE_PRESENT_1);
1468                 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np);
1469                 uv_pb += hweight64(np);
1470         }
1471         if (uv_possible_blades != uv_pb)
1472                 uv_possible_blades = uv_pb;
1473
1474         pr_info("UV: number nodes/possible blades %d\n", uv_pb);
1475 }
1476
1477 static void __init build_socket_tables(void)
1478 {
1479         struct uv_gam_range_entry *gre = uv_gre_table;
1480         int num, nump;
1481         int cpu, i, lnid;
1482         int minsock = _min_socket;
1483         int maxsock = _max_socket;
1484         int minpnode = _min_pnode;
1485         int maxpnode = _max_pnode;
1486         size_t bytes;
1487
1488         if (!gre) {
1489                 if (is_uv2_hub() || is_uv3_hub()) {
1490                         pr_info("UV: No UVsystab socket table, ignoring\n");
1491                         return;
1492                 }
1493                 pr_err("UV: Error: UVsystab address translations not available!\n");
1494                 BUG();
1495         }
1496
1497         /* Build socket id -> node id, pnode */
1498         num = maxsock - minsock + 1;
1499         bytes = num * sizeof(_socket_to_node[0]);
1500         _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1501         _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1502
1503         nump = maxpnode - minpnode + 1;
1504         bytes = nump * sizeof(_pnode_to_socket[0]);
1505         _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1506         BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1507
1508         for (i = 0; i < num; i++)
1509                 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1510
1511         for (i = 0; i < nump; i++)
1512                 _pnode_to_socket[i] = SOCK_EMPTY;
1513
1514         /* Fill in pnode/node/addr conversion list values: */
1515         pr_info("UV: GAM Building socket/pnode conversion tables\n");
1516         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1517                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1518                         continue;
1519                 i = gre->sockid - minsock;
1520                 /* Duplicate: */
1521                 if (_socket_to_pnode[i] != SOCK_EMPTY)
1522                         continue;
1523                 _socket_to_pnode[i] = gre->pnode;
1524
1525                 i = gre->pnode - minpnode;
1526                 _pnode_to_socket[i] = gre->sockid;
1527
1528                 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1529                         gre->sockid, gre->type, gre->nasid,
1530                         _socket_to_pnode[gre->sockid - minsock],
1531                         _pnode_to_socket[gre->pnode - minpnode]);
1532         }
1533
1534         /* Set socket -> node values: */
1535         lnid = NUMA_NO_NODE;
1536         for_each_present_cpu(cpu) {
1537                 int nid = cpu_to_node(cpu);
1538                 int apicid, sockid;
1539
1540                 if (lnid == nid)
1541                         continue;
1542                 lnid = nid;
1543                 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1544                 sockid = apicid >> uv_cpuid.socketid_shift;
1545                 _socket_to_node[sockid - minsock] = nid;
1546                 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1547                         sockid, apicid, nid);
1548         }
1549
1550         /* Set up physical blade to pnode translation from GAM Range Table: */
1551         bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1552         _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1553         BUG_ON(!_node_to_pnode);
1554
1555         for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1556                 unsigned short sockid;
1557
1558                 for (sockid = minsock; sockid <= maxsock; sockid++) {
1559                         if (lnid == _socket_to_node[sockid - minsock]) {
1560                                 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1561                                 break;
1562                         }
1563                 }
1564                 if (sockid > maxsock) {
1565                         pr_err("UV: socket for node %d not found!\n", lnid);
1566                         BUG();
1567                 }
1568         }
1569
1570         /*
1571          * If socket id == pnode or socket id == node for all nodes,
1572          *   system runs faster by removing corresponding conversion table.
1573          */
1574         pr_info("UV: Checking socket->node/pnode for identity maps\n");
1575         if (minsock == 0) {
1576                 for (i = 0; i < num; i++)
1577                         if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1578                                 break;
1579                 if (i >= num) {
1580                         kfree(_socket_to_node);
1581                         _socket_to_node = NULL;
1582                         pr_info("UV: 1:1 socket_to_node table removed\n");
1583                 }
1584         }
1585         if (minsock == minpnode) {
1586                 for (i = 0; i < num; i++)
1587                         if (_socket_to_pnode[i] != SOCK_EMPTY &&
1588                                 _socket_to_pnode[i] != i + minpnode)
1589                                 break;
1590                 if (i >= num) {
1591                         kfree(_socket_to_pnode);
1592                         _socket_to_pnode = NULL;
1593                         pr_info("UV: 1:1 socket_to_pnode table removed\n");
1594                 }
1595         }
1596 }
1597
1598 /* Check which reboot to use */
1599 static void check_efi_reboot(void)
1600 {
1601         /* If EFI reboot not available, use ACPI reboot */
1602         if (!efi_enabled(EFI_BOOT))
1603                 reboot_type = BOOT_ACPI;
1604 }
1605
1606 /* Setup user proc fs files */
1607 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1608 {
1609         seq_printf(file, "0x%x\n", uv_hubbed_system);
1610         return 0;
1611 }
1612
1613 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1614 {
1615         seq_printf(file, "0x%x\n", uv_hubless_system);
1616         return 0;
1617 }
1618
1619 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data)
1620 {
1621         seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id);
1622         return 0;
1623 }
1624
1625 static __init void uv_setup_proc_files(int hubless)
1626 {
1627         struct proc_dir_entry *pde;
1628
1629         pde = proc_mkdir(UV_PROC_NODE, NULL);
1630         proc_create_single("archtype", 0, pde, proc_archtype_show);
1631         if (hubless)
1632                 proc_create_single("hubless", 0, pde, proc_hubless_show);
1633         else
1634                 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1635 }
1636
1637 /* Initialize UV hubless systems */
1638 static __init int uv_system_init_hubless(void)
1639 {
1640         int rc;
1641
1642         /* Setup PCH NMI handler */
1643         uv_nmi_setup_hubless();
1644
1645         /* Init kernel/BIOS interface */
1646         rc = uv_bios_init();
1647         if (rc < 0)
1648                 return rc;
1649
1650         /* Process UVsystab */
1651         rc = decode_uv_systab();
1652         if (rc < 0)
1653                 return rc;
1654
1655         /* Create user access node */
1656         if (rc >= 0)
1657                 uv_setup_proc_files(1);
1658
1659         check_efi_reboot();
1660
1661         return rc;
1662 }
1663
1664 static void __init uv_system_init_hub(void)
1665 {
1666         struct uv_hub_info_s hub_info = {0};
1667         int bytes, cpu, nodeid;
1668         unsigned short min_pnode = 9999, max_pnode = 0;
1669         char *hub = is_uv5_hub() ? "UV500" :
1670                     is_uv4_hub() ? "UV400" :
1671                     is_uv3_hub() ? "UV300" :
1672                     is_uv2_hub() ? "UV2000/3000" : NULL;
1673
1674         if (!hub) {
1675                 pr_err("UV: Unknown/unsupported UV hub\n");
1676                 return;
1677         }
1678         pr_info("UV: Found %s hub\n", hub);
1679
1680         map_low_mmrs();
1681
1682         /* Get uv_systab for decoding, setup UV BIOS calls */
1683         uv_bios_init();
1684
1685         /* If there's an UVsystab problem then abort UV init: */
1686         if (decode_uv_systab() < 0) {
1687                 pr_err("UV: Mangled UVsystab format\n");
1688                 return;
1689         }
1690
1691         build_socket_tables();
1692         build_uv_gr_table();
1693         set_block_size();
1694         uv_init_hub_info(&hub_info);
1695         uv_possible_blades = num_possible_nodes();
1696         if (!_node_to_pnode)
1697                 boot_init_possible_blades(&hub_info);
1698
1699         /* uv_num_possible_blades() is really the hub count: */
1700         pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1701
1702         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1703         hub_info.coherency_domain_number = sn_coherency_id;
1704         uv_rtc_init();
1705
1706         bytes = sizeof(void *) * uv_num_possible_blades();
1707         __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1708         BUG_ON(!__uv_hub_info_list);
1709
1710         bytes = sizeof(struct uv_hub_info_s);
1711         for_each_node(nodeid) {
1712                 struct uv_hub_info_s *new_hub;
1713
1714                 if (__uv_hub_info_list[nodeid]) {
1715                         pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1716                         BUG();
1717                 }
1718
1719                 /* Allocate new per hub info list */
1720                 new_hub = (nodeid == 0) ?  &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1721                 BUG_ON(!new_hub);
1722                 __uv_hub_info_list[nodeid] = new_hub;
1723                 new_hub = uv_hub_info_list(nodeid);
1724                 BUG_ON(!new_hub);
1725                 *new_hub = hub_info;
1726
1727                 /* Use information from GAM table if available: */
1728                 if (_node_to_pnode)
1729                         new_hub->pnode = _node_to_pnode[nodeid];
1730                 else /* Or fill in during CPU loop: */
1731                         new_hub->pnode = 0xffff;
1732
1733                 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1734                 new_hub->memory_nid = NUMA_NO_NODE;
1735                 new_hub->nr_possible_cpus = 0;
1736                 new_hub->nr_online_cpus = 0;
1737         }
1738
1739         /* Initialize per CPU info: */
1740         for_each_possible_cpu(cpu) {
1741                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1742                 int numa_node_id;
1743                 unsigned short pnode;
1744
1745                 nodeid = cpu_to_node(cpu);
1746                 numa_node_id = numa_cpu_node(cpu);
1747                 pnode = uv_apicid_to_pnode(apicid);
1748
1749                 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1750                 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1751                 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1752                         uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1753
1754                 /* Init memoryless node: */
1755                 if (nodeid != numa_node_id &&
1756                     uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1757                         uv_hub_info_list(numa_node_id)->pnode = pnode;
1758                 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1759                         uv_cpu_hub_info(cpu)->pnode = pnode;
1760         }
1761
1762         for_each_node(nodeid) {
1763                 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1764
1765                 /* Add pnode info for pre-GAM list nodes without CPUs: */
1766                 if (pnode == 0xffff) {
1767                         unsigned long paddr;
1768
1769                         paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1770                         pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1771                         uv_hub_info_list(nodeid)->pnode = pnode;
1772                 }
1773                 min_pnode = min(pnode, min_pnode);
1774                 max_pnode = max(pnode, max_pnode);
1775                 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1776                         nodeid,
1777                         uv_hub_info_list(nodeid)->pnode,
1778                         uv_hub_info_list(nodeid)->nr_possible_cpus);
1779         }
1780
1781         pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1782         map_gru_high(max_pnode);
1783         map_mmr_high(max_pnode);
1784         map_mmioh_high(min_pnode, max_pnode);
1785
1786         uv_nmi_setup();
1787         uv_cpu_init();
1788         uv_setup_proc_files(0);
1789
1790         /* Register Legacy VGA I/O redirection handler: */
1791         pci_register_set_vga_state(uv_set_vga_state);
1792
1793         check_efi_reboot();
1794 }
1795
1796 /*
1797  * There is a different code path needed to initialize a UV system that does
1798  * not have a "UV HUB" (referred to as "hubless").
1799  */
1800 void __init uv_system_init(void)
1801 {
1802         if (likely(!is_uv_system() && !is_uv_hubless(1)))
1803                 return;
1804
1805         if (is_uv_system())
1806                 uv_system_init_hub();
1807         else
1808                 uv_system_init_hubless();
1809 }
1810
1811 apic_driver(apic_x2apic_uv_x);