1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support of MSI, HPET and DMAR interrupts.
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * Jiang Liu <jiang.liu@linux.intel.com>
8 * Convert to hierarchical irqdomain
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/pci.h>
14 #include <linux/dmar.h>
15 #include <linux/hpet.h>
16 #include <linux/msi.h>
17 #include <asm/irqdomain.h>
18 #include <asm/msidef.h>
20 #include <asm/hw_irq.h>
22 #include <asm/irq_remapping.h>
24 struct irq_domain *x86_pci_msi_default_domain __ro_after_init;
26 static void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg)
28 msg->address_hi = MSI_ADDR_BASE_HI;
31 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
35 ((apic->irq_dest_mode == 0) ?
36 MSI_ADDR_DEST_MODE_PHYSICAL :
37 MSI_ADDR_DEST_MODE_LOGICAL) |
38 MSI_ADDR_REDIRECTION_CPU |
39 MSI_ADDR_DEST_ID(cfg->dest_apicid);
42 MSI_DATA_TRIGGER_EDGE |
43 MSI_DATA_LEVEL_ASSERT |
44 MSI_DATA_DELIVERY_FIXED |
45 MSI_DATA_VECTOR(cfg->vector);
48 void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
50 __irq_msi_compose_msg(irqd_cfg(data), msg);
53 static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg)
55 struct msi_msg msg[2] = { [1] = { }, };
57 __irq_msi_compose_msg(cfg, msg);
58 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg);
62 msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force)
64 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd);
65 struct irq_data *parent = irqd->parent_data;
69 /* Save the current configuration */
70 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
73 /* Allocate a new target vector */
74 ret = parent->chip->irq_set_affinity(parent, mask, force);
75 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
79 * For non-maskable and non-remapped MSI interrupts the migration
80 * to a different destination CPU and a different vector has to be
81 * done careful to handle the possible stray interrupt which can be
82 * caused by the non-atomic update of the address/data pair.
84 * Direct update is possible when:
85 * - The MSI is maskable (remapped MSI does not use this code path)).
86 * The quirk bit is not set in this case.
87 * - The new vector is the same as the old vector
88 * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up)
89 * - The new destination CPU is the same as the old destination CPU
91 if (!irqd_msi_nomask_quirk(irqd) ||
92 cfg->vector == old_cfg.vector ||
93 old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR ||
94 cfg->dest_apicid == old_cfg.dest_apicid) {
95 irq_msi_update_msg(irqd, cfg);
100 * Paranoia: Validate that the interrupt target is the local
103 if (WARN_ON_ONCE(cpu != smp_processor_id())) {
104 irq_msi_update_msg(irqd, cfg);
109 * Redirect the interrupt to the new vector on the current CPU
110 * first. This might cause a spurious interrupt on this vector if
111 * the device raises an interrupt right between this update and the
112 * update to the final destination CPU.
114 * If the vector is in use then the installed device handler will
115 * denote it as spurious which is no harm as this is a rare event
116 * and interrupt handlers have to cope with spurious interrupts
117 * anyway. If the vector is unused, then it is marked so it won't
118 * trigger the 'No irq handler for vector' warning in
119 * common_interrupt().
121 * This requires to hold vector lock to prevent concurrent updates to
122 * the affected vector.
127 * Mark the new target vector on the local CPU if it is currently
128 * unused. Reuse the VECTOR_RETRIGGERED state which is also used in
129 * the CPU hotplug path for a similar purpose. This cannot be
130 * undone here as the current CPU has interrupts disabled and
131 * cannot handle the interrupt before the whole set_affinity()
132 * section is done. In the CPU unplug case, the current CPU is
133 * about to vanish and will not handle any interrupts anymore. The
134 * vector is cleaned up when the CPU comes online again.
136 if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector])))
137 this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED);
139 /* Redirect it to the new vector on the local CPU temporarily */
140 old_cfg.vector = cfg->vector;
141 irq_msi_update_msg(irqd, &old_cfg);
143 /* Now transition it to the target CPU */
144 irq_msi_update_msg(irqd, cfg);
147 * All interrupts after this point are now targeted at the new
150 * Drop vector lock before testing whether the temporary assignment
151 * to the local CPU was hit by an interrupt raised in the device,
152 * because the retrigger function acquires vector lock again.
154 unlock_vector_lock();
157 * Check whether the transition raced with a device interrupt and
158 * is pending in the local APICs IRR. It is safe to do this outside
159 * of vector lock as the irq_desc::lock of this interrupt is still
160 * held and interrupts are disabled: The check is not accessing the
161 * underlying vector store. It's just checking the local APIC's
164 if (lapic_vector_set_in_irr(cfg->vector))
165 irq_data_get_irq_chip(irqd)->irq_retrigger(irqd);
171 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
172 * which implement the MSI or MSI-X Capability Structure.
174 static struct irq_chip pci_msi_controller = {
176 .irq_unmask = pci_msi_unmask_irq,
177 .irq_mask = pci_msi_mask_irq,
178 .irq_ack = irq_chip_ack_parent,
179 .irq_retrigger = irq_chip_retrigger_hierarchy,
180 .irq_set_affinity = msi_set_affinity,
181 .flags = IRQCHIP_SKIP_SET_WAKE,
184 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
185 msi_alloc_info_t *arg)
187 struct pci_dev *pdev = to_pci_dev(dev);
188 struct msi_desc *desc = first_pci_msi_entry(pdev);
190 init_irq_alloc_info(arg, NULL);
191 if (desc->msi_attrib.is_msix) {
192 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX;
194 arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
195 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
200 EXPORT_SYMBOL_GPL(pci_msi_prepare);
202 static struct msi_domain_ops pci_msi_domain_ops = {
203 .msi_prepare = pci_msi_prepare,
206 static struct msi_domain_info pci_msi_domain_info = {
207 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
209 .ops = &pci_msi_domain_ops,
210 .chip = &pci_msi_controller,
211 .handler = handle_edge_irq,
212 .handler_name = "edge",
215 struct irq_domain * __init native_create_pci_msi_domain(void)
217 struct fwnode_handle *fn;
218 struct irq_domain *d;
223 fn = irq_domain_alloc_named_fwnode("PCI-MSI");
227 d = pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
230 irq_domain_free_fwnode(fn);
231 pr_warn("Failed to initialize PCI-MSI irqdomain.\n");
233 d->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK;
238 void __init x86_create_pci_msi_domain(void)
240 x86_pci_msi_default_domain = x86_init.irqs.create_pci_msi_domain();
243 #ifdef CONFIG_IRQ_REMAP
244 static struct irq_chip pci_msi_ir_controller = {
245 .name = "IR-PCI-MSI",
246 .irq_unmask = pci_msi_unmask_irq,
247 .irq_mask = pci_msi_mask_irq,
248 .irq_ack = irq_chip_ack_parent,
249 .irq_retrigger = irq_chip_retrigger_hierarchy,
250 .flags = IRQCHIP_SKIP_SET_WAKE,
253 static struct msi_domain_info pci_msi_ir_domain_info = {
254 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
255 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
256 .ops = &pci_msi_domain_ops,
257 .chip = &pci_msi_ir_controller,
258 .handler = handle_edge_irq,
259 .handler_name = "edge",
262 struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
263 const char *name, int id)
265 struct fwnode_handle *fn;
266 struct irq_domain *d;
268 fn = irq_domain_alloc_named_id_fwnode(name, id);
271 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
273 irq_domain_free_fwnode(fn);
278 #ifdef CONFIG_DMAR_TABLE
279 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
281 dmar_msi_write(data->irq, msg);
284 static struct irq_chip dmar_msi_controller = {
286 .irq_unmask = dmar_msi_unmask,
287 .irq_mask = dmar_msi_mask,
288 .irq_ack = irq_chip_ack_parent,
289 .irq_set_affinity = msi_domain_set_affinity,
290 .irq_retrigger = irq_chip_retrigger_hierarchy,
291 .irq_write_msi_msg = dmar_msi_write_msg,
292 .flags = IRQCHIP_SKIP_SET_WAKE,
295 static int dmar_msi_init(struct irq_domain *domain,
296 struct msi_domain_info *info, unsigned int virq,
297 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
299 irq_domain_set_info(domain, virq, arg->devid, info->chip, NULL,
300 handle_edge_irq, arg->data, "edge");
305 static struct msi_domain_ops dmar_msi_domain_ops = {
306 .msi_init = dmar_msi_init,
309 static struct msi_domain_info dmar_msi_domain_info = {
310 .ops = &dmar_msi_domain_ops,
311 .chip = &dmar_msi_controller,
314 static struct irq_domain *dmar_get_irq_domain(void)
316 static struct irq_domain *dmar_domain;
317 static DEFINE_MUTEX(dmar_lock);
318 struct fwnode_handle *fn;
320 mutex_lock(&dmar_lock);
324 fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
326 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
329 irq_domain_free_fwnode(fn);
332 mutex_unlock(&dmar_lock);
336 int dmar_alloc_hwirq(int id, int node, void *arg)
338 struct irq_domain *domain = dmar_get_irq_domain();
339 struct irq_alloc_info info;
344 init_irq_alloc_info(&info, NULL);
345 info.type = X86_IRQ_ALLOC_TYPE_DMAR;
350 return irq_domain_alloc_irqs(domain, 1, node, &info);
353 void dmar_free_hwirq(int irq)
355 irq_domain_free_irqs(irq, 1);
360 * MSI message composition
362 #ifdef CONFIG_HPET_TIMER
363 static inline int hpet_dev_id(struct irq_domain *domain)
365 struct msi_domain_info *info = msi_get_domain_info(domain);
367 return (int)(long)info->data;
370 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
372 hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
375 static struct irq_chip hpet_msi_controller __ro_after_init = {
377 .irq_unmask = hpet_msi_unmask,
378 .irq_mask = hpet_msi_mask,
379 .irq_ack = irq_chip_ack_parent,
380 .irq_set_affinity = msi_domain_set_affinity,
381 .irq_retrigger = irq_chip_retrigger_hierarchy,
382 .irq_write_msi_msg = hpet_msi_write_msg,
383 .flags = IRQCHIP_SKIP_SET_WAKE,
386 static int hpet_msi_init(struct irq_domain *domain,
387 struct msi_domain_info *info, unsigned int virq,
388 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
390 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
391 irq_domain_set_info(domain, virq, arg->hwirq, info->chip, NULL,
392 handle_edge_irq, arg->data, "edge");
397 static void hpet_msi_free(struct irq_domain *domain,
398 struct msi_domain_info *info, unsigned int virq)
400 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
403 static struct msi_domain_ops hpet_msi_domain_ops = {
404 .msi_init = hpet_msi_init,
405 .msi_free = hpet_msi_free,
408 static struct msi_domain_info hpet_msi_domain_info = {
409 .ops = &hpet_msi_domain_ops,
410 .chip = &hpet_msi_controller,
413 struct irq_domain *hpet_create_irq_domain(int hpet_id)
415 struct msi_domain_info *domain_info;
416 struct irq_domain *parent, *d;
417 struct irq_alloc_info info;
418 struct fwnode_handle *fn;
420 if (x86_vector_domain == NULL)
423 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
427 *domain_info = hpet_msi_domain_info;
428 domain_info->data = (void *)(long)hpet_id;
430 init_irq_alloc_info(&info, NULL);
431 info.type = X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT;
432 info.devid = hpet_id;
433 parent = irq_remapping_get_irq_domain(&info);
435 parent = x86_vector_domain;
437 hpet_msi_controller.name = "IR-HPET-MSI";
439 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
446 d = msi_create_irq_domain(fn, domain_info, parent);
448 irq_domain_free_fwnode(fn);
454 int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc,
457 struct irq_alloc_info info;
459 init_irq_alloc_info(&info, NULL);
460 info.type = X86_IRQ_ALLOC_TYPE_HPET;
462 info.devid = hpet_dev_id(domain);
463 info.hwirq = dev_num;
465 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);