1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
23 * Historical information which is worth to be preserved:
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
35 #include <linux/interrupt.h>
36 #include <linux/irq.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/pci.h>
41 #include <linux/mc146818rtc.h>
42 #include <linux/compiler.h>
43 #include <linux/acpi.h>
44 #include <linux/export.h>
45 #include <linux/syscore_ops.h>
46 #include <linux/freezer.h>
47 #include <linux/kthread.h>
48 #include <linux/jiffies.h> /* time_after() */
49 #include <linux/slab.h>
50 #include <linux/memblock.h>
51 #include <linux/msi.h>
53 #include <asm/irqdomain.h>
58 #include <asm/proto.h>
61 #include <asm/timer.h>
63 #include <asm/i8259.h>
64 #include <asm/setup.h>
65 #include <asm/irq_remapping.h>
66 #include <asm/hw_irq.h>
69 #define for_each_ioapic(idx) \
70 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
71 #define for_each_ioapic_reverse(idx) \
72 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
73 #define for_each_pin(idx, pin) \
74 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
75 #define for_each_ioapic_pin(idx, pin) \
76 for_each_ioapic((idx)) \
77 for_each_pin((idx), (pin))
78 #define for_each_irq_pin(entry, head) \
79 list_for_each_entry(entry, &head, list)
81 static DEFINE_RAW_SPINLOCK(ioapic_lock);
82 static DEFINE_MUTEX(ioapic_mutex);
83 static unsigned int ioapic_dynirq_base;
84 static int ioapic_initialized;
87 struct list_head list;
92 struct list_head irq_2_pin;
93 struct IO_APIC_route_entry entry;
100 struct mp_ioapic_gsi {
105 static struct ioapic {
107 * # of IRQ routing registers
111 * Saved state during suspend/resume, or while enabling intr-remap.
113 struct IO_APIC_route_entry *saved_registers;
114 /* I/O APIC config */
115 struct mpc_ioapic mp_config;
116 /* IO APIC gsi routing info */
117 struct mp_ioapic_gsi gsi_config;
118 struct ioapic_domain_cfg irqdomain_cfg;
119 struct irq_domain *irqdomain;
120 struct resource *iomem_res;
121 } ioapics[MAX_IO_APICS];
123 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
125 int mpc_ioapic_id(int ioapic_idx)
127 return ioapics[ioapic_idx].mp_config.apicid;
130 unsigned int mpc_ioapic_addr(int ioapic_idx)
132 return ioapics[ioapic_idx].mp_config.apicaddr;
135 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
137 return &ioapics[ioapic_idx].gsi_config;
140 static inline int mp_ioapic_pin_count(int ioapic)
142 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
144 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
147 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
149 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
152 static inline bool mp_is_legacy_irq(int irq)
154 return irq >= 0 && irq < nr_legacy_irqs();
157 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
159 return ioapics[ioapic].irqdomain;
164 /* The one past the highest gsi number used */
167 /* MP IRQ source entries */
168 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
170 /* # of MP IRQ source entries */
174 int mp_bus_id_to_type[MAX_MP_BUSSES];
177 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
179 int skip_ioapic_setup;
182 * disable_ioapic_support() - disables ioapic support at runtime
184 void disable_ioapic_support(void)
188 noioapicreroute = -1;
190 skip_ioapic_setup = 1;
193 static int __init parse_noapic(char *str)
195 /* disable IO-APIC */
196 disable_ioapic_support();
199 early_param("noapic", parse_noapic);
201 /* Will be called in mpparse/ACPI codes for saving IRQ info */
202 void mp_save_irq(struct mpc_intsrc *m)
206 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
207 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
208 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
209 m->srcbusirq, m->dstapic, m->dstirq);
211 for (i = 0; i < mp_irq_entries; i++) {
212 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
216 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
217 if (++mp_irq_entries == MAX_IRQ_SOURCES)
218 panic("Max # of irq sources exceeded!!\n");
221 static void alloc_ioapic_saved_registers(int idx)
225 if (ioapics[idx].saved_registers)
228 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
229 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
230 if (!ioapics[idx].saved_registers)
231 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
234 static void free_ioapic_saved_registers(int idx)
236 kfree(ioapics[idx].saved_registers);
237 ioapics[idx].saved_registers = NULL;
240 int __init arch_early_ioapic_init(void)
244 if (!nr_legacy_irqs())
248 alloc_ioapic_saved_registers(i);
255 unsigned int unused[3];
257 unsigned int unused2[11];
261 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
263 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
264 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
267 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
269 struct io_apic __iomem *io_apic = io_apic_base(apic);
270 writel(vector, &io_apic->eoi);
273 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
275 struct io_apic __iomem *io_apic = io_apic_base(apic);
276 writel(reg, &io_apic->index);
277 return readl(&io_apic->data);
280 static void io_apic_write(unsigned int apic, unsigned int reg,
283 struct io_apic __iomem *io_apic = io_apic_base(apic);
285 writel(reg, &io_apic->index);
286 writel(value, &io_apic->data);
289 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
291 struct IO_APIC_route_entry entry;
293 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
294 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
299 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
301 struct IO_APIC_route_entry entry;
304 raw_spin_lock_irqsave(&ioapic_lock, flags);
305 entry = __ioapic_read_entry(apic, pin);
306 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
312 * When we write a new IO APIC routing entry, we need to write the high
313 * word first! If the mask bit in the low word is clear, we will enable
314 * the interrupt, and we need to make sure the entry is fully populated
315 * before that happens.
317 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
319 io_apic_write(apic, 0x11 + 2*pin, e.w2);
320 io_apic_write(apic, 0x10 + 2*pin, e.w1);
323 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
327 raw_spin_lock_irqsave(&ioapic_lock, flags);
328 __ioapic_write_entry(apic, pin, e);
329 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
333 * When we mask an IO APIC routing entry, we need to write the low
334 * word first, in order to set the mask bit before we change the
337 static void ioapic_mask_entry(int apic, int pin)
339 struct IO_APIC_route_entry e = { .masked = true };
342 raw_spin_lock_irqsave(&ioapic_lock, flags);
343 io_apic_write(apic, 0x10 + 2*pin, e.w1);
344 io_apic_write(apic, 0x11 + 2*pin, e.w2);
345 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
349 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
350 * shared ISA-space IRQs, so we have to support them. We are super
351 * fast in the common case, and fast for shared ISA-space IRQs.
353 static int __add_pin_to_irq_node(struct mp_chip_data *data,
354 int node, int apic, int pin)
356 struct irq_pin_list *entry;
358 /* don't allow duplicates */
359 for_each_irq_pin(entry, data->irq_2_pin)
360 if (entry->apic == apic && entry->pin == pin)
363 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
365 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
371 list_add_tail(&entry->list, &data->irq_2_pin);
376 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
378 struct irq_pin_list *tmp, *entry;
380 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
381 if (entry->apic == apic && entry->pin == pin) {
382 list_del(&entry->list);
388 static void add_pin_to_irq_node(struct mp_chip_data *data,
389 int node, int apic, int pin)
391 if (__add_pin_to_irq_node(data, node, apic, pin))
392 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
396 * Reroute an IRQ to a different pin.
398 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
399 int oldapic, int oldpin,
400 int newapic, int newpin)
402 struct irq_pin_list *entry;
404 for_each_irq_pin(entry, data->irq_2_pin) {
405 if (entry->apic == oldapic && entry->pin == oldpin) {
406 entry->apic = newapic;
408 /* every one is different, right? */
413 /* old apic/pin didn't exist, so just add new ones */
414 add_pin_to_irq_node(data, node, newapic, newpin);
417 static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
418 void (*final)(struct irq_pin_list *entry))
420 struct irq_pin_list *entry;
422 data->entry.masked = masked;
424 for_each_irq_pin(entry, data->irq_2_pin) {
425 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
431 static void io_apic_sync(struct irq_pin_list *entry)
434 * Synchronize the IO-APIC and the CPU by doing
435 * a dummy read from the IO-APIC
437 struct io_apic __iomem *io_apic;
439 io_apic = io_apic_base(entry->apic);
440 readl(&io_apic->data);
443 static void mask_ioapic_irq(struct irq_data *irq_data)
445 struct mp_chip_data *data = irq_data->chip_data;
448 raw_spin_lock_irqsave(&ioapic_lock, flags);
449 io_apic_modify_irq(data, true, &io_apic_sync);
450 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
453 static void __unmask_ioapic(struct mp_chip_data *data)
455 io_apic_modify_irq(data, false, NULL);
458 static void unmask_ioapic_irq(struct irq_data *irq_data)
460 struct mp_chip_data *data = irq_data->chip_data;
463 raw_spin_lock_irqsave(&ioapic_lock, flags);
464 __unmask_ioapic(data);
465 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
469 * IO-APIC versions below 0x20 don't support EOI register.
470 * For the record, here is the information about various versions:
472 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
473 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
476 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
477 * version as 0x2. This is an error with documentation and these ICH chips
478 * use io-apic's of version 0x20.
480 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
481 * Otherwise, we simulate the EOI message manually by changing the trigger
482 * mode to edge and then back to level, with RTE being masked during this.
484 static void __eoi_ioapic_pin(int apic, int pin, int vector)
486 if (mpc_ioapic_ver(apic) >= 0x20) {
487 io_apic_eoi(apic, vector);
489 struct IO_APIC_route_entry entry, entry1;
491 entry = entry1 = __ioapic_read_entry(apic, pin);
494 * Mask the entry and change the trigger mode to edge.
496 entry1.masked = true;
497 entry1.is_level = false;
499 __ioapic_write_entry(apic, pin, entry1);
502 * Restore the previous level triggered entry.
504 __ioapic_write_entry(apic, pin, entry);
508 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
511 struct irq_pin_list *entry;
513 raw_spin_lock_irqsave(&ioapic_lock, flags);
514 for_each_irq_pin(entry, data->irq_2_pin)
515 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
516 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
519 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
521 struct IO_APIC_route_entry entry;
523 /* Check delivery_mode to be sure we're not clearing an SMI pin */
524 entry = ioapic_read_entry(apic, pin);
525 if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
529 * Make sure the entry is masked and re-read the contents to check
530 * if it is a level triggered pin and if the remote-IRR is set.
534 ioapic_write_entry(apic, pin, entry);
535 entry = ioapic_read_entry(apic, pin);
542 * Make sure the trigger mode is set to level. Explicit EOI
543 * doesn't clear the remote-IRR if the trigger mode is not
546 if (!entry.is_level) {
547 entry.is_level = true;
548 ioapic_write_entry(apic, pin, entry);
550 raw_spin_lock_irqsave(&ioapic_lock, flags);
551 __eoi_ioapic_pin(apic, pin, entry.vector);
552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
556 * Clear the rest of the bits in the IO-APIC RTE except for the mask
559 ioapic_mask_entry(apic, pin);
560 entry = ioapic_read_entry(apic, pin);
562 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
563 mpc_ioapic_id(apic), pin);
566 void clear_IO_APIC (void)
570 for_each_ioapic_pin(apic, pin)
571 clear_IO_APIC_pin(apic, pin);
576 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
577 * specific CPU-side IRQs.
581 static int pirq_entries[MAX_PIRQS] = {
582 [0 ... MAX_PIRQS - 1] = -1
585 static int __init ioapic_pirq_setup(char *str)
588 int ints[MAX_PIRQS+1];
590 get_options(str, ARRAY_SIZE(ints), ints);
592 apic_printk(APIC_VERBOSE, KERN_INFO
593 "PIRQ redirection, working around broken MP-BIOS.\n");
595 if (ints[0] < MAX_PIRQS)
598 for (i = 0; i < max; i++) {
599 apic_printk(APIC_VERBOSE, KERN_DEBUG
600 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
602 * PIRQs are mapped upside down, usually.
604 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
609 __setup("pirq=", ioapic_pirq_setup);
610 #endif /* CONFIG_X86_32 */
613 * Saves all the IO-APIC RTE's
615 int save_ioapic_entries(void)
620 for_each_ioapic(apic) {
621 if (!ioapics[apic].saved_registers) {
626 for_each_pin(apic, pin)
627 ioapics[apic].saved_registers[pin] =
628 ioapic_read_entry(apic, pin);
635 * Mask all IO APIC entries.
637 void mask_ioapic_entries(void)
641 for_each_ioapic(apic) {
642 if (!ioapics[apic].saved_registers)
645 for_each_pin(apic, pin) {
646 struct IO_APIC_route_entry entry;
648 entry = ioapics[apic].saved_registers[pin];
651 ioapic_write_entry(apic, pin, entry);
658 * Restore IO APIC entries which was saved in the ioapic structure.
660 int restore_ioapic_entries(void)
664 for_each_ioapic(apic) {
665 if (!ioapics[apic].saved_registers)
668 for_each_pin(apic, pin)
669 ioapic_write_entry(apic, pin,
670 ioapics[apic].saved_registers[pin]);
676 * Find the IRQ entry number of a certain pin.
678 static int find_irq_entry(int ioapic_idx, int pin, int type)
682 for (i = 0; i < mp_irq_entries; i++)
683 if (mp_irqs[i].irqtype == type &&
684 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
685 mp_irqs[i].dstapic == MP_APIC_ALL) &&
686 mp_irqs[i].dstirq == pin)
693 * Find the pin to which IRQ[irq] (ISA) is connected
695 static int __init find_isa_irq_pin(int irq, int type)
699 for (i = 0; i < mp_irq_entries; i++) {
700 int lbus = mp_irqs[i].srcbus;
702 if (test_bit(lbus, mp_bus_not_pci) &&
703 (mp_irqs[i].irqtype == type) &&
704 (mp_irqs[i].srcbusirq == irq))
706 return mp_irqs[i].dstirq;
711 static int __init find_isa_irq_apic(int irq, int type)
715 for (i = 0; i < mp_irq_entries; i++) {
716 int lbus = mp_irqs[i].srcbus;
718 if (test_bit(lbus, mp_bus_not_pci) &&
719 (mp_irqs[i].irqtype == type) &&
720 (mp_irqs[i].srcbusirq == irq))
724 if (i < mp_irq_entries) {
727 for_each_ioapic(ioapic_idx)
728 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
735 static bool irq_active_low(int idx)
737 int bus = mp_irqs[idx].srcbus;
740 * Determine IRQ line polarity (high active or low active):
742 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
743 case MP_IRQPOL_DEFAULT:
745 * Conforms to spec, ie. bus-type dependent polarity. PCI
746 * defaults to low active. [E]ISA defaults to high active.
748 return !test_bit(bus, mp_bus_not_pci);
749 case MP_IRQPOL_ACTIVE_HIGH:
751 case MP_IRQPOL_RESERVED:
752 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
754 case MP_IRQPOL_ACTIVE_LOW:
755 default: /* Pointless default required due to do gcc stupidity */
762 * EISA Edge/Level control register, ELCR
764 static bool EISA_ELCR(unsigned int irq)
766 if (irq < nr_legacy_irqs()) {
767 unsigned int port = PIC_ELCR1 + (irq >> 3);
768 return (inb(port) >> (irq & 7)) & 1;
770 apic_printk(APIC_VERBOSE, KERN_INFO
771 "Broken MPtable reports ISA irq %d\n", irq);
776 * EISA interrupts are always active high and can be edge or level
777 * triggered depending on the ELCR value. If an interrupt is listed as
778 * EISA conforming in the MP table, that means its trigger type must be
779 * read in from the ELCR.
781 static bool eisa_irq_is_level(int idx, int bus, bool level)
783 switch (mp_bus_id_to_type[bus]) {
788 return EISA_ELCR(mp_irqs[idx].srcbusirq);
790 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
794 static inline int eisa_irq_is_level(int idx, int bus, bool level)
800 static bool irq_is_level(int idx)
802 int bus = mp_irqs[idx].srcbus;
806 * Determine IRQ trigger mode (edge or level sensitive):
808 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
809 case MP_IRQTRIG_DEFAULT:
811 * Conforms to spec, ie. bus-type dependent trigger
812 * mode. PCI defaults to level, ISA to edge.
814 level = !test_bit(bus, mp_bus_not_pci);
815 /* Take EISA into account */
816 return eisa_irq_is_level(idx, bus, level);
817 case MP_IRQTRIG_EDGE:
819 case MP_IRQTRIG_RESERVED:
820 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
822 case MP_IRQTRIG_LEVEL:
823 default: /* Pointless default required due to do gcc stupidity */
828 static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity)
830 int ioapic, pin, idx;
832 if (skip_ioapic_setup)
835 ioapic = mp_find_ioapic(gsi);
839 pin = mp_find_ioapic_pin(ioapic, gsi);
843 idx = find_irq_entry(ioapic, pin, mp_INT);
847 *trigger = irq_is_level(idx);
848 *polarity = irq_active_low(idx);
853 int acpi_get_override_irq(u32 gsi, int *is_level, int *active_low)
855 *is_level = *active_low = 0;
856 return __acpi_get_override_irq(gsi, (bool *)is_level,
861 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
862 int trigger, int polarity)
864 init_irq_alloc_info(info, NULL);
865 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
866 info->ioapic.node = node;
867 info->ioapic.is_level = trigger;
868 info->ioapic.active_low = polarity;
869 info->ioapic.valid = 1;
872 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
873 struct irq_alloc_info *src,
874 u32 gsi, int ioapic_idx, int pin)
878 copy_irq_alloc_info(dst, src);
879 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
880 dst->devid = mpc_ioapic_id(ioapic_idx);
881 dst->ioapic.pin = pin;
882 dst->ioapic.valid = 1;
883 if (src && src->ioapic.valid) {
884 dst->ioapic.node = src->ioapic.node;
885 dst->ioapic.is_level = src->ioapic.is_level;
886 dst->ioapic.active_low = src->ioapic.active_low;
888 dst->ioapic.node = NUMA_NO_NODE;
889 if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) {
890 dst->ioapic.is_level = level;
891 dst->ioapic.active_low = pol_low;
894 * PCI interrupts are always active low level
897 dst->ioapic.is_level = true;
898 dst->ioapic.active_low = true;
903 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
905 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
908 static void mp_register_handler(unsigned int irq, bool level)
910 irq_flow_handler_t hdl;
914 irq_set_status_flags(irq, IRQ_LEVEL);
917 irq_clear_status_flags(irq, IRQ_LEVEL);
921 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
922 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
925 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
927 struct mp_chip_data *data = irq_get_chip_data(irq);
930 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
931 * and polarity attributes. So allow the first user to reprogram the
932 * pin with real trigger and polarity attributes.
934 if (irq < nr_legacy_irqs() && data->count == 1) {
935 if (info->ioapic.is_level != data->is_level)
936 mp_register_handler(irq, info->ioapic.is_level);
937 data->entry.is_level = data->is_level = info->ioapic.is_level;
938 data->entry.active_low = data->active_low = info->ioapic.active_low;
941 return data->is_level == info->ioapic.is_level &&
942 data->active_low == info->ioapic.active_low;
945 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
946 struct irq_alloc_info *info)
950 int type = ioapics[ioapic].irqdomain_cfg.type;
953 case IOAPIC_DOMAIN_LEGACY:
955 * Dynamically allocate IRQ number for non-ISA IRQs in the first
956 * 16 GSIs on some weird platforms.
958 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
960 legacy = mp_is_legacy_irq(irq);
962 case IOAPIC_DOMAIN_STRICT:
965 case IOAPIC_DOMAIN_DYNAMIC:
968 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
972 return __irq_domain_alloc_irqs(domain, irq, 1,
973 ioapic_alloc_attr_node(info),
978 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
979 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
980 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
981 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
982 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
983 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
984 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
985 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
987 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
988 int irq, int ioapic, int pin,
989 struct irq_alloc_info *info)
991 struct mp_chip_data *data;
992 struct irq_data *irq_data = irq_get_irq_data(irq);
993 int node = ioapic_alloc_attr_node(info);
996 * Legacy ISA IRQ has already been allocated, just add pin to
997 * the pin list associated with this IRQ and program the IOAPIC
998 * entry. The IOAPIC entry
1000 if (irq_data && irq_data->parent_data) {
1001 if (!mp_check_pin_attr(irq, info))
1003 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1007 info->flags |= X86_IRQ_ALLOC_LEGACY;
1008 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1011 irq_data = irq_domain_get_irq_data(domain, irq);
1012 data = irq_data->chip_data;
1013 data->isa_irq = true;
1020 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1021 unsigned int flags, struct irq_alloc_info *info)
1024 bool legacy = false;
1025 struct irq_alloc_info tmp;
1026 struct mp_chip_data *data;
1027 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1032 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1033 irq = mp_irqs[idx].srcbusirq;
1034 legacy = mp_is_legacy_irq(irq);
1036 * IRQ2 is unusable for historical reasons on systems which
1037 * have a legacy PIC. See the comment vs. IRQ2 further down.
1039 * If this gets removed at some point then the related code
1040 * in lapic_assign_system_vectors() needs to be adjusted as
1043 if (legacy && irq == PIC_CASCADE_IR)
1047 mutex_lock(&ioapic_mutex);
1048 if (!(flags & IOAPIC_MAP_ALLOC)) {
1050 irq = irq_find_mapping(domain, pin);
1055 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1057 irq = alloc_isa_irq_from_domain(domain, irq,
1059 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1060 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1061 else if (!mp_check_pin_attr(irq, &tmp))
1064 data = irq_get_chip_data(irq);
1068 mutex_unlock(&ioapic_mutex);
1073 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1075 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1078 * Debugging check, we are in big trouble if this message pops up!
1080 if (mp_irqs[idx].dstirq != pin)
1081 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1083 #ifdef CONFIG_X86_32
1085 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1087 if ((pin >= 16) && (pin <= 23)) {
1088 if (pirq_entries[pin-16] != -1) {
1089 if (!pirq_entries[pin-16]) {
1090 apic_printk(APIC_VERBOSE, KERN_DEBUG
1091 "disabling PIRQ%d\n", pin-16);
1093 int irq = pirq_entries[pin-16];
1094 apic_printk(APIC_VERBOSE, KERN_DEBUG
1095 "using PIRQ%d -> IRQ %d\n",
1103 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1106 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1108 int ioapic, pin, idx;
1110 ioapic = mp_find_ioapic(gsi);
1114 pin = mp_find_ioapic_pin(ioapic, gsi);
1115 idx = find_irq_entry(ioapic, pin, mp_INT);
1116 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1119 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1122 void mp_unmap_irq(int irq)
1124 struct irq_data *irq_data = irq_get_irq_data(irq);
1125 struct mp_chip_data *data;
1127 if (!irq_data || !irq_data->domain)
1130 data = irq_data->chip_data;
1131 if (!data || data->isa_irq)
1134 mutex_lock(&ioapic_mutex);
1135 if (--data->count == 0)
1136 irq_domain_free_irqs(irq, 1);
1137 mutex_unlock(&ioapic_mutex);
1141 * Find a specific PCI IRQ entry.
1142 * Not an __init, possibly needed by modules
1144 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1146 int irq, i, best_ioapic = -1, best_idx = -1;
1148 apic_printk(APIC_DEBUG,
1149 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1151 if (test_bit(bus, mp_bus_not_pci)) {
1152 apic_printk(APIC_VERBOSE,
1153 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1157 for (i = 0; i < mp_irq_entries; i++) {
1158 int lbus = mp_irqs[i].srcbus;
1159 int ioapic_idx, found = 0;
1161 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1162 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1165 for_each_ioapic(ioapic_idx)
1166 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1167 mp_irqs[i].dstapic == MP_APIC_ALL) {
1175 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1176 if (irq > 0 && !IO_APIC_IRQ(irq))
1179 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1181 best_ioapic = ioapic_idx;
1186 * Use the first all-but-pin matching entry as a
1187 * best-guess fuzzy result for broken mptables.
1191 best_ioapic = ioapic_idx;
1198 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1201 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1203 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1205 static void __init setup_IO_APIC_irqs(void)
1207 unsigned int ioapic, pin;
1210 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1212 for_each_ioapic_pin(ioapic, pin) {
1213 idx = find_irq_entry(ioapic, pin, mp_INT);
1215 apic_printk(APIC_VERBOSE,
1216 KERN_DEBUG " apic %d pin %d not connected\n",
1217 mpc_ioapic_id(ioapic), pin);
1219 pin_2_irq(idx, ioapic, pin,
1220 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1224 void ioapic_zap_locks(void)
1226 raw_spin_lock_init(&ioapic_lock);
1229 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1231 struct IO_APIC_route_entry entry;
1235 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1236 for (i = 0; i <= nr_entries; i++) {
1237 entry = ioapic_read_entry(apic, i);
1238 snprintf(buf, sizeof(buf),
1239 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1241 entry.masked ? "disabled" : "enabled ",
1242 entry.is_level ? "level" : "edge ",
1243 entry.active_low ? "low " : "high",
1244 entry.vector, entry.irr, entry.delivery_status);
1245 if (entry.ir_format) {
1246 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1248 (entry.ir_index_15 << 15) | entry.ir_index_0_14,
1251 printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf,
1252 entry.dest_mode_logical ? "logical " : "physical",
1253 entry.virt_destid_8_14, entry.destid_0_7,
1254 entry.delivery_mode);
1259 static void __init print_IO_APIC(int ioapic_idx)
1261 union IO_APIC_reg_00 reg_00;
1262 union IO_APIC_reg_01 reg_01;
1263 union IO_APIC_reg_02 reg_02;
1264 union IO_APIC_reg_03 reg_03;
1265 unsigned long flags;
1267 raw_spin_lock_irqsave(&ioapic_lock, flags);
1268 reg_00.raw = io_apic_read(ioapic_idx, 0);
1269 reg_01.raw = io_apic_read(ioapic_idx, 1);
1270 if (reg_01.bits.version >= 0x10)
1271 reg_02.raw = io_apic_read(ioapic_idx, 2);
1272 if (reg_01.bits.version >= 0x20)
1273 reg_03.raw = io_apic_read(ioapic_idx, 3);
1274 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1276 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1277 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1278 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1279 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1280 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1282 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1283 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1284 reg_01.bits.entries);
1286 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1287 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1288 reg_01.bits.version);
1291 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1292 * but the value of reg_02 is read as the previous read register
1293 * value, so ignore it if reg_02 == reg_01.
1295 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1296 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1297 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1301 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1302 * or reg_03, but the value of reg_0[23] is read as the previous read
1303 * register value, so ignore it if reg_03 == reg_0[12].
1305 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1306 reg_03.raw != reg_01.raw) {
1307 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1308 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1311 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1312 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1315 void __init print_IO_APICs(void)
1320 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1321 for_each_ioapic(ioapic_idx)
1322 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1323 mpc_ioapic_id(ioapic_idx),
1324 ioapics[ioapic_idx].nr_registers);
1327 * We are a bit conservative about what we expect. We have to
1328 * know about every hardware change ASAP.
1330 printk(KERN_INFO "testing the IO APIC.......................\n");
1332 for_each_ioapic(ioapic_idx)
1333 print_IO_APIC(ioapic_idx);
1335 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1336 for_each_active_irq(irq) {
1337 struct irq_pin_list *entry;
1338 struct irq_chip *chip;
1339 struct mp_chip_data *data;
1341 chip = irq_get_chip(irq);
1342 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1344 data = irq_get_chip_data(irq);
1347 if (list_empty(&data->irq_2_pin))
1350 printk(KERN_DEBUG "IRQ%d ", irq);
1351 for_each_irq_pin(entry, data->irq_2_pin)
1352 pr_cont("-> %d:%d", entry->apic, entry->pin);
1356 printk(KERN_INFO ".................................... done.\n");
1359 /* Where if anywhere is the i8259 connect in external int mode */
1360 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1362 void __init enable_IO_APIC(void)
1364 int i8259_apic, i8259_pin;
1367 if (skip_ioapic_setup)
1370 if (!nr_legacy_irqs() || !nr_ioapics)
1373 for_each_ioapic_pin(apic, pin) {
1374 /* See if any of the pins is in ExtINT mode */
1375 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1377 /* If the interrupt line is enabled and in ExtInt mode
1378 * I have found the pin where the i8259 is connected.
1380 if (!entry.masked &&
1381 entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
1382 ioapic_i8259.apic = apic;
1383 ioapic_i8259.pin = pin;
1388 /* Look to see what if the MP table has reported the ExtINT */
1389 /* If we could not find the appropriate pin by looking at the ioapic
1390 * the i8259 probably is not connected the ioapic but give the
1391 * mptable a chance anyway.
1393 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1394 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1395 /* Trust the MP table if nothing is setup in the hardware */
1396 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1397 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1398 ioapic_i8259.pin = i8259_pin;
1399 ioapic_i8259.apic = i8259_apic;
1401 /* Complain if the MP table and the hardware disagree */
1402 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1403 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1405 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1409 * Do not trust the IO-APIC being empty at bootup
1414 void native_restore_boot_irq_mode(void)
1417 * If the i8259 is routed through an IOAPIC
1418 * Put that IOAPIC in virtual wire mode
1419 * so legacy interrupts can be delivered.
1421 if (ioapic_i8259.pin != -1) {
1422 struct IO_APIC_route_entry entry;
1423 u32 apic_id = read_apic_id();
1425 memset(&entry, 0, sizeof(entry));
1426 entry.masked = false;
1427 entry.is_level = false;
1428 entry.active_low = false;
1429 entry.dest_mode_logical = false;
1430 entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1431 entry.destid_0_7 = apic_id & 0xFF;
1432 entry.virt_destid_8_14 = apic_id >> 8;
1435 * Add it to the IO-APIC irq-routing table:
1437 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1440 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1441 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1444 void restore_boot_irq_mode(void)
1446 if (!nr_legacy_irqs())
1449 x86_apic_ops.restore();
1452 #ifdef CONFIG_X86_32
1454 * function to set the IO-APIC physical IDs based on the
1455 * values stored in the MPC table.
1457 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1459 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1461 union IO_APIC_reg_00 reg_00;
1462 physid_mask_t phys_id_present_map;
1465 unsigned char old_id;
1466 unsigned long flags;
1469 * This is broken; anything with a real cpu count has to
1470 * circumvent this idiocy regardless.
1472 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1475 * Set the IOAPIC ID to the value stored in the MPC table.
1477 for_each_ioapic(ioapic_idx) {
1478 /* Read the register 0 value */
1479 raw_spin_lock_irqsave(&ioapic_lock, flags);
1480 reg_00.raw = io_apic_read(ioapic_idx, 0);
1481 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1483 old_id = mpc_ioapic_id(ioapic_idx);
1485 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1486 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1487 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1488 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1490 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1494 * Sanity check, is the ID really free? Every APIC in a
1495 * system must have a unique ID or we get lots of nice
1496 * 'stuck on smp_invalidate_needed IPI wait' messages.
1498 if (apic->check_apicid_used(&phys_id_present_map,
1499 mpc_ioapic_id(ioapic_idx))) {
1500 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1501 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1502 for (i = 0; i < get_physical_broadcast(); i++)
1503 if (!physid_isset(i, phys_id_present_map))
1505 if (i >= get_physical_broadcast())
1506 panic("Max APIC ID exceeded!\n");
1507 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1509 physid_set(i, phys_id_present_map);
1510 ioapics[ioapic_idx].mp_config.apicid = i;
1513 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1515 apic_printk(APIC_VERBOSE, "Setting %d in the "
1516 "phys_id_present_map\n",
1517 mpc_ioapic_id(ioapic_idx));
1518 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1522 * We need to adjust the IRQ routing table
1523 * if the ID changed.
1525 if (old_id != mpc_ioapic_id(ioapic_idx))
1526 for (i = 0; i < mp_irq_entries; i++)
1527 if (mp_irqs[i].dstapic == old_id)
1529 = mpc_ioapic_id(ioapic_idx);
1532 * Update the ID register according to the right value
1533 * from the MPC table if they are different.
1535 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1538 apic_printk(APIC_VERBOSE, KERN_INFO
1539 "...changing IO-APIC physical APIC ID to %d ...",
1540 mpc_ioapic_id(ioapic_idx));
1542 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1543 raw_spin_lock_irqsave(&ioapic_lock, flags);
1544 io_apic_write(ioapic_idx, 0, reg_00.raw);
1545 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1550 raw_spin_lock_irqsave(&ioapic_lock, flags);
1551 reg_00.raw = io_apic_read(ioapic_idx, 0);
1552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1553 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1554 pr_cont("could not set ID!\n");
1556 apic_printk(APIC_VERBOSE, " ok.\n");
1560 void __init setup_ioapic_ids_from_mpc(void)
1566 * Don't check I/O APIC IDs for xAPIC systems. They have
1567 * no meaning without the serial APIC bus.
1569 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1570 || APIC_XAPIC(boot_cpu_apic_version))
1572 setup_ioapic_ids_from_mpc_nocheck();
1576 int no_timer_check __initdata;
1578 static int __init notimercheck(char *s)
1583 __setup("no_timer_check", notimercheck);
1585 static void __init delay_with_tsc(void)
1587 unsigned long long start, now;
1588 unsigned long end = jiffies + 4;
1593 * We don't know the TSC frequency yet, but waiting for
1594 * 40000000000/HZ TSC cycles is safe:
1595 * 4 GHz == 10 jiffies
1596 * 1 GHz == 40 jiffies
1601 } while ((now - start) < 40000000000ULL / HZ &&
1602 time_before_eq(jiffies, end));
1605 static void __init delay_without_tsc(void)
1607 unsigned long end = jiffies + 4;
1611 * We don't know any frequency yet, but waiting for
1612 * 40940000000/HZ cycles is safe:
1613 * 4 GHz == 10 jiffies
1614 * 1 GHz == 40 jiffies
1615 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1618 __delay(((1U << band++) * 10000000UL) / HZ);
1619 } while (band < 12 && time_before_eq(jiffies, end));
1623 * There is a nasty bug in some older SMP boards, their mptable lies
1624 * about the timer IRQ. We do the following to work around the situation:
1626 * - timer IRQ defaults to IO-APIC IRQ
1627 * - if this function detects that timer IRQs are defunct, then we fall
1628 * back to ISA timer IRQs
1630 static int __init timer_irq_works(void)
1632 unsigned long t1 = jiffies;
1638 if (boot_cpu_has(X86_FEATURE_TSC))
1641 delay_without_tsc();
1644 * Expect a few ticks at least, to be sure some possible
1645 * glue logic does not lock up after one or two first
1646 * ticks in a non-ExtINT mode. Also the local APIC
1647 * might have cached one ExtINT interrupt. Finally, at
1648 * least one tick may be lost due to delays.
1651 local_irq_disable();
1653 /* Did jiffies advance? */
1654 return time_after(jiffies, t1 + 4);
1658 * In the SMP+IOAPIC case it might happen that there are an unspecified
1659 * number of pending IRQ events unhandled. These cases are very rare,
1660 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1661 * better to do it this way as thus we do not have to be aware of
1662 * 'pending' interrupts in the IRQ path, except at this point.
1665 * Edge triggered needs to resend any interrupt
1666 * that was delayed but this is now handled in the device
1671 * Starting up a edge-triggered IO-APIC interrupt is
1672 * nasty - we need to make sure that we get the edge.
1673 * If it is already asserted for some reason, we need
1674 * return 1 to indicate that is was pending.
1676 * This is not complete - we should be able to fake
1677 * an edge even if it isn't on the 8259A...
1679 static unsigned int startup_ioapic_irq(struct irq_data *data)
1681 int was_pending = 0, irq = data->irq;
1682 unsigned long flags;
1684 raw_spin_lock_irqsave(&ioapic_lock, flags);
1685 if (irq < nr_legacy_irqs()) {
1686 legacy_pic->mask(irq);
1687 if (legacy_pic->irq_pending(irq))
1690 __unmask_ioapic(data->chip_data);
1691 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1696 atomic_t irq_mis_count;
1698 #ifdef CONFIG_GENERIC_PENDING_IRQ
1699 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1701 struct irq_pin_list *entry;
1702 unsigned long flags;
1704 raw_spin_lock_irqsave(&ioapic_lock, flags);
1705 for_each_irq_pin(entry, data->irq_2_pin) {
1706 struct IO_APIC_route_entry e;
1710 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
1711 /* Is the remote IRR bit set? */
1713 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1717 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1722 static inline bool ioapic_prepare_move(struct irq_data *data)
1724 /* If we are moving the IRQ we need to mask it */
1725 if (unlikely(irqd_is_setaffinity_pending(data))) {
1726 if (!irqd_irq_masked(data))
1727 mask_ioapic_irq(data);
1733 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1735 if (unlikely(moveit)) {
1736 /* Only migrate the irq if the ack has been received.
1738 * On rare occasions the broadcast level triggered ack gets
1739 * delayed going to ioapics, and if we reprogram the
1740 * vector while Remote IRR is still set the irq will never
1743 * To prevent this scenario we read the Remote IRR bit
1744 * of the ioapic. This has two effects.
1745 * - On any sane system the read of the ioapic will
1746 * flush writes (and acks) going to the ioapic from
1748 * - We get to see if the ACK has actually been delivered.
1750 * Based on failed experiments of reprogramming the
1751 * ioapic entry from outside of irq context starting
1752 * with masking the ioapic entry and then polling until
1753 * Remote IRR was clear before reprogramming the
1754 * ioapic I don't trust the Remote IRR bit to be
1755 * completely accurate.
1757 * However there appears to be no other way to plug
1758 * this race, so if the Remote IRR bit is not
1759 * accurate and is causing problems then it is a hardware bug
1760 * and you can go talk to the chipset vendor about it.
1762 if (!io_apic_level_ack_pending(data->chip_data))
1763 irq_move_masked_irq(data);
1764 /* If the IRQ is masked in the core, leave it: */
1765 if (!irqd_irq_masked(data))
1766 unmask_ioapic_irq(data);
1770 static inline bool ioapic_prepare_move(struct irq_data *data)
1774 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1779 static void ioapic_ack_level(struct irq_data *irq_data)
1781 struct irq_cfg *cfg = irqd_cfg(irq_data);
1786 irq_complete_move(cfg);
1787 moveit = ioapic_prepare_move(irq_data);
1790 * It appears there is an erratum which affects at least version 0x11
1791 * of I/O APIC (that's the 82093AA and cores integrated into various
1792 * chipsets). Under certain conditions a level-triggered interrupt is
1793 * erroneously delivered as edge-triggered one but the respective IRR
1794 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1795 * message but it will never arrive and further interrupts are blocked
1796 * from the source. The exact reason is so far unknown, but the
1797 * phenomenon was observed when two consecutive interrupt requests
1798 * from a given source get delivered to the same CPU and the source is
1799 * temporarily disabled in between.
1801 * A workaround is to simulate an EOI message manually. We achieve it
1802 * by setting the trigger mode to edge and then to level when the edge
1803 * trigger mode gets detected in the TMR of a local APIC for a
1804 * level-triggered interrupt. We mask the source for the time of the
1805 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1806 * The idea is from Manfred Spraul. --macro
1808 * Also in the case when cpu goes offline, fixup_irqs() will forward
1809 * any unhandled interrupt on the offlined cpu to the new cpu
1810 * destination that is handling the corresponding interrupt. This
1811 * interrupt forwarding is done via IPI's. Hence, in this case also
1812 * level-triggered io-apic interrupt will be seen as an edge
1813 * interrupt in the IRR. And we can't rely on the cpu's EOI
1814 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1815 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1816 * supporting EOI register, we do an explicit EOI to clear the
1817 * remote IRR and on IO-APIC's which don't have an EOI register,
1818 * we use the above logic (mask+edge followed by unmask+level) from
1819 * Manfred Spraul to clear the remote IRR.
1822 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1825 * We must acknowledge the irq before we move it or the acknowledge will
1826 * not propagate properly.
1831 * Tail end of clearing remote IRR bit (either by delivering the EOI
1832 * message via io-apic EOI register write or simulating it using
1833 * mask+edge followed by unmask+level logic) manually when the
1834 * level triggered interrupt is seen as the edge triggered interrupt
1837 if (!(v & (1 << (i & 0x1f)))) {
1838 atomic_inc(&irq_mis_count);
1839 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1842 ioapic_finish_move(irq_data, moveit);
1845 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1847 struct mp_chip_data *data = irq_data->chip_data;
1850 * Intr-remapping uses pin number as the virtual vector
1851 * in the RTE. Actual vector is programmed in
1852 * intr-remapping table entry. Hence for the io-apic
1853 * EOI we use the pin number.
1855 apic_ack_irq(irq_data);
1856 eoi_ioapic_pin(data->entry.vector, data);
1860 * The I/OAPIC is just a device for generating MSI messages from legacy
1861 * interrupt pins. Various fields of the RTE translate into bits of the
1862 * resulting MSI which had a historical meaning.
1864 * With interrupt remapping, many of those bits have different meanings
1865 * in the underlying MSI, but the way that the I/OAPIC transforms them
1866 * from its RTE to the MSI message is the same. This function allows
1867 * the parent IRQ domain to compose the MSI message, then takes the
1868 * relevant bits to put them in the appropriate places in the RTE in
1869 * order to generate that message when the IRQ happens.
1871 * The setup here relies on a preconfigured route entry (is_level,
1872 * active_low, masked) because the parent domain is merely composing the
1873 * generic message routing information which is used for the MSI.
1875 static void ioapic_setup_msg_from_msi(struct irq_data *irq_data,
1876 struct IO_APIC_route_entry *entry)
1880 /* Let the parent domain compose the MSI message */
1881 irq_chip_compose_msi_msg(irq_data, &msg);
1885 * - DMAR/IR: 8bit subhandle (ioapic.pin)
1886 * - AMD/IR: 8bit IRTE index
1888 entry->vector = msg.arch_data.vector;
1889 /* Delivery mode (for DMAR/IR all 0) */
1890 entry->delivery_mode = msg.arch_data.delivery_mode;
1891 /* Destination mode or DMAR/IR index bit 15 */
1892 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical;
1893 /* DMAR/IR: 1, 0 for all other modes */
1894 entry->ir_format = msg.arch_addr_lo.dmar_format;
1896 * - DMAR/IR: index bit 0-14.
1898 * - Virt: If the host supports x2apic without a virtualized IR
1899 * unit then bit 0-6 of dmar_index_0_14 are providing bit
1900 * 8-14 of the destination id.
1902 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the
1903 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7).
1905 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14;
1908 static void ioapic_configure_entry(struct irq_data *irqd)
1910 struct mp_chip_data *mpd = irqd->chip_data;
1911 struct irq_pin_list *entry;
1913 ioapic_setup_msg_from_msi(irqd, &mpd->entry);
1915 for_each_irq_pin(entry, mpd->irq_2_pin)
1916 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1919 static int ioapic_set_affinity(struct irq_data *irq_data,
1920 const struct cpumask *mask, bool force)
1922 struct irq_data *parent = irq_data->parent_data;
1923 unsigned long flags;
1926 ret = parent->chip->irq_set_affinity(parent, mask, force);
1927 raw_spin_lock_irqsave(&ioapic_lock, flags);
1928 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1929 ioapic_configure_entry(irq_data);
1930 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1936 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1937 * be in flight, but not yet serviced by the target CPU. That means
1938 * __synchronize_hardirq() would return and claim that everything is calmed
1939 * down. So free_irq() would proceed and deactivate the interrupt and free
1942 * Once the target CPU comes around to service it it will find a cleared
1943 * vector and complain. While the spurious interrupt is harmless, the full
1944 * release of resources might prevent the interrupt from being acknowledged
1945 * which keeps the hardware in a weird state.
1947 * Verify that the corresponding Remote-IRR bits are clear.
1949 static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1950 enum irqchip_irq_state which,
1953 struct mp_chip_data *mcd = irqd->chip_data;
1954 struct IO_APIC_route_entry rentry;
1955 struct irq_pin_list *p;
1957 if (which != IRQCHIP_STATE_ACTIVE)
1961 raw_spin_lock(&ioapic_lock);
1962 for_each_irq_pin(p, mcd->irq_2_pin) {
1963 rentry = __ioapic_read_entry(p->apic, p->pin);
1965 * The remote IRR is only valid in level trigger mode. It's
1966 * meaning is undefined for edge triggered interrupts and
1967 * irrelevant because the IO-APIC treats them as fire and
1970 if (rentry.irr && rentry.is_level) {
1975 raw_spin_unlock(&ioapic_lock);
1979 static struct irq_chip ioapic_chip __read_mostly = {
1981 .irq_startup = startup_ioapic_irq,
1982 .irq_mask = mask_ioapic_irq,
1983 .irq_unmask = unmask_ioapic_irq,
1984 .irq_ack = irq_chip_ack_parent,
1985 .irq_eoi = ioapic_ack_level,
1986 .irq_set_affinity = ioapic_set_affinity,
1987 .irq_retrigger = irq_chip_retrigger_hierarchy,
1988 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1989 .flags = IRQCHIP_SKIP_SET_WAKE |
1990 IRQCHIP_AFFINITY_PRE_STARTUP,
1993 static struct irq_chip ioapic_ir_chip __read_mostly = {
1994 .name = "IR-IO-APIC",
1995 .irq_startup = startup_ioapic_irq,
1996 .irq_mask = mask_ioapic_irq,
1997 .irq_unmask = unmask_ioapic_irq,
1998 .irq_ack = irq_chip_ack_parent,
1999 .irq_eoi = ioapic_ir_ack_level,
2000 .irq_set_affinity = ioapic_set_affinity,
2001 .irq_retrigger = irq_chip_retrigger_hierarchy,
2002 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
2003 .flags = IRQCHIP_SKIP_SET_WAKE |
2004 IRQCHIP_AFFINITY_PRE_STARTUP,
2007 static inline void init_IO_APIC_traps(void)
2009 struct irq_cfg *cfg;
2012 for_each_active_irq(irq) {
2014 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2016 * Hmm.. We don't have an entry for this,
2017 * so default to an old-fashioned 8259
2018 * interrupt if we can..
2020 if (irq < nr_legacy_irqs())
2021 legacy_pic->make_irq(irq);
2023 /* Strange. Oh, well.. */
2024 irq_set_chip(irq, &no_irq_chip);
2030 * The local APIC irq-chip implementation:
2033 static void mask_lapic_irq(struct irq_data *data)
2037 v = apic_read(APIC_LVT0);
2038 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2041 static void unmask_lapic_irq(struct irq_data *data)
2045 v = apic_read(APIC_LVT0);
2046 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2049 static void ack_lapic_irq(struct irq_data *data)
2054 static struct irq_chip lapic_chip __read_mostly = {
2055 .name = "local-APIC",
2056 .irq_mask = mask_lapic_irq,
2057 .irq_unmask = unmask_lapic_irq,
2058 .irq_ack = ack_lapic_irq,
2061 static void lapic_register_intr(int irq)
2063 irq_clear_status_flags(irq, IRQ_LEVEL);
2064 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2069 * This looks a bit hackish but it's about the only one way of sending
2070 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2071 * not support the ExtINT mode, unfortunately. We need to send these
2072 * cycles as some i82489DX-based boards have glue logic that keeps the
2073 * 8259A interrupt line asserted until INTA. --macro
2075 static inline void __init unlock_ExtINT_logic(void)
2078 struct IO_APIC_route_entry entry0, entry1;
2079 unsigned char save_control, save_freq_select;
2082 pin = find_isa_irq_pin(8, mp_INT);
2087 apic = find_isa_irq_apic(8, mp_INT);
2093 entry0 = ioapic_read_entry(apic, pin);
2094 clear_IO_APIC_pin(apic, pin);
2096 apic_id = hard_smp_processor_id();
2097 memset(&entry1, 0, sizeof(entry1));
2099 entry1.dest_mode_logical = true;
2100 entry1.masked = false;
2101 entry1.destid_0_7 = apic_id & 0xFF;
2102 entry1.virt_destid_8_14 = apic_id >> 8;
2103 entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
2104 entry1.active_low = entry0.active_low;
2105 entry1.is_level = false;
2108 ioapic_write_entry(apic, pin, entry1);
2110 save_control = CMOS_READ(RTC_CONTROL);
2111 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2112 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2114 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2119 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2123 CMOS_WRITE(save_control, RTC_CONTROL);
2124 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2125 clear_IO_APIC_pin(apic, pin);
2127 ioapic_write_entry(apic, pin, entry0);
2130 static int disable_timer_pin_1 __initdata;
2131 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2132 static int __init disable_timer_pin_setup(char *arg)
2134 disable_timer_pin_1 = 1;
2137 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2139 static int mp_alloc_timer_irq(int ioapic, int pin)
2142 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2145 struct irq_alloc_info info;
2147 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2148 info.devid = mpc_ioapic_id(ioapic);
2149 info.ioapic.pin = pin;
2150 mutex_lock(&ioapic_mutex);
2151 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2152 mutex_unlock(&ioapic_mutex);
2159 * This code may look a bit paranoid, but it's supposed to cooperate with
2160 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2161 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2162 * fanatically on his truly buggy board.
2164 * FIXME: really need to revamp this for all platforms.
2166 static inline void __init check_timer(void)
2168 struct irq_data *irq_data = irq_get_irq_data(0);
2169 struct mp_chip_data *data = irq_data->chip_data;
2170 struct irq_cfg *cfg = irqd_cfg(irq_data);
2171 int node = cpu_to_node(0);
2172 int apic1, pin1, apic2, pin2;
2175 if (!global_clock_event)
2178 local_irq_disable();
2181 * get/set the timer IRQ vector:
2183 legacy_pic->mask(0);
2186 * As IRQ0 is to be enabled in the 8259A, the virtual
2187 * wire has to be disabled in the local APIC. Also
2188 * timer interrupts need to be acknowledged manually in
2189 * the 8259A for the i82489DX when using the NMI
2190 * watchdog as that APIC treats NMIs as level-triggered.
2191 * The AEOI mode will finish them in the 8259A
2194 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2195 legacy_pic->init(1);
2197 pin1 = find_isa_irq_pin(0, mp_INT);
2198 apic1 = find_isa_irq_apic(0, mp_INT);
2199 pin2 = ioapic_i8259.pin;
2200 apic2 = ioapic_i8259.apic;
2202 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2203 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2204 cfg->vector, apic1, pin1, apic2, pin2);
2207 * Some BIOS writers are clueless and report the ExtINTA
2208 * I/O APIC input from the cascaded 8259A as the timer
2209 * interrupt input. So just in case, if only one pin
2210 * was found above, try it both directly and through the
2214 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2218 } else if (pin2 == -1) {
2224 /* Ok, does IRQ0 through the IOAPIC work? */
2226 mp_alloc_timer_irq(apic1, pin1);
2229 * for edge trigger, it's already unmasked,
2230 * so only need to unmask if it is level-trigger
2231 * do we really have level trigger timer?
2233 int idx = find_irq_entry(apic1, pin1, mp_INT);
2235 if (idx != -1 && irq_is_level(idx))
2236 unmask_ioapic_irq(irq_get_irq_data(0));
2238 irq_domain_deactivate_irq(irq_data);
2239 irq_domain_activate_irq(irq_data, false);
2240 if (timer_irq_works()) {
2241 if (disable_timer_pin_1 > 0)
2242 clear_IO_APIC_pin(0, pin1);
2245 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2246 clear_IO_APIC_pin(apic1, pin1);
2248 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2249 "8254 timer not connected to IO-APIC\n");
2251 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2252 "(IRQ0) through the 8259A ...\n");
2253 apic_printk(APIC_QUIET, KERN_INFO
2254 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2256 * legacy devices should be connected to IO APIC #0
2258 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2259 irq_domain_deactivate_irq(irq_data);
2260 irq_domain_activate_irq(irq_data, false);
2261 legacy_pic->unmask(0);
2262 if (timer_irq_works()) {
2263 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2267 * Cleanup, just in case ...
2269 legacy_pic->mask(0);
2270 clear_IO_APIC_pin(apic2, pin2);
2271 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2274 apic_printk(APIC_QUIET, KERN_INFO
2275 "...trying to set up timer as Virtual Wire IRQ...\n");
2277 lapic_register_intr(0);
2278 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2279 legacy_pic->unmask(0);
2281 if (timer_irq_works()) {
2282 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2285 legacy_pic->mask(0);
2286 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2287 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2289 apic_printk(APIC_QUIET, KERN_INFO
2290 "...trying to set up timer as ExtINT IRQ...\n");
2292 legacy_pic->init(0);
2293 legacy_pic->make_irq(0);
2294 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2295 legacy_pic->unmask(0);
2297 unlock_ExtINT_logic();
2299 if (timer_irq_works()) {
2300 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2303 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2304 if (apic_is_x2apic_enabled())
2305 apic_printk(APIC_QUIET, KERN_INFO
2306 "Perhaps problem with the pre-enabled x2apic mode\n"
2307 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2308 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2309 "report. Then try booting with the 'noapic' option.\n");
2315 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2316 * to devices. However there may be an I/O APIC pin available for
2317 * this interrupt regardless. The pin may be left unconnected, but
2318 * typically it will be reused as an ExtINT cascade interrupt for
2319 * the master 8259A. In the MPS case such a pin will normally be
2320 * reported as an ExtINT interrupt in the MP table. With ACPI
2321 * there is no provision for ExtINT interrupts, and in the absence
2322 * of an override it would be treated as an ordinary ISA I/O APIC
2323 * interrupt, that is edge-triggered and unmasked by default. We
2324 * used to do this, but it caused problems on some systems because
2325 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2326 * the same ExtINT cascade interrupt to drive the local APIC of the
2327 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2328 * the I/O APIC in all cases now. No actual device should request
2329 * it anyway. --macro
2331 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2333 static int mp_irqdomain_create(int ioapic)
2335 struct irq_domain *parent;
2336 int hwirqs = mp_ioapic_pin_count(ioapic);
2337 struct ioapic *ip = &ioapics[ioapic];
2338 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2339 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2340 struct fwnode_handle *fn;
2341 struct irq_fwspec fwspec;
2343 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2346 /* Handle device tree enumerated APICs proper */
2348 fn = of_node_to_fwnode(cfg->dev);
2350 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic));
2356 fwspec.param_count = 1;
2357 fwspec.param[0] = mpc_ioapic_id(ioapic);
2359 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
2362 irq_domain_free_fwnode(fn);
2366 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2367 (void *)(long)ioapic);
2369 if (!ip->irqdomain) {
2370 /* Release fw handle if it was allocated above */
2372 irq_domain_free_fwnode(fn);
2376 ip->irqdomain->parent = parent;
2378 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2379 cfg->type == IOAPIC_DOMAIN_STRICT)
2380 ioapic_dynirq_base = max(ioapic_dynirq_base,
2381 gsi_cfg->gsi_end + 1);
2386 static void ioapic_destroy_irqdomain(int idx)
2388 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2389 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2391 if (ioapics[idx].irqdomain) {
2392 irq_domain_remove(ioapics[idx].irqdomain);
2394 irq_domain_free_fwnode(fn);
2395 ioapics[idx].irqdomain = NULL;
2399 void __init setup_IO_APIC(void)
2403 if (skip_ioapic_setup || !nr_ioapics)
2406 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2408 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2409 for_each_ioapic(ioapic)
2410 BUG_ON(mp_irqdomain_create(ioapic));
2413 * Set up IO-APIC IRQ routing.
2415 x86_init.mpparse.setup_ioapic_ids();
2418 setup_IO_APIC_irqs();
2419 init_IO_APIC_traps();
2420 if (nr_legacy_irqs())
2423 ioapic_initialized = 1;
2426 static void resume_ioapic_id(int ioapic_idx)
2428 unsigned long flags;
2429 union IO_APIC_reg_00 reg_00;
2431 raw_spin_lock_irqsave(&ioapic_lock, flags);
2432 reg_00.raw = io_apic_read(ioapic_idx, 0);
2433 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2434 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2435 io_apic_write(ioapic_idx, 0, reg_00.raw);
2437 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2440 static void ioapic_resume(void)
2444 for_each_ioapic_reverse(ioapic_idx)
2445 resume_ioapic_id(ioapic_idx);
2447 restore_ioapic_entries();
2450 static struct syscore_ops ioapic_syscore_ops = {
2451 .suspend = save_ioapic_entries,
2452 .resume = ioapic_resume,
2455 static int __init ioapic_init_ops(void)
2457 register_syscore_ops(&ioapic_syscore_ops);
2462 device_initcall(ioapic_init_ops);
2464 static int io_apic_get_redir_entries(int ioapic)
2466 union IO_APIC_reg_01 reg_01;
2467 unsigned long flags;
2469 raw_spin_lock_irqsave(&ioapic_lock, flags);
2470 reg_01.raw = io_apic_read(ioapic, 1);
2471 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2473 /* The register returns the maximum index redir index
2474 * supported, which is one less than the total number of redir
2477 return reg_01.bits.entries + 1;
2480 unsigned int arch_dynirq_lower_bound(unsigned int from)
2483 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2484 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2486 if (!ioapic_initialized)
2489 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2490 * updated. So simply return @from if ioapic_dynirq_base == 0.
2492 return ioapic_dynirq_base ? : from;
2495 #ifdef CONFIG_X86_32
2496 static int io_apic_get_unique_id(int ioapic, int apic_id)
2498 union IO_APIC_reg_00 reg_00;
2499 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2501 unsigned long flags;
2505 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2506 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2507 * supports up to 16 on one shared APIC bus.
2509 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2510 * advantage of new APIC bus architecture.
2513 if (physids_empty(apic_id_map))
2514 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2516 raw_spin_lock_irqsave(&ioapic_lock, flags);
2517 reg_00.raw = io_apic_read(ioapic, 0);
2518 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2520 if (apic_id >= get_physical_broadcast()) {
2521 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2522 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2523 apic_id = reg_00.bits.ID;
2527 * Every APIC in a system must have a unique ID or we get lots of nice
2528 * 'stuck on smp_invalidate_needed IPI wait' messages.
2530 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2532 for (i = 0; i < get_physical_broadcast(); i++) {
2533 if (!apic->check_apicid_used(&apic_id_map, i))
2537 if (i == get_physical_broadcast())
2538 panic("Max apic_id exceeded!\n");
2540 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2541 "trying %d\n", ioapic, apic_id, i);
2546 apic->apicid_to_cpu_present(apic_id, &tmp);
2547 physids_or(apic_id_map, apic_id_map, tmp);
2549 if (reg_00.bits.ID != apic_id) {
2550 reg_00.bits.ID = apic_id;
2552 raw_spin_lock_irqsave(&ioapic_lock, flags);
2553 io_apic_write(ioapic, 0, reg_00.raw);
2554 reg_00.raw = io_apic_read(ioapic, 0);
2555 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2558 if (reg_00.bits.ID != apic_id) {
2559 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2565 apic_printk(APIC_VERBOSE, KERN_INFO
2566 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2571 static u8 io_apic_unique_id(int idx, u8 id)
2573 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2574 !APIC_XAPIC(boot_cpu_apic_version))
2575 return io_apic_get_unique_id(idx, id);
2580 static u8 io_apic_unique_id(int idx, u8 id)
2582 union IO_APIC_reg_00 reg_00;
2583 DECLARE_BITMAP(used, 256);
2584 unsigned long flags;
2588 bitmap_zero(used, 256);
2590 __set_bit(mpc_ioapic_id(i), used);
2592 /* Hand out the requested id if available */
2593 if (!test_bit(id, used))
2597 * Read the current id from the ioapic and keep it if
2600 raw_spin_lock_irqsave(&ioapic_lock, flags);
2601 reg_00.raw = io_apic_read(idx, 0);
2602 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2603 new_id = reg_00.bits.ID;
2604 if (!test_bit(new_id, used)) {
2605 apic_printk(APIC_VERBOSE, KERN_INFO
2606 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2612 * Get the next free id and write it to the ioapic.
2614 new_id = find_first_zero_bit(used, 256);
2615 reg_00.bits.ID = new_id;
2616 raw_spin_lock_irqsave(&ioapic_lock, flags);
2617 io_apic_write(idx, 0, reg_00.raw);
2618 reg_00.raw = io_apic_read(idx, 0);
2619 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2621 BUG_ON(reg_00.bits.ID != new_id);
2627 static int io_apic_get_version(int ioapic)
2629 union IO_APIC_reg_01 reg_01;
2630 unsigned long flags;
2632 raw_spin_lock_irqsave(&ioapic_lock, flags);
2633 reg_01.raw = io_apic_read(ioapic, 1);
2634 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2636 return reg_01.bits.version;
2640 * This function updates target affinity of IOAPIC interrupts to include
2641 * the CPUs which came online during SMP bringup.
2643 #define IOAPIC_RESOURCE_NAME_SIZE 11
2645 static struct resource *ioapic_resources;
2647 static struct resource * __init ioapic_setup_resources(void)
2650 struct resource *res;
2654 if (nr_ioapics == 0)
2657 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2660 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2662 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2665 mem += sizeof(struct resource) * nr_ioapics;
2667 for_each_ioapic(i) {
2669 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2670 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2671 mem += IOAPIC_RESOURCE_NAME_SIZE;
2672 ioapics[i].iomem_res = &res[i];
2675 ioapic_resources = res;
2680 void __init io_apic_init_mappings(void)
2682 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2683 struct resource *ioapic_res;
2686 ioapic_res = ioapic_setup_resources();
2687 for_each_ioapic(i) {
2688 if (smp_found_config) {
2689 ioapic_phys = mpc_ioapic_addr(i);
2690 #ifdef CONFIG_X86_32
2693 "WARNING: bogus zero IO-APIC "
2694 "address found in MPTABLE, "
2695 "disabling IO/APIC support!\n");
2696 smp_found_config = 0;
2697 skip_ioapic_setup = 1;
2698 goto fake_ioapic_page;
2702 #ifdef CONFIG_X86_32
2705 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2708 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2709 __func__, PAGE_SIZE, PAGE_SIZE);
2710 ioapic_phys = __pa(ioapic_phys);
2712 set_fixmap_nocache(idx, ioapic_phys);
2713 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2714 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2718 ioapic_res->start = ioapic_phys;
2719 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2724 void __init ioapic_insert_resources(void)
2727 struct resource *r = ioapic_resources;
2732 "IO APIC resources couldn't be allocated.\n");
2736 for_each_ioapic(i) {
2737 insert_resource(&iomem_resource, r);
2742 int mp_find_ioapic(u32 gsi)
2746 if (nr_ioapics == 0)
2749 /* Find the IOAPIC that manages this GSI. */
2750 for_each_ioapic(i) {
2751 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2752 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2756 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2760 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2762 struct mp_ioapic_gsi *gsi_cfg;
2764 if (WARN_ON(ioapic < 0))
2767 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2768 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2771 return gsi - gsi_cfg->gsi_base;
2774 static int bad_ioapic_register(int idx)
2776 union IO_APIC_reg_00 reg_00;
2777 union IO_APIC_reg_01 reg_01;
2778 union IO_APIC_reg_02 reg_02;
2780 reg_00.raw = io_apic_read(idx, 0);
2781 reg_01.raw = io_apic_read(idx, 1);
2782 reg_02.raw = io_apic_read(idx, 2);
2784 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2785 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2786 mpc_ioapic_addr(idx));
2793 static int find_free_ioapic_entry(void)
2797 for (idx = 0; idx < MAX_IO_APICS; idx++)
2798 if (ioapics[idx].nr_registers == 0)
2801 return MAX_IO_APICS;
2805 * mp_register_ioapic - Register an IOAPIC device
2806 * @id: hardware IOAPIC ID
2807 * @address: physical address of IOAPIC register area
2808 * @gsi_base: base of GSI associated with the IOAPIC
2809 * @cfg: configuration information for the IOAPIC
2811 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2812 struct ioapic_domain_cfg *cfg)
2814 bool hotplug = !!ioapic_initialized;
2815 struct mp_ioapic_gsi *gsi_cfg;
2816 int idx, ioapic, entries;
2820 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2823 for_each_ioapic(ioapic)
2824 if (ioapics[ioapic].mp_config.apicaddr == address) {
2825 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2830 idx = find_free_ioapic_entry();
2831 if (idx >= MAX_IO_APICS) {
2832 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2837 ioapics[idx].mp_config.type = MP_IOAPIC;
2838 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2839 ioapics[idx].mp_config.apicaddr = address;
2841 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2842 if (bad_ioapic_register(idx)) {
2843 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2847 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2848 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2851 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2852 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2854 entries = io_apic_get_redir_entries(idx);
2855 gsi_end = gsi_base + entries - 1;
2856 for_each_ioapic(ioapic) {
2857 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2858 if ((gsi_base >= gsi_cfg->gsi_base &&
2859 gsi_base <= gsi_cfg->gsi_end) ||
2860 (gsi_end >= gsi_cfg->gsi_base &&
2861 gsi_end <= gsi_cfg->gsi_end)) {
2862 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2864 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2865 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2869 gsi_cfg = mp_ioapic_gsi_routing(idx);
2870 gsi_cfg->gsi_base = gsi_base;
2871 gsi_cfg->gsi_end = gsi_end;
2873 ioapics[idx].irqdomain = NULL;
2874 ioapics[idx].irqdomain_cfg = *cfg;
2877 * If mp_register_ioapic() is called during early boot stage when
2878 * walking ACPI/DT tables, it's too early to create irqdomain,
2879 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2882 if (mp_irqdomain_create(idx)) {
2883 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2886 alloc_ioapic_saved_registers(idx);
2889 if (gsi_cfg->gsi_end >= gsi_top)
2890 gsi_top = gsi_cfg->gsi_end + 1;
2891 if (nr_ioapics <= idx)
2892 nr_ioapics = idx + 1;
2894 /* Set nr_registers to mark entry present */
2895 ioapics[idx].nr_registers = entries;
2897 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2898 idx, mpc_ioapic_id(idx),
2899 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2900 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2905 int mp_unregister_ioapic(u32 gsi_base)
2910 for_each_ioapic(ioapic)
2911 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2916 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2920 for_each_pin(ioapic, pin) {
2921 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2922 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2923 struct mp_chip_data *data;
2926 data = irq_get_chip_data(irq);
2927 if (data && data->count) {
2928 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2935 /* Mark entry not present */
2936 ioapics[ioapic].nr_registers = 0;
2937 ioapic_destroy_irqdomain(ioapic);
2938 free_ioapic_saved_registers(ioapic);
2939 if (ioapics[ioapic].iomem_res)
2940 release_resource(ioapics[ioapic].iomem_res);
2941 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2942 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2947 int mp_ioapic_registered(u32 gsi_base)
2951 for_each_ioapic(ioapic)
2952 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2958 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2959 struct irq_alloc_info *info)
2961 if (info && info->ioapic.valid) {
2962 data->is_level = info->ioapic.is_level;
2963 data->active_low = info->ioapic.active_low;
2964 } else if (__acpi_get_override_irq(gsi, &data->is_level,
2965 &data->active_low) < 0) {
2966 /* PCI interrupts are always active low level triggered. */
2967 data->is_level = true;
2968 data->active_low = true;
2973 * Configure the I/O-APIC specific fields in the routing entry.
2975 * This is important to setup the I/O-APIC specific bits (is_level,
2976 * active_low, masked) because the underlying parent domain will only
2977 * provide the routing information and is oblivious of the I/O-APIC
2980 * The entry is just preconfigured at this point and not written into the
2981 * RTE. This happens later during activation which will fill in the actual
2982 * routing information.
2984 static void mp_preconfigure_entry(struct mp_chip_data *data)
2986 struct IO_APIC_route_entry *entry = &data->entry;
2988 memset(entry, 0, sizeof(*entry));
2989 entry->is_level = data->is_level;
2990 entry->active_low = data->active_low;
2992 * Mask level triggered irqs. Edge triggered irqs are masked
2993 * by the irq core code in case they fire.
2995 entry->masked = data->is_level;
2998 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2999 unsigned int nr_irqs, void *arg)
3001 struct irq_alloc_info *info = arg;
3002 struct mp_chip_data *data;
3003 struct irq_data *irq_data;
3004 int ret, ioapic, pin;
3005 unsigned long flags;
3007 if (!info || nr_irqs > 1)
3009 irq_data = irq_domain_get_irq_data(domain, virq);
3013 ioapic = mp_irqdomain_ioapic_idx(domain);
3014 pin = info->ioapic.pin;
3015 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3018 data = kzalloc(sizeof(*data), GFP_KERNEL);
3022 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3028 INIT_LIST_HEAD(&data->irq_2_pin);
3029 irq_data->hwirq = info->ioapic.pin;
3030 irq_data->chip = (domain->parent == x86_vector_domain) ?
3031 &ioapic_chip : &ioapic_ir_chip;
3032 irq_data->chip_data = data;
3033 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3035 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3037 mp_preconfigure_entry(data);
3038 mp_register_handler(virq, data->is_level);
3040 local_irq_save(flags);
3041 if (virq < nr_legacy_irqs())
3042 legacy_pic->mask(virq);
3043 local_irq_restore(flags);
3045 apic_printk(APIC_VERBOSE, KERN_DEBUG
3046 "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n",
3047 ioapic, mpc_ioapic_id(ioapic), pin, virq,
3048 data->is_level, data->active_low);
3052 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3053 unsigned int nr_irqs)
3055 struct irq_data *irq_data;
3056 struct mp_chip_data *data;
3058 BUG_ON(nr_irqs != 1);
3059 irq_data = irq_domain_get_irq_data(domain, virq);
3060 if (irq_data && irq_data->chip_data) {
3061 data = irq_data->chip_data;
3062 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3063 (int)irq_data->hwirq);
3064 WARN_ON(!list_empty(&data->irq_2_pin));
3065 kfree(irq_data->chip_data);
3067 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3070 int mp_irqdomain_activate(struct irq_domain *domain,
3071 struct irq_data *irq_data, bool reserve)
3073 unsigned long flags;
3075 raw_spin_lock_irqsave(&ioapic_lock, flags);
3076 ioapic_configure_entry(irq_data);
3077 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3081 void mp_irqdomain_deactivate(struct irq_domain *domain,
3082 struct irq_data *irq_data)
3084 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3085 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3086 (int)irq_data->hwirq);
3089 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3091 return (int)(long)domain->host_data;
3094 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3095 .alloc = mp_irqdomain_alloc,
3096 .free = mp_irqdomain_free,
3097 .activate = mp_irqdomain_activate,
3098 .deactivate = mp_irqdomain_deactivate,